1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Repeat fill, corresponds to X86::REP_STOSx.
132 /// Repeat move, corresponds to X86::REP_MOVSx.
135 /// On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// Copies a 32-bit value from the low word of a MMX
156 /// Copies a GPR into the low 32-bit word of a MMX vector
157 /// and zero out the high word.
160 /// Extract an 8-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRB.
164 /// Extract a 16-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRW.
168 /// Insert any element of a 4 x float vector into any element
169 /// of a destination 4 x floatvector.
172 /// Insert the lower 8-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRB.
176 /// Insert the lower 16-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRW.
180 /// Shuffle 16 8-bit values within a vector.
183 /// Compute Sum of Absolute Differences.
186 /// Bitwise Logical AND NOT of Packed FP values.
189 /// Copy integer sign.
192 /// Blend where the selector is an immediate.
195 /// Blend where the condition has been shrunk.
196 /// This is used to emphasize that the condition mask is
197 /// no more valid for generic VSELECT optimizations.
200 /// Combined add and sub on an FP vector.
202 // FP vector ops with rounding mode.
210 // Integer add/sub with unsigned saturation.
213 // Integer add/sub with signed saturation.
217 /// Integer horizontal add.
220 /// Integer horizontal sub.
223 /// Floating point horizontal add.
226 /// Floating point horizontal sub.
229 /// Unsigned integer max and min.
232 /// Signed integer max and min.
235 /// Floating point max and min.
238 /// Commutative FMIN and FMAX.
241 /// Floating point reciprocal-sqrt and reciprocal approximation.
242 /// Note that these typically require refinement
243 /// in order to obtain suitable precision.
246 // Thread Local Storage.
249 // Thread Local Storage. A call to get the start address
250 // of the TLS block for the current module.
253 // Thread Local Storage. When calling to an OS provided
254 // thunk at the address from an earlier relocation.
257 // Exception Handling helpers.
260 // SjLj exception handling setjmp.
263 // SjLj exception handling longjmp.
266 /// Tail call return. See X86TargetLowering::LowerCall for
267 /// the list of operands.
270 // Vector move to low scalar and zero higher vector elements.
273 // Vector integer zero-extend.
276 // Vector integer signed-extend.
279 // Vector integer truncate.
282 // Vector integer truncate with mask.
291 // 128-bit vector logical left / right shift
294 // Vector shift elements
297 // Vector shift elements by immediate
300 // Vector packed double/float comparison.
303 // Vector integer comparisons.
305 // Vector integer comparisons, the result is in a mask vector.
308 /// Vector comparison generating mask bits for fp and
309 /// integer signed and unsigned data types.
312 // Vector comparison with rounding mode for FP values
315 // Arithmetic operations with FLAGS results.
316 ADD, SUB, ADC, SBB, SMUL,
317 INC, DEC, OR, XOR, AND,
319 BEXTR, // Bit field extract
321 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
323 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
326 // 8-bit divrem that zero-extend the high result (AH).
330 // X86-specific multiply by immediate.
333 // Vector bitwise comparisons.
336 // Vector packed fp sign bitwise comparisons.
339 // Vector "test" in AVX-512, the result is in a mask vector.
343 // OR/AND test for masks
346 // Several flavors of instructions with vector shuffle behaviors.
351 // AVX512 inter-lane alignr
376 //Fix Up Special Packed Float32/64 values
378 //Range Restriction Calculation For Packed Pairs of Float32/64 values
380 // Broadcast scalar to vector
382 // Broadcast subvector to vector
384 // Insert/Extract vector element
388 // Vector multiply packed unsigned doubleword integers
390 // Vector multiply packed signed doubleword integers
400 // FMA with rounding mode
409 // Compress and expand
413 // Save xmm argument registers to the stack, according to %al. An operator
414 // is needed so that this can be expanded with control flow.
415 VASTART_SAVE_XMM_REGS,
417 // Windows's _chkstk call to do stack probing.
420 // For allocating variable amounts of stack space when using
421 // segmented stacks. Check if the current stacklet has enough space, and
422 // falls back to heap allocation if not.
425 // Windows's _ftol2 runtime routine to do fptoui.
434 // Store FP status word into i16 register.
437 // Store contents of %ah into %eflags.
440 // Get a random integer and indicate whether it is valid in CF.
443 // Get a NIST SP800-90B & C compliant random integer and
444 // indicate whether it is valid in CF.
450 // Test if in transactional execution.
454 RSQRT28, RCP28, EXP2,
457 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
461 // Load, scalar_to_vector, and zero extend.
464 // Store FP control world into i16 memory.
467 /// This instruction implements FP_TO_SINT with the
468 /// integer destination in memory and a FP reg source. This corresponds
469 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
470 /// has two inputs (token chain and address) and two outputs (int value
471 /// and token chain).
476 /// This instruction implements SINT_TO_FP with the
477 /// integer source in memory and FP reg result. This corresponds to the
478 /// X86::FILD*m instructions. It has three inputs (token chain, address,
479 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
480 /// also produces a flag).
484 /// This instruction implements an extending load to FP stack slots.
485 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
486 /// operand, ptr to load from, and a ValueType node indicating the type
490 /// This instruction implements a truncating store to FP stack
491 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
492 /// chain operand, value to store, address, and a ValueType to store it
496 /// This instruction grabs the address of the next argument
497 /// from a va_list. (reads and modifies the va_list in memory)
500 // WARNING: Do not add anything in the end unless you want the node to
501 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
502 // thought as target memory ops!
506 /// Define some predicates that are used for node matching.
508 /// Return true if the specified
509 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
510 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
511 bool isVEXTRACT128Index(SDNode *N);
513 /// Return true if the specified
514 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
515 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
516 bool isVINSERT128Index(SDNode *N);
518 /// Return true if the specified
519 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
520 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
521 bool isVEXTRACT256Index(SDNode *N);
523 /// Return true if the specified
524 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
525 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
526 bool isVINSERT256Index(SDNode *N);
528 /// Return the appropriate
529 /// immediate to extract the specified EXTRACT_SUBVECTOR index
530 /// with VEXTRACTF128, VEXTRACTI128 instructions.
531 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
533 /// Return the appropriate
534 /// immediate to insert at the specified INSERT_SUBVECTOR index
535 /// with VINSERTF128, VINSERT128 instructions.
536 unsigned getInsertVINSERT128Immediate(SDNode *N);
538 /// Return the appropriate
539 /// immediate to extract the specified EXTRACT_SUBVECTOR index
540 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
541 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
543 /// Return the appropriate
544 /// immediate to insert at the specified INSERT_SUBVECTOR index
545 /// with VINSERTF64x4, VINSERTI64x4 instructions.
546 unsigned getInsertVINSERT256Immediate(SDNode *N);
548 /// Returns true if Elt is a constant zero or floating point constant +0.0.
549 bool isZeroNode(SDValue Elt);
551 /// Returns true of the given offset can be
552 /// fit into displacement field of the instruction.
553 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
554 bool hasSymbolicDisplacement = true);
557 /// Determines whether the callee is required to pop its
558 /// own arguments. Callee pop is necessary to support tail calls.
559 bool isCalleePop(CallingConv::ID CallingConv,
560 bool is64Bit, bool IsVarArg, bool TailCallOpt);
562 /// AVX512 static rounding constants. These need to match the values in
564 enum STATIC_ROUNDING {
573 //===--------------------------------------------------------------------===//
574 // X86 Implementation of the TargetLowering interface
575 class X86TargetLowering final : public TargetLowering {
577 explicit X86TargetLowering(const X86TargetMachine &TM,
578 const X86Subtarget &STI);
580 unsigned getJumpTableEncoding() const override;
581 bool useSoftFloat() const override;
583 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
586 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
587 const MachineBasicBlock *MBB, unsigned uid,
588 MCContext &Ctx) const override;
590 /// Returns relocation base for the given PIC jumptable.
591 SDValue getPICJumpTableRelocBase(SDValue Table,
592 SelectionDAG &DAG) const override;
594 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
595 unsigned JTI, MCContext &Ctx) const override;
597 /// Return the desired alignment for ByVal aggregate
598 /// function arguments in the caller parameter area. For X86, aggregates
599 /// that contains are placed at 16-byte boundaries while the rest are at
600 /// 4-byte boundaries.
601 unsigned getByValTypeAlignment(Type *Ty) const override;
603 /// Returns the target specific optimal type for load
604 /// and store operations as a result of memset, memcpy, and memmove
605 /// lowering. If DstAlign is zero that means it's safe to destination
606 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
607 /// means there isn't a need to check it against alignment requirement,
608 /// probably because the source does not need to be loaded. If 'IsMemset' is
609 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
610 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
611 /// source is constant so it does not need to be loaded.
612 /// It returns EVT::Other if the type should be determined using generic
613 /// target-independent logic.
614 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
615 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
616 MachineFunction &MF) const override;
618 /// Returns true if it's safe to use load / store of the
619 /// specified type to expand memcpy / memset inline. This is mostly true
620 /// for all types except for some special cases. For example, on X86
621 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
622 /// also does type conversion. Note the specified type doesn't have to be
623 /// legal as the hook is used before type legalization.
624 bool isSafeMemOpType(MVT VT) const override;
626 /// Returns true if the target allows
627 /// unaligned memory accesses. of the specified type. Returns whether it
628 /// is "fast" by reference in the second argument.
629 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
630 bool *Fast) const override;
632 /// Provide custom lowering hooks for some operations.
634 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
636 /// Replace the results of node with an illegal result
637 /// type with new values built out of custom code.
639 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
640 SelectionDAG &DAG) const override;
643 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
645 /// Return true if the target has native support for
646 /// the specified value type and it is 'desirable' to use the type for the
647 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
648 /// instruction encodings are longer and some i16 instructions are slow.
649 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
651 /// Return true if the target has native support for the
652 /// specified value type and it is 'desirable' to use the type. e.g. On x86
653 /// i16 is legal, but undesirable since i16 instruction encodings are longer
654 /// and some i16 instructions are slow.
655 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
658 EmitInstrWithCustomInserter(MachineInstr *MI,
659 MachineBasicBlock *MBB) const override;
662 /// This method returns the name of a target specific DAG node.
663 const char *getTargetNodeName(unsigned Opcode) const override;
665 bool isCheapToSpeculateCttz() const override;
667 bool isCheapToSpeculateCtlz() const override;
669 /// Return the value type to use for ISD::SETCC.
670 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
672 /// Determine which of the bits specified in Mask are known to be either
673 /// zero or one and return them in the KnownZero/KnownOne bitsets.
674 void computeKnownBitsForTargetNode(const SDValue Op,
677 const SelectionDAG &DAG,
678 unsigned Depth = 0) const override;
680 /// Determine the number of bits in the operation that are sign bits.
681 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
682 const SelectionDAG &DAG,
683 unsigned Depth) const override;
685 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
686 int64_t &Offset) const override;
688 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
690 bool ExpandInlineAsm(CallInst *CI) const override;
693 getConstraintType(const std::string &Constraint) const override;
695 /// Examine constraint string and operand type and determine a weight value.
696 /// The operand object must already have been set up with the operand type.
698 getSingleConstraintMatchWeight(AsmOperandInfo &info,
699 const char *constraint) const override;
701 const char *LowerXConstraint(EVT ConstraintVT) const override;
703 /// Lower the specified operand into the Ops vector. If it is invalid, don't
704 /// add anything to Ops. If hasMemory is true it means one of the asm
705 /// constraint of the inline asm instruction being processed is 'm'.
706 void LowerAsmOperandForConstraint(SDValue Op,
707 std::string &Constraint,
708 std::vector<SDValue> &Ops,
709 SelectionDAG &DAG) const override;
711 unsigned getInlineAsmMemConstraint(
712 const std::string &ConstraintCode) const override {
713 if (ConstraintCode == "i")
714 return InlineAsm::Constraint_i;
715 else if (ConstraintCode == "o")
716 return InlineAsm::Constraint_o;
717 else if (ConstraintCode == "v")
718 return InlineAsm::Constraint_v;
719 else if (ConstraintCode == "X")
720 return InlineAsm::Constraint_X;
721 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
724 /// Given a physical register constraint
725 /// (e.g. {edx}), return the register number and the register class for the
726 /// register. This should only be used for C_Register constraints. On
727 /// error, this returns a register number of 0.
728 std::pair<unsigned, const TargetRegisterClass *>
729 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
730 const std::string &Constraint,
731 MVT VT) const override;
733 /// Return true if the addressing mode represented
734 /// by AM is legal for this target, for a load/store of the specified type.
735 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
736 unsigned AS) const override;
738 /// Return true if the specified immediate is legal
739 /// icmp immediate, that is the target has icmp instructions which can
740 /// compare a register against the immediate without having to materialize
741 /// the immediate into a register.
742 bool isLegalICmpImmediate(int64_t Imm) const override;
744 /// Return true if the specified immediate is legal
745 /// add immediate, that is the target has add instructions which can
746 /// add a register and the immediate without having to materialize
747 /// the immediate into a register.
748 bool isLegalAddImmediate(int64_t Imm) const override;
750 /// \brief Return the cost of the scaling factor used in the addressing
751 /// mode represented by AM for this target, for a load/store
752 /// of the specified type.
753 /// If the AM is supported, the return value must be >= 0.
754 /// If the AM is not supported, it returns a negative value.
755 int getScalingFactorCost(const AddrMode &AM, Type *Ty,
756 unsigned AS) const override;
758 bool isVectorShiftByScalarCheap(Type *Ty) const override;
760 /// Return true if it's free to truncate a value of
761 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
762 /// register EAX to i16 by referencing its sub-register AX.
763 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
764 bool isTruncateFree(EVT VT1, EVT VT2) const override;
766 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
768 /// Return true if any actual instruction that defines a
769 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
770 /// register. This does not necessarily include registers defined in
771 /// unknown ways, such as incoming arguments, or copies from unknown
772 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
773 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
774 /// all instructions that define 32-bit values implicit zero-extend the
775 /// result out to 64 bits.
776 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
777 bool isZExtFree(EVT VT1, EVT VT2) const override;
778 bool isZExtFree(SDValue Val, EVT VT2) const override;
780 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
781 /// extend node) is profitable.
782 bool isVectorLoadExtDesirable(SDValue) const override;
784 /// Return true if an FMA operation is faster than a pair of fmul and fadd
785 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
786 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
787 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
789 /// Return true if it's profitable to narrow
790 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
791 /// from i32 to i8 but not from i32 to i16.
792 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
794 /// Returns true if the target can instruction select the
795 /// specified FP immediate natively. If false, the legalizer will
796 /// materialize the FP immediate as a load from a constant pool.
797 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
799 /// Targets can use this to indicate that they only support *some*
800 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
801 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
803 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
804 EVT VT) const override;
806 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
807 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
808 /// replace a VAND with a constant pool entry.
809 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
810 EVT VT) const override;
812 /// If true, then instruction selection should
813 /// seek to shrink the FP constant of the specified type to a smaller type
814 /// in order to save space and / or reduce runtime.
815 bool ShouldShrinkFPConstant(EVT VT) const override {
816 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
817 // expensive than a straight movsd. On the other hand, it's important to
818 // shrink long double fp constant since fldt is very slow.
819 return !X86ScalarSSEf64 || VT == MVT::f80;
822 /// Return true if we believe it is correct and profitable to reduce the
823 /// load node to a smaller type.
824 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
825 EVT NewVT) const override;
827 /// Return true if the specified scalar FP type is computed in an SSE
828 /// register, not on the X87 floating point stack.
829 bool isScalarFPTypeInSSEReg(EVT VT) const {
830 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
831 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
834 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
835 bool isTargetFTOL() const;
837 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
839 bool isIntegerTypeFTOL(EVT VT) const {
840 return isTargetFTOL() && VT == MVT::i64;
843 /// \brief Returns true if it is beneficial to convert a load of a constant
844 /// to just the constant itself.
845 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
846 Type *Ty) const override;
848 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
850 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
852 /// Intel processors have a unified instruction and data cache
853 const char * getClearCacheBuiltinName() const override {
854 return nullptr; // nothing to do, move along.
857 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
859 /// This method returns a target specific FastISel object,
860 /// or null if the target does not support "fast" ISel.
861 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
862 const TargetLibraryInfo *libInfo) const override;
864 /// Return true if the target stores stack protector cookies at a fixed
865 /// offset in some non-standard address space, and populates the address
866 /// space and offset as appropriate.
867 bool getStackCookieLocation(unsigned &AddressSpace,
868 unsigned &Offset) const override;
870 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
871 SelectionDAG &DAG) const;
873 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
875 bool useLoadStackGuardNode() const override;
876 /// \brief Customize the preferred legalization strategy for certain types.
877 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
880 std::pair<const TargetRegisterClass *, uint8_t>
881 findRepresentativeClass(const TargetRegisterInfo *TRI,
882 MVT VT) const override;
885 /// Keep a pointer to the X86Subtarget around so that we can
886 /// make the right decision when generating code for different targets.
887 const X86Subtarget *Subtarget;
888 const DataLayout *TD;
890 /// Select between SSE or x87 floating point ops.
891 /// When SSE is available, use it for f32 operations.
892 /// When SSE2 is available, use it for f64 operations.
893 bool X86ScalarSSEf32;
894 bool X86ScalarSSEf64;
896 /// A list of legal FP immediates.
897 std::vector<APFloat> LegalFPImmediates;
899 /// Indicate that this x86 target can instruction
900 /// select the specified FP immediate natively.
901 void addLegalFPImmediate(const APFloat& Imm) {
902 LegalFPImmediates.push_back(Imm);
905 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
906 CallingConv::ID CallConv, bool isVarArg,
907 const SmallVectorImpl<ISD::InputArg> &Ins,
908 SDLoc dl, SelectionDAG &DAG,
909 SmallVectorImpl<SDValue> &InVals) const;
910 SDValue LowerMemArgument(SDValue Chain,
911 CallingConv::ID CallConv,
912 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
913 SDLoc dl, SelectionDAG &DAG,
914 const CCValAssign &VA, MachineFrameInfo *MFI,
916 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
917 SDLoc dl, SelectionDAG &DAG,
918 const CCValAssign &VA,
919 ISD::ArgFlagsTy Flags) const;
921 // Call lowering helpers.
923 /// Check whether the call is eligible for tail call optimization. Targets
924 /// that want to do tail call optimization should implement this function.
925 bool IsEligibleForTailCallOptimization(SDValue Callee,
926 CallingConv::ID CalleeCC,
928 bool isCalleeStructRet,
929 bool isCallerStructRet,
931 const SmallVectorImpl<ISD::OutputArg> &Outs,
932 const SmallVectorImpl<SDValue> &OutVals,
933 const SmallVectorImpl<ISD::InputArg> &Ins,
934 SelectionDAG& DAG) const;
935 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
936 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
937 SDValue Chain, bool IsTailCall, bool Is64Bit,
938 int FPDiff, SDLoc dl) const;
940 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
941 SelectionDAG &DAG) const;
943 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
945 bool isReplace) const;
947 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
948 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
949 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
950 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
951 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
952 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
953 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
955 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
956 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
957 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
958 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
959 int64_t Offset, SelectionDAG &DAG) const;
960 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
961 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
962 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
963 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
964 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
965 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
966 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
967 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
968 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
969 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
970 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
971 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
972 SDLoc dl, SelectionDAG &DAG) const;
973 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
974 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
975 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
976 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
977 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
978 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
979 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
980 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
981 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
982 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
983 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
984 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
985 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
986 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
987 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
988 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
989 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
990 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
991 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
994 LowerFormalArguments(SDValue Chain,
995 CallingConv::ID CallConv, bool isVarArg,
996 const SmallVectorImpl<ISD::InputArg> &Ins,
997 SDLoc dl, SelectionDAG &DAG,
998 SmallVectorImpl<SDValue> &InVals) const override;
999 SDValue LowerCall(CallLoweringInfo &CLI,
1000 SmallVectorImpl<SDValue> &InVals) const override;
1002 SDValue LowerReturn(SDValue Chain,
1003 CallingConv::ID CallConv, bool isVarArg,
1004 const SmallVectorImpl<ISD::OutputArg> &Outs,
1005 const SmallVectorImpl<SDValue> &OutVals,
1006 SDLoc dl, SelectionDAG &DAG) const override;
1008 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1010 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1012 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1013 ISD::NodeType ExtendKind) const override;
1015 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1017 const SmallVectorImpl<ISD::OutputArg> &Outs,
1018 LLVMContext &Context) const override;
1020 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1022 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1023 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1024 TargetLoweringBase::AtomicRMWExpansionKind
1025 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1028 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1030 bool needsCmpXchgNb(const Type *MemType) const;
1032 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1033 /// nand, max, min, umax, umin). It takes the corresponding instruction to
1034 /// expand, the associated machine basic block, and the associated X86
1035 /// opcodes for reg/reg.
1036 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1037 MachineBasicBlock *MBB) const;
1039 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1040 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1041 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1042 MachineBasicBlock *MBB) const;
1044 // Utility function to emit the low-level va_arg code for X86-64.
1045 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1047 MachineBasicBlock *MBB) const;
1049 /// Utility function to emit the xmm reg save portion of va_start.
1050 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1051 MachineInstr *BInstr,
1052 MachineBasicBlock *BB) const;
1054 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1055 MachineBasicBlock *BB) const;
1057 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1058 MachineBasicBlock *BB) const;
1060 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1061 MachineBasicBlock *BB) const;
1063 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1064 MachineBasicBlock *BB) const;
1066 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1067 MachineBasicBlock *BB) const;
1069 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1070 MachineBasicBlock *MBB) const;
1072 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1073 MachineBasicBlock *MBB) const;
1075 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1076 MachineBasicBlock *MBB) const;
1078 /// Emit nodes that will be selected as "test Op0,Op0", or something
1079 /// equivalent, for use with the given x86 condition code.
1080 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1081 SelectionDAG &DAG) const;
1083 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1084 /// equivalent, for use with the given x86 condition code.
1085 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1086 SelectionDAG &DAG) const;
1088 /// Convert a comparison if required by the subtarget.
1089 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1091 /// Use rsqrt* to speed up sqrt calculations.
1092 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1093 unsigned &RefinementSteps,
1094 bool &UseOneConstNR) const override;
1096 /// Use rcp* to speed up fdiv calculations.
1097 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1098 unsigned &RefinementSteps) const override;
1100 /// Reassociate floating point divisions into multiply by reciprocal.
1101 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
1105 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1106 const TargetLibraryInfo *libInfo);
1110 #endif // X86ISELLOWERING_H