1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
26 // X86 Specific DAG Nodes
28 // Start the numbering where the builtin ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
31 /// SHLD, SHRD - Double shift instructions. These correspond to
32 /// X86::SHLDxx and X86::SHRDxx instructions.
36 /// FAND - Bitwise logical AND of floating point values. This corresponds
37 /// to X86::ANDPS or X86::ANDPD.
40 /// FOR - Bitwise logical OR of floating point values. This corresponds
41 /// to X86::ORPS or X86::ORPD.
44 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
45 /// to X86::XORPS or X86::XORPD.
48 /// FSRL - Bitwise logical right shift of floating point values. These
49 /// corresponds to X86::PSRLDQ.
52 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
53 /// integer source in memory and FP reg result. This corresponds to the
54 /// X86::FILD*m instructions. It has three inputs (token chain, address,
55 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
56 /// also produces a flag).
60 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
61 /// integer destination in memory and a FP reg source. This corresponds
62 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
63 /// has two inputs (token chain and address) and two outputs (int value
69 /// FLD - This instruction implements an extending load to FP stack slots.
70 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
71 /// operand, ptr to load from, and a ValueType node indicating the type
75 /// FST - This instruction implements a truncating store to FP stack
76 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
77 /// chain operand, value to store, address, and a ValueType to store it
81 /// FP_GET_RESULT - This corresponds to FpGETRESULT pseudo instruction
82 /// which copies from ST(0) to the destination. It takes a chain and
83 /// writes a RFP result and a chain.
86 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instruction
87 /// which copies the source operand to ST(0). It takes a chain+value and
88 /// returns a chain and a flag.
91 /// CALL/TAILCALL - These operations represent an abstract X86 call
92 /// instruction, which includes a bunch of information. In particular the
93 /// operands of these node are:
95 /// #0 - The incoming token chain
97 /// #2 - The number of arg bytes the caller pushes on the stack.
98 /// #3 - The number of arg bytes the callee pops off the stack.
99 /// #4 - The value to pass in AL/AX/EAX (optional)
100 /// #5 - The value to pass in DL/DX/EDX (optional)
102 /// The result values of these nodes are:
104 /// #0 - The outgoing token chain
105 /// #1 - The first register result value (optional)
106 /// #2 - The second register result value (optional)
108 /// The CALL vs TAILCALL distinction boils down to whether the callee is
109 /// known not to modify the caller's stack frame, as is standard with
114 /// RDTSC_DAG - This operation implements the lowering for
118 /// X86 compare and logical compare instructions.
121 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
122 /// operand produced by a CMP instruction.
125 /// X86 conditional moves. Operand 1 and operand 2 are the two values
126 /// to select from (operand 1 is a R/W operand). Operand 3 is the
127 /// condition code, and operand 4 is the flag operand produced by a CMP
128 /// or TEST instruction. It also writes a flag result.
131 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
132 /// is the block to branch if condition is true, operand 3 is the
133 /// condition code, and operand 4 is the flag operand produced by a CMP
134 /// or TEST instruction.
137 /// Return with a flag operand. Operand 1 is the chain operand, operand
138 /// 2 is the number of bytes of stack to pop.
141 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
144 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
147 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
148 /// at function entry, used for PIC code.
151 /// Wrapper - A wrapper node for TargetConstantPool,
152 /// TargetExternalSymbol, and TargetGlobalAddress.
155 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
156 /// relative displacements.
159 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
160 /// have to match the operand type.
163 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
164 /// i32, corresponds to X86::PEXTRW.
167 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
168 /// corresponds to X86::PINSRW.
171 /// FMAX, FMIN - Floating point max and min.
175 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
176 /// approximation. Note that these typically require refinement
177 /// in order to obtain suitable precision.
180 // Thread Local Storage
181 TLSADDR, THREAD_POINTER,
183 // Exception Handling helpers
188 /// Define some predicates that are used for node matching.
190 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
191 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
192 bool isPSHUFDMask(SDNode *N);
194 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
195 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
196 bool isPSHUFHWMask(SDNode *N);
198 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
199 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
200 bool isPSHUFLWMask(SDNode *N);
202 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
203 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
204 bool isSHUFPMask(SDNode *N);
206 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
207 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
208 bool isMOVHLPSMask(SDNode *N);
210 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
211 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
213 bool isMOVHLPS_v_undef_Mask(SDNode *N);
215 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
216 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
217 bool isMOVLPMask(SDNode *N);
219 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
220 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
221 /// as well as MOVLHPS.
222 bool isMOVHPMask(SDNode *N);
224 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
225 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
226 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
228 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
229 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
230 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
232 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
233 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
235 bool isUNPCKL_v_undef_Mask(SDNode *N);
237 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
238 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
240 bool isUNPCKH_v_undef_Mask(SDNode *N);
242 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
243 /// specifies a shuffle of elements that is suitable for input to MOVSS,
244 /// MOVSD, and MOVD, i.e. setting the lowest element.
245 bool isMOVLMask(SDNode *N);
247 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
248 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
249 bool isMOVSHDUPMask(SDNode *N);
251 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
252 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
253 bool isMOVSLDUPMask(SDNode *N);
255 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
256 /// specifies a splat of a single element.
257 bool isSplatMask(SDNode *N);
259 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
260 /// specifies a splat of zero element.
261 bool isSplatLoMask(SDNode *N);
263 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
264 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
266 unsigned getShuffleSHUFImmediate(SDNode *N);
268 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
269 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
271 unsigned getShufflePSHUFHWImmediate(SDNode *N);
273 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
274 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
276 unsigned getShufflePSHUFLWImmediate(SDNode *N);
279 //===--------------------------------------------------------------------===//
280 // X86TargetLowering - X86 Implementation of the TargetLowering interface
281 class X86TargetLowering : public TargetLowering {
282 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
283 int RegSaveFrameIndex; // X86-64 vararg func register save area.
284 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
285 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
286 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
287 int BytesCallerReserves; // Number of arg bytes caller makes.
289 explicit X86TargetLowering(TargetMachine &TM);
291 // Return the number of bytes that a function should pop when it returns (in
292 // addition to the space used by the return address).
294 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
296 // Return the number of bytes that the caller reserves for arguments passed
298 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
300 /// getStackPtrReg - Return the stack pointer register we are using: either
302 unsigned getStackPtrReg() const { return X86StackPtr; }
304 /// LowerOperation - Provide custom lowering hooks for some operations.
306 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
308 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
310 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
311 MachineBasicBlock *MBB);
313 /// getTargetNodeName - This method returns the name of a target specific
315 virtual const char *getTargetNodeName(unsigned Opcode) const;
317 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
318 /// in Mask are known to be either zero or one and return them in the
319 /// KnownZero/KnownOne bitsets.
320 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
324 const SelectionDAG &DAG,
325 unsigned Depth = 0) const;
327 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
329 ConstraintType getConstraintType(const std::string &Constraint) const;
331 std::vector<unsigned>
332 getRegClassForInlineAsmConstraint(const std::string &Constraint,
333 MVT::ValueType VT) const;
335 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
336 /// vector. If it is invalid, don't add anything to Ops.
337 virtual void LowerAsmOperandForConstraint(SDOperand Op,
338 char ConstraintLetter,
339 std::vector<SDOperand> &Ops,
342 /// getRegForInlineAsmConstraint - Given a physical register constraint
343 /// (e.g. {edx}), return the register number and the register class for the
344 /// register. This should only be used for C_Register constraints. On
345 /// error, this returns a register number of 0.
346 std::pair<unsigned, const TargetRegisterClass*>
347 getRegForInlineAsmConstraint(const std::string &Constraint,
348 MVT::ValueType VT) const;
350 /// isLegalAddressingMode - Return true if the addressing mode represented
351 /// by AM is legal for this target, for a load/store of the specified type.
352 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
354 /// isShuffleMaskLegal - Targets can use this to indicate that they only
355 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
356 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
357 /// values are assumed to be legal.
358 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
360 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
361 /// used by Targets can use this to indicate if there is a suitable
362 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
364 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
366 SelectionDAG &DAG) const;
368 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
369 /// make the right decision when generating code for different targets.
370 const X86Subtarget *Subtarget;
371 const MRegisterInfo *RegInfo;
373 /// X86StackPtr - X86 physical register used as stack ptr.
374 unsigned X86StackPtr;
376 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
377 /// floating point ops.
378 /// When SSE is available, use it for f32 operations.
379 /// When SSE2 is available, use it for f64 operations.
380 bool X86ScalarSSEf32;
381 bool X86ScalarSSEf64;
383 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
384 unsigned CallingConv, SelectionDAG &DAG);
387 SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
388 const CCValAssign &VA, MachineFrameInfo *MFI,
389 SDOperand Root, unsigned i);
391 SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
392 const SDOperand &StackPtr,
393 const CCValAssign &VA, SDOperand Chain,
396 // C and StdCall Calling Convention implementation.
397 SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
398 bool isStdCall = false);
399 SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
401 // X86-64 C Calling Convention implementation.
402 SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
403 SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,unsigned CC);
405 // Fast and FastCall Calling Convention implementation.
406 SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
407 SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
409 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
410 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
411 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
412 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
413 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
414 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
415 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
416 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
417 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
418 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
419 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
420 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
421 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
422 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
423 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
424 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
425 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
426 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
427 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
428 SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
429 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
430 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
431 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
432 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
433 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
434 SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
435 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
436 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
437 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
438 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
439 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
440 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
441 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
442 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
446 #endif // X86ISELLOWERING_H