1 //===-- X86ISelPattern.cpp - A pattern matching inst selector for X86 -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for X86.
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86RegisterInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86ISelLowering.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/CodeGen/SSARegMap.h"
29 #include "llvm/Target/TargetData.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CFG.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/ADT/Statistic.h"
41 //===----------------------------------------------------------------------===//
42 // Pattern Matcher Implementation
43 //===----------------------------------------------------------------------===//
46 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
47 /// SDOperand's instead of register numbers for the leaves of the matched
49 struct X86ISelAddressMode {
55 struct { // This is really a union, discriminated by BaseType!
66 : BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
74 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
76 //===--------------------------------------------------------------------===//
77 /// ISel - X86 specific code to select X86 machine instructions for
78 /// SelectionDAG operations.
80 class ISel : public SelectionDAGISel {
81 /// ContainsFPCode - Every instruction we select that uses or defines a FP
82 /// register should set this to true.
85 /// X86Lowering - This object fully describes how to lower LLVM code to an
86 /// X86-specific SelectionDAG.
87 X86TargetLowering X86Lowering;
89 /// RegPressureMap - This keeps an approximate count of the number of
90 /// registers required to evaluate each node in the graph.
91 std::map<SDNode*, unsigned> RegPressureMap;
93 /// ExprMap - As shared expressions are codegen'd, we keep track of which
94 /// vreg the value is produced in, so we only emit one copy of each compiled
96 std::map<SDOperand, unsigned> ExprMap;
98 /// TheDAG - The DAG being selected during Select* operations.
101 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
102 /// make the right decision when generating code for different targets.
103 const X86Subtarget *Subtarget;
105 const TargetData &TD;
107 /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
110 ISel(TargetMachine &TM) : SelectionDAGISel(X86Lowering),
111 X86Lowering(TM), TD(TM.getTargetData()) {
112 Subtarget = &TM.getSubtarget<X86Subtarget>();
113 X86ScalarSSE = Subtarget->hasSSE2();
116 virtual const char *getPassName() const {
117 return "X86 Pattern Instruction Selection";
120 unsigned getRegPressure(SDOperand O) {
121 return RegPressureMap[O.Val];
123 unsigned ComputeRegPressure(SDOperand O);
125 /// InstructionSelectBasicBlock - This callback is invoked by
126 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
127 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
129 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
131 bool isFoldableLoad(SDOperand Op, SDOperand OtherOp,
132 bool FloatPromoteOk = false);
133 void EmitFoldedLoad(SDOperand Op, X86AddressMode &AM);
134 bool TryToFoldLoadOpStore(SDNode *Node);
135 bool EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg);
136 void EmitCMP(SDOperand LHS, SDOperand RHS, bool isOnlyUse);
137 bool EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain, SDOperand Cond);
138 void EmitSelectCC(SDOperand Cond, SDOperand True, SDOperand False,
139 MVT::ValueType SVT, unsigned RDest);
140 unsigned SelectExpr(SDOperand N);
142 X86AddressMode SelectAddrExprs(const X86ISelAddressMode &IAM);
143 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
144 void SelectAddress(SDOperand N, X86AddressMode &AM);
145 bool EmitPotentialTailCall(SDNode *Node);
146 void EmitFastCCToFastCCTailCall(SDNode *TailCallNode);
147 void Select(SDOperand N);
151 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
152 /// the main function.
153 static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
154 MachineFrameInfo *MFI) {
155 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
156 int CWFrameIdx = MFI->CreateStackObject(2, 2);
157 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
159 // Set the high part to be 64-bit precision.
160 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
161 CWFrameIdx, 1).addImm(2);
163 // Reload the modified control word now.
164 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
167 void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
168 // If this is main, emit special code for main.
169 MachineBasicBlock *BB = MF.begin();
170 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
171 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
175 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
176 /// when it has created a SelectionDAG for us to codegen.
177 void ISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
178 // While we're doing this, keep track of whether we see any FP code for
179 // FP_REG_KILL insertion.
180 ContainsFPCode = false;
181 MachineFunction *MF = BB->getParent();
183 // Scan the PHI nodes that already are inserted into this basic block. If any
184 // of them is a PHI of a floating point value, we need to insert an
186 SSARegMap *RegMap = MF->getSSARegMap();
187 if (BB != MF->begin())
188 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
190 assert(I->getOpcode() == X86::PHI &&
191 "Isn't just PHI nodes?");
192 if (RegMap->getRegClass(I->getOperand(0).getReg()) ==
193 X86::RFPRegisterClass) {
194 ContainsFPCode = true;
199 // Compute the RegPressureMap, which is an approximation for the number of
200 // registers required to compute each node.
201 ComputeRegPressure(DAG.getRoot());
205 // Codegen the basic block.
206 Select(DAG.getRoot());
210 // Finally, look at all of the successors of this block. If any contain a PHI
211 // node of FP type, we need to insert an FP_REG_KILL in this block.
212 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
213 E = BB->succ_end(); SI != E && !ContainsFPCode; ++SI)
214 for (MachineBasicBlock::iterator I = (*SI)->begin(), E = (*SI)->end();
215 I != E && I->getOpcode() == X86::PHI; ++I) {
216 if (RegMap->getRegClass(I->getOperand(0).getReg()) ==
217 X86::RFPRegisterClass) {
218 ContainsFPCode = true;
223 // Final check, check LLVM BB's that are successors to the LLVM BB
224 // corresponding to BB for FP PHI nodes.
225 const BasicBlock *LLVMBB = BB->getBasicBlock();
228 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
229 SI != E && !ContainsFPCode; ++SI)
230 for (BasicBlock::const_iterator II = SI->begin();
231 (PN = dyn_cast<PHINode>(II)); ++II)
232 if (PN->getType()->isFloatingPoint()) {
233 ContainsFPCode = true;
237 // Insert FP_REG_KILL instructions into basic blocks that need them. This
238 // only occurs due to the floating point stackifier not being aggressive
239 // enough to handle arbitrary global stackification.
241 // Currently we insert an FP_REG_KILL instruction into each block that uses or
242 // defines a floating point virtual register.
244 // When the global register allocators (like linear scan) finally update live
245 // variable analysis, we can keep floating point values in registers across
246 // basic blocks. This will be a huge win, but we are waiting on the global
247 // allocators before we can do this.
249 if (ContainsFPCode) {
250 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
254 // Clear state used for selection.
256 RegPressureMap.clear();
260 // ComputeRegPressure - Compute the RegPressureMap, which is an approximation
261 // for the number of registers required to compute each node. This is basically
262 // computing a generalized form of the Sethi-Ullman number for each node.
263 unsigned ISel::ComputeRegPressure(SDOperand O) {
265 unsigned &Result = RegPressureMap[N];
266 if (Result) return Result;
268 // FIXME: Should operations like CALL (which clobber lots o regs) have a
269 // higher fixed cost??
271 if (N->getNumOperands() == 0) {
274 unsigned MaxRegUse = 0;
275 unsigned NumExtraMaxRegUsers = 0;
276 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
278 if (N->getOperand(i).getOpcode() == ISD::Constant)
281 Regs = ComputeRegPressure(N->getOperand(i));
282 if (Regs > MaxRegUse) {
284 NumExtraMaxRegUsers = 0;
285 } else if (Regs == MaxRegUse &&
286 N->getOperand(i).getValueType() != MVT::Other) {
287 ++NumExtraMaxRegUsers;
291 if (O.getOpcode() != ISD::TokenFactor)
292 Result = MaxRegUse+NumExtraMaxRegUsers;
294 Result = MaxRegUse == 1 ? 0 : MaxRegUse-1;
297 //std::cerr << " WEIGHT: " << Result << " "; N->dump(); std::cerr << "\n";
301 /// NodeTransitivelyUsesValue - Return true if N or any of its uses uses Op.
302 /// The DAG cannot have cycles in it, by definition, so the visited set is not
303 /// needed to prevent infinite loops. The DAG CAN, however, have unbounded
304 /// reuse, so it prevents exponential cases.
306 static bool NodeTransitivelyUsesValue(SDOperand N, SDOperand Op,
307 std::set<SDNode*> &Visited) {
308 if (N == Op) return true; // Found it.
309 SDNode *Node = N.Val;
310 if (Node->getNumOperands() == 0 || // Leaf?
311 Node->getNodeDepth() <= Op.getNodeDepth()) return false; // Can't find it?
312 if (!Visited.insert(Node).second) return false; // Already visited?
314 // Recurse for the first N-1 operands.
315 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
316 if (NodeTransitivelyUsesValue(Node->getOperand(i), Op, Visited))
319 // Tail recurse for the last operand.
320 return NodeTransitivelyUsesValue(Node->getOperand(0), Op, Visited);
323 X86AddressMode ISel::SelectAddrExprs(const X86ISelAddressMode &IAM) {
324 X86AddressMode Result;
326 // If we need to emit two register operands, emit the one with the highest
327 // register pressure first.
328 if (IAM.BaseType == X86ISelAddressMode::RegBase &&
329 IAM.Base.Reg.Val && IAM.IndexReg.Val) {
330 bool EmitBaseThenIndex;
331 if (getRegPressure(IAM.Base.Reg) > getRegPressure(IAM.IndexReg)) {
332 std::set<SDNode*> Visited;
333 EmitBaseThenIndex = true;
334 // If Base ends up pointing to Index, we must emit index first. This is
335 // because of the way we fold loads, we may end up doing bad things with
337 if (NodeTransitivelyUsesValue(IAM.Base.Reg, IAM.IndexReg, Visited))
338 EmitBaseThenIndex = false;
340 std::set<SDNode*> Visited;
341 EmitBaseThenIndex = false;
342 // If Base ends up pointing to Index, we must emit index first. This is
343 // because of the way we fold loads, we may end up doing bad things with
345 if (NodeTransitivelyUsesValue(IAM.IndexReg, IAM.Base.Reg, Visited))
346 EmitBaseThenIndex = true;
349 if (EmitBaseThenIndex) {
350 Result.Base.Reg = SelectExpr(IAM.Base.Reg);
351 Result.IndexReg = SelectExpr(IAM.IndexReg);
353 Result.IndexReg = SelectExpr(IAM.IndexReg);
354 Result.Base.Reg = SelectExpr(IAM.Base.Reg);
357 } else if (IAM.BaseType == X86ISelAddressMode::RegBase && IAM.Base.Reg.Val) {
358 Result.Base.Reg = SelectExpr(IAM.Base.Reg);
359 } else if (IAM.IndexReg.Val) {
360 Result.IndexReg = SelectExpr(IAM.IndexReg);
363 switch (IAM.BaseType) {
364 case X86ISelAddressMode::RegBase:
365 Result.BaseType = X86AddressMode::RegBase;
367 case X86ISelAddressMode::FrameIndexBase:
368 Result.BaseType = X86AddressMode::FrameIndexBase;
369 Result.Base.FrameIndex = IAM.Base.FrameIndex;
372 assert(0 && "Unknown base type!");
375 Result.Scale = IAM.Scale;
376 Result.Disp = IAM.Disp;
381 /// SelectAddress - Pattern match the maximal addressing mode for this node and
382 /// emit all of the leaf registers.
383 void ISel::SelectAddress(SDOperand N, X86AddressMode &AM) {
384 X86ISelAddressMode IAM;
385 MatchAddress(N, IAM);
386 AM = SelectAddrExprs(IAM);
389 /// MatchAddress - Add the specified node to the specified addressing mode,
390 /// returning true if it cannot be done. This just pattern matches for the
391 /// addressing mode, it does not cause any code to be emitted. For that, use
393 bool ISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
394 switch (N.getOpcode()) {
396 case ISD::FrameIndex:
397 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
398 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
399 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
403 case ISD::GlobalAddress:
405 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
406 // For Darwin, external and weak symbols are indirect, so we want to load
407 // the value at address GV, not the value of GV itself. This means that
408 // the GlobalAddress must be in the base or index register of the address,
409 // not the GV offset field.
410 if (Subtarget->getIndirectExternAndWeakGlobals() &&
411 (GV->hasWeakLinkage() || GV->isExternal())) {
420 AM.Disp += cast<ConstantSDNode>(N)->getValue();
423 // We might have folded the load into this shift, so don't regen the value
425 if (ExprMap.count(N)) break;
427 if (AM.IndexReg.Val == 0 && AM.Scale == 1)
428 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
429 unsigned Val = CN->getValue();
430 if (Val == 1 || Val == 2 || Val == 3) {
432 SDOperand ShVal = N.Val->getOperand(0);
434 // Okay, we know that we have a scale by now. However, if the scaled
435 // value is an add of something and a constant, we can fold the
436 // constant into the disp field here.
437 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
438 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
439 AM.IndexReg = ShVal.Val->getOperand(0);
440 ConstantSDNode *AddVal =
441 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
442 AM.Disp += AddVal->getValue() << Val;
451 // We might have folded the load into this mul, so don't regen the value if
453 if (ExprMap.count(N)) break;
455 // X*[3,5,9] -> X+X*[2,4,8]
456 if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
457 AM.Base.Reg.Val == 0)
458 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
459 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
460 AM.Scale = unsigned(CN->getValue())-1;
462 SDOperand MulVal = N.Val->getOperand(0);
465 // Okay, we know that we have a scale by now. However, if the scaled
466 // value is an add of something and a constant, we can fold the
467 // constant into the disp field here.
468 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
469 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
470 Reg = MulVal.Val->getOperand(0);
471 ConstantSDNode *AddVal =
472 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
473 AM.Disp += AddVal->getValue() * CN->getValue();
475 Reg = N.Val->getOperand(0);
478 AM.IndexReg = AM.Base.Reg = Reg;
484 // We might have folded the load into this mul, so don't regen the value if
486 if (ExprMap.count(N)) break;
488 X86ISelAddressMode Backup = AM;
489 if (!MatchAddress(N.Val->getOperand(0), AM) &&
490 !MatchAddress(N.Val->getOperand(1), AM))
493 if (!MatchAddress(N.Val->getOperand(1), AM) &&
494 !MatchAddress(N.Val->getOperand(0), AM))
501 // Is the base register already occupied?
502 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
503 // If so, check to see if the scale index register is set.
504 if (AM.IndexReg.Val == 0) {
510 // Otherwise, we cannot select it.
514 // Default, generate it as a register.
515 AM.BaseType = X86ISelAddressMode::RegBase;
520 /// Emit2SetCCsAndLogical - Emit the following sequence of instructions,
521 /// assuming that the temporary registers are in the 8-bit register class.
525 /// DestReg = logicalop Tmp1, Tmp2
527 static void Emit2SetCCsAndLogical(MachineBasicBlock *BB, unsigned SetCC1,
528 unsigned SetCC2, unsigned LogicalOp,
530 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
531 unsigned Tmp1 = RegMap->createVirtualRegister(X86::R8RegisterClass);
532 unsigned Tmp2 = RegMap->createVirtualRegister(X86::R8RegisterClass);
533 BuildMI(BB, SetCC1, 0, Tmp1);
534 BuildMI(BB, SetCC2, 0, Tmp2);
535 BuildMI(BB, LogicalOp, 2, DestReg).addReg(Tmp1).addReg(Tmp2);
538 /// EmitSetCC - Emit the code to set the specified 8-bit register to 1 if the
539 /// condition codes match the specified SetCCOpcode. Note that some conditions
540 /// require multiple instructions to generate the correct value.
541 static void EmitSetCC(MachineBasicBlock *BB, unsigned DestReg,
542 ISD::CondCode SetCCOpcode, bool isFP) {
545 switch (SetCCOpcode) {
546 default: assert(0 && "Illegal integer SetCC!");
547 case ISD::SETEQ: Opc = X86::SETEr; break;
548 case ISD::SETGT: Opc = X86::SETGr; break;
549 case ISD::SETGE: Opc = X86::SETGEr; break;
550 case ISD::SETLT: Opc = X86::SETLr; break;
551 case ISD::SETLE: Opc = X86::SETLEr; break;
552 case ISD::SETNE: Opc = X86::SETNEr; break;
553 case ISD::SETULT: Opc = X86::SETBr; break;
554 case ISD::SETUGT: Opc = X86::SETAr; break;
555 case ISD::SETULE: Opc = X86::SETBEr; break;
556 case ISD::SETUGE: Opc = X86::SETAEr; break;
559 // On a floating point condition, the flags are set as follows:
563 // 1 | 0 | 0 | X == Y
564 // 1 | 1 | 1 | unordered
566 switch (SetCCOpcode) {
567 default: assert(0 && "Invalid FP setcc!");
570 Opc = X86::SETEr; // True if ZF = 1
574 Opc = X86::SETAr; // True if CF = 0 and ZF = 0
578 Opc = X86::SETAEr; // True if CF = 0
582 Opc = X86::SETBr; // True if CF = 1
586 Opc = X86::SETBEr; // True if CF = 1 or ZF = 1
590 Opc = X86::SETNEr; // True if ZF = 0
593 Opc = X86::SETPr; // True if PF = 1
596 Opc = X86::SETNPr; // True if PF = 0
598 case ISD::SETOEQ: // !PF & ZF
599 Emit2SetCCsAndLogical(BB, X86::SETNPr, X86::SETEr, X86::AND8rr, DestReg);
601 case ISD::SETOLT: // !PF & CF
602 Emit2SetCCsAndLogical(BB, X86::SETNPr, X86::SETBr, X86::AND8rr, DestReg);
604 case ISD::SETOLE: // !PF & (CF || ZF)
605 Emit2SetCCsAndLogical(BB, X86::SETNPr, X86::SETBEr, X86::AND8rr, DestReg);
607 case ISD::SETUGT: // PF | (!ZF & !CF)
608 Emit2SetCCsAndLogical(BB, X86::SETPr, X86::SETAr, X86::OR8rr, DestReg);
610 case ISD::SETUGE: // PF | !CF
611 Emit2SetCCsAndLogical(BB, X86::SETPr, X86::SETAEr, X86::OR8rr, DestReg);
613 case ISD::SETUNE: // PF | !ZF
614 Emit2SetCCsAndLogical(BB, X86::SETPr, X86::SETNEr, X86::OR8rr, DestReg);
618 BuildMI(BB, Opc, 0, DestReg);
622 /// EmitBranchCC - Emit code into BB that arranges for control to transfer to
623 /// the Dest block if the Cond condition is true. If we cannot fold this
624 /// condition into the branch, return true.
626 bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain,
628 // FIXME: Evaluate whether it would be good to emit code like (X < Y) | (A >
629 // B) using two conditional branches instead of one condbr, two setcc's, and
631 if ((Cond.getOpcode() == ISD::OR ||
632 Cond.getOpcode() == ISD::AND) && Cond.Val->hasOneUse()) {
633 // And and or set the flags for us, so there is no need to emit a TST of the
634 // result. It is only safe to do this if there is only a single use of the
635 // AND/OR though, otherwise we don't know it will be emitted here.
638 BuildMI(BB, X86::JNE, 1).addMBB(Dest);
642 // Codegen br not C -> JE.
643 if (Cond.getOpcode() == ISD::XOR)
644 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(Cond.Val->getOperand(1)))
645 if (NC->isAllOnesValue()) {
647 if (getRegPressure(Chain) > getRegPressure(Cond)) {
649 CondR = SelectExpr(Cond.Val->getOperand(0));
651 CondR = SelectExpr(Cond.Val->getOperand(0));
654 BuildMI(BB, X86::TEST8rr, 2).addReg(CondR).addReg(CondR);
655 BuildMI(BB, X86::JE, 1).addMBB(Dest);
659 if (Cond.getOpcode() != ISD::SETCC)
660 return true; // Can only handle simple setcc's so far.
661 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
665 // Handle integer conditions first.
666 if (MVT::isInteger(Cond.getOperand(0).getValueType())) {
668 default: assert(0 && "Illegal integer SetCC!");
669 case ISD::SETEQ: Opc = X86::JE; break;
670 case ISD::SETGT: Opc = X86::JG; break;
671 case ISD::SETGE: Opc = X86::JGE; break;
672 case ISD::SETLT: Opc = X86::JL; break;
673 case ISD::SETLE: Opc = X86::JLE; break;
674 case ISD::SETNE: Opc = X86::JNE; break;
675 case ISD::SETULT: Opc = X86::JB; break;
676 case ISD::SETUGT: Opc = X86::JA; break;
677 case ISD::SETULE: Opc = X86::JBE; break;
678 case ISD::SETUGE: Opc = X86::JAE; break;
681 EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.hasOneUse());
682 BuildMI(BB, Opc, 1).addMBB(Dest);
686 unsigned Opc2 = 0; // Second branch if needed.
688 // On a floating point condition, the flags are set as follows:
692 // 1 | 0 | 0 | X == Y
693 // 1 | 1 | 1 | unordered
696 default: assert(0 && "Invalid FP setcc!");
698 case ISD::SETEQ: Opc = X86::JE; break; // True if ZF = 1
700 case ISD::SETGT: Opc = X86::JA; break; // True if CF = 0 and ZF = 0
702 case ISD::SETGE: Opc = X86::JAE; break; // True if CF = 0
704 case ISD::SETLT: Opc = X86::JB; break; // True if CF = 1
706 case ISD::SETLE: Opc = X86::JBE; break; // True if CF = 1 or ZF = 1
708 case ISD::SETNE: Opc = X86::JNE; break; // True if ZF = 0
709 case ISD::SETUO: Opc = X86::JP; break; // True if PF = 1
710 case ISD::SETO: Opc = X86::JNP; break; // True if PF = 0
711 case ISD::SETUGT: // PF = 1 | (ZF = 0 & CF = 0)
712 Opc = X86::JA; // ZF = 0 & CF = 0
713 Opc2 = X86::JP; // PF = 1
715 case ISD::SETUGE: // PF = 1 | CF = 0
716 Opc = X86::JAE; // CF = 0
717 Opc2 = X86::JP; // PF = 1
719 case ISD::SETUNE: // PF = 1 | ZF = 0
720 Opc = X86::JNE; // ZF = 0
721 Opc2 = X86::JP; // PF = 1
723 case ISD::SETOEQ: // PF = 0 & ZF = 1
726 return true; // FIXME: Emit more efficient code for this branch.
727 case ISD::SETOLT: // PF = 0 & CF = 1
730 return true; // FIXME: Emit more efficient code for this branch.
731 case ISD::SETOLE: // PF = 0 & (CF = 1 || ZF = 1)
734 return true; // FIXME: Emit more efficient code for this branch.
738 EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.hasOneUse());
739 BuildMI(BB, Opc, 1).addMBB(Dest);
741 BuildMI(BB, Opc2, 1).addMBB(Dest);
745 /// EmitSelectCC - Emit code into BB that performs a select operation between
746 /// the two registers RTrue and RFalse, generating a result into RDest.
748 void ISel::EmitSelectCC(SDOperand Cond, SDOperand True, SDOperand False,
749 MVT::ValueType SVT, unsigned RDest) {
750 unsigned RTrue, RFalse;
752 EQ, NE, LT, LE, GT, GE, B, BE, A, AE, P, NP,
754 } CondCode = NOT_SET;
756 static const unsigned CMOVTAB16[] = {
757 X86::CMOVE16rr, X86::CMOVNE16rr, X86::CMOVL16rr, X86::CMOVLE16rr,
758 X86::CMOVG16rr, X86::CMOVGE16rr, X86::CMOVB16rr, X86::CMOVBE16rr,
759 X86::CMOVA16rr, X86::CMOVAE16rr, X86::CMOVP16rr, X86::CMOVNP16rr,
761 static const unsigned CMOVTAB32[] = {
762 X86::CMOVE32rr, X86::CMOVNE32rr, X86::CMOVL32rr, X86::CMOVLE32rr,
763 X86::CMOVG32rr, X86::CMOVGE32rr, X86::CMOVB32rr, X86::CMOVBE32rr,
764 X86::CMOVA32rr, X86::CMOVAE32rr, X86::CMOVP32rr, X86::CMOVNP32rr,
766 static const unsigned CMOVTABFP[] = {
767 X86::FpCMOVE, X86::FpCMOVNE, /*missing*/0, /*missing*/0,
768 /*missing*/0, /*missing*/ 0, X86::FpCMOVB, X86::FpCMOVBE,
769 X86::FpCMOVNBE,X86::FpCMOVNB, X86::FpCMOVP, X86::FpCMOVNP
771 static const int SSE_CMOVTAB[] = {
772 /*CMPEQ*/ 0, /*CMPNEQ*/ 4, /*missing*/ 0, /*missing*/ 0,
773 /*missing*/ 0, /*missing*/ 0, /*CMPLT*/ 1, /*CMPLE*/ 2,
774 /*CMPNLE*/ 6, /*CMPNLT*/ 5, /*CMPUNORD*/ 3, /*CMPORD*/ 7
777 if (Cond.getOpcode() == ISD::SETCC) {
778 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
779 if (MVT::isInteger(Cond.getOperand(0).getValueType())) {
781 default: assert(0 && "Unknown integer comparison!");
782 case ISD::SETEQ: CondCode = EQ; break;
783 case ISD::SETGT: CondCode = GT; break;
784 case ISD::SETGE: CondCode = GE; break;
785 case ISD::SETLT: CondCode = LT; break;
786 case ISD::SETLE: CondCode = LE; break;
787 case ISD::SETNE: CondCode = NE; break;
788 case ISD::SETULT: CondCode = B; break;
789 case ISD::SETUGT: CondCode = A; break;
790 case ISD::SETULE: CondCode = BE; break;
791 case ISD::SETUGE: CondCode = AE; break;
794 // On a floating point condition, the flags are set as follows:
798 // 1 | 0 | 0 | X == Y
799 // 1 | 1 | 1 | unordered
802 default: assert(0 && "Unknown FP comparison!");
804 case ISD::SETEQ: CondCode = EQ; break; // True if ZF = 1
806 case ISD::SETGT: CondCode = A; break; // True if CF = 0 and ZF = 0
808 case ISD::SETGE: CondCode = AE; break; // True if CF = 0
810 case ISD::SETLT: CondCode = B; break; // True if CF = 1
812 case ISD::SETLE: CondCode = BE; break; // True if CF = 1 or ZF = 1
814 case ISD::SETNE: CondCode = NE; break; // True if ZF = 0
815 case ISD::SETUO: CondCode = P; break; // True if PF = 1
816 case ISD::SETO: CondCode = NP; break; // True if PF = 0
817 case ISD::SETUGT: // PF = 1 | (ZF = 0 & CF = 0)
818 case ISD::SETUGE: // PF = 1 | CF = 0
819 case ISD::SETUNE: // PF = 1 | ZF = 0
820 case ISD::SETOEQ: // PF = 0 & ZF = 1
821 case ISD::SETOLT: // PF = 0 & CF = 1
822 case ISD::SETOLE: // PF = 0 & (CF = 1 || ZF = 1)
823 // We cannot emit this comparison as a single cmov.
829 // There's no SSE equivalent of FCMOVE. For cases where we set a condition
830 // code above and one of the results of the select is +0.0, then we can fake
831 // it up through a clever AND with mask. Otherwise, we will fall through to
832 // the code below that will use a PHI node to select the right value.
833 if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
834 if (Cond.getOperand(0).getValueType() == SVT &&
835 NOT_SET != CondCode) {
836 ConstantFPSDNode *CT = dyn_cast<ConstantFPSDNode>(True);
837 ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(False);
838 bool TrueZero = CT && CT->isExactlyValue(0.0);
839 bool FalseZero = CF && CF->isExactlyValue(0.0);
840 if (TrueZero || FalseZero) {
841 SDOperand LHS = Cond.getOperand(0);
842 SDOperand RHS = Cond.getOperand(1);
844 // Select the two halves of the condition
846 if (getRegPressure(LHS) > getRegPressure(RHS)) {
847 RLHS = SelectExpr(LHS);
848 RRHS = SelectExpr(RHS);
850 RRHS = SelectExpr(RHS);
851 RLHS = SelectExpr(LHS);
854 // Emit the comparison and generate a mask from it
855 unsigned MaskReg = MakeReg(SVT);
856 unsigned Opc = (SVT == MVT::f32) ? X86::CMPSSrr : X86::CMPSDrr;
857 BuildMI(BB, Opc, 3, MaskReg).addReg(RLHS).addReg(RRHS)
858 .addImm(SSE_CMOVTAB[CondCode]);
861 RFalse = SelectExpr(False);
862 Opc = (SVT == MVT::f32) ? X86::ANDNPSrr : X86::ANDNPDrr;
863 BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RFalse);
865 RTrue = SelectExpr(True);
866 Opc = (SVT == MVT::f32) ? X86::ANDPSrr : X86::ANDPDrr;
867 BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RTrue);
875 // Select the true and false values for use in both the SSE PHI case, and the
876 // integer or x87 cmov cases below.
877 if (getRegPressure(True) > getRegPressure(False)) {
878 RTrue = SelectExpr(True);
879 RFalse = SelectExpr(False);
881 RFalse = SelectExpr(False);
882 RTrue = SelectExpr(True);
885 // Since there's no SSE equivalent of FCMOVE, and we couldn't generate an
886 // AND with mask, we'll have to do the normal RISC thing and generate a PHI
887 // node to select between the true and false values.
888 if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
889 // FIXME: emit a direct compare and branch rather than setting a cond reg
891 unsigned CondReg = SelectExpr(Cond);
892 BuildMI(BB, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
894 // Create an iterator with which to insert the MBB for copying the false
895 // value and the MBB to hold the PHI instruction for this SetCC.
896 MachineBasicBlock *thisMBB = BB;
897 const BasicBlock *LLVM_BB = BB->getBasicBlock();
898 ilist<MachineBasicBlock>::iterator It = BB;
906 // fallthrough --> copy0MBB
907 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
908 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
909 BuildMI(BB, X86::JNE, 1).addMBB(sinkMBB);
910 MachineFunction *F = BB->getParent();
911 F->getBasicBlockList().insert(It, copy0MBB);
912 F->getBasicBlockList().insert(It, sinkMBB);
913 // Update machine-CFG edges
914 BB->addSuccessor(copy0MBB);
915 BB->addSuccessor(sinkMBB);
919 // # fallthrough to sinkMBB
921 // Update machine-CFG edges
922 BB->addSuccessor(sinkMBB);
925 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
928 BuildMI(BB, X86::PHI, 4, RDest).addReg(RFalse)
929 .addMBB(copy0MBB).addReg(RTrue).addMBB(thisMBB);
934 if (CondCode != NOT_SET) {
936 default: assert(0 && "Cannot select this type!");
937 case MVT::i16: Opc = CMOVTAB16[CondCode]; break;
938 case MVT::i32: Opc = CMOVTAB32[CondCode]; break;
939 case MVT::f64: Opc = CMOVTABFP[CondCode]; break;
943 // Finally, if we weren't able to fold this, just emit the condition and test
945 if (CondCode == NOT_SET || Opc == 0) {
946 // Get the condition into the zero flag.
947 unsigned CondReg = SelectExpr(Cond);
948 BuildMI(BB, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
951 default: assert(0 && "Cannot select this type!");
952 case MVT::i16: Opc = X86::CMOVE16rr; break;
953 case MVT::i32: Opc = X86::CMOVE32rr; break;
954 case MVT::f64: Opc = X86::FpCMOVE; break;
957 // FIXME: CMP R, 0 -> TEST R, R
958 EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.Val->hasOneUse());
959 std::swap(RTrue, RFalse);
961 BuildMI(BB, Opc, 2, RDest).addReg(RTrue).addReg(RFalse);
964 void ISel::EmitCMP(SDOperand LHS, SDOperand RHS, bool HasOneUse) {
966 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS)) {
968 if (HasOneUse && isFoldableLoad(LHS, RHS)) {
969 switch (RHS.getValueType()) {
972 case MVT::i8: Opc = X86::CMP8mi; break;
973 case MVT::i16: Opc = X86::CMP16mi; break;
974 case MVT::i32: Opc = X86::CMP32mi; break;
978 EmitFoldedLoad(LHS, AM);
979 addFullAddress(BuildMI(BB, Opc, 5), AM).addImm(CN->getValue());
984 switch (RHS.getValueType()) {
987 case MVT::i8: Opc = X86::CMP8ri; break;
988 case MVT::i16: Opc = X86::CMP16ri; break;
989 case MVT::i32: Opc = X86::CMP32ri; break;
992 unsigned Tmp1 = SelectExpr(LHS);
993 BuildMI(BB, Opc, 2).addReg(Tmp1).addImm(CN->getValue());
996 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(RHS)) {
997 if (!X86ScalarSSE && (CN->isExactlyValue(+0.0) ||
998 CN->isExactlyValue(-0.0))) {
999 unsigned Reg = SelectExpr(LHS);
1000 BuildMI(BB, X86::FpTST, 1).addReg(Reg);
1001 BuildMI(BB, X86::FNSTSW8r, 0);
1002 BuildMI(BB, X86::SAHF, 1);
1008 if (HasOneUse && isFoldableLoad(LHS, RHS)) {
1009 switch (RHS.getValueType()) {
1012 case MVT::i8: Opc = X86::CMP8mr; break;
1013 case MVT::i16: Opc = X86::CMP16mr; break;
1014 case MVT::i32: Opc = X86::CMP32mr; break;
1018 EmitFoldedLoad(LHS, AM);
1019 unsigned Reg = SelectExpr(RHS);
1020 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(Reg);
1025 switch (LHS.getValueType()) {
1026 default: assert(0 && "Cannot compare this value!");
1028 case MVT::i8: Opc = X86::CMP8rr; break;
1029 case MVT::i16: Opc = X86::CMP16rr; break;
1030 case MVT::i32: Opc = X86::CMP32rr; break;
1031 case MVT::f32: Opc = X86::UCOMISSrr; break;
1032 case MVT::f64: Opc = X86ScalarSSE ? X86::UCOMISDrr : X86::FpUCOMIr; break;
1034 unsigned Tmp1, Tmp2;
1035 if (getRegPressure(LHS) > getRegPressure(RHS)) {
1036 Tmp1 = SelectExpr(LHS);
1037 Tmp2 = SelectExpr(RHS);
1039 Tmp2 = SelectExpr(RHS);
1040 Tmp1 = SelectExpr(LHS);
1042 BuildMI(BB, Opc, 2).addReg(Tmp1).addReg(Tmp2);
1045 /// isFoldableLoad - Return true if this is a load instruction that can safely
1046 /// be folded into an operation that uses it.
1047 bool ISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp, bool FloatPromoteOk){
1048 if (Op.getOpcode() == ISD::LOAD) {
1049 // FIXME: currently can't fold constant pool indexes.
1050 if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
1052 } else if (FloatPromoteOk && Op.getOpcode() == ISD::EXTLOAD &&
1053 cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::f32) {
1054 // FIXME: currently can't fold constant pool indexes.
1055 if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
1061 // If this load has already been emitted, we clearly can't fold it.
1062 assert(Op.ResNo == 0 && "Not a use of the value of the load?");
1063 if (ExprMap.count(Op.getValue(1))) return false;
1064 assert(!ExprMap.count(Op.getValue(0)) && "Value in map but not token chain?");
1065 assert(!ExprMap.count(Op.getValue(1))&&"Token lowered but value not in map?");
1067 // If there is not just one use of its value, we cannot fold.
1068 if (!Op.Val->hasNUsesOfValue(1, 0)) return false;
1070 // Finally, we cannot fold the load into the operation if this would induce a
1071 // cycle into the resultant dag. To check for this, see if OtherOp (the other
1072 // operand of the operation we are folding the load into) can possible use the
1073 // chain node defined by the load.
1074 if (OtherOp.Val && !Op.Val->hasNUsesOfValue(0, 1)) { // Has uses of chain?
1075 std::set<SDNode*> Visited;
1076 if (NodeTransitivelyUsesValue(OtherOp, Op.getValue(1), Visited))
1083 /// EmitFoldedLoad - Ensure that the arguments of the load are code generated,
1084 /// and compute the address being loaded into AM.
1085 void ISel::EmitFoldedLoad(SDOperand Op, X86AddressMode &AM) {
1086 SDOperand Chain = Op.getOperand(0);
1087 SDOperand Address = Op.getOperand(1);
1089 if (getRegPressure(Chain) > getRegPressure(Address)) {
1091 SelectAddress(Address, AM);
1093 SelectAddress(Address, AM);
1097 // The chain for this load is now lowered.
1098 assert(ExprMap.count(SDOperand(Op.Val, 1)) == 0 &&
1099 "Load emitted more than once?");
1100 if (!ExprMap.insert(std::make_pair(Op.getValue(1), 1)).second)
1101 assert(0 && "Load emitted more than once!");
1104 // EmitOrOpOp - Pattern match the expression (Op1|Op2), where we know that op1
1105 // and op2 are i8/i16/i32 values with one use each (the or). If we can form a
1106 // SHLD or SHRD, emit the instruction (generating the value into DestReg) and
1108 bool ISel::EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
1109 if (Op1.getOpcode() == ISD::SHL && Op2.getOpcode() == ISD::SRL) {
1111 } else if (Op2.getOpcode() == ISD::SHL && Op1.getOpcode() == ISD::SRL) {
1112 std::swap(Op1, Op2); // Op1 is the SHL now.
1114 return false; // No match
1117 SDOperand ShlVal = Op1.getOperand(0);
1118 SDOperand ShlAmt = Op1.getOperand(1);
1119 SDOperand ShrVal = Op2.getOperand(0);
1120 SDOperand ShrAmt = Op2.getOperand(1);
1122 unsigned RegSize = MVT::getSizeInBits(Op1.getValueType());
1124 // Find out if ShrAmt = 32-ShlAmt or ShlAmt = 32-ShrAmt.
1125 if (ShlAmt.getOpcode() == ISD::SUB && ShlAmt.getOperand(1) == ShrAmt)
1126 if (ConstantSDNode *SubCST = dyn_cast<ConstantSDNode>(ShlAmt.getOperand(0)))
1127 if (SubCST->getValue() == RegSize) {
1128 // (A >> ShrAmt) | (A << (32-ShrAmt)) ==> ROR A, ShrAmt
1129 // (A >> ShrAmt) | (B << (32-ShrAmt)) ==> SHRD A, B, ShrAmt
1130 if (ShrVal == ShlVal) {
1131 unsigned Reg, ShAmt;
1132 if (getRegPressure(ShrVal) > getRegPressure(ShrAmt)) {
1133 Reg = SelectExpr(ShrVal);
1134 ShAmt = SelectExpr(ShrAmt);
1136 ShAmt = SelectExpr(ShrAmt);
1137 Reg = SelectExpr(ShrVal);
1139 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1140 unsigned Opc = RegSize == 8 ? X86::ROR8rCL :
1141 (RegSize == 16 ? X86::ROR16rCL : X86::ROR32rCL);
1142 BuildMI(BB, Opc, 1, DestReg).addReg(Reg);
1144 } else if (RegSize != 8) {
1145 unsigned AReg, BReg;
1146 if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
1147 BReg = SelectExpr(ShlVal);
1148 AReg = SelectExpr(ShrVal);
1150 AReg = SelectExpr(ShrVal);
1151 BReg = SelectExpr(ShlVal);
1153 unsigned ShAmt = SelectExpr(ShrAmt);
1154 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1155 unsigned Opc = RegSize == 16 ? X86::SHRD16rrCL : X86::SHRD32rrCL;
1156 BuildMI(BB, Opc, 2, DestReg).addReg(AReg).addReg(BReg);
1161 if (ShrAmt.getOpcode() == ISD::SUB && ShrAmt.getOperand(1) == ShlAmt)
1162 if (ConstantSDNode *SubCST = dyn_cast<ConstantSDNode>(ShrAmt.getOperand(0)))
1163 if (SubCST->getValue() == RegSize) {
1164 // (A << ShlAmt) | (A >> (32-ShlAmt)) ==> ROL A, ShrAmt
1165 // (A << ShlAmt) | (B >> (32-ShlAmt)) ==> SHLD A, B, ShrAmt
1166 if (ShrVal == ShlVal) {
1167 unsigned Reg, ShAmt;
1168 if (getRegPressure(ShrVal) > getRegPressure(ShlAmt)) {
1169 Reg = SelectExpr(ShrVal);
1170 ShAmt = SelectExpr(ShlAmt);
1172 ShAmt = SelectExpr(ShlAmt);
1173 Reg = SelectExpr(ShrVal);
1175 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1176 unsigned Opc = RegSize == 8 ? X86::ROL8rCL :
1177 (RegSize == 16 ? X86::ROL16rCL : X86::ROL32rCL);
1178 BuildMI(BB, Opc, 1, DestReg).addReg(Reg);
1180 } else if (RegSize != 8) {
1181 unsigned AReg, BReg;
1182 if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
1183 AReg = SelectExpr(ShlVal);
1184 BReg = SelectExpr(ShrVal);
1186 BReg = SelectExpr(ShrVal);
1187 AReg = SelectExpr(ShlVal);
1189 unsigned ShAmt = SelectExpr(ShlAmt);
1190 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1191 unsigned Opc = RegSize == 16 ? X86::SHLD16rrCL : X86::SHLD32rrCL;
1192 BuildMI(BB, Opc, 2, DestReg).addReg(AReg).addReg(BReg);
1197 if (ConstantSDNode *ShrCst = dyn_cast<ConstantSDNode>(ShrAmt))
1198 if (ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(ShlAmt))
1199 if (ShrCst->getValue() < RegSize && ShlCst->getValue() < RegSize)
1200 if (ShrCst->getValue() == RegSize-ShlCst->getValue()) {
1201 // (A >> 5) | (A << 27) --> ROR A, 5
1202 // (A >> 5) | (B << 27) --> SHRD A, B, 5
1203 if (ShrVal == ShlVal) {
1204 unsigned Reg = SelectExpr(ShrVal);
1205 unsigned Opc = RegSize == 8 ? X86::ROR8ri :
1206 (RegSize == 16 ? X86::ROR16ri : X86::ROR32ri);
1207 BuildMI(BB, Opc, 2, DestReg).addReg(Reg).addImm(ShrCst->getValue());
1209 } else if (RegSize != 8) {
1210 unsigned AReg, BReg;
1211 if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
1212 BReg = SelectExpr(ShlVal);
1213 AReg = SelectExpr(ShrVal);
1215 AReg = SelectExpr(ShrVal);
1216 BReg = SelectExpr(ShlVal);
1218 unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8;
1219 BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)
1220 .addImm(ShrCst->getValue());
1228 unsigned ISel::SelectExpr(SDOperand N) {
1230 unsigned Tmp1 = 0, Tmp2 = 0, Tmp3 = 0, Opc = 0;
1231 SDNode *Node = N.Val;
1234 if (Node->getOpcode() == ISD::CopyFromReg ||
1235 Node->getOpcode() == ISD::Register) {
1236 unsigned Reg = (Node->getOpcode() == ISD::CopyFromReg) ?
1237 cast<RegisterSDNode>(Node->getOperand(1))->getReg() :
1238 cast<RegisterSDNode>(Node)->getReg();
1239 // Just use the specified register as our input if we can.
1240 if (Node->getOpcode() == ISD::Register ||
1241 MRegisterInfo::isVirtualRegister(Reg))
1245 unsigned &Reg = ExprMap[N];
1246 if (Reg) return Reg;
1248 switch (N.getOpcode()) {
1250 Reg = Result = (N.getValueType() != MVT::Other) ?
1251 MakeReg(N.getValueType()) : 1;
1253 case X86ISD::TAILCALL:
1255 // If this is a call instruction, make sure to prepare ALL of the result
1256 // values as well as the chain.
1257 ExprMap[N.getValue(0)] = 1;
1258 if (Node->getNumValues() > 1) {
1259 Result = MakeReg(Node->getValueType(1));
1260 ExprMap[N.getValue(1)] = Result;
1261 for (unsigned i = 2, e = Node->getNumValues(); i != e; ++i)
1262 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1267 case ISD::ADD_PARTS:
1268 case ISD::SUB_PARTS:
1269 case ISD::SHL_PARTS:
1270 case ISD::SRL_PARTS:
1271 case ISD::SRA_PARTS:
1272 Result = MakeReg(Node->getValueType(0));
1273 ExprMap[N.getValue(0)] = Result;
1274 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
1275 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1279 switch (N.getOpcode()) {
1282 assert(0 && "Node not handled!\n");
1283 case ISD::FP_EXTEND:
1284 assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
1285 Tmp1 = SelectExpr(N.getOperand(0));
1286 BuildMI(BB, X86::CVTSS2SDrr, 1, Result).addReg(Tmp1);
1289 assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
1290 Tmp1 = SelectExpr(N.getOperand(0));
1291 BuildMI(BB, X86::CVTSD2SSrr, 1, Result).addReg(Tmp1);
1293 case ISD::CopyFromReg:
1294 Select(N.getOperand(0));
1296 Reg = Result = ExprMap[N.getValue(0)] =
1297 MakeReg(N.getValue(0).getValueType());
1299 Tmp1 = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1300 switch (Node->getValueType(0)) {
1301 default: assert(0 && "Cannot CopyFromReg this!");
1304 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(Tmp1);
1307 BuildMI(BB, X86::MOV16rr, 1, Result).addReg(Tmp1);
1310 BuildMI(BB, X86::MOV32rr, 1, Result).addReg(Tmp1);
1314 case ISD::FrameIndex:
1315 Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
1316 addFrameReference(BuildMI(BB, X86::LEA32r, 4, Result), (int)Tmp1);
1318 case ISD::ConstantPool: {
1319 Constant *C = cast<ConstantPoolSDNode>(N)->get();
1320 unsigned Align = cast<ConstantPoolSDNode>(N)->getAlignment();
1322 Align = C->getType() == Type::DoubleTy ? 3 :
1323 TD.getTypeAlignmentShift(C->getType());
1325 Tmp1 = BB->getParent()->getConstantPool()->getConstantPoolIndex(C, Align);
1326 addConstantPoolReference(BuildMI(BB, X86::LEA32r, 4, Result), Tmp1);
1329 case ISD::ConstantFP:
1331 assert(cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) &&
1332 "SSE only supports +0.0");
1333 Opc = (N.getValueType() == MVT::f32) ? X86::FLD0SS : X86::FLD0SD;
1334 BuildMI(BB, Opc, 0, Result);
1337 ContainsFPCode = true;
1338 Tmp1 = Result; // Intermediate Register
1339 if (cast<ConstantFPSDNode>(N)->getValue() < 0.0 ||
1340 cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
1341 Tmp1 = MakeReg(MVT::f64);
1343 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) ||
1344 cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
1345 BuildMI(BB, X86::FpLD0, 0, Tmp1);
1346 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0) ||
1347 cast<ConstantFPSDNode>(N)->isExactlyValue(-1.0))
1348 BuildMI(BB, X86::FpLD1, 0, Tmp1);
1350 assert(0 && "Unexpected constant!");
1352 BuildMI(BB, X86::FpCHS, 1, Result).addReg(Tmp1);
1355 switch (N.getValueType()) {
1356 default: assert(0 && "Cannot use constants of this type!");
1358 case MVT::i8: Opc = X86::MOV8ri; break;
1359 case MVT::i16: Opc = X86::MOV16ri; break;
1360 case MVT::i32: Opc = X86::MOV32ri; break;
1362 BuildMI(BB, Opc, 1,Result).addImm(cast<ConstantSDNode>(N)->getValue());
1365 BuildMI(BB, X86::IMPLICIT_DEF, 0, Result);
1367 case ISD::GlobalAddress: {
1368 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
1369 // For Darwin, external and weak symbols are indirect, so we want to load
1370 // the value at address GV, not the value of GV itself.
1371 if (Subtarget->getIndirectExternAndWeakGlobals() &&
1372 (GV->hasWeakLinkage() || GV->isExternal())) {
1373 BuildMI(BB, X86::MOV32rm, 4, Result).addReg(0).addZImm(1).addReg(0)
1374 .addGlobalAddress(GV, false, 0);
1376 BuildMI(BB, X86::MOV32ri, 1, Result).addGlobalAddress(GV);
1380 case ISD::ExternalSymbol: {
1381 const char *Sym = cast<ExternalSymbolSDNode>(N)->getSymbol();
1382 BuildMI(BB, X86::MOV32ri, 1, Result).addExternalSymbol(Sym);
1385 case ISD::ANY_EXTEND: // treat any extend like zext
1386 case ISD::ZERO_EXTEND: {
1387 int DestIs16 = N.getValueType() == MVT::i16;
1388 int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
1390 // FIXME: This hack is here for zero extension casts from bool to i8. This
1391 // would not be needed if bools were promoted by Legalize.
1392 if (N.getValueType() == MVT::i8) {
1393 Tmp1 = SelectExpr(N.getOperand(0));
1394 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(Tmp1);
1398 if (isFoldableLoad(N.getOperand(0), SDOperand())) {
1399 static const unsigned Opc[3] = {
1400 X86::MOVZX32rm8, X86::MOVZX32rm16, X86::MOVZX16rm8
1404 EmitFoldedLoad(N.getOperand(0), AM);
1405 addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
1410 static const unsigned Opc[3] = {
1411 X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOVZX16rr8
1413 Tmp1 = SelectExpr(N.getOperand(0));
1414 BuildMI(BB, Opc[SrcIs16+DestIs16*2], 1, Result).addReg(Tmp1);
1417 case ISD::SIGN_EXTEND: {
1418 int DestIs16 = N.getValueType() == MVT::i16;
1419 int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
1421 // FIXME: Legalize should promote bools to i8!
1422 assert(N.getOperand(0).getValueType() != MVT::i1 &&
1423 "Sign extend from bool not implemented!");
1425 if (isFoldableLoad(N.getOperand(0), SDOperand())) {
1426 static const unsigned Opc[3] = {
1427 X86::MOVSX32rm8, X86::MOVSX32rm16, X86::MOVSX16rm8
1431 EmitFoldedLoad(N.getOperand(0), AM);
1432 addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
1436 static const unsigned Opc[3] = {
1437 X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOVSX16rr8
1439 Tmp1 = SelectExpr(N.getOperand(0));
1440 BuildMI(BB, Opc[SrcIs16+DestIs16*2], 1, Result).addReg(Tmp1);
1444 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by
1445 // a move out of AX or AL.
1446 switch (N.getOperand(0).getValueType()) {
1447 default: assert(0 && "Unknown truncate!");
1448 case MVT::i8: Tmp2 = X86::AL; Opc = X86::MOV8rr; break;
1449 case MVT::i16: Tmp2 = X86::AX; Opc = X86::MOV16rr; break;
1450 case MVT::i32: Tmp2 = X86::EAX; Opc = X86::MOV32rr; break;
1452 Tmp1 = SelectExpr(N.getOperand(0));
1453 BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
1455 switch (N.getValueType()) {
1456 default: assert(0 && "Unknown truncate!");
1458 case MVT::i8: Tmp2 = X86::AL; Opc = X86::MOV8rr; break;
1459 case MVT::i16: Tmp2 = X86::AX; Opc = X86::MOV16rr; break;
1461 BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
1464 case ISD::SINT_TO_FP: {
1465 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1466 unsigned PromoteOpcode = 0;
1468 // We can handle any sint to fp with the direct sse conversion instructions.
1470 Opc = (N.getValueType() == MVT::f64) ? X86::CVTSI2SDrr : X86::CVTSI2SSrr;
1471 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1475 ContainsFPCode = true;
1477 // Spill the integer to memory and reload it from there.
1478 MVT::ValueType SrcTy = N.getOperand(0).getValueType();
1479 unsigned Size = MVT::getSizeInBits(SrcTy)/8;
1480 MachineFunction *F = BB->getParent();
1481 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
1485 addFrameReference(BuildMI(BB, X86::MOV32mr, 5), FrameIdx).addReg(Tmp1);
1486 addFrameReference(BuildMI(BB, X86::FpILD32m, 5, Result), FrameIdx);
1489 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), FrameIdx).addReg(Tmp1);
1490 addFrameReference(BuildMI(BB, X86::FpILD16m, 5, Result), FrameIdx);
1492 default: break; // No promotion required.
1496 case ISD::FP_TO_SINT:
1497 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1499 // If the target supports SSE2 and is performing FP operations in SSE regs
1500 // instead of the FP stack, then we can use the efficient CVTSS2SI and
1501 // CVTSD2SI instructions.
1502 assert(X86ScalarSSE);
1503 if (MVT::f32 == N.getOperand(0).getValueType()) {
1504 BuildMI(BB, X86::CVTTSS2SIrr, 1, Result).addReg(Tmp1);
1505 } else if (MVT::f64 == N.getOperand(0).getValueType()) {
1506 BuildMI(BB, X86::CVTTSD2SIrr, 1, Result).addReg(Tmp1);
1508 assert(0 && "Not an f32 or f64?");
1515 Op0 = N.getOperand(0);
1516 Op1 = N.getOperand(1);
1518 if (isFoldableLoad(Op0, Op1, true)) {
1519 std::swap(Op0, Op1);
1523 if (isFoldableLoad(Op1, Op0, true)) {
1525 switch (N.getValueType()) {
1526 default: assert(0 && "Cannot add this type!");
1528 case MVT::i8: Opc = X86::ADD8rm; break;
1529 case MVT::i16: Opc = X86::ADD16rm; break;
1530 case MVT::i32: Opc = X86::ADD32rm; break;
1531 case MVT::f32: Opc = X86::ADDSSrm; break;
1533 // For F64, handle promoted load operations (from F32) as well!
1535 assert(Op1.getOpcode() == ISD::LOAD && "SSE load not promoted");
1538 Opc = Op1.getOpcode() == ISD::LOAD ? X86::FpADD64m : X86::FpADD32m;
1543 EmitFoldedLoad(Op1, AM);
1544 Tmp1 = SelectExpr(Op0);
1545 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
1549 // See if we can codegen this as an LEA to fold operations together.
1550 if (N.getValueType() == MVT::i32) {
1552 X86ISelAddressMode AM;
1553 MatchAddress(N, AM);
1554 ExprMap[N] = Result;
1556 // If this is not just an add, emit the LEA. For a simple add (like
1557 // reg+reg or reg+imm), we just emit an add. It might be a good idea to
1558 // leave this as LEA, then peephole it to 'ADD' after two address elim
1560 if (AM.Scale != 1 || AM.BaseType == X86ISelAddressMode::FrameIndexBase||
1561 AM.GV || (AM.Base.Reg.Val && AM.IndexReg.Val && AM.Disp)) {
1562 X86AddressMode XAM = SelectAddrExprs(AM);
1563 addFullAddress(BuildMI(BB, X86::LEA32r, 4, Result), XAM);
1568 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
1570 if (CN->getValue() == 1) { // add X, 1 -> inc X
1571 switch (N.getValueType()) {
1572 default: assert(0 && "Cannot integer add this type!");
1573 case MVT::i8: Opc = X86::INC8r; break;
1574 case MVT::i16: Opc = X86::INC16r; break;
1575 case MVT::i32: Opc = X86::INC32r; break;
1577 } else if (CN->isAllOnesValue()) { // add X, -1 -> dec X
1578 switch (N.getValueType()) {
1579 default: assert(0 && "Cannot integer add this type!");
1580 case MVT::i8: Opc = X86::DEC8r; break;
1581 case MVT::i16: Opc = X86::DEC16r; break;
1582 case MVT::i32: Opc = X86::DEC32r; break;
1587 Tmp1 = SelectExpr(Op0);
1588 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1592 switch (N.getValueType()) {
1593 default: assert(0 && "Cannot add this type!");
1594 case MVT::i8: Opc = X86::ADD8ri; break;
1595 case MVT::i16: Opc = X86::ADD16ri; break;
1596 case MVT::i32: Opc = X86::ADD32ri; break;
1599 Tmp1 = SelectExpr(Op0);
1600 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
1605 switch (N.getValueType()) {
1606 default: assert(0 && "Cannot add this type!");
1607 case MVT::i8: Opc = X86::ADD8rr; break;
1608 case MVT::i16: Opc = X86::ADD16rr; break;
1609 case MVT::i32: Opc = X86::ADD32rr; break;
1610 case MVT::f32: Opc = X86::ADDSSrr; break;
1611 case MVT::f64: Opc = X86ScalarSSE ? X86::ADDSDrr : X86::FpADD; break;
1614 if (getRegPressure(Op0) > getRegPressure(Op1)) {
1615 Tmp1 = SelectExpr(Op0);
1616 Tmp2 = SelectExpr(Op1);
1618 Tmp2 = SelectExpr(Op1);
1619 Tmp1 = SelectExpr(Op0);
1622 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1626 Tmp1 = SelectExpr(Node->getOperand(0));
1628 Opc = (N.getValueType() == MVT::f32) ? X86::SQRTSSrr : X86::SQRTSDrr;
1629 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1631 BuildMI(BB, X86::FpSQRT, 1, Result).addReg(Tmp1);
1636 // Once we can spill 16 byte constants into the constant pool, we can
1637 // implement SSE equivalents of FABS and FCHS.
1642 assert(N.getValueType()==MVT::f64 && "Illegal type for this operation");
1643 Tmp1 = SelectExpr(Node->getOperand(0));
1644 switch (N.getOpcode()) {
1645 default: assert(0 && "Unreachable!");
1646 case ISD::FABS: BuildMI(BB, X86::FpABS, 1, Result).addReg(Tmp1); break;
1647 case ISD::FNEG: BuildMI(BB, X86::FpCHS, 1, Result).addReg(Tmp1); break;
1648 case ISD::FSIN: BuildMI(BB, X86::FpSIN, 1, Result).addReg(Tmp1); break;
1649 case ISD::FCOS: BuildMI(BB, X86::FpCOS, 1, Result).addReg(Tmp1); break;
1654 switch (N.getValueType()) {
1655 default: assert(0 && "Unsupported VT!");
1656 case MVT::i8: Tmp2 = X86::MUL8r; break;
1657 case MVT::i16: Tmp2 = X86::MUL16r; break;
1658 case MVT::i32: Tmp2 = X86::MUL32r; break;
1662 unsigned MovOpc, LowReg, HiReg;
1663 switch (N.getValueType()) {
1664 default: assert(0 && "Unsupported VT!");
1666 MovOpc = X86::MOV8rr;
1672 MovOpc = X86::MOV16rr;
1678 MovOpc = X86::MOV32rr;
1684 if (Node->getOpcode() != ISD::MULHS)
1685 Opc = Tmp2; // Get the MULHU opcode.
1687 Op0 = Node->getOperand(0);
1688 Op1 = Node->getOperand(1);
1689 if (getRegPressure(Op0) > getRegPressure(Op1)) {
1690 Tmp1 = SelectExpr(Op0);
1691 Tmp2 = SelectExpr(Op1);
1693 Tmp2 = SelectExpr(Op1);
1694 Tmp1 = SelectExpr(Op0);
1697 // FIXME: Implement folding of loads into the memory operands here!
1698 BuildMI(BB, MovOpc, 1, LowReg).addReg(Tmp1);
1699 BuildMI(BB, Opc, 1).addReg(Tmp2);
1700 BuildMI(BB, MovOpc, 1, Result).addReg(HiReg);
1711 static const unsigned SUBTab[] = {
1712 X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, 0,
1713 X86::SUB8rm, X86::SUB16rm, X86::SUB32rm, X86::FpSUB32m, X86::FpSUB64m,
1714 X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB , X86::FpSUB,
1716 static const unsigned SSE_SUBTab[] = {
1717 X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, 0,
1718 X86::SUB8rm, X86::SUB16rm, X86::SUB32rm, X86::SUBSSrm, X86::SUBSDrm,
1719 X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::SUBSSrr, X86::SUBSDrr,
1721 static const unsigned MULTab[] = {
1722 0, X86::IMUL16rri, X86::IMUL32rri, 0, 0,
1723 0, X86::IMUL16rm , X86::IMUL32rm, X86::FpMUL32m, X86::FpMUL64m,
1724 0, X86::IMUL16rr , X86::IMUL32rr, X86::FpMUL , X86::FpMUL,
1726 static const unsigned SSE_MULTab[] = {
1727 0, X86::IMUL16rri, X86::IMUL32rri, 0, 0,
1728 0, X86::IMUL16rm , X86::IMUL32rm, X86::MULSSrm, X86::MULSDrm,
1729 0, X86::IMUL16rr , X86::IMUL32rr, X86::MULSSrr, X86::MULSDrr,
1731 static const unsigned ANDTab[] = {
1732 X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, 0,
1733 X86::AND8rm, X86::AND16rm, X86::AND32rm, 0, 0,
1734 X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, 0,
1736 static const unsigned ORTab[] = {
1737 X86::OR8ri, X86::OR16ri, X86::OR32ri, 0, 0,
1738 X86::OR8rm, X86::OR16rm, X86::OR32rm, 0, 0,
1739 X86::OR8rr, X86::OR16rr, X86::OR32rr, 0, 0,
1741 static const unsigned XORTab[] = {
1742 X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, 0,
1743 X86::XOR8rm, X86::XOR16rm, X86::XOR32rm, 0, 0,
1744 X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, 0,
1747 Op0 = Node->getOperand(0);
1748 Op1 = Node->getOperand(1);
1750 if (Node->getOpcode() == ISD::OR && Op0.hasOneUse() && Op1.hasOneUse())
1751 if (EmitOrOpOp(Op0, Op1, Result)) // Match SHLD, SHRD, and rotates.
1754 if (Node->getOpcode() == ISD::SUB)
1755 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(0)))
1756 if (CN->isNullValue()) { // 0 - N -> neg N
1757 switch (N.getValueType()) {
1758 default: assert(0 && "Cannot sub this type!");
1760 case MVT::i8: Opc = X86::NEG8r; break;
1761 case MVT::i16: Opc = X86::NEG16r; break;
1762 case MVT::i32: Opc = X86::NEG32r; break;
1764 Tmp1 = SelectExpr(N.getOperand(1));
1765 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1769 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
1770 if (CN->isAllOnesValue() && Node->getOpcode() == ISD::XOR) {
1772 switch (N.getValueType()) {
1773 default: assert(0 && "Cannot add this type!");
1774 case MVT::i1: break; // Not supported, don't invert upper bits!
1775 case MVT::i8: Opc = X86::NOT8r; break;
1776 case MVT::i16: Opc = X86::NOT16r; break;
1777 case MVT::i32: Opc = X86::NOT32r; break;
1780 Tmp1 = SelectExpr(Op0);
1781 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1786 // Fold common multiplies into LEA instructions.
1787 if (Node->getOpcode() == ISD::MUL && N.getValueType() == MVT::i32) {
1788 switch ((int)CN->getValue()) {
1793 // Remove N from exprmap so SelectAddress doesn't get confused.
1796 SelectAddress(N, AM);
1797 // Restore it to the map.
1798 ExprMap[N] = Result;
1799 addFullAddress(BuildMI(BB, X86::LEA32r, 4, Result), AM);
1804 switch (N.getValueType()) {
1805 default: assert(0 && "Cannot xor this type!");
1807 case MVT::i8: Opc = 0; break;
1808 case MVT::i16: Opc = 1; break;
1809 case MVT::i32: Opc = 2; break;
1811 switch (Node->getOpcode()) {
1812 default: assert(0 && "Unreachable!");
1814 case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
1816 case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
1817 case ISD::AND: Opc = ANDTab[Opc]; break;
1818 case ISD::OR: Opc = ORTab[Opc]; break;
1819 case ISD::XOR: Opc = XORTab[Opc]; break;
1821 if (Opc) { // Can't fold MUL:i8 R, imm
1822 Tmp1 = SelectExpr(Op0);
1823 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
1828 if (isFoldableLoad(Op0, Op1, true))
1829 if (Node->getOpcode() != ISD::SUB && Node->getOpcode() != ISD::FSUB) {
1830 std::swap(Op0, Op1);
1833 // For FP, emit 'reverse' subract, with a memory operand.
1834 if (N.getValueType() == MVT::f64 && !X86ScalarSSE) {
1835 if (Op0.getOpcode() == ISD::EXTLOAD)
1836 Opc = X86::FpSUBR32m;
1838 Opc = X86::FpSUBR64m;
1841 EmitFoldedLoad(Op0, AM);
1842 Tmp1 = SelectExpr(Op1);
1843 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
1848 if (isFoldableLoad(Op1, Op0, true)) {
1850 switch (N.getValueType()) {
1851 default: assert(0 && "Cannot operate on this type!");
1853 case MVT::i8: Opc = 5; break;
1854 case MVT::i16: Opc = 6; break;
1855 case MVT::i32: Opc = 7; break;
1856 case MVT::f32: Opc = 8; break;
1857 // For F64, handle promoted load operations (from F32) as well!
1859 assert((!X86ScalarSSE || Op1.getOpcode() == ISD::LOAD) &&
1860 "SSE load should have been promoted");
1861 Opc = Op1.getOpcode() == ISD::LOAD ? 9 : 8; break;
1863 switch (Node->getOpcode()) {
1864 default: assert(0 && "Unreachable!");
1866 case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
1868 case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
1869 case ISD::AND: Opc = ANDTab[Opc]; break;
1870 case ISD::OR: Opc = ORTab[Opc]; break;
1871 case ISD::XOR: Opc = XORTab[Opc]; break;
1875 EmitFoldedLoad(Op1, AM);
1876 Tmp1 = SelectExpr(Op0);
1878 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
1880 assert(Node->getOpcode() == ISD::MUL &&
1881 N.getValueType() == MVT::i8 && "Unexpected situation!");
1882 // Must use the MUL instruction, which forces use of AL.
1883 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(Tmp1);
1884 addFullAddress(BuildMI(BB, X86::MUL8m, 1), AM);
1885 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
1890 if (getRegPressure(Op0) > getRegPressure(Op1)) {
1891 Tmp1 = SelectExpr(Op0);
1892 Tmp2 = SelectExpr(Op1);
1894 Tmp2 = SelectExpr(Op1);
1895 Tmp1 = SelectExpr(Op0);
1898 switch (N.getValueType()) {
1899 default: assert(0 && "Cannot add this type!");
1901 case MVT::i8: Opc = 10; break;
1902 case MVT::i16: Opc = 11; break;
1903 case MVT::i32: Opc = 12; break;
1904 case MVT::f32: Opc = 13; break;
1905 case MVT::f64: Opc = 14; break;
1907 switch (Node->getOpcode()) {
1908 default: assert(0 && "Unreachable!");
1910 case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
1912 case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
1913 case ISD::AND: Opc = ANDTab[Opc]; break;
1914 case ISD::OR: Opc = ORTab[Opc]; break;
1915 case ISD::XOR: Opc = XORTab[Opc]; break;
1918 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1920 assert(Node->getOpcode() == ISD::MUL &&
1921 N.getValueType() == MVT::i8 && "Unexpected situation!");
1922 // Must use the MUL instruction, which forces use of AL.
1923 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(Tmp1);
1924 BuildMI(BB, X86::MUL8r, 1).addReg(Tmp2);
1925 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
1929 case ISD::ADD_PARTS:
1930 case ISD::SUB_PARTS: {
1931 assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
1932 "Not an i64 add/sub!");
1933 // Emit all of the operands.
1934 std::vector<unsigned> InVals;
1935 for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
1936 InVals.push_back(SelectExpr(N.getOperand(i)));
1937 if (N.getOpcode() == ISD::ADD_PARTS) {
1938 BuildMI(BB, X86::ADD32rr, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
1939 BuildMI(BB, X86::ADC32rr,2,Result+1).addReg(InVals[1]).addReg(InVals[3]);
1941 BuildMI(BB, X86::SUB32rr, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
1942 BuildMI(BB, X86::SBB32rr, 2,Result+1).addReg(InVals[1]).addReg(InVals[3]);
1944 return Result+N.ResNo;
1947 case ISD::SHL_PARTS:
1948 case ISD::SRA_PARTS:
1949 case ISD::SRL_PARTS: {
1950 assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
1951 "Not an i64 shift!");
1952 unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
1953 unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
1954 unsigned TmpReg = MakeReg(MVT::i32);
1955 if (N.getOpcode() == ISD::SRA_PARTS) {
1956 // If this is a SHR of a Long, then we need to do funny sign extension
1957 // stuff. TmpReg gets the value to use as the high-part if we are
1958 // shifting more than 32 bits.
1959 BuildMI(BB, X86::SAR32ri, 2, TmpReg).addReg(ShiftOpHi).addImm(31);
1961 // Other shifts use a fixed zero value if the shift is more than 32 bits.
1962 BuildMI(BB, X86::MOV32ri, 1, TmpReg).addImm(0);
1965 // Initialize CL with the shift amount.
1966 unsigned ShiftAmountReg = SelectExpr(N.getOperand(2));
1967 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
1969 unsigned TmpReg2 = MakeReg(MVT::i32);
1970 unsigned TmpReg3 = MakeReg(MVT::i32);
1971 if (N.getOpcode() == ISD::SHL_PARTS) {
1972 // TmpReg2 = shld inHi, inLo
1973 BuildMI(BB, X86::SHLD32rrCL, 2,TmpReg2).addReg(ShiftOpHi)
1975 // TmpReg3 = shl inLo, CL
1976 BuildMI(BB, X86::SHL32rCL, 1, TmpReg3).addReg(ShiftOpLo);
1978 // Set the flags to indicate whether the shift was by more than 32 bits.
1979 BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
1981 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1982 BuildMI(BB, X86::CMOVNE32rr, 2,
1983 Result+1).addReg(TmpReg2).addReg(TmpReg3);
1984 // DestLo = (>32) ? TmpReg : TmpReg3;
1985 BuildMI(BB, X86::CMOVNE32rr, 2,
1986 Result).addReg(TmpReg3).addReg(TmpReg);
1988 // TmpReg2 = shrd inLo, inHi
1989 BuildMI(BB, X86::SHRD32rrCL,2,TmpReg2).addReg(ShiftOpLo)
1991 // TmpReg3 = s[ah]r inHi, CL
1992 BuildMI(BB, N.getOpcode() == ISD::SRA_PARTS ? X86::SAR32rCL
1993 : X86::SHR32rCL, 1, TmpReg3)
1996 // Set the flags to indicate whether the shift was by more than 32 bits.
1997 BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
1999 // DestLo = (>32) ? TmpReg3 : TmpReg2;
2000 BuildMI(BB, X86::CMOVNE32rr, 2,
2001 Result).addReg(TmpReg2).addReg(TmpReg3);
2003 // DestHi = (>32) ? TmpReg : TmpReg3;
2004 BuildMI(BB, X86::CMOVNE32rr, 2,
2005 Result+1).addReg(TmpReg3).addReg(TmpReg);
2007 return Result+N.ResNo;
2011 EmitSelectCC(N.getOperand(0), N.getOperand(1), N.getOperand(2),
2012 N.getValueType(), Result);
2021 assert((N.getOpcode() != ISD::SREM || MVT::isInteger(N.getValueType())) &&
2022 "We don't support this operator!");
2024 if (N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::FDIV) {
2025 // We can fold loads into FpDIVs, but not really into any others.
2026 if (N.getValueType() == MVT::f64 && !X86ScalarSSE) {
2027 // Check for reversed and unreversed DIV.
2028 if (isFoldableLoad(N.getOperand(0), N.getOperand(1), true)) {
2029 if (N.getOperand(0).getOpcode() == ISD::EXTLOAD)
2030 Opc = X86::FpDIVR32m;
2032 Opc = X86::FpDIVR64m;
2034 EmitFoldedLoad(N.getOperand(0), AM);
2035 Tmp1 = SelectExpr(N.getOperand(1));
2036 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
2038 } else if (isFoldableLoad(N.getOperand(1), N.getOperand(0), true) &&
2039 N.getOperand(1).getOpcode() == ISD::LOAD) {
2040 if (N.getOperand(1).getOpcode() == ISD::EXTLOAD)
2041 Opc = X86::FpDIV32m;
2043 Opc = X86::FpDIV64m;
2045 EmitFoldedLoad(N.getOperand(1), AM);
2046 Tmp1 = SelectExpr(N.getOperand(0));
2047 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
2053 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2054 Tmp1 = SelectExpr(N.getOperand(0));
2055 Tmp2 = SelectExpr(N.getOperand(1));
2057 Tmp2 = SelectExpr(N.getOperand(1));
2058 Tmp1 = SelectExpr(N.getOperand(0));
2061 bool isSigned = N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::SREM;
2062 bool isDiv = N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::UDIV;
2063 unsigned LoReg, HiReg, DivOpcode, MovOpcode, ClrOpcode, SExtOpcode;
2064 switch (N.getValueType()) {
2065 default: assert(0 && "Cannot sdiv this type!");
2067 DivOpcode = isSigned ? X86::IDIV8r : X86::DIV8r;
2070 MovOpcode = X86::MOV8rr;
2071 ClrOpcode = X86::MOV8ri;
2072 SExtOpcode = X86::CBW;
2075 DivOpcode = isSigned ? X86::IDIV16r : X86::DIV16r;
2078 MovOpcode = X86::MOV16rr;
2079 ClrOpcode = X86::MOV16ri;
2080 SExtOpcode = X86::CWD;
2083 DivOpcode = isSigned ? X86::IDIV32r : X86::DIV32r;
2086 MovOpcode = X86::MOV32rr;
2087 ClrOpcode = X86::MOV32ri;
2088 SExtOpcode = X86::CDQ;
2091 BuildMI(BB, X86::DIVSSrr, 2, Result).addReg(Tmp1).addReg(Tmp2);
2094 Opc = X86ScalarSSE ? X86::DIVSDrr : X86::FpDIV;
2095 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
2099 // Set up the low part.
2100 BuildMI(BB, MovOpcode, 1, LoReg).addReg(Tmp1);
2103 // Sign extend the low part into the high part.
2104 BuildMI(BB, SExtOpcode, 0);
2106 // Zero out the high part, effectively zero extending the input.
2107 BuildMI(BB, ClrOpcode, 1, HiReg).addImm(0);
2110 // Emit the DIV/IDIV instruction.
2111 BuildMI(BB, DivOpcode, 1).addReg(Tmp2);
2113 // Get the result of the divide or rem.
2114 BuildMI(BB, MovOpcode, 1, Result).addReg(isDiv ? LoReg : HiReg);
2119 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2120 if (CN->getValue() == 1) { // X = SHL Y, 1 -> X = ADD Y, Y
2121 switch (N.getValueType()) {
2122 default: assert(0 && "Cannot shift this type!");
2123 case MVT::i8: Opc = X86::ADD8rr; break;
2124 case MVT::i16: Opc = X86::ADD16rr; break;
2125 case MVT::i32: Opc = X86::ADD32rr; break;
2127 Tmp1 = SelectExpr(N.getOperand(0));
2128 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp1);
2132 switch (N.getValueType()) {
2133 default: assert(0 && "Cannot shift this type!");
2134 case MVT::i8: Opc = X86::SHL8ri; break;
2135 case MVT::i16: Opc = X86::SHL16ri; break;
2136 case MVT::i32: Opc = X86::SHL32ri; break;
2138 Tmp1 = SelectExpr(N.getOperand(0));
2139 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
2143 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2144 Tmp1 = SelectExpr(N.getOperand(0));
2145 Tmp2 = SelectExpr(N.getOperand(1));
2147 Tmp2 = SelectExpr(N.getOperand(1));
2148 Tmp1 = SelectExpr(N.getOperand(0));
2151 switch (N.getValueType()) {
2152 default: assert(0 && "Cannot shift this type!");
2153 case MVT::i8 : Opc = X86::SHL8rCL; break;
2154 case MVT::i16: Opc = X86::SHL16rCL; break;
2155 case MVT::i32: Opc = X86::SHL32rCL; break;
2157 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
2158 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
2161 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2162 switch (N.getValueType()) {
2163 default: assert(0 && "Cannot shift this type!");
2164 case MVT::i8: Opc = X86::SHR8ri; break;
2165 case MVT::i16: Opc = X86::SHR16ri; break;
2166 case MVT::i32: Opc = X86::SHR32ri; break;
2168 Tmp1 = SelectExpr(N.getOperand(0));
2169 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
2173 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2174 Tmp1 = SelectExpr(N.getOperand(0));
2175 Tmp2 = SelectExpr(N.getOperand(1));
2177 Tmp2 = SelectExpr(N.getOperand(1));
2178 Tmp1 = SelectExpr(N.getOperand(0));
2181 switch (N.getValueType()) {
2182 default: assert(0 && "Cannot shift this type!");
2183 case MVT::i8 : Opc = X86::SHR8rCL; break;
2184 case MVT::i16: Opc = X86::SHR16rCL; break;
2185 case MVT::i32: Opc = X86::SHR32rCL; break;
2187 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
2188 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
2191 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2192 switch (N.getValueType()) {
2193 default: assert(0 && "Cannot shift this type!");
2194 case MVT::i8: Opc = X86::SAR8ri; break;
2195 case MVT::i16: Opc = X86::SAR16ri; break;
2196 case MVT::i32: Opc = X86::SAR32ri; break;
2198 Tmp1 = SelectExpr(N.getOperand(0));
2199 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
2203 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2204 Tmp1 = SelectExpr(N.getOperand(0));
2205 Tmp2 = SelectExpr(N.getOperand(1));
2207 Tmp2 = SelectExpr(N.getOperand(1));
2208 Tmp1 = SelectExpr(N.getOperand(0));
2211 switch (N.getValueType()) {
2212 default: assert(0 && "Cannot shift this type!");
2213 case MVT::i8 : Opc = X86::SAR8rCL; break;
2214 case MVT::i16: Opc = X86::SAR16rCL; break;
2215 case MVT::i32: Opc = X86::SAR32rCL; break;
2217 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
2218 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
2222 EmitCMP(N.getOperand(0), N.getOperand(1), Node->hasOneUse());
2223 EmitSetCC(BB, Result, cast<CondCodeSDNode>(N.getOperand(2))->get(),
2224 MVT::isFloatingPoint(N.getOperand(1).getValueType()));
2227 // Make sure we generate both values.
2228 if (Result != 1) { // Generate the token
2229 if (!ExprMap.insert(std::make_pair(N.getValue(1), 1)).second)
2230 assert(0 && "Load already emitted!?");
2232 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2234 switch (Node->getValueType(0)) {
2235 default: assert(0 && "Cannot load this type!");
2237 case MVT::i8: Opc = X86::MOV8rm; break;
2238 case MVT::i16: Opc = X86::MOV16rm; break;
2239 case MVT::i32: Opc = X86::MOV32rm; break;
2240 case MVT::f32: Opc = X86::MOVSSrm; break;
2246 ContainsFPCode = true;
2251 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1))){
2252 Constant *C = CP->get();
2253 unsigned Align = CP->getAlignment();
2255 Align = C->getType() == Type::DoubleTy ? 3 :
2256 TD.getTypeAlignmentShift(C->getType());
2259 unsigned CPIdx = BB->getParent()->getConstantPool()->
2260 getConstantPoolIndex(C, Align);
2261 Select(N.getOperand(0));
2262 addConstantPoolReference(BuildMI(BB, Opc, 4, Result), CPIdx);
2266 SDOperand Chain = N.getOperand(0);
2267 SDOperand Address = N.getOperand(1);
2268 if (getRegPressure(Chain) > getRegPressure(Address)) {
2270 SelectAddress(Address, AM);
2272 SelectAddress(Address, AM);
2276 addFullAddress(BuildMI(BB, Opc, 4, Result), AM);
2280 // Make sure we generate both values.
2281 assert(Result != 1 && N.getValueType() == MVT::f64);
2282 if (!ExprMap.insert(std::make_pair(N.getValue(1), 1)).second)
2283 assert(0 && "Load already emitted!?");
2288 SDOperand Chain = N.getOperand(0);
2289 SDOperand Address = N.getOperand(1);
2290 if (getRegPressure(Chain) > getRegPressure(Address)) {
2292 SelectAddress(Address, AM);
2294 SelectAddress(Address, AM);
2298 addFullAddress(BuildMI(BB, X86::FpILD64m, 4, Result), AM);
2302 case ISD::EXTLOAD: // Arbitrarily codegen extloads as MOVZX*
2303 case ISD::ZEXTLOAD: {
2304 // Make sure we generate both values.
2306 ExprMap[N.getValue(1)] = 1; // Generate the token
2308 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2310 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
2311 if (Node->getValueType(0) == MVT::f64) {
2312 assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::f32 &&
2314 unsigned CPIdx = BB->getParent()->getConstantPool()->
2315 getConstantPoolIndex(CP->get(), 2);
2317 addConstantPoolReference(BuildMI(BB, X86::FpLD32m, 4, Result), CPIdx);
2322 if (getRegPressure(Node->getOperand(0)) >
2323 getRegPressure(Node->getOperand(1))) {
2324 Select(Node->getOperand(0)); // chain
2325 SelectAddress(Node->getOperand(1), AM);
2327 SelectAddress(Node->getOperand(1), AM);
2328 Select(Node->getOperand(0)); // chain
2331 switch (Node->getValueType(0)) {
2332 default: assert(0 && "Unknown type to sign extend to.");
2334 assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::f32 &&
2336 addFullAddress(BuildMI(BB, X86::FpLD32m, 5, Result), AM);
2339 switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
2341 assert(0 && "Bad zero extend!");
2344 addFullAddress(BuildMI(BB, X86::MOVZX32rm8, 5, Result), AM);
2347 addFullAddress(BuildMI(BB, X86::MOVZX32rm16, 5, Result), AM);
2352 assert(cast<VTSDNode>(Node->getOperand(3))->getVT() <= MVT::i8 &&
2353 "Bad zero extend!");
2354 addFullAddress(BuildMI(BB, X86::MOVZX16rm8, 5, Result), AM);
2357 assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::i1 &&
2358 "Bad zero extend!");
2359 addFullAddress(BuildMI(BB, X86::MOV8rm, 5, Result), AM);
2364 case ISD::SEXTLOAD: {
2365 // Make sure we generate both values.
2367 ExprMap[N.getValue(1)] = 1; // Generate the token
2369 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2372 if (getRegPressure(Node->getOperand(0)) >
2373 getRegPressure(Node->getOperand(1))) {
2374 Select(Node->getOperand(0)); // chain
2375 SelectAddress(Node->getOperand(1), AM);
2377 SelectAddress(Node->getOperand(1), AM);
2378 Select(Node->getOperand(0)); // chain
2381 switch (Node->getValueType(0)) {
2382 case MVT::i8: assert(0 && "Cannot sign extend from bool!");
2383 default: assert(0 && "Unknown type to sign extend to.");
2385 switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
2387 case MVT::i1: assert(0 && "Cannot sign extend from bool!");
2389 addFullAddress(BuildMI(BB, X86::MOVSX32rm8, 5, Result), AM);
2392 addFullAddress(BuildMI(BB, X86::MOVSX32rm16, 5, Result), AM);
2397 assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::i8 &&
2398 "Cannot sign extend from bool!");
2399 addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
2405 case X86ISD::TAILCALL:
2406 case X86ISD::CALL: {
2407 // The chain for this call is now lowered.
2408 ExprMap.insert(std::make_pair(N.getValue(0), 1));
2410 bool isDirect = isa<GlobalAddressSDNode>(N.getOperand(1)) ||
2411 isa<ExternalSymbolSDNode>(N.getOperand(1));
2412 unsigned Callee = 0;
2414 Select(N.getOperand(0));
2416 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2417 Select(N.getOperand(0));
2418 Callee = SelectExpr(N.getOperand(1));
2420 Callee = SelectExpr(N.getOperand(1));
2421 Select(N.getOperand(0));
2425 // If this call has values to pass in registers, do so now.
2426 if (Node->getNumOperands() > 4) {
2427 // The first value is passed in (a part of) EAX, the second in EDX.
2428 unsigned RegOp1 = SelectExpr(N.getOperand(4));
2430 Node->getNumOperands() > 5 ? SelectExpr(N.getOperand(5)) : 0;
2432 switch (N.getOperand(4).getValueType()) {
2433 default: assert(0 && "Bad thing to pass in regs");
2435 case MVT::i8: BuildMI(BB, X86::MOV8rr , 1,X86::AL).addReg(RegOp1); break;
2436 case MVT::i16: BuildMI(BB, X86::MOV16rr, 1,X86::AX).addReg(RegOp1); break;
2437 case MVT::i32: BuildMI(BB, X86::MOV32rr, 1,X86::EAX).addReg(RegOp1);break;
2440 switch (N.getOperand(5).getValueType()) {
2441 default: assert(0 && "Bad thing to pass in regs");
2444 BuildMI(BB, X86::MOV8rr , 1, X86::DL).addReg(RegOp2);
2447 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(RegOp2);
2450 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RegOp2);
2455 if (GlobalAddressSDNode *GASD =
2456 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
2457 BuildMI(BB, X86::CALLpcrel32, 1).addGlobalAddress(GASD->getGlobal(),true);
2458 } else if (ExternalSymbolSDNode *ESSDN =
2459 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
2460 BuildMI(BB, X86::CALLpcrel32,
2461 1).addExternalSymbol(ESSDN->getSymbol(), true);
2463 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2464 Select(N.getOperand(0));
2465 Tmp1 = SelectExpr(N.getOperand(1));
2467 Tmp1 = SelectExpr(N.getOperand(1));
2468 Select(N.getOperand(0));
2471 BuildMI(BB, X86::CALL32r, 1).addReg(Tmp1);
2474 // Get caller stack amount and amount the callee added to the stack pointer.
2475 Tmp1 = cast<ConstantSDNode>(N.getOperand(2))->getValue();
2476 Tmp2 = cast<ConstantSDNode>(N.getOperand(3))->getValue();
2477 BuildMI(BB, X86::ADJCALLSTACKUP, 2).addImm(Tmp1).addImm(Tmp2);
2479 if (Node->getNumValues() != 1)
2480 switch (Node->getValueType(1)) {
2481 default: assert(0 && "Unknown value type for call result!");
2482 case MVT::Other: return 1;
2485 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
2488 BuildMI(BB, X86::MOV16rr, 1, Result).addReg(X86::AX);
2491 BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::EAX);
2492 if (Node->getNumValues() == 3 && Node->getValueType(2) == MVT::i32)
2493 BuildMI(BB, X86::MOV32rr, 1, Result+1).addReg(X86::EDX);
2495 case MVT::f64: // Floating-point return values live in %ST(0)
2497 ContainsFPCode = true;
2498 BuildMI(BB, X86::FpGETRESULT, 1, X86::FP0);
2500 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
2501 MachineFunction *F = BB->getParent();
2502 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
2503 addFrameReference(BuildMI(BB, X86::FpST64m, 5), FrameIdx).addReg(X86::FP0);
2504 addFrameReference(BuildMI(BB, X86::MOVSDrm, 4, Result), FrameIdx);
2507 ContainsFPCode = true;
2508 BuildMI(BB, X86::FpGETRESULT, 1, Result);
2512 return Result+N.ResNo-1;
2515 // First, determine that the size of the operand falls within the acceptable
2516 // range for this architecture.
2518 if (Node->getOperand(1).getValueType() != MVT::i16) {
2519 std::cerr << "llvm.readport: Address size is not 16 bits\n";
2523 // Make sure we generate both values.
2524 if (Result != 1) { // Generate the token
2525 if (!ExprMap.insert(std::make_pair(N.getValue(1), 1)).second)
2526 assert(0 && "readport already emitted!?");
2528 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2530 Select(Node->getOperand(0)); // Select the chain.
2532 // If the port is a single-byte constant, use the immediate form.
2533 if (ConstantSDNode *Port = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
2534 if ((Port->getValue() & 255) == Port->getValue()) {
2535 switch (Node->getValueType(0)) {
2537 BuildMI(BB, X86::IN8ri, 1).addImm(Port->getValue());
2538 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
2541 BuildMI(BB, X86::IN16ri, 1).addImm(Port->getValue());
2542 BuildMI(BB, X86::MOV16rr, 1, Result).addReg(X86::AX);
2545 BuildMI(BB, X86::IN32ri, 1).addImm(Port->getValue());
2546 BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::EAX);
2552 // Now, move the I/O port address into the DX register and use the IN
2553 // instruction to get the input data.
2555 Tmp1 = SelectExpr(Node->getOperand(1));
2556 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Tmp1);
2557 switch (Node->getValueType(0)) {
2559 BuildMI(BB, X86::IN8rr, 0);
2560 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
2563 BuildMI(BB, X86::IN16rr, 0);
2564 BuildMI(BB, X86::MOV16rr, 1, Result).addReg(X86::AX);
2567 BuildMI(BB, X86::IN32rr, 0);
2568 BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::EAX);
2571 std::cerr << "Cannot do input on this data type";
2580 /// TryToFoldLoadOpStore - Given a store node, try to fold together a
2581 /// load/op/store instruction. If successful return true.
2582 bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
2583 assert(Node->getOpcode() == ISD::STORE && "Can only do this for stores!");
2584 SDOperand Chain = Node->getOperand(0);
2585 SDOperand StVal = Node->getOperand(1);
2586 SDOperand StPtr = Node->getOperand(2);
2588 // The chain has to be a load, the stored value must be an integer binary
2589 // operation with one use.
2590 if (!StVal.Val->hasOneUse() || StVal.Val->getNumOperands() != 2 ||
2591 MVT::isFloatingPoint(StVal.getValueType()))
2594 // Token chain must either be a factor node or the load to fold.
2595 if (Chain.getOpcode() != ISD::LOAD && Chain.getOpcode() != ISD::TokenFactor)
2600 // Check to see if there is a load from the same pointer that we're storing
2601 // to in either operand of the binop.
2602 if (StVal.getOperand(0).getOpcode() == ISD::LOAD &&
2603 StVal.getOperand(0).getOperand(1) == StPtr)
2604 TheLoad = StVal.getOperand(0);
2605 else if (StVal.getOperand(1).getOpcode() == ISD::LOAD &&
2606 StVal.getOperand(1).getOperand(1) == StPtr)
2607 TheLoad = StVal.getOperand(1);
2609 return false; // No matching load operand.
2611 // We can only fold the load if there are no intervening side-effecting
2612 // operations. This means that the store uses the load as its token chain, or
2613 // there are only token factor nodes in between the store and load.
2614 if (Chain != TheLoad.getValue(1)) {
2615 // Okay, the other option is that we have a store referring to (possibly
2616 // nested) token factor nodes. For now, just try peeking through one level
2617 // of token factors to see if this is the case.
2618 bool ChainOk = false;
2619 if (Chain.getOpcode() == ISD::TokenFactor) {
2620 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
2621 if (Chain.getOperand(i) == TheLoad.getValue(1)) {
2627 if (!ChainOk) return false;
2630 if (TheLoad.getOperand(1) != StPtr)
2633 // Make sure that one of the operands of the binop is the load, and that the
2634 // load folds into the binop.
2635 if (((StVal.getOperand(0) != TheLoad ||
2636 !isFoldableLoad(TheLoad, StVal.getOperand(1))) &&
2637 (StVal.getOperand(1) != TheLoad ||
2638 !isFoldableLoad(TheLoad, StVal.getOperand(0)))))
2641 // Finally, check to see if this is one of the ops we can handle!
2642 static const unsigned ADDTAB[] = {
2643 X86::ADD8mi, X86::ADD16mi, X86::ADD32mi,
2644 X86::ADD8mr, X86::ADD16mr, X86::ADD32mr,
2646 static const unsigned SUBTAB[] = {
2647 X86::SUB8mi, X86::SUB16mi, X86::SUB32mi,
2648 X86::SUB8mr, X86::SUB16mr, X86::SUB32mr,
2650 static const unsigned ANDTAB[] = {
2651 X86::AND8mi, X86::AND16mi, X86::AND32mi,
2652 X86::AND8mr, X86::AND16mr, X86::AND32mr,
2654 static const unsigned ORTAB[] = {
2655 X86::OR8mi, X86::OR16mi, X86::OR32mi,
2656 X86::OR8mr, X86::OR16mr, X86::OR32mr,
2658 static const unsigned XORTAB[] = {
2659 X86::XOR8mi, X86::XOR16mi, X86::XOR32mi,
2660 X86::XOR8mr, X86::XOR16mr, X86::XOR32mr,
2662 static const unsigned SHLTAB[] = {
2663 X86::SHL8mi, X86::SHL16mi, X86::SHL32mi,
2664 /*Have to put the reg in CL*/0, 0, 0,
2666 static const unsigned SARTAB[] = {
2667 X86::SAR8mi, X86::SAR16mi, X86::SAR32mi,
2668 /*Have to put the reg in CL*/0, 0, 0,
2670 static const unsigned SHRTAB[] = {
2671 X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
2672 /*Have to put the reg in CL*/0, 0, 0,
2675 const unsigned *TabPtr = 0;
2676 switch (StVal.getOpcode()) {
2678 std::cerr << "CANNOT [mem] op= val: ";
2679 StVal.Val->dump(); std::cerr << "\n";
2687 case ISD::UREM: return false;
2689 case ISD::ADD: TabPtr = ADDTAB; break;
2690 case ISD::SUB: TabPtr = SUBTAB; break;
2691 case ISD::AND: TabPtr = ANDTAB; break;
2692 case ISD:: OR: TabPtr = ORTAB; break;
2693 case ISD::XOR: TabPtr = XORTAB; break;
2694 case ISD::SHL: TabPtr = SHLTAB; break;
2695 case ISD::SRA: TabPtr = SARTAB; break;
2696 case ISD::SRL: TabPtr = SHRTAB; break;
2699 // Handle: [mem] op= CST
2700 SDOperand Op0 = StVal.getOperand(0);
2701 SDOperand Op1 = StVal.getOperand(1);
2703 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
2704 switch (Op0.getValueType()) { // Use Op0's type because of shifts.
2707 case MVT::i8: Opc = TabPtr[0]; break;
2708 case MVT::i16: Opc = TabPtr[1]; break;
2709 case MVT::i32: Opc = TabPtr[2]; break;
2713 if (!ExprMap.insert(std::make_pair(TheLoad.getValue(1), 1)).second)
2714 assert(0 && "Already emitted?");
2718 if (getRegPressure(TheLoad.getOperand(0)) >
2719 getRegPressure(TheLoad.getOperand(1))) {
2720 Select(TheLoad.getOperand(0));
2721 SelectAddress(TheLoad.getOperand(1), AM);
2723 SelectAddress(TheLoad.getOperand(1), AM);
2724 Select(TheLoad.getOperand(0));
2727 if (StVal.getOpcode() == ISD::ADD) {
2728 if (CN->getValue() == 1) {
2729 switch (Op0.getValueType()) {
2732 addFullAddress(BuildMI(BB, X86::INC8m, 4), AM);
2734 case MVT::i16: Opc = TabPtr[1];
2735 addFullAddress(BuildMI(BB, X86::INC16m, 4), AM);
2737 case MVT::i32: Opc = TabPtr[2];
2738 addFullAddress(BuildMI(BB, X86::INC32m, 4), AM);
2741 } else if (CN->getValue()+1 == 0) { // [X] += -1 -> DEC [X]
2742 switch (Op0.getValueType()) {
2745 addFullAddress(BuildMI(BB, X86::DEC8m, 4), AM);
2747 case MVT::i16: Opc = TabPtr[1];
2748 addFullAddress(BuildMI(BB, X86::DEC16m, 4), AM);
2750 case MVT::i32: Opc = TabPtr[2];
2751 addFullAddress(BuildMI(BB, X86::DEC32m, 4), AM);
2757 addFullAddress(BuildMI(BB, Opc, 4+1),AM).addImm(CN->getValue());
2762 // If we have [mem] = V op [mem], try to turn it into:
2763 // [mem] = [mem] op V.
2764 if (Op1 == TheLoad &&
2765 StVal.getOpcode() != ISD::SUB && StVal.getOpcode() != ISD::FSUB &&
2766 StVal.getOpcode() != ISD::SHL && StVal.getOpcode() != ISD::SRA &&
2767 StVal.getOpcode() != ISD::SRL)
2768 std::swap(Op0, Op1);
2770 if (Op0 != TheLoad) return false;
2772 switch (Op0.getValueType()) {
2773 default: return false;
2775 case MVT::i8: Opc = TabPtr[3]; break;
2776 case MVT::i16: Opc = TabPtr[4]; break;
2777 case MVT::i32: Opc = TabPtr[5]; break;
2780 // Table entry doesn't exist?
2781 if (Opc == 0) return false;
2783 if (!ExprMap.insert(std::make_pair(TheLoad.getValue(1), 1)).second)
2784 assert(0 && "Already emitted?");
2786 Select(TheLoad.getOperand(0));
2789 SelectAddress(TheLoad.getOperand(1), AM);
2790 unsigned Reg = SelectExpr(Op1);
2791 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Reg);
2795 /// If node is a ret(tailcall) node, emit the specified tail call and return
2796 /// true, otherwise return false.
2798 /// FIXME: This whole thing should be a post-legalize optimization pass which
2799 /// recognizes and transforms the dag. We don't want the selection phase doing
2802 bool ISel::EmitPotentialTailCall(SDNode *RetNode) {
2803 assert(RetNode->getOpcode() == ISD::RET && "Not a return");
2805 SDOperand Chain = RetNode->getOperand(0);
2807 // If this is a token factor node where one operand is a call, dig into it.
2808 SDOperand TokFactor;
2809 unsigned TokFactorOperand = 0;
2810 if (Chain.getOpcode() == ISD::TokenFactor) {
2811 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
2812 if (Chain.getOperand(i).getOpcode() == ISD::CALLSEQ_END ||
2813 Chain.getOperand(i).getOpcode() == X86ISD::TAILCALL) {
2814 TokFactorOperand = i;
2816 Chain = Chain.getOperand(i);
2819 if (TokFactor.Val == 0) return false; // No call operand.
2822 // Skip the CALLSEQ_END node if present.
2823 if (Chain.getOpcode() == ISD::CALLSEQ_END)
2824 Chain = Chain.getOperand(0);
2826 // Is a tailcall the last control operation that occurs before the return?
2827 if (Chain.getOpcode() != X86ISD::TAILCALL)
2830 // If we return a value, is it the value produced by the call?
2831 if (RetNode->getNumOperands() > 1) {
2832 // Not returning the ret val of the call?
2833 if (Chain.Val->getNumValues() == 1 ||
2834 RetNode->getOperand(1) != Chain.getValue(1))
2837 if (RetNode->getNumOperands() > 2) {
2838 if (Chain.Val->getNumValues() == 2 ||
2839 RetNode->getOperand(2) != Chain.getValue(2))
2842 assert(RetNode->getNumOperands() <= 3);
2845 // CalleeCallArgAmt - The total number of bytes used for the callee arg area.
2846 // For FastCC, this will always be > 0.
2847 unsigned CalleeCallArgAmt =
2848 cast<ConstantSDNode>(Chain.getOperand(2))->getValue();
2850 // CalleeCallArgPopAmt - The number of bytes in the call area popped by the
2851 // callee. For FastCC this will always be > 0, for CCC this is always 0.
2852 unsigned CalleeCallArgPopAmt =
2853 cast<ConstantSDNode>(Chain.getOperand(3))->getValue();
2855 // There are several cases we can handle here. First, if the caller and
2856 // callee are both CCC functions, we can tailcall if the callee takes <= the
2857 // number of argument bytes that the caller does.
2858 if (CalleeCallArgPopAmt == 0 && // Callee is C CallingConv?
2859 X86Lowering.getBytesToPopOnReturn() == 0) { // Caller is C CallingConv?
2860 // Check to see if caller arg area size >= callee arg area size.
2861 if (X86Lowering.getBytesCallerReserves() >= CalleeCallArgAmt) {
2862 //std::cerr << "CCC TAILCALL UNIMP!\n";
2863 // If TokFactor is non-null, emit all operands.
2865 //EmitCCCToCCCTailCall(Chain.Val);
2871 // Second, if both are FastCC functions, we can always perform the tail call.
2872 if (CalleeCallArgPopAmt && X86Lowering.getBytesToPopOnReturn()) {
2873 // If TokFactor is non-null, emit all operands before the call.
2874 if (TokFactor.Val) {
2875 for (unsigned i = 0, e = TokFactor.getNumOperands(); i != e; ++i)
2876 if (i != TokFactorOperand)
2877 Select(TokFactor.getOperand(i));
2880 EmitFastCCToFastCCTailCall(Chain.Val);
2884 // We don't support mixed calls, due to issues with alignment. We could in
2885 // theory handle some mixed calls from CCC -> FastCC if the stack is properly
2886 // aligned (which depends on the number of arguments to the callee). TODO.
2890 static SDOperand GetAdjustedArgumentStores(SDOperand Chain, int Offset,
2891 SelectionDAG &DAG) {
2892 MVT::ValueType StoreVT;
2893 switch (Chain.getOpcode()) {
2894 default: assert(0 && "Unexpected node!");
2895 case ISD::CALLSEQ_START:
2896 // If we found the start of the call sequence, we're done. We actually
2897 // strip off the CALLSEQ_START node, to avoid generating the
2898 // ADJCALLSTACKDOWN marker for the tail call.
2899 return Chain.getOperand(0);
2900 case ISD::TokenFactor: {
2901 std::vector<SDOperand> Ops;
2902 Ops.reserve(Chain.getNumOperands());
2903 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
2904 Ops.push_back(GetAdjustedArgumentStores(Chain.getOperand(i), Offset,DAG));
2905 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
2907 case ISD::STORE: // Normal store
2908 StoreVT = Chain.getOperand(1).getValueType();
2910 case ISD::TRUNCSTORE: // FLOAT store
2911 StoreVT = cast<VTSDNode>(Chain.getOperand(4))->getVT();
2915 SDOperand OrigDest = Chain.getOperand(2);
2916 unsigned OrigOffset;
2918 if (OrigDest.getOpcode() == ISD::CopyFromReg) {
2920 assert(cast<RegisterSDNode>(OrigDest.getOperand(1))->getReg() == X86::ESP);
2921 } else if (OrigDest.getOpcode() == ISD::ADD &&
2922 isa<ConstantSDNode>(OrigDest.getOperand(1)) &&
2923 OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg &&
2924 cast<RegisterSDNode>(OrigDest.getOperand(0).getOperand(1))->getReg()
2926 // We expect only (ESP+C)
2927 OrigOffset = cast<ConstantSDNode>(OrigDest.getOperand(1))->getValue();
2928 } else if (OrigDest.getOpcode() == ISD::Register) {
2929 // We expect only (ESP+C)
2932 assert(OrigDest.getOpcode() == ISD::ADD &&
2933 isa<ConstantSDNode>(OrigDest.getOperand(1)) &&
2934 OrigDest.getOperand(0).getOpcode() == ISD::Register &&
2935 cast<RegisterSDNode>(OrigDest.getOperand(0))->getReg() == X86::ESP);
2936 OrigOffset = cast<ConstantSDNode>(OrigDest.getOperand(1))->getValue();
2939 // Compute the new offset from the incoming ESP value we wish to use.
2940 unsigned NewOffset = OrigOffset + Offset;
2942 unsigned OpSize = (MVT::getSizeInBits(StoreVT)+7)/8; // Bits -> Bytes
2943 MachineFunction &MF = DAG.getMachineFunction();
2944 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, NewOffset);
2945 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
2947 SDOperand InChain = GetAdjustedArgumentStores(Chain.getOperand(0), Offset,
2949 if (Chain.getOpcode() == ISD::STORE)
2950 return DAG.getNode(ISD::STORE, MVT::Other, InChain, Chain.getOperand(1),
2952 assert(Chain.getOpcode() == ISD::TRUNCSTORE);
2953 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, InChain, Chain.getOperand(1),
2954 FIN, DAG.getSrcValue(NULL), DAG.getValueType(StoreVT));
2958 /// EmitFastCCToFastCCTailCall - Given a tailcall in the tail position to a
2959 /// fastcc function from a fastcc function, emit the code to emit a 'proper'
2961 void ISel::EmitFastCCToFastCCTailCall(SDNode *TailCallNode) {
2962 unsigned CalleeCallArgSize =
2963 cast<ConstantSDNode>(TailCallNode->getOperand(2))->getValue();
2964 unsigned CallerArgSize = X86Lowering.getBytesToPopOnReturn();
2966 //std::cerr << "****\n*** EMITTING TAIL CALL!\n****\n";
2968 // Adjust argument stores. Instead of storing to [ESP], f.e., store to frame
2969 // indexes that are relative to the incoming ESP. If the incoming and
2970 // outgoing arg sizes are the same we will store to [InESP] instead of
2971 // [CurESP] and the ESP referenced will be relative to the incoming function
2973 int ESPOffset = CallerArgSize-CalleeCallArgSize;
2974 SDOperand AdjustedArgStores =
2975 GetAdjustedArgumentStores(TailCallNode->getOperand(0), ESPOffset, *TheDAG);
2977 // Copy the return address of the caller into a virtual register so we don't
2979 SDOperand RetVal(0, 0);
2981 SDOperand RetValAddr = X86Lowering.getReturnAddressFrameIndex(*TheDAG);
2982 RetVal = TheDAG->getLoad(MVT::i32, TheDAG->getEntryNode(),
2983 RetValAddr, TheDAG->getSrcValue(NULL));
2987 // Codegen all of the argument stores.
2988 Select(AdjustedArgStores);
2991 // Emit a store of the saved ret value to the new location.
2992 MachineFunction &MF = TheDAG->getMachineFunction();
2993 int ReturnAddrFI = MF.getFrameInfo()->CreateFixedObject(4, ESPOffset-4);
2994 SDOperand RetValAddr = TheDAG->getFrameIndex(ReturnAddrFI, MVT::i32);
2995 Select(TheDAG->getNode(ISD::STORE, MVT::Other, TheDAG->getEntryNode(),
2996 RetVal, RetValAddr));
2999 // Get the destination value.
3000 SDOperand Callee = TailCallNode->getOperand(1);
3001 bool isDirect = isa<GlobalAddressSDNode>(Callee) ||
3002 isa<ExternalSymbolSDNode>(Callee);
3003 unsigned CalleeReg = 0;
3005 // If this is not a direct tail call, evaluate the callee's address.
3006 CalleeReg = SelectExpr(Callee);
3009 unsigned RegOp1 = 0;
3010 unsigned RegOp2 = 0;
3012 if (TailCallNode->getNumOperands() > 4) {
3013 // The first value is passed in (a part of) EAX, the second in EDX.
3014 RegOp1 = SelectExpr(TailCallNode->getOperand(4));
3015 if (TailCallNode->getNumOperands() > 5)
3016 RegOp2 = SelectExpr(TailCallNode->getOperand(5));
3018 switch (TailCallNode->getOperand(4).getValueType()) {
3019 default: assert(0 && "Bad thing to pass in regs");
3022 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(RegOp1);
3026 BuildMI(BB, X86::MOV16rr, 1,X86::AX).addReg(RegOp1);
3030 BuildMI(BB, X86::MOV32rr, 1,X86::EAX).addReg(RegOp1);
3035 switch (TailCallNode->getOperand(5).getValueType()) {
3036 default: assert(0 && "Bad thing to pass in regs");
3039 BuildMI(BB, X86::MOV8rr, 1, X86::DL).addReg(RegOp2);
3043 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(RegOp2);
3047 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RegOp2);
3053 // If this is not a direct tail call, put the callee's address into ECX.
3054 // The address has to be evaluated into a non-callee save register that is
3055 // not used for arguments. This means either ECX, as EAX and EDX may be
3056 // used for argument passing. We do this here to make sure that the
3057 // expressions for arguments and callee are all evaluated before the copies
3058 // into physical registers.
3060 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CalleeReg);
3064 BuildMI(BB, X86::ADJSTACKPTRri, 2,
3065 X86::ESP).addReg(X86::ESP).addImm(ESPOffset);
3067 // TODO: handle jmp [mem]
3069 BuildMI(BB, X86::TAILJMPr, 1).addReg(X86::ECX);
3070 } else if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Callee)){
3071 BuildMI(BB, X86::TAILJMPd, 1).addGlobalAddress(GASD->getGlobal(), true);
3073 ExternalSymbolSDNode *ESSDN = cast<ExternalSymbolSDNode>(Callee);
3074 BuildMI(BB, X86::TAILJMPd, 1).addExternalSymbol(ESSDN->getSymbol(), true);
3076 // ADD IMPLICIT USE RegOp1/RegOp2's
3080 void ISel::Select(SDOperand N) {
3081 unsigned Tmp1 = 0, Tmp2 = 0, Opc = 0;
3083 if (!ExprMap.insert(std::make_pair(N, 1)).second)
3084 return; // Already selected.
3086 SDNode *Node = N.Val;
3088 switch (Node->getOpcode()) {
3090 Node->dump(); std::cerr << "\n";
3091 assert(0 && "Node not handled yet!");
3092 case X86ISD::RDTSC_DAG:
3093 Select(Node->getOperand(0)); //Chain
3094 BuildMI(BB, X86::RDTSC, 0);
3097 case ISD::EntryToken: return; // Noop
3098 case ISD::TokenFactor:
3099 if (Node->getNumOperands() == 2) {
3101 getRegPressure(Node->getOperand(1))>getRegPressure(Node->getOperand(0));
3102 Select(Node->getOperand(OneFirst));
3103 Select(Node->getOperand(!OneFirst));
3105 std::vector<std::pair<unsigned, unsigned> > OpsP;
3106 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
3107 OpsP.push_back(std::make_pair(getRegPressure(Node->getOperand(i)), i));
3108 std::sort(OpsP.begin(), OpsP.end());
3109 std::reverse(OpsP.begin(), OpsP.end());
3110 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
3111 Select(Node->getOperand(OpsP[i].second));
3114 case ISD::CopyToReg:
3115 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
3116 Select(N.getOperand(0));
3117 Tmp1 = SelectExpr(N.getOperand(2));
3119 Tmp1 = SelectExpr(N.getOperand(2));
3120 Select(N.getOperand(0));
3122 Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3125 switch (N.getOperand(2).getValueType()) {
3126 default: assert(0 && "Invalid type for operation!");
3128 case MVT::i8: Opc = X86::MOV8rr; break;
3129 case MVT::i16: Opc = X86::MOV16rr; break;
3130 case MVT::i32: Opc = X86::MOV32rr; break;
3131 case MVT::f32: Opc = X86::MOVSSrr; break;
3137 ContainsFPCode = true;
3141 BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
3145 if (N.getOperand(0).getOpcode() == ISD::CALLSEQ_END ||
3146 N.getOperand(0).getOpcode() == X86ISD::TAILCALL ||
3147 N.getOperand(0).getOpcode() == ISD::TokenFactor)
3148 if (EmitPotentialTailCall(Node))
3151 switch (N.getNumOperands()) {
3153 assert(0 && "Unknown return instruction!");
3155 assert(N.getOperand(1).getValueType() == MVT::i32 &&
3156 N.getOperand(2).getValueType() == MVT::i32 &&
3157 "Unknown two-register value!");
3158 if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
3159 Tmp1 = SelectExpr(N.getOperand(1));
3160 Tmp2 = SelectExpr(N.getOperand(2));
3162 Tmp2 = SelectExpr(N.getOperand(2));
3163 Tmp1 = SelectExpr(N.getOperand(1));
3165 Select(N.getOperand(0));
3167 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
3168 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(Tmp2);
3171 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
3172 Select(N.getOperand(0));
3173 Tmp1 = SelectExpr(N.getOperand(1));
3175 Tmp1 = SelectExpr(N.getOperand(1));
3176 Select(N.getOperand(0));
3178 switch (N.getOperand(1).getValueType()) {
3179 default: assert(0 && "All other types should have been promoted!!");
3182 // Spill the value to memory and reload it into top of stack.
3183 unsigned Size = MVT::getSizeInBits(MVT::f32)/8;
3184 MachineFunction *F = BB->getParent();
3185 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
3186 addFrameReference(BuildMI(BB, X86::MOVSSmr, 5), FrameIdx).addReg(Tmp1);
3187 addFrameReference(BuildMI(BB, X86::FpLD32m, 4, X86::FP0), FrameIdx);
3188 BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0);
3189 ContainsFPCode = true;
3191 assert(0 && "MVT::f32 only legal with scalar sse fp");
3197 // Spill the value to memory and reload it into top of stack.
3198 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
3199 MachineFunction *F = BB->getParent();
3200 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
3201 addFrameReference(BuildMI(BB, X86::MOVSDmr, 5), FrameIdx).addReg(Tmp1);
3202 addFrameReference(BuildMI(BB, X86::FpLD64m, 4, X86::FP0), FrameIdx);
3203 BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0);
3204 ContainsFPCode = true;
3206 BuildMI(BB, X86::FpSETRESULT, 1).addReg(Tmp1);
3210 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
3215 Select(N.getOperand(0));
3218 if (X86Lowering.getBytesToPopOnReturn() == 0)
3219 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
3221 BuildMI(BB, X86::RETI, 1).addImm(X86Lowering.getBytesToPopOnReturn());
3224 Select(N.getOperand(0));
3225 MachineBasicBlock *Dest =
3226 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
3227 BuildMI(BB, X86::JMP, 1).addMBB(Dest);
3232 MachineBasicBlock *Dest =
3233 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
3235 // Try to fold a setcc into the branch. If this fails, emit a test/jne
3237 if (EmitBranchCC(Dest, N.getOperand(0), N.getOperand(1))) {
3238 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
3239 Select(N.getOperand(0));
3240 Tmp1 = SelectExpr(N.getOperand(1));
3242 Tmp1 = SelectExpr(N.getOperand(1));
3243 Select(N.getOperand(0));
3245 BuildMI(BB, X86::TEST8rr, 2).addReg(Tmp1).addReg(Tmp1);
3246 BuildMI(BB, X86::JNE, 1).addMBB(Dest);
3253 // If this load could be folded into the only using instruction, and if it
3254 // is safe to emit the instruction here, try to do so now.
3255 if (Node->hasNUsesOfValue(1, 0)) {
3256 SDOperand TheVal = N.getValue(0);
3258 for (SDNode::use_iterator UI = Node->use_begin(); ; ++UI) {
3259 assert(UI != Node->use_end() && "Didn't find use!");
3261 for (unsigned i = 0, e = UN->getNumOperands(); i != e; ++i)
3262 if (UN->getOperand(i) == TheVal) {
3268 // Only handle unary operators right now.
3269 if (User->getNumOperands() == 1) {
3271 SelectExpr(SDOperand(User, 0));
3282 case X86ISD::TAILCALL:
3287 case ISD::CopyFromReg:
3290 SelectExpr(N.getValue(0));
3293 case X86ISD::FP_TO_INT16_IN_MEM:
3294 case X86ISD::FP_TO_INT32_IN_MEM:
3295 case X86ISD::FP_TO_INT64_IN_MEM: {
3296 assert(N.getOperand(1).getValueType() == MVT::f64);
3298 Select(N.getOperand(0)); // Select the token chain
3301 if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
3302 ValReg = SelectExpr(N.getOperand(1));
3303 SelectAddress(N.getOperand(2), AM);
3305 SelectAddress(N.getOperand(2), AM);
3306 ValReg = SelectExpr(N.getOperand(1));
3309 // Change the floating point control register to use "round towards zero"
3310 // mode when truncating to an integer value.
3312 MachineFunction *F = BB->getParent();
3313 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
3314 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
3316 // Load the old value of the high byte of the control word...
3317 unsigned OldCW = MakeReg(MVT::i16);
3318 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
3320 // Set the high part to be round to zero...
3321 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
3323 // Reload the modified control word now...
3324 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
3326 // Restore the memory image of control word to original value
3327 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
3329 // Get the X86 opcode to use.
3330 switch (N.getOpcode()) {
3331 case X86ISD::FP_TO_INT16_IN_MEM: Tmp1 = X86::FpIST16m; break;
3332 case X86ISD::FP_TO_INT32_IN_MEM: Tmp1 = X86::FpIST32m; break;
3333 case X86ISD::FP_TO_INT64_IN_MEM: Tmp1 = X86::FpIST64m; break;
3336 addFullAddress(BuildMI(BB, Tmp1, 5), AM).addReg(ValReg);
3338 // Reload the original control word now.
3339 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
3343 case ISD::TRUNCSTORE: { // truncstore chain, val, ptr, SRCVALUE, storety
3345 MVT::ValueType StoredTy = cast<VTSDNode>(N.getOperand(4))->getVT();
3346 assert((StoredTy == MVT::i1 || StoredTy == MVT::f32 ||
3347 StoredTy == MVT::i16 /*FIXME: THIS IS JUST FOR TESTING!*/)
3348 && "Unsupported TRUNCSTORE for this target!");
3350 if (StoredTy == MVT::i16) {
3351 // FIXME: This is here just to allow testing. X86 doesn't really have a
3352 // TRUNCSTORE i16 operation, but this is required for targets that do not
3353 // have 16-bit integer registers. We occasionally disable 16-bit integer
3354 // registers to test the promotion code.
3355 Select(N.getOperand(0));
3356 Tmp1 = SelectExpr(N.getOperand(1));
3357 SelectAddress(N.getOperand(2), AM);
3359 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
3360 addFullAddress(BuildMI(BB, X86::MOV16mr, 5), AM).addReg(X86::AX);
3364 // Store of constant bool?
3365 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
3366 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
3367 Select(N.getOperand(0));
3368 SelectAddress(N.getOperand(2), AM);
3370 SelectAddress(N.getOperand(2), AM);
3371 Select(N.getOperand(0));
3373 addFullAddress(BuildMI(BB, X86::MOV8mi, 5), AM).addImm(CN->getValue());
3378 default: assert(0 && "Cannot truncstore this type!");
3379 case MVT::i1: Opc = X86::MOV8mr; break;
3381 assert(!X86ScalarSSE && "Cannot truncstore scalar SSE regs");
3382 Opc = X86::FpST32m; break;
3385 std::vector<std::pair<unsigned, unsigned> > RP;
3386 RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
3387 RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
3388 RP.push_back(std::make_pair(getRegPressure(N.getOperand(2)), 2));
3389 std::sort(RP.begin(), RP.end());
3391 Tmp1 = 0; // Silence a warning.
3392 for (unsigned i = 0; i != 3; ++i)
3393 switch (RP[2-i].second) {
3394 default: assert(0 && "Unknown operand number!");
3395 case 0: Select(N.getOperand(0)); break;
3396 case 1: Tmp1 = SelectExpr(N.getOperand(1)); break;
3397 case 2: SelectAddress(N.getOperand(2), AM); break;
3400 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Tmp1);
3406 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
3408 switch (CN->getValueType(0)) {
3409 default: assert(0 && "Invalid type for operation!");
3411 case MVT::i8: Opc = X86::MOV8mi; break;
3412 case MVT::i16: Opc = X86::MOV16mi; break;
3413 case MVT::i32: Opc = X86::MOV32mi; break;
3416 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
3417 Select(N.getOperand(0));
3418 SelectAddress(N.getOperand(2), AM);
3420 SelectAddress(N.getOperand(2), AM);
3421 Select(N.getOperand(0));
3423 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addImm(CN->getValue());
3426 } else if (GlobalAddressSDNode *GA =
3427 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
3428 assert(GA->getValueType(0) == MVT::i32 && "Bad pointer operand");
3430 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
3431 Select(N.getOperand(0));
3432 SelectAddress(N.getOperand(2), AM);
3434 SelectAddress(N.getOperand(2), AM);
3435 Select(N.getOperand(0));
3437 GlobalValue *GV = GA->getGlobal();
3438 // For Darwin, external and weak symbols are indirect, so we want to load
3439 // the value at address GV, not the value of GV itself.
3440 if (Subtarget->getIndirectExternAndWeakGlobals() &&
3441 (GV->hasWeakLinkage() || GV->isExternal())) {
3442 Tmp1 = MakeReg(MVT::i32);
3443 BuildMI(BB, X86::MOV32rm, 4, Tmp1).addReg(0).addZImm(1).addReg(0)
3444 .addGlobalAddress(GV, false, 0);
3445 addFullAddress(BuildMI(BB, X86::MOV32mr, 4+1),AM).addReg(Tmp1);
3447 addFullAddress(BuildMI(BB, X86::MOV32mi, 4+1),AM).addGlobalAddress(GV);
3452 // Check to see if this is a load/op/store combination.
3453 if (TryToFoldLoadOpStore(Node))
3456 switch (N.getOperand(1).getValueType()) {
3457 default: assert(0 && "Cannot store this type!");
3459 case MVT::i8: Opc = X86::MOV8mr; break;
3460 case MVT::i16: Opc = X86::MOV16mr; break;
3461 case MVT::i32: Opc = X86::MOV32mr; break;
3462 case MVT::f32: Opc = X86::MOVSSmr; break;
3463 case MVT::f64: Opc = X86ScalarSSE ? X86::MOVSDmr : X86::FpST64m; break;
3466 std::vector<std::pair<unsigned, unsigned> > RP;
3467 RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
3468 RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
3469 RP.push_back(std::make_pair(getRegPressure(N.getOperand(2)), 2));
3470 std::sort(RP.begin(), RP.end());
3472 Tmp1 = 0; // Silence a warning.
3473 for (unsigned i = 0; i != 3; ++i)
3474 switch (RP[2-i].second) {
3475 default: assert(0 && "Unknown operand number!");
3476 case 0: Select(N.getOperand(0)); break;
3477 case 1: Tmp1 = SelectExpr(N.getOperand(1)); break;
3478 case 2: SelectAddress(N.getOperand(2), AM); break;
3481 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Tmp1);
3484 case ISD::CALLSEQ_START:
3485 Select(N.getOperand(0));
3487 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
3488 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(Tmp1);
3490 case ISD::CALLSEQ_END:
3491 Select(N.getOperand(0));
3494 Select(N.getOperand(0)); // Select the chain.
3496 (unsigned)cast<ConstantSDNode>(Node->getOperand(4))->getValue();
3497 if (Align == 0) Align = 1;
3499 // Turn the byte code into # iterations
3502 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
3503 unsigned Val = ValC->getValue() & 255;
3505 // If the value is a constant, then we can potentially use larger sets.
3506 switch (Align & 3) {
3507 case 2: // WORD aligned
3508 CountReg = MakeReg(MVT::i32);
3509 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3510 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/2);
3512 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3513 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
3515 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
3516 Opcode = X86::REP_STOSW;
3518 case 0: // DWORD aligned
3519 CountReg = MakeReg(MVT::i32);
3520 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3521 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/4);
3523 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3524 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
3526 Val = (Val << 8) | Val;
3527 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
3528 Opcode = X86::REP_STOSD;
3530 default: // BYTE aligned
3531 CountReg = SelectExpr(Node->getOperand(3));
3532 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
3533 Opcode = X86::REP_STOSB;
3537 // If it's not a constant value we are storing, just fall back. We could
3538 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
3539 unsigned ValReg = SelectExpr(Node->getOperand(2));
3540 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
3541 CountReg = SelectExpr(Node->getOperand(3));
3542 Opcode = X86::REP_STOSB;
3545 // No matter what the alignment is, we put the destination in EDI, and the
3547 unsigned TmpReg1 = SelectExpr(Node->getOperand(1));
3548 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
3549 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
3550 BuildMI(BB, Opcode, 0);
3554 Select(N.getOperand(0)); // Select the chain.
3556 (unsigned)cast<ConstantSDNode>(Node->getOperand(4))->getValue();
3557 if (Align == 0) Align = 1;
3559 // Turn the byte code into # iterations
3562 switch (Align & 3) {
3563 case 2: // WORD aligned
3564 CountReg = MakeReg(MVT::i32);
3565 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3566 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/2);
3568 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3569 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
3571 Opcode = X86::REP_MOVSW;
3573 case 0: // DWORD aligned
3574 CountReg = MakeReg(MVT::i32);
3575 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3576 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/4);
3578 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3579 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
3581 Opcode = X86::REP_MOVSD;
3583 default: // BYTE aligned
3584 CountReg = SelectExpr(Node->getOperand(3));
3585 Opcode = X86::REP_MOVSB;
3589 // No matter what the alignment is, we put the source in ESI, the
3590 // destination in EDI, and the count in ECX.
3591 unsigned TmpReg1 = SelectExpr(Node->getOperand(1));
3592 unsigned TmpReg2 = SelectExpr(Node->getOperand(2));
3593 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
3594 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
3595 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
3596 BuildMI(BB, Opcode, 0);
3599 case ISD::WRITEPORT:
3600 if (Node->getOperand(2).getValueType() != MVT::i16) {
3601 std::cerr << "llvm.writeport: Address size is not 16 bits\n";
3604 Select(Node->getOperand(0)); // Emit the chain.
3606 Tmp1 = SelectExpr(Node->getOperand(1));
3607 switch (Node->getOperand(1).getValueType()) {
3609 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(Tmp1);
3610 Tmp2 = X86::OUT8ir; Opc = X86::OUT8rr;
3613 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(Tmp1);
3614 Tmp2 = X86::OUT16ir; Opc = X86::OUT16rr;
3617 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
3618 Tmp2 = X86::OUT32ir; Opc = X86::OUT32rr;
3621 std::cerr << "llvm.writeport: invalid data type for X86 target";
3625 // If the port is a single-byte constant, use the immediate form.
3626 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node->getOperand(2)))
3627 if ((CN->getValue() & 255) == CN->getValue()) {
3628 BuildMI(BB, Tmp2, 1).addImm(CN->getValue());
3632 // Otherwise, move the I/O port address into the DX register.
3633 unsigned Reg = SelectExpr(Node->getOperand(2));
3634 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
3635 BuildMI(BB, Opc, 0);
3638 assert(0 && "Should not be reached!");
3642 /// createX86ISelPattern - This pass converts an LLVM function
3643 /// into a machine code representation using pattern matching and a machine
3644 /// description file.
3646 FunctionPass *llvm::createX86ISelPattern(TargetMachine &TM) {
3647 return new ISel(TM);