1 //===-- X86ISelPattern.cpp - A pattern matching inst selector for X86 -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for X86.
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86RegisterInfo.h"
17 #include "llvm/Constants.h" // FIXME: REMOVE
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/ADT/Statistic.h"
33 //===----------------------------------------------------------------------===//
34 // X86TargetLowering - X86 Implementation of the TargetLowering interface
36 class X86TargetLowering : public TargetLowering {
37 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
38 int ReturnAddrIndex; // FrameIndex for return slot.
40 X86TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
43 // X86 is wierd, it always uses i8 for shift amounts and setcc results.
44 setShiftAmountType(MVT::i8);
45 setSetCCResultType(MVT::i8);
46 setSetCCResultContents(ZeroOrOneSetCCResult);
47 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
49 // Set up the register classes.
50 addRegisterClass(MVT::i8, X86::R8RegisterClass);
51 addRegisterClass(MVT::i16, X86::R16RegisterClass);
52 addRegisterClass(MVT::i32, X86::R32RegisterClass);
53 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
55 // FIXME: Eliminate these two classes when legalize can handle promotions
57 /**/ addRegisterClass(MVT::i1, X86::R8RegisterClass);
59 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
60 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
61 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
62 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
63 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
64 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
65 setOperationAction(ISD::SREM , MVT::f64 , Expand);
67 // These should be promoted to a larger select which is supported.
68 /**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
69 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
71 computeRegisterProperties();
73 addLegalFPImmediate(+0.0); // FLD0
74 addLegalFPImmediate(+1.0); // FLD1
75 addLegalFPImmediate(-0.0); // FLD0/FCHS
76 addLegalFPImmediate(-1.0); // FLD1/FCHS
79 /// LowerArguments - This hook must be implemented to indicate how we should
80 /// lower the arguments for the specified function, into the specified DAG.
81 virtual std::vector<SDOperand>
82 LowerArguments(Function &F, SelectionDAG &DAG);
84 /// LowerCallTo - This hook lowers an abstract call to a function into an
86 virtual std::pair<SDOperand, SDOperand>
87 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
88 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
90 virtual std::pair<SDOperand, SDOperand>
91 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
93 virtual std::pair<SDOperand,SDOperand>
94 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
95 const Type *ArgTy, SelectionDAG &DAG);
97 virtual std::pair<SDOperand, SDOperand>
98 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
104 std::vector<SDOperand>
105 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
106 std::vector<SDOperand> ArgValues;
108 // Add DAG nodes to load the arguments... On entry to a function on the X86,
109 // the stack frame looks like this:
111 // [ESP] -- return address
112 // [ESP + 4] -- first argument (leftmost lexically)
113 // [ESP + 8] -- second argument, if first argument is four bytes in size
116 MachineFunction &MF = DAG.getMachineFunction();
117 MachineFrameInfo *MFI = MF.getFrameInfo();
119 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
120 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
121 MVT::ValueType ObjectVT = getValueType(I->getType());
122 unsigned ArgIncrement = 4;
125 default: assert(0 && "Unhandled argument type!");
127 case MVT::i8: ObjSize = 1; break;
128 case MVT::i16: ObjSize = 2; break;
129 case MVT::i32: ObjSize = 4; break;
130 case MVT::i64: ObjSize = ArgIncrement = 8; break;
131 case MVT::f32: ObjSize = 4; break;
132 case MVT::f64: ObjSize = ArgIncrement = 8; break;
134 // Create the frame index object for this incoming parameter...
135 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
137 // Create the SelectionDAG nodes corresponding to a load from this parameter
138 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
140 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
144 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
146 if (MVT::isInteger(ObjectVT))
147 ArgValue = DAG.getConstant(0, ObjectVT);
149 ArgValue = DAG.getConstantFP(0, ObjectVT);
151 ArgValues.push_back(ArgValue);
153 ArgOffset += ArgIncrement; // Move on to the next argument...
156 // If the function takes variable number of arguments, make a frame index for
157 // the start of the first vararg value... for expansion of llvm.va_start.
159 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
160 ReturnAddrIndex = 0; // No return address slot generated yet.
162 // Finally, inform the code generator which regs we return values in.
163 switch (getValueType(F.getReturnType())) {
164 default: assert(0 && "Unknown type!");
165 case MVT::isVoid: break;
170 MF.addLiveOut(X86::EAX);
173 MF.addLiveOut(X86::EAX);
174 MF.addLiveOut(X86::EDX);
178 MF.addLiveOut(X86::ST0);
184 std::pair<SDOperand, SDOperand>
185 X86TargetLowering::LowerCallTo(SDOperand Chain,
186 const Type *RetTy, bool isVarArg,
187 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
188 // Count how many bytes are to be pushed on the stack.
189 unsigned NumBytes = 0;
193 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
194 DAG.getConstant(0, getPointerTy()));
196 for (unsigned i = 0, e = Args.size(); i != e; ++i)
197 switch (getValueType(Args[i].second)) {
198 default: assert(0 && "Unknown value type!");
212 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
213 DAG.getConstant(NumBytes, getPointerTy()));
215 // Arguments go on the stack in reverse order, as specified by the ABI.
216 unsigned ArgOffset = 0;
217 SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32,
219 std::vector<SDOperand> Stores;
221 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
223 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
224 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
226 switch (getValueType(Args[i].second)) {
227 default: assert(0 && "Unexpected ValueType for argument!");
231 // Promote the integer to 32 bits. If the input type is signed use a
232 // sign extend, otherwise use a zero extend.
233 if (Args[i].second->isSigned())
234 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
236 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
241 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
242 Args[i].first, PtrOff));
247 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
248 Args[i].first, PtrOff));
253 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
256 std::vector<MVT::ValueType> RetVals;
257 MVT::ValueType RetTyVT = getValueType(RetTy);
258 if (RetTyVT != MVT::isVoid)
259 RetVals.push_back(RetTyVT);
260 RetVals.push_back(MVT::Other);
262 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain, Callee), 0);
263 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
264 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
265 DAG.getConstant(NumBytes, getPointerTy()));
266 return std::make_pair(TheCall, Chain);
269 std::pair<SDOperand, SDOperand>
270 X86TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
271 // vastart just returns the address of the VarArgsFrameIndex slot.
272 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
275 std::pair<SDOperand,SDOperand> X86TargetLowering::
276 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
277 const Type *ArgTy, SelectionDAG &DAG) {
278 MVT::ValueType ArgVT = getValueType(ArgTy);
281 Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
284 if (ArgVT == MVT::i32)
287 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
288 "Other types should have been promoted for varargs!");
291 Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
292 DAG.getConstant(Amt, VAList.getValueType()));
294 return std::make_pair(Result, Chain);
298 std::pair<SDOperand, SDOperand> X86TargetLowering::
299 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
302 if (Depth) // Depths > 0 not supported yet!
303 Result = DAG.getConstant(0, getPointerTy());
305 if (ReturnAddrIndex == 0) {
306 // Set up a frame object for the return address.
307 MachineFunction &MF = DAG.getMachineFunction();
308 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
311 SDOperand RetAddrFI = DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
314 // Just load the return address
315 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI);
317 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
318 DAG.getConstant(4, MVT::i32));
320 return std::make_pair(Result, Chain);
325 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
326 /// SDOperand's instead of register numbers for the leaves of the matched
328 struct X86ISelAddressMode {
334 struct { // This is really a union, discriminated by BaseType!
345 : BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
353 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
355 //===--------------------------------------------------------------------===//
356 /// ISel - X86 specific code to select X86 machine instructions for
357 /// SelectionDAG operations.
359 class ISel : public SelectionDAGISel {
360 /// ContainsFPCode - Every instruction we select that uses or defines a FP
361 /// register should set this to true.
364 /// X86Lowering - This object fully describes how to lower LLVM code to an
365 /// X86-specific SelectionDAG.
366 X86TargetLowering X86Lowering;
368 /// RegPressureMap - This keeps an approximate count of the number of
369 /// registers required to evaluate each node in the graph.
370 std::map<SDNode*, unsigned> RegPressureMap;
372 /// ExprMap - As shared expressions are codegen'd, we keep track of which
373 /// vreg the value is produced in, so we only emit one copy of each compiled
375 std::map<SDOperand, unsigned> ExprMap;
378 ISel(TargetMachine &TM) : SelectionDAGISel(X86Lowering), X86Lowering(TM) {
381 virtual const char *getPassName() const {
382 return "X86 Pattern Instruction Selection";
385 unsigned getRegPressure(SDOperand O) {
386 return RegPressureMap[O.Val];
388 unsigned ComputeRegPressure(SDOperand O);
390 /// InstructionSelectBasicBlock - This callback is invoked by
391 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
392 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
394 bool isFoldableLoad(SDOperand Op, SDOperand OtherOp,
395 bool FloatPromoteOk = false);
396 void EmitFoldedLoad(SDOperand Op, X86AddressMode &AM);
397 bool TryToFoldLoadOpStore(SDNode *Node);
399 bool EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg);
400 void EmitCMP(SDOperand LHS, SDOperand RHS, bool isOnlyUse);
401 bool EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain, SDOperand Cond);
402 void EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
403 unsigned RTrue, unsigned RFalse, unsigned RDest);
404 unsigned SelectExpr(SDOperand N);
406 X86AddressMode SelectAddrExprs(const X86ISelAddressMode &IAM);
407 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
408 void SelectAddress(SDOperand N, X86AddressMode &AM);
409 void Select(SDOperand N);
413 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
414 /// when it has created a SelectionDAG for us to codegen.
415 void ISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
416 // While we're doing this, keep track of whether we see any FP code for
417 // FP_REG_KILL insertion.
418 ContainsFPCode = false;
420 // Scan the PHI nodes that already are inserted into this basic block. If any
421 // of them is a PHI of a floating point value, we need to insert an
423 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
424 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
426 assert(I->getOpcode() == X86::PHI &&
427 "Isn't just PHI nodes?");
428 if (RegMap->getRegClass(I->getOperand(0).getReg()) ==
429 X86::RFPRegisterClass) {
430 ContainsFPCode = true;
435 // Compute the RegPressureMap, which is an approximation for the number of
436 // registers required to compute each node.
437 ComputeRegPressure(DAG.getRoot());
439 // Codegen the basic block.
440 Select(DAG.getRoot());
442 // Finally, look at all of the successors of this block. If any contain a PHI
443 // node of FP type, we need to insert an FP_REG_KILL in this block.
444 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
445 E = BB->succ_end(); SI != E && !ContainsFPCode; ++SI)
446 for (MachineBasicBlock::iterator I = (*SI)->begin(), E = (*SI)->end();
447 I != E && I->getOpcode() == X86::PHI; ++I) {
448 if (RegMap->getRegClass(I->getOperand(0).getReg()) ==
449 X86::RFPRegisterClass) {
450 ContainsFPCode = true;
455 // Insert FP_REG_KILL instructions into basic blocks that need them. This
456 // only occurs due to the floating point stackifier not being aggressive
457 // enough to handle arbitrary global stackification.
459 // Currently we insert an FP_REG_KILL instruction into each block that uses or
460 // defines a floating point virtual register.
462 // When the global register allocators (like linear scan) finally update live
463 // variable analysis, we can keep floating point values in registers across
464 // basic blocks. This will be a huge win, but we are waiting on the global
465 // allocators before we can do this.
467 if (ContainsFPCode) {
468 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
472 // Clear state used for selection.
474 RegPressureMap.clear();
478 // ComputeRegPressure - Compute the RegPressureMap, which is an approximation
479 // for the number of registers required to compute each node. This is basically
480 // computing a generalized form of the Sethi-Ullman number for each node.
481 unsigned ISel::ComputeRegPressure(SDOperand O) {
483 unsigned &Result = RegPressureMap[N];
484 if (Result) return Result;
486 // FIXME: Should operations like CALL (which clobber lots o regs) have a
487 // higher fixed cost??
489 if (N->getNumOperands() == 0) {
492 unsigned MaxRegUse = 0;
493 unsigned NumExtraMaxRegUsers = 0;
494 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
496 if (N->getOperand(i).getOpcode() == ISD::Constant)
499 Regs = ComputeRegPressure(N->getOperand(i));
500 if (Regs > MaxRegUse) {
502 NumExtraMaxRegUsers = 0;
503 } else if (Regs == MaxRegUse &&
504 N->getOperand(i).getValueType() != MVT::Other) {
505 ++NumExtraMaxRegUsers;
509 if (O.getOpcode() != ISD::TokenFactor)
510 Result = MaxRegUse+NumExtraMaxRegUsers;
512 Result = MaxRegUse == 1 ? 0 : MaxRegUse-1;
515 //std::cerr << " WEIGHT: " << Result << " "; N->dump(); std::cerr << "\n";
519 /// NodeTransitivelyUsesValue - Return true if N or any of its uses uses Op.
520 /// The DAG cannot have cycles in it, by definition, so the visited set is not
521 /// needed to prevent infinite loops. The DAG CAN, however, have unbounded
522 /// reuse, so it prevents exponential cases.
524 static bool NodeTransitivelyUsesValue(SDOperand N, SDOperand Op,
525 std::set<SDNode*> &Visited) {
526 if (N == Op) return true; // Found it.
527 SDNode *Node = N.Val;
528 if (Node->getNumOperands() == 0 || // Leaf?
529 Node->getNodeDepth() <= Op.getNodeDepth()) return false; // Can't find it?
530 if (!Visited.insert(Node).second) return false; // Already visited?
532 // Recurse for the first N-1 operands.
533 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
534 if (NodeTransitivelyUsesValue(Node->getOperand(i), Op, Visited))
537 // Tail recurse for the last operand.
538 return NodeTransitivelyUsesValue(Node->getOperand(0), Op, Visited);
541 X86AddressMode ISel::SelectAddrExprs(const X86ISelAddressMode &IAM) {
542 X86AddressMode Result;
544 // If we need to emit two register operands, emit the one with the highest
545 // register pressure first.
546 if (IAM.BaseType == X86ISelAddressMode::RegBase &&
547 IAM.Base.Reg.Val && IAM.IndexReg.Val) {
548 bool EmitBaseThenIndex;
549 if (getRegPressure(IAM.Base.Reg) > getRegPressure(IAM.IndexReg)) {
550 std::set<SDNode*> Visited;
551 EmitBaseThenIndex = true;
552 // If Base ends up pointing to Index, we must emit index first. This is
553 // because of the way we fold loads, we may end up doing bad things with
555 if (NodeTransitivelyUsesValue(IAM.Base.Reg, IAM.IndexReg, Visited))
556 EmitBaseThenIndex = false;
558 std::set<SDNode*> Visited;
559 EmitBaseThenIndex = false;
560 // If Base ends up pointing to Index, we must emit index first. This is
561 // because of the way we fold loads, we may end up doing bad things with
563 if (NodeTransitivelyUsesValue(IAM.IndexReg, IAM.Base.Reg, Visited))
564 EmitBaseThenIndex = true;
567 if (EmitBaseThenIndex) {
568 Result.Base.Reg = SelectExpr(IAM.Base.Reg);
569 Result.IndexReg = SelectExpr(IAM.IndexReg);
571 Result.IndexReg = SelectExpr(IAM.IndexReg);
572 Result.Base.Reg = SelectExpr(IAM.Base.Reg);
575 } else if (IAM.BaseType == X86ISelAddressMode::RegBase && IAM.Base.Reg.Val) {
576 Result.Base.Reg = SelectExpr(IAM.Base.Reg);
577 } else if (IAM.IndexReg.Val) {
578 Result.IndexReg = SelectExpr(IAM.IndexReg);
581 switch (IAM.BaseType) {
582 case X86ISelAddressMode::RegBase:
583 Result.BaseType = X86AddressMode::RegBase;
585 case X86ISelAddressMode::FrameIndexBase:
586 Result.BaseType = X86AddressMode::FrameIndexBase;
587 Result.Base.FrameIndex = IAM.Base.FrameIndex;
590 assert(0 && "Unknown base type!");
593 Result.Scale = IAM.Scale;
594 Result.Disp = IAM.Disp;
599 /// SelectAddress - Pattern match the maximal addressing mode for this node and
600 /// emit all of the leaf registers.
601 void ISel::SelectAddress(SDOperand N, X86AddressMode &AM) {
602 X86ISelAddressMode IAM;
603 MatchAddress(N, IAM);
604 AM = SelectAddrExprs(IAM);
607 /// MatchAddress - Add the specified node to the specified addressing mode,
608 /// returning true if it cannot be done. This just pattern matches for the
609 /// addressing mode, it does not cause any code to be emitted. For that, use
611 bool ISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
612 switch (N.getOpcode()) {
614 case ISD::FrameIndex:
615 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
616 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
617 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
621 case ISD::GlobalAddress:
623 AM.GV = cast<GlobalAddressSDNode>(N)->getGlobal();
628 AM.Disp += cast<ConstantSDNode>(N)->getValue();
631 // We might have folded the load into this shift, so don't regen the value
633 if (ExprMap.count(N)) break;
635 if (AM.IndexReg.Val == 0 && AM.Scale == 1)
636 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
637 unsigned Val = CN->getValue();
638 if (Val == 1 || Val == 2 || Val == 3) {
640 SDOperand ShVal = N.Val->getOperand(0);
642 // Okay, we know that we have a scale by now. However, if the scaled
643 // value is an add of something and a constant, we can fold the
644 // constant into the disp field here.
645 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
646 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
647 AM.IndexReg = ShVal.Val->getOperand(0);
648 ConstantSDNode *AddVal =
649 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
650 AM.Disp += AddVal->getValue() << Val;
659 // We might have folded the load into this mul, so don't regen the value if
661 if (ExprMap.count(N)) break;
663 // X*[3,5,9] -> X+X*[2,4,8]
664 if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
665 AM.Base.Reg.Val == 0)
666 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
667 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
668 AM.Scale = unsigned(CN->getValue())-1;
670 SDOperand MulVal = N.Val->getOperand(0);
673 // Okay, we know that we have a scale by now. However, if the scaled
674 // value is an add of something and a constant, we can fold the
675 // constant into the disp field here.
676 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
677 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
678 Reg = MulVal.Val->getOperand(0);
679 ConstantSDNode *AddVal =
680 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
681 AM.Disp += AddVal->getValue() * CN->getValue();
683 Reg = N.Val->getOperand(0);
686 AM.IndexReg = AM.Base.Reg = Reg;
692 // We might have folded the load into this mul, so don't regen the value if
694 if (ExprMap.count(N)) break;
696 X86ISelAddressMode Backup = AM;
697 if (!MatchAddress(N.Val->getOperand(0), AM) &&
698 !MatchAddress(N.Val->getOperand(1), AM))
701 if (!MatchAddress(N.Val->getOperand(1), AM) &&
702 !MatchAddress(N.Val->getOperand(0), AM))
709 // Is the base register already occupied?
710 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
711 // If so, check to see if the scale index register is set.
712 if (AM.IndexReg.Val == 0) {
718 // Otherwise, we cannot select it.
722 // Default, generate it as a register.
723 AM.BaseType = X86ISelAddressMode::RegBase;
728 /// Emit2SetCCsAndLogical - Emit the following sequence of instructions,
729 /// assuming that the temporary registers are in the 8-bit register class.
733 /// DestReg = logicalop Tmp1, Tmp2
735 static void Emit2SetCCsAndLogical(MachineBasicBlock *BB, unsigned SetCC1,
736 unsigned SetCC2, unsigned LogicalOp,
738 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
739 unsigned Tmp1 = RegMap->createVirtualRegister(X86::R8RegisterClass);
740 unsigned Tmp2 = RegMap->createVirtualRegister(X86::R8RegisterClass);
741 BuildMI(BB, SetCC1, 0, Tmp1);
742 BuildMI(BB, SetCC2, 0, Tmp2);
743 BuildMI(BB, LogicalOp, 2, DestReg).addReg(Tmp1).addReg(Tmp2);
746 /// EmitSetCC - Emit the code to set the specified 8-bit register to 1 if the
747 /// condition codes match the specified SetCCOpcode. Note that some conditions
748 /// require multiple instructions to generate the correct value.
749 static void EmitSetCC(MachineBasicBlock *BB, unsigned DestReg,
750 ISD::CondCode SetCCOpcode, bool isFP) {
753 switch (SetCCOpcode) {
754 default: assert(0 && "Illegal integer SetCC!");
755 case ISD::SETEQ: Opc = X86::SETEr; break;
756 case ISD::SETGT: Opc = X86::SETGr; break;
757 case ISD::SETGE: Opc = X86::SETGEr; break;
758 case ISD::SETLT: Opc = X86::SETLr; break;
759 case ISD::SETLE: Opc = X86::SETLEr; break;
760 case ISD::SETNE: Opc = X86::SETNEr; break;
761 case ISD::SETULT: Opc = X86::SETBr; break;
762 case ISD::SETUGT: Opc = X86::SETAr; break;
763 case ISD::SETULE: Opc = X86::SETBEr; break;
764 case ISD::SETUGE: Opc = X86::SETAEr; break;
767 // On a floating point condition, the flags are set as follows:
771 // 1 | 0 | 0 | X == Y
772 // 1 | 1 | 1 | unordered
774 switch (SetCCOpcode) {
775 default: assert(0 && "Invalid FP setcc!");
778 Opc = X86::SETEr; // True if ZF = 1
782 Opc = X86::SETAr; // True if CF = 0 and ZF = 0
786 Opc = X86::SETAEr; // True if CF = 0
790 Opc = X86::SETBr; // True if CF = 1
794 Opc = X86::SETBEr; // True if CF = 1 or ZF = 1
798 Opc = X86::SETNEr; // True if ZF = 0
801 Opc = X86::SETPr; // True if PF = 1
804 Opc = X86::SETNPr; // True if PF = 0
806 case ISD::SETOEQ: // !PF & ZF
807 Emit2SetCCsAndLogical(BB, X86::SETNPr, X86::SETEr, X86::AND8rr, DestReg);
809 case ISD::SETOLT: // !PF & CF
810 Emit2SetCCsAndLogical(BB, X86::SETNPr, X86::SETBr, X86::AND8rr, DestReg);
812 case ISD::SETOLE: // !PF & (CF || ZF)
813 Emit2SetCCsAndLogical(BB, X86::SETNPr, X86::SETBEr, X86::AND8rr, DestReg);
815 case ISD::SETUGT: // PF | (!ZF & !CF)
816 Emit2SetCCsAndLogical(BB, X86::SETPr, X86::SETAr, X86::OR8rr, DestReg);
818 case ISD::SETUGE: // PF | !CF
819 Emit2SetCCsAndLogical(BB, X86::SETPr, X86::SETAEr, X86::OR8rr, DestReg);
821 case ISD::SETUNE: // PF | !ZF
822 Emit2SetCCsAndLogical(BB, X86::SETPr, X86::SETNEr, X86::OR8rr, DestReg);
826 BuildMI(BB, Opc, 0, DestReg);
830 /// EmitBranchCC - Emit code into BB that arranges for control to transfer to
831 /// the Dest block if the Cond condition is true. If we cannot fold this
832 /// condition into the branch, return true.
834 bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain,
836 // FIXME: Evaluate whether it would be good to emit code like (X < Y) | (A >
837 // B) using two conditional branches instead of one condbr, two setcc's, and
839 if ((Cond.getOpcode() == ISD::OR ||
840 Cond.getOpcode() == ISD::AND) && Cond.Val->hasOneUse()) {
841 // And and or set the flags for us, so there is no need to emit a TST of the
842 // result. It is only safe to do this if there is only a single use of the
843 // AND/OR though, otherwise we don't know it will be emitted here.
846 BuildMI(BB, X86::JNE, 1).addMBB(Dest);
850 // Codegen br not C -> JE.
851 if (Cond.getOpcode() == ISD::XOR)
852 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(Cond.Val->getOperand(1)))
853 if (NC->isAllOnesValue()) {
855 if (getRegPressure(Chain) > getRegPressure(Cond)) {
857 CondR = SelectExpr(Cond.Val->getOperand(0));
859 CondR = SelectExpr(Cond.Val->getOperand(0));
862 BuildMI(BB, X86::TEST8rr, 2).addReg(CondR).addReg(CondR);
863 BuildMI(BB, X86::JE, 1).addMBB(Dest);
867 SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Cond);
869 return true; // Can only handle simple setcc's so far.
873 // Handle integer conditions first.
874 if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
875 switch (SetCC->getCondition()) {
876 default: assert(0 && "Illegal integer SetCC!");
877 case ISD::SETEQ: Opc = X86::JE; break;
878 case ISD::SETGT: Opc = X86::JG; break;
879 case ISD::SETGE: Opc = X86::JGE; break;
880 case ISD::SETLT: Opc = X86::JL; break;
881 case ISD::SETLE: Opc = X86::JLE; break;
882 case ISD::SETNE: Opc = X86::JNE; break;
883 case ISD::SETULT: Opc = X86::JB; break;
884 case ISD::SETUGT: Opc = X86::JA; break;
885 case ISD::SETULE: Opc = X86::JBE; break;
886 case ISD::SETUGE: Opc = X86::JAE; break;
889 EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1), SetCC->hasOneUse());
890 BuildMI(BB, Opc, 1).addMBB(Dest);
894 unsigned Opc2 = 0; // Second branch if needed.
896 // On a floating point condition, the flags are set as follows:
900 // 1 | 0 | 0 | X == Y
901 // 1 | 1 | 1 | unordered
903 switch (SetCC->getCondition()) {
904 default: assert(0 && "Invalid FP setcc!");
906 case ISD::SETEQ: Opc = X86::JE; break; // True if ZF = 1
908 case ISD::SETGT: Opc = X86::JA; break; // True if CF = 0 and ZF = 0
910 case ISD::SETGE: Opc = X86::JAE; break; // True if CF = 0
912 case ISD::SETLT: Opc = X86::JB; break; // True if CF = 1
914 case ISD::SETLE: Opc = X86::JBE; break; // True if CF = 1 or ZF = 1
916 case ISD::SETNE: Opc = X86::JNE; break; // True if ZF = 0
917 case ISD::SETUO: Opc = X86::JP; break; // True if PF = 1
918 case ISD::SETO: Opc = X86::JNP; break; // True if PF = 0
919 case ISD::SETUGT: // PF = 1 | (ZF = 0 & CF = 0)
920 Opc = X86::JA; // ZF = 0 & CF = 0
921 Opc2 = X86::JP; // PF = 1
923 case ISD::SETUGE: // PF = 1 | CF = 0
924 Opc = X86::JAE; // CF = 0
925 Opc2 = X86::JP; // PF = 1
927 case ISD::SETUNE: // PF = 1 | ZF = 0
928 Opc = X86::JNE; // ZF = 0
929 Opc2 = X86::JP; // PF = 1
931 case ISD::SETOEQ: // PF = 0 & ZF = 1
934 return true; // FIXME: Emit more efficient code for this branch.
935 case ISD::SETOLT: // PF = 0 & CF = 1
938 return true; // FIXME: Emit more efficient code for this branch.
939 case ISD::SETOLE: // PF = 0 & (CF = 1 || ZF = 1)
942 return true; // FIXME: Emit more efficient code for this branch.
946 EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1), SetCC->hasOneUse());
947 BuildMI(BB, Opc, 1).addMBB(Dest);
949 BuildMI(BB, Opc2, 1).addMBB(Dest);
953 /// EmitSelectCC - Emit code into BB that performs a select operation between
954 /// the two registers RTrue and RFalse, generating a result into RDest. Return
955 /// true if the fold cannot be performed.
957 void ISel::EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
958 unsigned RTrue, unsigned RFalse, unsigned RDest) {
960 EQ, NE, LT, LE, GT, GE, B, BE, A, AE, P, NP,
962 } CondCode = NOT_SET;
964 static const unsigned CMOVTAB16[] = {
965 X86::CMOVE16rr, X86::CMOVNE16rr, X86::CMOVL16rr, X86::CMOVLE16rr,
966 X86::CMOVG16rr, X86::CMOVGE16rr, X86::CMOVB16rr, X86::CMOVBE16rr,
967 X86::CMOVA16rr, X86::CMOVAE16rr, X86::CMOVP16rr, X86::CMOVNP16rr,
969 static const unsigned CMOVTAB32[] = {
970 X86::CMOVE32rr, X86::CMOVNE32rr, X86::CMOVL32rr, X86::CMOVLE32rr,
971 X86::CMOVG32rr, X86::CMOVGE32rr, X86::CMOVB32rr, X86::CMOVBE32rr,
972 X86::CMOVA32rr, X86::CMOVAE32rr, X86::CMOVP32rr, X86::CMOVNP32rr,
974 static const unsigned CMOVTABFP[] = {
975 X86::FCMOVE , X86::FCMOVNE, /*missing*/0, /*missing*/0,
976 /*missing*/0, /*missing*/0, X86::FCMOVB , X86::FCMOVBE,
977 X86::FCMOVA , X86::FCMOVAE, X86::FCMOVP , X86::FCMOVNP
980 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Cond)) {
981 if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
982 switch (SetCC->getCondition()) {
983 default: assert(0 && "Unknown integer comparison!");
984 case ISD::SETEQ: CondCode = EQ; break;
985 case ISD::SETGT: CondCode = GT; break;
986 case ISD::SETGE: CondCode = GE; break;
987 case ISD::SETLT: CondCode = LT; break;
988 case ISD::SETLE: CondCode = LE; break;
989 case ISD::SETNE: CondCode = NE; break;
990 case ISD::SETULT: CondCode = B; break;
991 case ISD::SETUGT: CondCode = A; break;
992 case ISD::SETULE: CondCode = BE; break;
993 case ISD::SETUGE: CondCode = AE; break;
996 // On a floating point condition, the flags are set as follows:
1000 // 1 | 0 | 0 | X == Y
1001 // 1 | 1 | 1 | unordered
1003 switch (SetCC->getCondition()) {
1004 default: assert(0 && "Unknown FP comparison!");
1006 case ISD::SETEQ: CondCode = EQ; break; // True if ZF = 1
1008 case ISD::SETGT: CondCode = A; break; // True if CF = 0 and ZF = 0
1010 case ISD::SETGE: CondCode = AE; break; // True if CF = 0
1012 case ISD::SETLT: CondCode = B; break; // True if CF = 1
1014 case ISD::SETLE: CondCode = BE; break; // True if CF = 1 or ZF = 1
1016 case ISD::SETNE: CondCode = NE; break; // True if ZF = 0
1017 case ISD::SETUO: CondCode = P; break; // True if PF = 1
1018 case ISD::SETO: CondCode = NP; break; // True if PF = 0
1019 case ISD::SETUGT: // PF = 1 | (ZF = 0 & CF = 0)
1020 case ISD::SETUGE: // PF = 1 | CF = 0
1021 case ISD::SETUNE: // PF = 1 | ZF = 0
1022 case ISD::SETOEQ: // PF = 0 & ZF = 1
1023 case ISD::SETOLT: // PF = 0 & CF = 1
1024 case ISD::SETOLE: // PF = 0 & (CF = 1 || ZF = 1)
1025 // We cannot emit this comparison as a single cmov.
1032 if (CondCode != NOT_SET) {
1034 default: assert(0 && "Cannot select this type!");
1035 case MVT::i16: Opc = CMOVTAB16[CondCode]; break;
1036 case MVT::i32: Opc = CMOVTAB32[CondCode]; break;
1037 case MVT::f64: Opc = CMOVTABFP[CondCode]; break;
1041 // Finally, if we weren't able to fold this, just emit the condition and test
1043 if (CondCode == NOT_SET || Opc == 0) {
1044 // Get the condition into the zero flag.
1045 unsigned CondReg = SelectExpr(Cond);
1046 BuildMI(BB, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1049 default: assert(0 && "Cannot select this type!");
1050 case MVT::i16: Opc = X86::CMOVE16rr; break;
1051 case MVT::i32: Opc = X86::CMOVE32rr; break;
1052 case MVT::f64: Opc = X86::FCMOVE; break;
1055 // FIXME: CMP R, 0 -> TEST R, R
1056 EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.Val->hasOneUse());
1057 std::swap(RTrue, RFalse);
1059 BuildMI(BB, Opc, 2, RDest).addReg(RTrue).addReg(RFalse);
1062 void ISel::EmitCMP(SDOperand LHS, SDOperand RHS, bool HasOneUse) {
1064 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS)) {
1066 if (HasOneUse && isFoldableLoad(LHS, RHS)) {
1067 switch (RHS.getValueType()) {
1070 case MVT::i8: Opc = X86::CMP8mi; break;
1071 case MVT::i16: Opc = X86::CMP16mi; break;
1072 case MVT::i32: Opc = X86::CMP32mi; break;
1076 EmitFoldedLoad(LHS, AM);
1077 addFullAddress(BuildMI(BB, Opc, 5), AM).addImm(CN->getValue());
1082 switch (RHS.getValueType()) {
1085 case MVT::i8: Opc = X86::CMP8ri; break;
1086 case MVT::i16: Opc = X86::CMP16ri; break;
1087 case MVT::i32: Opc = X86::CMP32ri; break;
1090 unsigned Tmp1 = SelectExpr(LHS);
1091 BuildMI(BB, Opc, 2).addReg(Tmp1).addImm(CN->getValue());
1094 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(RHS)) {
1095 if (CN->isExactlyValue(+0.0) ||
1096 CN->isExactlyValue(-0.0)) {
1097 unsigned Reg = SelectExpr(LHS);
1098 BuildMI(BB, X86::FTST, 1).addReg(Reg);
1099 BuildMI(BB, X86::FNSTSW8r, 0);
1100 BuildMI(BB, X86::SAHF, 1);
1106 if (HasOneUse && isFoldableLoad(LHS, RHS)) {
1107 switch (RHS.getValueType()) {
1110 case MVT::i8: Opc = X86::CMP8mr; break;
1111 case MVT::i16: Opc = X86::CMP16mr; break;
1112 case MVT::i32: Opc = X86::CMP32mr; break;
1116 EmitFoldedLoad(LHS, AM);
1117 unsigned Reg = SelectExpr(RHS);
1118 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(Reg);
1123 switch (LHS.getValueType()) {
1124 default: assert(0 && "Cannot compare this value!");
1126 case MVT::i8: Opc = X86::CMP8rr; break;
1127 case MVT::i16: Opc = X86::CMP16rr; break;
1128 case MVT::i32: Opc = X86::CMP32rr; break;
1129 case MVT::f64: Opc = X86::FUCOMIr; break;
1131 unsigned Tmp1, Tmp2;
1132 if (getRegPressure(LHS) > getRegPressure(RHS)) {
1133 Tmp1 = SelectExpr(LHS);
1134 Tmp2 = SelectExpr(RHS);
1136 Tmp2 = SelectExpr(RHS);
1137 Tmp1 = SelectExpr(LHS);
1139 BuildMI(BB, Opc, 2).addReg(Tmp1).addReg(Tmp2);
1142 /// isFoldableLoad - Return true if this is a load instruction that can safely
1143 /// be folded into an operation that uses it.
1144 bool ISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp, bool FloatPromoteOk){
1145 if (Op.getOpcode() == ISD::LOAD) {
1146 // FIXME: currently can't fold constant pool indexes.
1147 if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
1149 } else if (FloatPromoteOk && Op.getOpcode() == ISD::EXTLOAD &&
1150 cast<MVTSDNode>(Op)->getExtraValueType() == MVT::f32) {
1151 // FIXME: currently can't fold constant pool indexes.
1152 if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
1158 // If this load has already been emitted, we clearly can't fold it.
1159 assert(Op.ResNo == 0 && "Not a use of the value of the load?");
1160 if (ExprMap.count(Op.getValue(1))) return false;
1161 assert(!ExprMap.count(Op.getValue(0)) && "Value in map but not token chain?");
1162 assert(!ExprMap.count(Op.getValue(1))&&"Token lowered but value not in map?");
1164 // If there is not just one use of its value, we cannot fold.
1165 if (!Op.Val->hasNUsesOfValue(1, 0)) return false;
1167 // Finally, we cannot fold the load into the operation if this would induce a
1168 // cycle into the resultant dag. To check for this, see if OtherOp (the other
1169 // operand of the operation we are folding the load into) can possible use the
1170 // chain node defined by the load.
1171 if (OtherOp.Val && !Op.Val->hasNUsesOfValue(0, 1)) { // Has uses of chain?
1172 std::set<SDNode*> Visited;
1173 if (NodeTransitivelyUsesValue(OtherOp, Op.getValue(1), Visited))
1180 /// EmitFoldedLoad - Ensure that the arguments of the load are code generated,
1181 /// and compute the address being loaded into AM.
1182 void ISel::EmitFoldedLoad(SDOperand Op, X86AddressMode &AM) {
1183 SDOperand Chain = Op.getOperand(0);
1184 SDOperand Address = Op.getOperand(1);
1186 if (getRegPressure(Chain) > getRegPressure(Address)) {
1188 SelectAddress(Address, AM);
1190 SelectAddress(Address, AM);
1194 // The chain for this load is now lowered.
1195 assert(ExprMap.count(SDOperand(Op.Val, 1)) == 0 &&
1196 "Load emitted more than once?");
1197 if (!ExprMap.insert(std::make_pair(Op.getValue(1), 1)).second)
1198 assert(0 && "Load emitted more than once!");
1201 // EmitOrOpOp - Pattern match the expression (Op1|Op2), where we know that op1
1202 // and op2 are i8/i16/i32 values with one use each (the or). If we can form a
1203 // SHLD or SHRD, emit the instruction (generating the value into DestReg) and
1205 bool ISel::EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
1206 if (Op1.getOpcode() == ISD::SHL && Op2.getOpcode() == ISD::SRL) {
1208 } else if (Op2.getOpcode() == ISD::SHL && Op1.getOpcode() == ISD::SRL) {
1209 std::swap(Op1, Op2); // Op1 is the SHL now.
1211 return false; // No match
1214 SDOperand ShlVal = Op1.getOperand(0);
1215 SDOperand ShlAmt = Op1.getOperand(1);
1216 SDOperand ShrVal = Op2.getOperand(0);
1217 SDOperand ShrAmt = Op2.getOperand(1);
1219 unsigned RegSize = MVT::getSizeInBits(Op1.getValueType());
1221 // Find out if ShrAmt = 32-ShlAmt or ShlAmt = 32-ShrAmt.
1222 if (ShlAmt.getOpcode() == ISD::SUB && ShlAmt.getOperand(1) == ShrAmt)
1223 if (ConstantSDNode *SubCST = dyn_cast<ConstantSDNode>(ShlAmt.getOperand(0)))
1224 if (SubCST->getValue() == RegSize) {
1225 // (A >> ShrAmt) | (A << (32-ShrAmt)) ==> ROR A, ShrAmt
1226 // (A >> ShrAmt) | (B << (32-ShrAmt)) ==> SHRD A, B, ShrAmt
1227 if (ShrVal == ShlVal) {
1228 unsigned Reg, ShAmt;
1229 if (getRegPressure(ShrVal) > getRegPressure(ShrAmt)) {
1230 Reg = SelectExpr(ShrVal);
1231 ShAmt = SelectExpr(ShrAmt);
1233 ShAmt = SelectExpr(ShrAmt);
1234 Reg = SelectExpr(ShrVal);
1236 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1237 unsigned Opc = RegSize == 8 ? X86::ROR8rCL :
1238 (RegSize == 16 ? X86::ROR16rCL : X86::ROR32rCL);
1239 BuildMI(BB, Opc, 1, DestReg).addReg(Reg);
1241 } else if (RegSize != 8) {
1242 unsigned AReg, BReg;
1243 if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
1244 BReg = SelectExpr(ShlVal);
1245 AReg = SelectExpr(ShrVal);
1247 AReg = SelectExpr(ShrVal);
1248 BReg = SelectExpr(ShlVal);
1250 unsigned ShAmt = SelectExpr(ShrAmt);
1251 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1252 unsigned Opc = RegSize == 16 ? X86::SHRD16rrCL : X86::SHRD32rrCL;
1253 BuildMI(BB, Opc, 2, DestReg).addReg(AReg).addReg(BReg);
1258 if (ShrAmt.getOpcode() == ISD::SUB && ShrAmt.getOperand(1) == ShlAmt)
1259 if (ConstantSDNode *SubCST = dyn_cast<ConstantSDNode>(ShrAmt.getOperand(0)))
1260 if (SubCST->getValue() == RegSize) {
1261 // (A << ShlAmt) | (A >> (32-ShlAmt)) ==> ROL A, ShrAmt
1262 // (A << ShlAmt) | (B >> (32-ShlAmt)) ==> SHLD A, B, ShrAmt
1263 if (ShrVal == ShlVal) {
1264 unsigned Reg, ShAmt;
1265 if (getRegPressure(ShrVal) > getRegPressure(ShlAmt)) {
1266 Reg = SelectExpr(ShrVal);
1267 ShAmt = SelectExpr(ShlAmt);
1269 ShAmt = SelectExpr(ShlAmt);
1270 Reg = SelectExpr(ShrVal);
1272 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1273 unsigned Opc = RegSize == 8 ? X86::ROL8rCL :
1274 (RegSize == 16 ? X86::ROL16rCL : X86::ROL32rCL);
1275 BuildMI(BB, Opc, 1, DestReg).addReg(Reg);
1277 } else if (RegSize != 8) {
1278 unsigned AReg, BReg;
1279 if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
1280 AReg = SelectExpr(ShlVal);
1281 BReg = SelectExpr(ShrVal);
1283 BReg = SelectExpr(ShrVal);
1284 AReg = SelectExpr(ShlVal);
1286 unsigned ShAmt = SelectExpr(ShlAmt);
1287 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
1288 unsigned Opc = RegSize == 16 ? X86::SHLD16rrCL : X86::SHLD32rrCL;
1289 BuildMI(BB, Opc, 2, DestReg).addReg(AReg).addReg(BReg);
1294 if (ConstantSDNode *ShrCst = dyn_cast<ConstantSDNode>(ShrAmt))
1295 if (ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(ShlAmt))
1296 if (ShrCst->getValue() < RegSize && ShlCst->getValue() < RegSize)
1297 if (ShrCst->getValue() == RegSize-ShlCst->getValue()) {
1298 // (A >> 5) | (A << 27) --> ROR A, 5
1299 // (A >> 5) | (B << 27) --> SHRD A, B, 5
1300 if (ShrVal == ShlVal) {
1301 unsigned Reg = SelectExpr(ShrVal);
1302 unsigned Opc = RegSize == 8 ? X86::ROR8ri :
1303 (RegSize == 16 ? X86::ROR16ri : X86::ROR32ri);
1304 BuildMI(BB, Opc, 2, DestReg).addReg(Reg).addImm(ShrCst->getValue());
1306 } else if (RegSize != 8) {
1307 unsigned AReg, BReg;
1308 if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
1309 BReg = SelectExpr(ShlVal);
1310 AReg = SelectExpr(ShrVal);
1312 AReg = SelectExpr(ShrVal);
1313 BReg = SelectExpr(ShlVal);
1315 unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8;
1316 BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)
1317 .addImm(ShrCst->getValue());
1325 unsigned ISel::SelectExpr(SDOperand N) {
1327 unsigned Tmp1, Tmp2, Tmp3;
1329 SDNode *Node = N.Val;
1332 if (Node->getOpcode() == ISD::CopyFromReg) {
1333 // FIXME: Handle copy from physregs!
1335 // Just use the specified register as our input.
1336 return dyn_cast<RegSDNode>(Node)->getReg();
1339 unsigned &Reg = ExprMap[N];
1340 if (Reg) return Reg;
1342 switch (N.getOpcode()) {
1344 Reg = Result = (N.getValueType() != MVT::Other) ?
1345 MakeReg(N.getValueType()) : 1;
1348 // If this is a call instruction, make sure to prepare ALL of the result
1349 // values as well as the chain.
1350 if (Node->getNumValues() == 1)
1351 Reg = Result = 1; // Void call, just a chain.
1353 Result = MakeReg(Node->getValueType(0));
1354 ExprMap[N.getValue(0)] = Result;
1355 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
1356 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1357 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
1360 case ISD::ADD_PARTS:
1361 case ISD::SUB_PARTS:
1362 case ISD::SHL_PARTS:
1363 case ISD::SRL_PARTS:
1364 case ISD::SRA_PARTS:
1365 Result = MakeReg(Node->getValueType(0));
1366 ExprMap[N.getValue(0)] = Result;
1367 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
1368 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1372 switch (N.getOpcode()) {
1375 assert(0 && "Node not handled!\n");
1376 case ISD::FrameIndex:
1377 Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
1378 addFrameReference(BuildMI(BB, X86::LEA32r, 4, Result), (int)Tmp1);
1380 case ISD::ConstantPool:
1381 Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
1382 addConstantPoolReference(BuildMI(BB, X86::LEA32r, 4, Result), Tmp1);
1384 case ISD::ConstantFP:
1385 ContainsFPCode = true;
1386 Tmp1 = Result; // Intermediate Register
1387 if (cast<ConstantFPSDNode>(N)->getValue() < 0.0 ||
1388 cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
1389 Tmp1 = MakeReg(MVT::f64);
1391 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) ||
1392 cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
1393 BuildMI(BB, X86::FLD0, 0, Tmp1);
1394 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0) ||
1395 cast<ConstantFPSDNode>(N)->isExactlyValue(-1.0))
1396 BuildMI(BB, X86::FLD1, 0, Tmp1);
1398 assert(0 && "Unexpected constant!");
1400 BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1);
1403 switch (N.getValueType()) {
1404 default: assert(0 && "Cannot use constants of this type!");
1406 case MVT::i8: Opc = X86::MOV8ri; break;
1407 case MVT::i16: Opc = X86::MOV16ri; break;
1408 case MVT::i32: Opc = X86::MOV32ri; break;
1410 BuildMI(BB, Opc, 1,Result).addImm(cast<ConstantSDNode>(N)->getValue());
1413 if (Node->getValueType(0) == MVT::f64) {
1414 // FIXME: SHOULD TEACH STACKIFIER ABOUT UNDEF VALUES!
1415 BuildMI(BB, X86::FLD0, 0, Result);
1417 BuildMI(BB, X86::IMPLICIT_DEF, 0, Result);
1420 case ISD::GlobalAddress: {
1421 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
1422 BuildMI(BB, X86::MOV32ri, 1, Result).addGlobalAddress(GV);
1425 case ISD::ExternalSymbol: {
1426 const char *Sym = cast<ExternalSymbolSDNode>(N)->getSymbol();
1427 BuildMI(BB, X86::MOV32ri, 1, Result).addExternalSymbol(Sym);
1430 case ISD::ZERO_EXTEND: {
1431 int DestIs16 = N.getValueType() == MVT::i16;
1432 int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
1434 // FIXME: This hack is here for zero extension casts from bool to i8. This
1435 // would not be needed if bools were promoted by Legalize.
1436 if (N.getValueType() == MVT::i8) {
1437 Tmp1 = SelectExpr(N.getOperand(0));
1438 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(Tmp1);
1442 if (isFoldableLoad(N.getOperand(0), SDOperand())) {
1443 static const unsigned Opc[3] = {
1444 X86::MOVZX32rm8, X86::MOVZX32rm16, X86::MOVZX16rm8
1448 EmitFoldedLoad(N.getOperand(0), AM);
1449 addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
1454 static const unsigned Opc[3] = {
1455 X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOVZX16rr8
1457 Tmp1 = SelectExpr(N.getOperand(0));
1458 BuildMI(BB, Opc[SrcIs16+DestIs16*2], 1, Result).addReg(Tmp1);
1461 case ISD::SIGN_EXTEND: {
1462 int DestIs16 = N.getValueType() == MVT::i16;
1463 int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
1465 // FIXME: Legalize should promote bools to i8!
1466 assert(N.getOperand(0).getValueType() != MVT::i1 &&
1467 "Sign extend from bool not implemented!");
1469 if (isFoldableLoad(N.getOperand(0), SDOperand())) {
1470 static const unsigned Opc[3] = {
1471 X86::MOVSX32rm8, X86::MOVSX32rm16, X86::MOVSX16rm8
1475 EmitFoldedLoad(N.getOperand(0), AM);
1476 addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
1480 static const unsigned Opc[3] = {
1481 X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOVSX16rr8
1483 Tmp1 = SelectExpr(N.getOperand(0));
1484 BuildMI(BB, Opc[SrcIs16+DestIs16*2], 1, Result).addReg(Tmp1);
1488 // Fold TRUNCATE (LOAD P) into a smaller load from P.
1489 // FIXME: This should be performed by the DAGCombiner.
1490 if (isFoldableLoad(N.getOperand(0), SDOperand())) {
1491 switch (N.getValueType()) {
1492 default: assert(0 && "Unknown truncate!");
1494 case MVT::i8: Opc = X86::MOV8rm; break;
1495 case MVT::i16: Opc = X86::MOV16rm; break;
1498 EmitFoldedLoad(N.getOperand(0), AM);
1499 addFullAddress(BuildMI(BB, Opc, 4, Result), AM);
1503 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by
1504 // a move out of AX or AL.
1505 switch (N.getOperand(0).getValueType()) {
1506 default: assert(0 && "Unknown truncate!");
1507 case MVT::i8: Tmp2 = X86::AL; Opc = X86::MOV8rr; break;
1508 case MVT::i16: Tmp2 = X86::AX; Opc = X86::MOV16rr; break;
1509 case MVT::i32: Tmp2 = X86::EAX; Opc = X86::MOV32rr; break;
1511 Tmp1 = SelectExpr(N.getOperand(0));
1512 BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
1514 switch (N.getValueType()) {
1515 default: assert(0 && "Unknown truncate!");
1517 case MVT::i8: Tmp2 = X86::AL; Opc = X86::MOV8rr; break;
1518 case MVT::i16: Tmp2 = X86::AX; Opc = X86::MOV16rr; break;
1520 BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
1523 case ISD::SINT_TO_FP:
1524 case ISD::UINT_TO_FP: {
1525 // FIXME: Most of this grunt work should be done by legalize!
1526 ContainsFPCode = true;
1528 // Promote the integer to a type supported by FLD. We do this because there
1529 // are no unsigned FLD instructions, so we must promote an unsigned value to
1530 // a larger signed value, then use FLD on the larger value.
1532 MVT::ValueType PromoteType = MVT::Other;
1533 MVT::ValueType SrcTy = N.getOperand(0).getValueType();
1534 unsigned PromoteOpcode = 0;
1535 unsigned RealDestReg = Result;
1539 // We don't have the facilities for directly loading byte sized data from
1540 // memory (even signed). Promote it to 16 bits.
1541 PromoteType = MVT::i16;
1542 PromoteOpcode = Node->getOpcode() == ISD::SINT_TO_FP ?
1543 X86::MOVSX16rr8 : X86::MOVZX16rr8;
1546 if (Node->getOpcode() == ISD::UINT_TO_FP) {
1547 PromoteType = MVT::i32;
1548 PromoteOpcode = X86::MOVZX32rr16;
1552 // Don't fild into the real destination.
1553 if (Node->getOpcode() == ISD::UINT_TO_FP)
1554 Result = MakeReg(Node->getValueType(0));
1558 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1560 if (PromoteType != MVT::Other) {
1561 Tmp2 = MakeReg(PromoteType);
1562 BuildMI(BB, PromoteOpcode, 1, Tmp2).addReg(Tmp1);
1563 SrcTy = PromoteType;
1567 // Spill the integer to memory and reload it from there.
1568 unsigned Size = MVT::getSizeInBits(SrcTy)/8;
1569 MachineFunction *F = BB->getParent();
1570 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
1574 assert(0 && "Cast ulong to FP not implemented yet!");
1575 // FIXME: this won't work for cast [u]long to FP
1576 addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
1577 FrameIdx).addReg(Tmp1);
1578 addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
1579 FrameIdx, 4).addReg(Tmp1+1);
1580 addFrameReference(BuildMI(BB, X86::FILD64m, 5, Result), FrameIdx);
1583 addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
1584 FrameIdx).addReg(Tmp1);
1585 addFrameReference(BuildMI(BB, X86::FILD32m, 5, Result), FrameIdx);
1588 addFrameReference(BuildMI(BB, X86::MOV16mr, 5),
1589 FrameIdx).addReg(Tmp1);
1590 addFrameReference(BuildMI(BB, X86::FILD16m, 5, Result), FrameIdx);
1592 default: break; // No promotion required.
1595 if (Node->getOpcode() == ISD::UINT_TO_FP && Result != RealDestReg) {
1596 // If this is a cast from uint -> double, we need to be careful when if
1597 // the "sign" bit is set. If so, we don't want to make a negative number,
1598 // we want to make a positive number. Emit code to add an offset if the
1601 // Compute whether the sign bit is set by shifting the reg right 31 bits.
1602 unsigned IsNeg = MakeReg(MVT::i32);
1603 BuildMI(BB, X86::SHR32ri, 2, IsNeg).addReg(Tmp1).addImm(31);
1605 // Create a CP value that has the offset in one word and 0 in the other.
1606 static ConstantInt *TheOffset = ConstantUInt::get(Type::ULongTy,
1607 0x4f80000000000000ULL);
1608 unsigned CPI = F->getConstantPool()->getConstantPoolIndex(TheOffset);
1609 BuildMI(BB, X86::FADD32m, 5, RealDestReg).addReg(Result)
1610 .addConstantPoolIndex(CPI).addZImm(4).addReg(IsNeg).addSImm(0);
1612 } else if (Node->getOpcode() == ISD::UINT_TO_FP && SrcTy == MVT::i64) {
1613 // We need special handling for unsigned 64-bit integer sources. If the
1614 // input number has the "sign bit" set, then we loaded it incorrectly as a
1615 // negative 64-bit number. In this case, add an offset value.
1617 // Emit a test instruction to see if the dynamic input value was signed.
1618 BuildMI(BB, X86::TEST32rr, 2).addReg(Tmp1+1).addReg(Tmp1+1);
1620 // If the sign bit is set, get a pointer to an offset, otherwise get a
1621 // pointer to a zero.
1622 MachineConstantPool *CP = F->getConstantPool();
1623 unsigned Zero = MakeReg(MVT::i32);
1624 Constant *Null = Constant::getNullValue(Type::UIntTy);
1625 addConstantPoolReference(BuildMI(BB, X86::LEA32r, 5, Zero),
1626 CP->getConstantPoolIndex(Null));
1627 unsigned Offset = MakeReg(MVT::i32);
1628 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
1630 addConstantPoolReference(BuildMI(BB, X86::LEA32r, 5, Offset),
1631 CP->getConstantPoolIndex(OffsetCst));
1632 unsigned Addr = MakeReg(MVT::i32);
1633 BuildMI(BB, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
1635 // Load the constant for an add. FIXME: this could make an 'fadd' that
1636 // reads directly from memory, but we don't support these yet.
1637 unsigned ConstReg = MakeReg(MVT::f64);
1638 addDirectMem(BuildMI(BB, X86::FLD32m, 4, ConstReg), Addr);
1640 BuildMI(BB, X86::FpADD, 2, RealDestReg).addReg(ConstReg).addReg(Result);
1644 case ISD::FP_TO_SINT:
1645 case ISD::FP_TO_UINT: {
1646 // FIXME: Most of this grunt work should be done by legalize!
1647 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1649 // Change the floating point control register to use "round towards zero"
1650 // mode when truncating to an integer value.
1652 MachineFunction *F = BB->getParent();
1653 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1654 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1656 // Load the old value of the high byte of the control word...
1657 unsigned HighPartOfCW = MakeReg(MVT::i8);
1658 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, HighPartOfCW),
1661 // Set the high part to be round to zero...
1662 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
1663 CWFrameIdx, 1).addImm(12);
1665 // Reload the modified control word now...
1666 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1668 // Restore the memory image of control word to original value
1669 addFrameReference(BuildMI(BB, X86::MOV8mr, 5),
1670 CWFrameIdx, 1).addReg(HighPartOfCW);
1672 // We don't have the facilities for directly storing byte sized data to
1673 // memory. Promote it to 16 bits. We also must promote unsigned values to
1674 // larger classes because we only have signed FP stores.
1675 MVT::ValueType StoreClass = Node->getValueType(0);
1676 if (StoreClass == MVT::i8 || Node->getOpcode() == ISD::FP_TO_UINT)
1677 switch (StoreClass) {
1678 case MVT::i8: StoreClass = MVT::i16; break;
1679 case MVT::i16: StoreClass = MVT::i32; break;
1680 case MVT::i32: StoreClass = MVT::i64; break;
1681 // The following treatment of cLong may not be perfectly right,
1682 // but it survives chains of casts of the form
1683 // double->ulong->double.
1684 case MVT::i64: StoreClass = MVT::i64; break;
1685 default: assert(0 && "Unknown store class!");
1688 // Spill the integer to memory and reload it from there.
1689 unsigned Size = MVT::getSizeInBits(StoreClass)/8;
1690 int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
1692 switch (StoreClass) {
1693 default: assert(0 && "Unknown store class!");
1695 addFrameReference(BuildMI(BB, X86::FIST16m, 5), FrameIdx).addReg(Tmp1);
1698 addFrameReference(BuildMI(BB, X86::FIST32m, 5), FrameIdx).addReg(Tmp1);
1701 addFrameReference(BuildMI(BB, X86::FISTP64m, 5), FrameIdx).addReg(Tmp1);
1705 switch (Node->getValueType(0)) {
1707 assert(0 && "Unknown integer type!");
1709 // FIXME: this isn't gunna work.
1710 assert(0 && "Cast FP to long not implemented yet!");
1711 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result), FrameIdx);
1712 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result+1), FrameIdx, 4);
1714 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result), FrameIdx);
1717 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Result), FrameIdx);
1720 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Result), FrameIdx);
1724 // Reload the original control word now.
1725 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1729 Op0 = N.getOperand(0);
1730 Op1 = N.getOperand(1);
1732 if (isFoldableLoad(Op0, Op1, true)) {
1733 std::swap(Op0, Op1);
1737 if (isFoldableLoad(Op1, Op0, true)) {
1739 switch (N.getValueType()) {
1740 default: assert(0 && "Cannot add this type!");
1742 case MVT::i8: Opc = X86::ADD8rm; break;
1743 case MVT::i16: Opc = X86::ADD16rm; break;
1744 case MVT::i32: Opc = X86::ADD32rm; break;
1746 // For F64, handle promoted load operations (from F32) as well!
1747 Opc = Op1.getOpcode() == ISD::LOAD ? X86::FADD64m : X86::FADD32m;
1751 EmitFoldedLoad(Op1, AM);
1752 Tmp1 = SelectExpr(Op0);
1753 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
1757 // See if we can codegen this as an LEA to fold operations together.
1758 if (N.getValueType() == MVT::i32) {
1760 X86ISelAddressMode AM;
1761 MatchAddress(N, AM);
1762 ExprMap[N] = Result;
1764 // If this is not just an add, emit the LEA. For a simple add (like
1765 // reg+reg or reg+imm), we just emit an add. It might be a good idea to
1766 // leave this as LEA, then peephole it to 'ADD' after two address elim
1768 if (AM.Scale != 1 || AM.BaseType == X86ISelAddressMode::FrameIndexBase||
1769 AM.GV || (AM.Base.Reg.Val && AM.IndexReg.Val && AM.Disp)) {
1770 X86AddressMode XAM = SelectAddrExprs(AM);
1771 addFullAddress(BuildMI(BB, X86::LEA32r, 4, Result), XAM);
1776 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
1778 if (CN->getValue() == 1) { // add X, 1 -> inc X
1779 switch (N.getValueType()) {
1780 default: assert(0 && "Cannot integer add this type!");
1781 case MVT::i8: Opc = X86::INC8r; break;
1782 case MVT::i16: Opc = X86::INC16r; break;
1783 case MVT::i32: Opc = X86::INC32r; break;
1785 } else if (CN->isAllOnesValue()) { // add X, -1 -> dec X
1786 switch (N.getValueType()) {
1787 default: assert(0 && "Cannot integer add this type!");
1788 case MVT::i8: Opc = X86::DEC8r; break;
1789 case MVT::i16: Opc = X86::DEC16r; break;
1790 case MVT::i32: Opc = X86::DEC32r; break;
1795 Tmp1 = SelectExpr(Op0);
1796 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1800 switch (N.getValueType()) {
1801 default: assert(0 && "Cannot add this type!");
1802 case MVT::i8: Opc = X86::ADD8ri; break;
1803 case MVT::i16: Opc = X86::ADD16ri; break;
1804 case MVT::i32: Opc = X86::ADD32ri; break;
1807 Tmp1 = SelectExpr(Op0);
1808 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
1813 switch (N.getValueType()) {
1814 default: assert(0 && "Cannot add this type!");
1815 case MVT::i8: Opc = X86::ADD8rr; break;
1816 case MVT::i16: Opc = X86::ADD16rr; break;
1817 case MVT::i32: Opc = X86::ADD32rr; break;
1818 case MVT::f64: Opc = X86::FpADD; break;
1821 if (getRegPressure(Op0) > getRegPressure(Op1)) {
1822 Tmp1 = SelectExpr(Op0);
1823 Tmp2 = SelectExpr(Op1);
1825 Tmp2 = SelectExpr(Op1);
1826 Tmp1 = SelectExpr(Op0);
1829 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1833 Tmp1 = SelectExpr(Node->getOperand(0));
1834 BuildMI(BB, X86::FABS, 1, Result).addReg(Tmp1);
1837 Tmp1 = SelectExpr(Node->getOperand(0));
1838 BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1);
1842 switch (N.getValueType()) {
1843 default: assert(0 && "Unsupported VT!");
1844 case MVT::i8: Tmp2 = X86::MUL8r; break;
1845 case MVT::i16: Tmp2 = X86::MUL16r; break;
1846 case MVT::i32: Tmp2 = X86::MUL32r; break;
1850 unsigned MovOpc, LowReg, HiReg;
1851 switch (N.getValueType()) {
1852 default: assert(0 && "Unsupported VT!");
1854 MovOpc = X86::MOV8rr;
1860 MovOpc = X86::MOV16rr;
1866 MovOpc = X86::MOV32rr;
1872 if (Node->getOpcode() != ISD::MULHS)
1873 Opc = Tmp2; // Get the MULHU opcode.
1875 Op0 = Node->getOperand(0);
1876 Op1 = Node->getOperand(1);
1877 if (getRegPressure(Op0) > getRegPressure(Op1)) {
1878 Tmp1 = SelectExpr(Op0);
1879 Tmp2 = SelectExpr(Op1);
1881 Tmp2 = SelectExpr(Op1);
1882 Tmp1 = SelectExpr(Op0);
1885 // FIXME: Implement folding of loads into the memory operands here!
1886 BuildMI(BB, MovOpc, 1, LowReg).addReg(Tmp1);
1887 BuildMI(BB, Opc, 1).addReg(Tmp2);
1888 BuildMI(BB, MovOpc, 1, Result).addReg(HiReg);
1897 static const unsigned SUBTab[] = {
1898 X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, 0,
1899 X86::SUB8rm, X86::SUB16rm, X86::SUB32rm, X86::FSUB32m, X86::FSUB64m,
1900 X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB , X86::FpSUB,
1902 static const unsigned MULTab[] = {
1903 0, X86::IMUL16rri, X86::IMUL32rri, 0, 0,
1904 0, X86::IMUL16rm , X86::IMUL32rm, X86::FMUL32m, X86::FMUL64m,
1905 0, X86::IMUL16rr , X86::IMUL32rr, X86::FpMUL , X86::FpMUL,
1907 static const unsigned ANDTab[] = {
1908 X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, 0,
1909 X86::AND8rm, X86::AND16rm, X86::AND32rm, 0, 0,
1910 X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, 0,
1912 static const unsigned ORTab[] = {
1913 X86::OR8ri, X86::OR16ri, X86::OR32ri, 0, 0,
1914 X86::OR8rm, X86::OR16rm, X86::OR32rm, 0, 0,
1915 X86::OR8rr, X86::OR16rr, X86::OR32rr, 0, 0,
1917 static const unsigned XORTab[] = {
1918 X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, 0,
1919 X86::XOR8rm, X86::XOR16rm, X86::XOR32rm, 0, 0,
1920 X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, 0,
1923 Op0 = Node->getOperand(0);
1924 Op1 = Node->getOperand(1);
1926 if (Node->getOpcode() == ISD::OR && Op0.hasOneUse() && Op1.hasOneUse())
1927 if (EmitOrOpOp(Op0, Op1, Result)) // Match SHLD, SHRD, and rotates.
1930 if (Node->getOpcode() == ISD::SUB)
1931 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(0)))
1932 if (CN->isNullValue()) { // 0 - N -> neg N
1933 switch (N.getValueType()) {
1934 default: assert(0 && "Cannot sub this type!");
1936 case MVT::i8: Opc = X86::NEG8r; break;
1937 case MVT::i16: Opc = X86::NEG16r; break;
1938 case MVT::i32: Opc = X86::NEG32r; break;
1940 Tmp1 = SelectExpr(N.getOperand(1));
1941 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1945 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
1946 if (CN->isAllOnesValue() && Node->getOpcode() == ISD::XOR) {
1948 switch (N.getValueType()) {
1949 default: assert(0 && "Cannot add this type!");
1950 case MVT::i1: break; // Not supported, don't invert upper bits!
1951 case MVT::i8: Opc = X86::NOT8r; break;
1952 case MVT::i16: Opc = X86::NOT16r; break;
1953 case MVT::i32: Opc = X86::NOT32r; break;
1956 Tmp1 = SelectExpr(Op0);
1957 BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
1962 // Fold common multiplies into LEA instructions.
1963 if (Node->getOpcode() == ISD::MUL && N.getValueType() == MVT::i32) {
1964 switch ((int)CN->getValue()) {
1969 // Remove N from exprmap so SelectAddress doesn't get confused.
1972 SelectAddress(N, AM);
1973 // Restore it to the map.
1974 ExprMap[N] = Result;
1975 addFullAddress(BuildMI(BB, X86::LEA32r, 4, Result), AM);
1980 switch (N.getValueType()) {
1981 default: assert(0 && "Cannot xor this type!");
1983 case MVT::i8: Opc = 0; break;
1984 case MVT::i16: Opc = 1; break;
1985 case MVT::i32: Opc = 2; break;
1987 switch (Node->getOpcode()) {
1988 default: assert(0 && "Unreachable!");
1989 case ISD::SUB: Opc = SUBTab[Opc]; break;
1990 case ISD::MUL: Opc = MULTab[Opc]; break;
1991 case ISD::AND: Opc = ANDTab[Opc]; break;
1992 case ISD::OR: Opc = ORTab[Opc]; break;
1993 case ISD::XOR: Opc = XORTab[Opc]; break;
1995 if (Opc) { // Can't fold MUL:i8 R, imm
1996 Tmp1 = SelectExpr(Op0);
1997 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
2002 if (isFoldableLoad(Op0, Op1, true))
2003 if (Node->getOpcode() != ISD::SUB) {
2004 std::swap(Op0, Op1);
2007 // For FP, emit 'reverse' subract, with a memory operand.
2008 if (N.getValueType() == MVT::f64) {
2009 if (Op0.getOpcode() == ISD::EXTLOAD)
2010 Opc = X86::FSUBR32m;
2012 Opc = X86::FSUBR64m;
2015 EmitFoldedLoad(Op0, AM);
2016 Tmp1 = SelectExpr(Op1);
2017 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
2022 if (isFoldableLoad(Op1, Op0, true)) {
2024 switch (N.getValueType()) {
2025 default: assert(0 && "Cannot operate on this type!");
2027 case MVT::i8: Opc = 5; break;
2028 case MVT::i16: Opc = 6; break;
2029 case MVT::i32: Opc = 7; break;
2030 // For F64, handle promoted load operations (from F32) as well!
2031 case MVT::f64: Opc = Op1.getOpcode() == ISD::LOAD ? 9 : 8; break;
2033 switch (Node->getOpcode()) {
2034 default: assert(0 && "Unreachable!");
2035 case ISD::SUB: Opc = SUBTab[Opc]; break;
2036 case ISD::MUL: Opc = MULTab[Opc]; break;
2037 case ISD::AND: Opc = ANDTab[Opc]; break;
2038 case ISD::OR: Opc = ORTab[Opc]; break;
2039 case ISD::XOR: Opc = XORTab[Opc]; break;
2043 EmitFoldedLoad(Op1, AM);
2044 Tmp1 = SelectExpr(Op0);
2046 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
2048 assert(Node->getOpcode() == ISD::MUL &&
2049 N.getValueType() == MVT::i8 && "Unexpected situation!");
2050 // Must use the MUL instruction, which forces use of AL.
2051 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(Tmp1);
2052 addFullAddress(BuildMI(BB, X86::MUL8m, 1), AM);
2053 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
2058 if (getRegPressure(Op0) > getRegPressure(Op1)) {
2059 Tmp1 = SelectExpr(Op0);
2060 Tmp2 = SelectExpr(Op1);
2062 Tmp2 = SelectExpr(Op1);
2063 Tmp1 = SelectExpr(Op0);
2066 switch (N.getValueType()) {
2067 default: assert(0 && "Cannot add this type!");
2069 case MVT::i8: Opc = 10; break;
2070 case MVT::i16: Opc = 11; break;
2071 case MVT::i32: Opc = 12; break;
2072 case MVT::f32: Opc = 13; break;
2073 case MVT::f64: Opc = 14; break;
2075 switch (Node->getOpcode()) {
2076 default: assert(0 && "Unreachable!");
2077 case ISD::SUB: Opc = SUBTab[Opc]; break;
2078 case ISD::MUL: Opc = MULTab[Opc]; break;
2079 case ISD::AND: Opc = ANDTab[Opc]; break;
2080 case ISD::OR: Opc = ORTab[Opc]; break;
2081 case ISD::XOR: Opc = XORTab[Opc]; break;
2084 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
2086 assert(Node->getOpcode() == ISD::MUL &&
2087 N.getValueType() == MVT::i8 && "Unexpected situation!");
2088 // Must use the MUL instruction, which forces use of AL.
2089 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(Tmp1);
2090 BuildMI(BB, X86::MUL8r, 1).addReg(Tmp2);
2091 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
2095 case ISD::ADD_PARTS:
2096 case ISD::SUB_PARTS: {
2097 assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
2098 "Not an i64 add/sub!");
2099 // Emit all of the operands.
2100 std::vector<unsigned> InVals;
2101 for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
2102 InVals.push_back(SelectExpr(N.getOperand(i)));
2103 if (N.getOpcode() == ISD::ADD_PARTS) {
2104 BuildMI(BB, X86::ADD32rr, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
2105 BuildMI(BB, X86::ADC32rr,2,Result+1).addReg(InVals[1]).addReg(InVals[3]);
2107 BuildMI(BB, X86::SUB32rr, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
2108 BuildMI(BB, X86::SBB32rr, 2,Result+1).addReg(InVals[1]).addReg(InVals[3]);
2110 return Result+N.ResNo;
2113 case ISD::SHL_PARTS:
2114 case ISD::SRA_PARTS:
2115 case ISD::SRL_PARTS: {
2116 assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
2117 "Not an i64 shift!");
2118 unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
2119 unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
2120 unsigned TmpReg = MakeReg(MVT::i32);
2121 if (N.getOpcode() == ISD::SRA_PARTS) {
2122 // If this is a SHR of a Long, then we need to do funny sign extension
2123 // stuff. TmpReg gets the value to use as the high-part if we are
2124 // shifting more than 32 bits.
2125 BuildMI(BB, X86::SAR32ri, 2, TmpReg).addReg(ShiftOpHi).addImm(31);
2127 // Other shifts use a fixed zero value if the shift is more than 32 bits.
2128 BuildMI(BB, X86::MOV32ri, 1, TmpReg).addImm(0);
2131 // Initialize CL with the shift amount.
2132 unsigned ShiftAmountReg = SelectExpr(N.getOperand(2));
2133 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2135 unsigned TmpReg2 = MakeReg(MVT::i32);
2136 unsigned TmpReg3 = MakeReg(MVT::i32);
2137 if (N.getOpcode() == ISD::SHL_PARTS) {
2138 // TmpReg2 = shld inHi, inLo
2139 BuildMI(BB, X86::SHLD32rrCL, 2,TmpReg2).addReg(ShiftOpHi)
2141 // TmpReg3 = shl inLo, CL
2142 BuildMI(BB, X86::SHL32rCL, 1, TmpReg3).addReg(ShiftOpLo);
2144 // Set the flags to indicate whether the shift was by more than 32 bits.
2145 BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2147 // DestHi = (>32) ? TmpReg3 : TmpReg2;
2148 BuildMI(BB, X86::CMOVNE32rr, 2,
2149 Result+1).addReg(TmpReg2).addReg(TmpReg3);
2150 // DestLo = (>32) ? TmpReg : TmpReg3;
2151 BuildMI(BB, X86::CMOVNE32rr, 2,
2152 Result).addReg(TmpReg3).addReg(TmpReg);
2154 // TmpReg2 = shrd inLo, inHi
2155 BuildMI(BB, X86::SHRD32rrCL,2,TmpReg2).addReg(ShiftOpLo)
2157 // TmpReg3 = s[ah]r inHi, CL
2158 BuildMI(BB, N.getOpcode() == ISD::SRA_PARTS ? X86::SAR32rCL
2159 : X86::SHR32rCL, 1, TmpReg3)
2162 // Set the flags to indicate whether the shift was by more than 32 bits.
2163 BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2165 // DestLo = (>32) ? TmpReg3 : TmpReg2;
2166 BuildMI(BB, X86::CMOVNE32rr, 2,
2167 Result).addReg(TmpReg2).addReg(TmpReg3);
2169 // DestHi = (>32) ? TmpReg : TmpReg3;
2170 BuildMI(BB, X86::CMOVNE32rr, 2,
2171 Result+1).addReg(TmpReg3).addReg(TmpReg);
2173 return Result+N.ResNo;
2177 if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
2178 Tmp2 = SelectExpr(N.getOperand(1));
2179 Tmp3 = SelectExpr(N.getOperand(2));
2181 Tmp3 = SelectExpr(N.getOperand(2));
2182 Tmp2 = SelectExpr(N.getOperand(1));
2184 EmitSelectCC(N.getOperand(0), N.getValueType(), Tmp2, Tmp3, Result);
2191 assert((N.getOpcode() != ISD::SREM || MVT::isInteger(N.getValueType())) &&
2192 "We don't support this operator!");
2194 if (N.getOpcode() == ISD::SDIV) {
2195 // We can fold loads into FpDIVs, but not really into any others.
2196 if (N.getValueType() == MVT::f64) {
2197 // Check for reversed and unreversed DIV.
2198 if (isFoldableLoad(N.getOperand(0), N.getOperand(1), true)) {
2199 if (N.getOperand(0).getOpcode() == ISD::EXTLOAD)
2200 Opc = X86::FDIVR32m;
2202 Opc = X86::FDIVR64m;
2204 EmitFoldedLoad(N.getOperand(0), AM);
2205 Tmp1 = SelectExpr(N.getOperand(1));
2206 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
2208 } else if (isFoldableLoad(N.getOperand(1), N.getOperand(0), true) &&
2209 N.getOperand(1).getOpcode() == ISD::LOAD) {
2210 if (N.getOperand(1).getOpcode() == ISD::EXTLOAD)
2215 EmitFoldedLoad(N.getOperand(1), AM);
2216 Tmp1 = SelectExpr(N.getOperand(0));
2217 addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
2222 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2223 // FIXME: These special cases should be handled by the lowering impl!
2224 unsigned RHS = CN->getValue();
2230 if (RHS && (RHS & (RHS-1)) == 0) { // Signed division by power of 2?
2231 unsigned Log = log2(RHS);
2232 unsigned TmpReg = MakeReg(N.getValueType());
2233 unsigned SAROpc, SHROpc, ADDOpc, NEGOpc;
2234 switch (N.getValueType()) {
2235 default: assert("Unknown type to signed divide!");
2237 SAROpc = X86::SAR8ri;
2238 SHROpc = X86::SHR8ri;
2239 ADDOpc = X86::ADD8rr;
2240 NEGOpc = X86::NEG8r;
2243 SAROpc = X86::SAR16ri;
2244 SHROpc = X86::SHR16ri;
2245 ADDOpc = X86::ADD16rr;
2246 NEGOpc = X86::NEG16r;
2249 SAROpc = X86::SAR32ri;
2250 SHROpc = X86::SHR32ri;
2251 ADDOpc = X86::ADD32rr;
2252 NEGOpc = X86::NEG32r;
2255 Tmp1 = SelectExpr(N.getOperand(0));
2256 BuildMI(BB, SAROpc, 2, TmpReg).addReg(Tmp1).addImm(Log-1);
2257 unsigned TmpReg2 = MakeReg(N.getValueType());
2258 BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(32-Log);
2259 unsigned TmpReg3 = MakeReg(N.getValueType());
2260 BuildMI(BB, ADDOpc, 2, TmpReg3).addReg(Tmp1).addReg(TmpReg2);
2262 unsigned TmpReg4 = isNeg ? MakeReg(N.getValueType()) : Result;
2263 BuildMI(BB, SAROpc, 2, TmpReg4).addReg(TmpReg3).addImm(Log);
2265 BuildMI(BB, NEGOpc, 1, Result).addReg(TmpReg4);
2271 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2272 Tmp1 = SelectExpr(N.getOperand(0));
2273 Tmp2 = SelectExpr(N.getOperand(1));
2275 Tmp2 = SelectExpr(N.getOperand(1));
2276 Tmp1 = SelectExpr(N.getOperand(0));
2279 bool isSigned = N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::SREM;
2280 bool isDiv = N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::UDIV;
2281 unsigned LoReg, HiReg, DivOpcode, MovOpcode, ClrOpcode, SExtOpcode;
2282 switch (N.getValueType()) {
2283 default: assert(0 && "Cannot sdiv this type!");
2285 DivOpcode = isSigned ? X86::IDIV8r : X86::DIV8r;
2288 MovOpcode = X86::MOV8rr;
2289 ClrOpcode = X86::MOV8ri;
2290 SExtOpcode = X86::CBW;
2293 DivOpcode = isSigned ? X86::IDIV16r : X86::DIV16r;
2296 MovOpcode = X86::MOV16rr;
2297 ClrOpcode = X86::MOV16ri;
2298 SExtOpcode = X86::CWD;
2301 DivOpcode = isSigned ? X86::IDIV32r : X86::DIV32r;
2304 MovOpcode = X86::MOV32rr;
2305 ClrOpcode = X86::MOV32ri;
2306 SExtOpcode = X86::CDQ;
2309 BuildMI(BB, X86::FpDIV, 2, Result).addReg(Tmp1).addReg(Tmp2);
2313 // Set up the low part.
2314 BuildMI(BB, MovOpcode, 1, LoReg).addReg(Tmp1);
2317 // Sign extend the low part into the high part.
2318 BuildMI(BB, SExtOpcode, 0);
2320 // Zero out the high part, effectively zero extending the input.
2321 BuildMI(BB, ClrOpcode, 1, HiReg).addImm(0);
2324 // Emit the DIV/IDIV instruction.
2325 BuildMI(BB, DivOpcode, 1).addReg(Tmp2);
2327 // Get the result of the divide or rem.
2328 BuildMI(BB, MovOpcode, 1, Result).addReg(isDiv ? LoReg : HiReg);
2333 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2334 if (CN->getValue() == 1) { // X = SHL Y, 1 -> X = ADD Y, Y
2335 switch (N.getValueType()) {
2336 default: assert(0 && "Cannot shift this type!");
2337 case MVT::i8: Opc = X86::ADD8rr; break;
2338 case MVT::i16: Opc = X86::ADD16rr; break;
2339 case MVT::i32: Opc = X86::ADD32rr; break;
2341 Tmp1 = SelectExpr(N.getOperand(0));
2342 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp1);
2346 switch (N.getValueType()) {
2347 default: assert(0 && "Cannot shift this type!");
2348 case MVT::i8: Opc = X86::SHL8ri; break;
2349 case MVT::i16: Opc = X86::SHL16ri; break;
2350 case MVT::i32: Opc = X86::SHL32ri; break;
2352 Tmp1 = SelectExpr(N.getOperand(0));
2353 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
2357 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2358 Tmp1 = SelectExpr(N.getOperand(0));
2359 Tmp2 = SelectExpr(N.getOperand(1));
2361 Tmp2 = SelectExpr(N.getOperand(1));
2362 Tmp1 = SelectExpr(N.getOperand(0));
2365 switch (N.getValueType()) {
2366 default: assert(0 && "Cannot shift this type!");
2367 case MVT::i8 : Opc = X86::SHL8rCL; break;
2368 case MVT::i16: Opc = X86::SHL16rCL; break;
2369 case MVT::i32: Opc = X86::SHL32rCL; break;
2371 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
2372 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
2375 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2376 switch (N.getValueType()) {
2377 default: assert(0 && "Cannot shift this type!");
2378 case MVT::i8: Opc = X86::SHR8ri; break;
2379 case MVT::i16: Opc = X86::SHR16ri; break;
2380 case MVT::i32: Opc = X86::SHR32ri; break;
2382 Tmp1 = SelectExpr(N.getOperand(0));
2383 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
2387 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2388 Tmp1 = SelectExpr(N.getOperand(0));
2389 Tmp2 = SelectExpr(N.getOperand(1));
2391 Tmp2 = SelectExpr(N.getOperand(1));
2392 Tmp1 = SelectExpr(N.getOperand(0));
2395 switch (N.getValueType()) {
2396 default: assert(0 && "Cannot shift this type!");
2397 case MVT::i8 : Opc = X86::SHR8rCL; break;
2398 case MVT::i16: Opc = X86::SHR16rCL; break;
2399 case MVT::i32: Opc = X86::SHR32rCL; break;
2401 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
2402 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
2405 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2406 switch (N.getValueType()) {
2407 default: assert(0 && "Cannot shift this type!");
2408 case MVT::i8: Opc = X86::SAR8ri; break;
2409 case MVT::i16: Opc = X86::SAR16ri; break;
2410 case MVT::i32: Opc = X86::SAR32ri; break;
2412 Tmp1 = SelectExpr(N.getOperand(0));
2413 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CN->getValue());
2417 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2418 Tmp1 = SelectExpr(N.getOperand(0));
2419 Tmp2 = SelectExpr(N.getOperand(1));
2421 Tmp2 = SelectExpr(N.getOperand(1));
2422 Tmp1 = SelectExpr(N.getOperand(0));
2425 switch (N.getValueType()) {
2426 default: assert(0 && "Cannot shift this type!");
2427 case MVT::i8 : Opc = X86::SAR8rCL; break;
2428 case MVT::i16: Opc = X86::SAR16rCL; break;
2429 case MVT::i32: Opc = X86::SAR32rCL; break;
2431 BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
2432 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
2436 EmitCMP(N.getOperand(0), N.getOperand(1), Node->hasOneUse());
2437 EmitSetCC(BB, Result, cast<SetCCSDNode>(N)->getCondition(),
2438 MVT::isFloatingPoint(N.getOperand(1).getValueType()));
2441 // Make sure we generate both values.
2442 if (Result != 1) { // Generate the token
2443 if (!ExprMap.insert(std::make_pair(N.getValue(1), 1)).second)
2444 assert(0 && "Load already emitted!?");
2446 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2448 switch (Node->getValueType(0)) {
2449 default: assert(0 && "Cannot load this type!");
2451 case MVT::i8: Opc = X86::MOV8rm; break;
2452 case MVT::i16: Opc = X86::MOV16rm; break;
2453 case MVT::i32: Opc = X86::MOV32rm; break;
2454 case MVT::f64: Opc = X86::FLD64m; ContainsFPCode = true; break;
2457 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1))){
2458 Select(N.getOperand(0));
2459 addConstantPoolReference(BuildMI(BB, Opc, 4, Result), CP->getIndex());
2463 SDOperand Chain = N.getOperand(0);
2464 SDOperand Address = N.getOperand(1);
2465 if (getRegPressure(Chain) > getRegPressure(Address)) {
2467 SelectAddress(Address, AM);
2469 SelectAddress(Address, AM);
2473 addFullAddress(BuildMI(BB, Opc, 4, Result), AM);
2477 case ISD::EXTLOAD: // Arbitrarily codegen extloads as MOVZX*
2478 case ISD::ZEXTLOAD: {
2479 // Make sure we generate both values.
2481 ExprMap[N.getValue(1)] = 1; // Generate the token
2483 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2485 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
2486 if (Node->getValueType(0) == MVT::f64) {
2487 assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
2489 addConstantPoolReference(BuildMI(BB, X86::FLD32m, 4, Result),
2495 if (getRegPressure(Node->getOperand(0)) >
2496 getRegPressure(Node->getOperand(1))) {
2497 Select(Node->getOperand(0)); // chain
2498 SelectAddress(Node->getOperand(1), AM);
2500 SelectAddress(Node->getOperand(1), AM);
2501 Select(Node->getOperand(0)); // chain
2504 switch (Node->getValueType(0)) {
2505 default: assert(0 && "Unknown type to sign extend to.");
2507 assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
2509 addFullAddress(BuildMI(BB, X86::FLD32m, 5, Result), AM);
2512 switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
2514 assert(0 && "Bad zero extend!");
2517 addFullAddress(BuildMI(BB, X86::MOVZX32rm8, 5, Result), AM);
2520 addFullAddress(BuildMI(BB, X86::MOVZX32rm16, 5, Result), AM);
2525 assert(cast<MVTSDNode>(Node)->getExtraValueType() <= MVT::i8 &&
2526 "Bad zero extend!");
2527 addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
2530 assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i1 &&
2531 "Bad zero extend!");
2532 addFullAddress(BuildMI(BB, X86::MOV8rm, 5, Result), AM);
2537 case ISD::SEXTLOAD: {
2538 // Make sure we generate both values.
2540 ExprMap[N.getValue(1)] = 1; // Generate the token
2542 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2545 if (getRegPressure(Node->getOperand(0)) >
2546 getRegPressure(Node->getOperand(1))) {
2547 Select(Node->getOperand(0)); // chain
2548 SelectAddress(Node->getOperand(1), AM);
2550 SelectAddress(Node->getOperand(1), AM);
2551 Select(Node->getOperand(0)); // chain
2554 switch (Node->getValueType(0)) {
2555 case MVT::i8: assert(0 && "Cannot sign extend from bool!");
2556 default: assert(0 && "Unknown type to sign extend to.");
2558 switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
2560 case MVT::i1: assert(0 && "Cannot sign extend from bool!");
2562 addFullAddress(BuildMI(BB, X86::MOVSX32rm8, 5, Result), AM);
2565 addFullAddress(BuildMI(BB, X86::MOVSX32rm16, 5, Result), AM);
2570 assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i8 &&
2571 "Cannot sign extend from bool!");
2572 addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
2578 case ISD::DYNAMIC_STACKALLOC:
2579 // Generate both result values.
2581 ExprMap[N.getValue(1)] = 1; // Generate the token
2583 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
2585 // FIXME: We are currently ignoring the requested alignment for handling
2586 // greater than the stack alignment. This will need to be revisited at some
2587 // point. Align = N.getOperand(2);
2589 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
2590 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
2591 std::cerr << "Cannot allocate stack object with greater alignment than"
2592 << " the stack alignment yet!";
2596 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
2597 Select(N.getOperand(0));
2598 BuildMI(BB, X86::SUB32ri, 2, X86::ESP).addReg(X86::ESP)
2599 .addImm(CN->getValue());
2601 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2602 Select(N.getOperand(0));
2603 Tmp1 = SelectExpr(N.getOperand(1));
2605 Tmp1 = SelectExpr(N.getOperand(1));
2606 Select(N.getOperand(0));
2609 // Subtract size from stack pointer, thereby allocating some space.
2610 BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(Tmp1);
2613 // Put a pointer to the space into the result register, by copying the stack
2615 BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::ESP);
2619 // The chain for this call is now lowered.
2620 ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), 1));
2622 if (GlobalAddressSDNode *GASD =
2623 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
2624 Select(N.getOperand(0));
2625 BuildMI(BB, X86::CALLpcrel32, 1).addGlobalAddress(GASD->getGlobal(),true);
2626 } else if (ExternalSymbolSDNode *ESSDN =
2627 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
2628 Select(N.getOperand(0));
2629 BuildMI(BB, X86::CALLpcrel32,
2630 1).addExternalSymbol(ESSDN->getSymbol(), true);
2632 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2633 Select(N.getOperand(0));
2634 Tmp1 = SelectExpr(N.getOperand(1));
2636 Tmp1 = SelectExpr(N.getOperand(1));
2637 Select(N.getOperand(0));
2640 BuildMI(BB, X86::CALL32r, 1).addReg(Tmp1);
2642 switch (Node->getValueType(0)) {
2643 default: assert(0 && "Unknown value type for call result!");
2644 case MVT::Other: return 1;
2647 BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
2650 BuildMI(BB, X86::MOV16rr, 1, Result).addReg(X86::AX);
2653 BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::EAX);
2654 if (Node->getValueType(1) == MVT::i32)
2655 BuildMI(BB, X86::MOV32rr, 1, Result+1).addReg(X86::EDX);
2657 case MVT::f64: // Floating-point return values live in %ST(0)
2658 ContainsFPCode = true;
2659 BuildMI(BB, X86::FpGETRESULT, 1, Result);
2662 return Result+N.ResNo;
2668 /// TryToFoldLoadOpStore - Given a store node, try to fold together a
2669 /// load/op/store instruction. If successful return true.
2670 bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
2671 assert(Node->getOpcode() == ISD::STORE && "Can only do this for stores!");
2672 SDOperand Chain = Node->getOperand(0);
2673 SDOperand StVal = Node->getOperand(1);
2674 SDOperand StPtr = Node->getOperand(2);
2676 // The chain has to be a load, the stored value must be an integer binary
2677 // operation with one use.
2678 if (!StVal.Val->hasOneUse() || StVal.Val->getNumOperands() != 2 ||
2679 MVT::isFloatingPoint(StVal.getValueType()))
2682 // Token chain must either be a factor node or the load to fold.
2683 if (Chain.getOpcode() != ISD::LOAD && Chain.getOpcode() != ISD::TokenFactor)
2688 // Check to see if there is a load from the same pointer that we're storing
2689 // to in either operand of the binop.
2690 if (StVal.getOperand(0).getOpcode() == ISD::LOAD &&
2691 StVal.getOperand(0).getOperand(1) == StPtr)
2692 TheLoad = StVal.getOperand(0);
2693 else if (StVal.getOperand(1).getOpcode() == ISD::LOAD &&
2694 StVal.getOperand(1).getOperand(1) == StPtr)
2695 TheLoad = StVal.getOperand(1);
2697 return false; // No matching load operand.
2699 // We can only fold the load if there are no intervening side-effecting
2700 // operations. This means that the store uses the load as its token chain, or
2701 // there are only token factor nodes in between the store and load.
2702 if (Chain != TheLoad.getValue(1)) {
2703 // Okay, the other option is that we have a store referring to (possibly
2704 // nested) token factor nodes. For now, just try peeking through one level
2705 // of token factors to see if this is the case.
2706 bool ChainOk = false;
2707 if (Chain.getOpcode() == ISD::TokenFactor) {
2708 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
2709 if (Chain.getOperand(i) == TheLoad.getValue(1)) {
2715 if (!ChainOk) return false;
2718 if (TheLoad.getOperand(1) != StPtr)
2721 // Make sure that one of the operands of the binop is the load, and that the
2722 // load folds into the binop.
2723 if (((StVal.getOperand(0) != TheLoad ||
2724 !isFoldableLoad(TheLoad, StVal.getOperand(1))) &&
2725 (StVal.getOperand(1) != TheLoad ||
2726 !isFoldableLoad(TheLoad, StVal.getOperand(0)))))
2729 // Finally, check to see if this is one of the ops we can handle!
2730 static const unsigned ADDTAB[] = {
2731 X86::ADD8mi, X86::ADD16mi, X86::ADD32mi,
2732 X86::ADD8mr, X86::ADD16mr, X86::ADD32mr,
2734 static const unsigned SUBTAB[] = {
2735 X86::SUB8mi, X86::SUB16mi, X86::SUB32mi,
2736 X86::SUB8mr, X86::SUB16mr, X86::SUB32mr,
2738 static const unsigned ANDTAB[] = {
2739 X86::AND8mi, X86::AND16mi, X86::AND32mi,
2740 X86::AND8mr, X86::AND16mr, X86::AND32mr,
2742 static const unsigned ORTAB[] = {
2743 X86::OR8mi, X86::OR16mi, X86::OR32mi,
2744 X86::OR8mr, X86::OR16mr, X86::OR32mr,
2746 static const unsigned XORTAB[] = {
2747 X86::XOR8mi, X86::XOR16mi, X86::XOR32mi,
2748 X86::XOR8mr, X86::XOR16mr, X86::XOR32mr,
2750 static const unsigned SHLTAB[] = {
2751 X86::SHL8mi, X86::SHL16mi, X86::SHL32mi,
2752 /*Have to put the reg in CL*/0, 0, 0,
2754 static const unsigned SARTAB[] = {
2755 X86::SAR8mi, X86::SAR16mi, X86::SAR32mi,
2756 /*Have to put the reg in CL*/0, 0, 0,
2758 static const unsigned SHRTAB[] = {
2759 X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
2760 /*Have to put the reg in CL*/0, 0, 0,
2763 const unsigned *TabPtr = 0;
2764 switch (StVal.getOpcode()) {
2766 std::cerr << "CANNOT [mem] op= val: ";
2767 StVal.Val->dump(); std::cerr << "\n";
2772 case ISD::UREM: return false;
2774 case ISD::ADD: TabPtr = ADDTAB; break;
2775 case ISD::SUB: TabPtr = SUBTAB; break;
2776 case ISD::AND: TabPtr = ANDTAB; break;
2777 case ISD:: OR: TabPtr = ORTAB; break;
2778 case ISD::XOR: TabPtr = XORTAB; break;
2779 case ISD::SHL: TabPtr = SHLTAB; break;
2780 case ISD::SRA: TabPtr = SARTAB; break;
2781 case ISD::SRL: TabPtr = SHRTAB; break;
2784 // Handle: [mem] op= CST
2785 SDOperand Op0 = StVal.getOperand(0);
2786 SDOperand Op1 = StVal.getOperand(1);
2788 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
2789 switch (Op0.getValueType()) { // Use Op0's type because of shifts.
2792 case MVT::i8: Opc = TabPtr[0]; break;
2793 case MVT::i16: Opc = TabPtr[1]; break;
2794 case MVT::i32: Opc = TabPtr[2]; break;
2798 if (!ExprMap.insert(std::make_pair(TheLoad.getValue(1), 1)).second)
2799 assert(0 && "Already emitted?");
2803 if (getRegPressure(TheLoad.getOperand(0)) >
2804 getRegPressure(TheLoad.getOperand(1))) {
2805 Select(TheLoad.getOperand(0));
2806 SelectAddress(TheLoad.getOperand(1), AM);
2808 SelectAddress(TheLoad.getOperand(1), AM);
2809 Select(TheLoad.getOperand(0));
2812 if (StVal.getOpcode() == ISD::ADD) {
2813 if (CN->getValue() == 1) {
2814 switch (Op0.getValueType()) {
2817 addFullAddress(BuildMI(BB, X86::INC8m, 4), AM);
2819 case MVT::i16: Opc = TabPtr[1];
2820 addFullAddress(BuildMI(BB, X86::INC16m, 4), AM);
2822 case MVT::i32: Opc = TabPtr[2];
2823 addFullAddress(BuildMI(BB, X86::INC32m, 4), AM);
2826 } else if (CN->getValue()+1 == 0) { // [X] += -1 -> DEC [X]
2827 switch (Op0.getValueType()) {
2830 addFullAddress(BuildMI(BB, X86::DEC8m, 4), AM);
2832 case MVT::i16: Opc = TabPtr[1];
2833 addFullAddress(BuildMI(BB, X86::DEC16m, 4), AM);
2835 case MVT::i32: Opc = TabPtr[2];
2836 addFullAddress(BuildMI(BB, X86::DEC32m, 4), AM);
2842 addFullAddress(BuildMI(BB, Opc, 4+1),AM).addImm(CN->getValue());
2847 // If we have [mem] = V op [mem], try to turn it into:
2848 // [mem] = [mem] op V.
2849 if (Op1 == TheLoad && StVal.getOpcode() != ISD::SUB &&
2850 StVal.getOpcode() != ISD::SHL && StVal.getOpcode() != ISD::SRA &&
2851 StVal.getOpcode() != ISD::SRL)
2852 std::swap(Op0, Op1);
2854 if (Op0 != TheLoad) return false;
2856 switch (Op0.getValueType()) {
2857 default: return false;
2859 case MVT::i8: Opc = TabPtr[3]; break;
2860 case MVT::i16: Opc = TabPtr[4]; break;
2861 case MVT::i32: Opc = TabPtr[5]; break;
2864 // Table entry doesn't exist?
2865 if (Opc == 0) return false;
2867 if (!ExprMap.insert(std::make_pair(TheLoad.getValue(1), 1)).second)
2868 assert(0 && "Already emitted?");
2870 Select(TheLoad.getOperand(0));
2873 SelectAddress(TheLoad.getOperand(1), AM);
2874 unsigned Reg = SelectExpr(Op1);
2875 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Reg);
2880 void ISel::Select(SDOperand N) {
2881 unsigned Tmp1, Tmp2, Opc;
2883 if (!ExprMap.insert(std::make_pair(N, 1)).second)
2884 return; // Already selected.
2886 SDNode *Node = N.Val;
2888 switch (Node->getOpcode()) {
2890 Node->dump(); std::cerr << "\n";
2891 assert(0 && "Node not handled yet!");
2892 case ISD::EntryToken: return; // Noop
2893 case ISD::TokenFactor:
2894 if (Node->getNumOperands() == 2) {
2896 getRegPressure(Node->getOperand(1))>getRegPressure(Node->getOperand(0));
2897 Select(Node->getOperand(OneFirst));
2898 Select(Node->getOperand(!OneFirst));
2900 std::vector<std::pair<unsigned, unsigned> > OpsP;
2901 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
2902 OpsP.push_back(std::make_pair(getRegPressure(Node->getOperand(i)), i));
2903 std::sort(OpsP.begin(), OpsP.end());
2904 std::reverse(OpsP.begin(), OpsP.end());
2905 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
2906 Select(Node->getOperand(OpsP[i].second));
2909 case ISD::CopyToReg:
2910 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2911 Select(N.getOperand(0));
2912 Tmp1 = SelectExpr(N.getOperand(1));
2914 Tmp1 = SelectExpr(N.getOperand(1));
2915 Select(N.getOperand(0));
2917 Tmp2 = cast<RegSDNode>(N)->getReg();
2920 switch (N.getOperand(1).getValueType()) {
2921 default: assert(0 && "Invalid type for operation!");
2923 case MVT::i8: Opc = X86::MOV8rr; break;
2924 case MVT::i16: Opc = X86::MOV16rr; break;
2925 case MVT::i32: Opc = X86::MOV32rr; break;
2926 case MVT::f64: Opc = X86::FpMOV; ContainsFPCode = true; break;
2928 BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
2932 switch (N.getNumOperands()) {
2934 assert(0 && "Unknown return instruction!");
2936 assert(N.getOperand(1).getValueType() == MVT::i32 &&
2937 N.getOperand(2).getValueType() == MVT::i32 &&
2938 "Unknown two-register value!");
2939 if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
2940 Tmp1 = SelectExpr(N.getOperand(1));
2941 Tmp2 = SelectExpr(N.getOperand(2));
2943 Tmp2 = SelectExpr(N.getOperand(2));
2944 Tmp1 = SelectExpr(N.getOperand(1));
2946 Select(N.getOperand(0));
2948 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
2949 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(Tmp2);
2952 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2953 Select(N.getOperand(0));
2954 Tmp1 = SelectExpr(N.getOperand(1));
2956 Tmp1 = SelectExpr(N.getOperand(1));
2957 Select(N.getOperand(0));
2959 switch (N.getOperand(1).getValueType()) {
2960 default: assert(0 && "All other types should have been promoted!!");
2962 BuildMI(BB, X86::FpSETRESULT, 1).addReg(Tmp1);
2965 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
2970 Select(N.getOperand(0));
2973 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
2976 Select(N.getOperand(0));
2977 MachineBasicBlock *Dest =
2978 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
2979 BuildMI(BB, X86::JMP, 1).addMBB(Dest);
2984 MachineBasicBlock *Dest =
2985 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
2987 // Try to fold a setcc into the branch. If this fails, emit a test/jne
2989 if (EmitBranchCC(Dest, N.getOperand(0), N.getOperand(1))) {
2990 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
2991 Select(N.getOperand(0));
2992 Tmp1 = SelectExpr(N.getOperand(1));
2994 Tmp1 = SelectExpr(N.getOperand(1));
2995 Select(N.getOperand(0));
2997 BuildMI(BB, X86::TEST8rr, 2).addReg(Tmp1).addReg(Tmp1);
2998 BuildMI(BB, X86::JNE, 1).addMBB(Dest);
3005 // If this load could be folded into the only using instruction, and if it
3006 // is safe to emit the instruction here, try to do so now.
3007 if (Node->hasNUsesOfValue(1, 0)) {
3008 SDOperand TheVal = N.getValue(0);
3010 for (SDNode::use_iterator UI = Node->use_begin(); ; ++UI) {
3011 assert(UI != Node->use_end() && "Didn't find use!");
3013 for (unsigned i = 0, e = UN->getNumOperands(); i != e; ++i)
3014 if (UN->getOperand(i) == TheVal) {
3020 // Only handle unary operators right now.
3021 if (User->getNumOperands() == 1) {
3023 SelectExpr(SDOperand(User, 0));
3035 case ISD::DYNAMIC_STACKALLOC:
3040 case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety
3041 // On X86, we can represent all types except for Bool and Float natively.
3043 MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType();
3044 assert((StoredTy == MVT::i1 || StoredTy == MVT::f32 ||
3045 StoredTy == MVT::i16 /*FIXME: THIS IS JUST FOR TESTING!*/)
3046 && "Unsupported TRUNCSTORE for this target!");
3048 if (StoredTy == MVT::i16) {
3049 // FIXME: This is here just to allow testing. X86 doesn't really have a
3050 // TRUNCSTORE i16 operation, but this is required for targets that do not
3051 // have 16-bit integer registers. We occasionally disable 16-bit integer
3052 // registers to test the promotion code.
3053 Select(N.getOperand(0));
3054 Tmp1 = SelectExpr(N.getOperand(1));
3055 SelectAddress(N.getOperand(2), AM);
3057 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
3058 addFullAddress(BuildMI(BB, X86::MOV16mr, 5), AM).addReg(X86::AX);
3062 // Store of constant bool?
3063 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
3064 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
3065 Select(N.getOperand(0));
3066 SelectAddress(N.getOperand(2), AM);
3068 SelectAddress(N.getOperand(2), AM);
3069 Select(N.getOperand(0));
3071 addFullAddress(BuildMI(BB, X86::MOV8mi, 5), AM).addImm(CN->getValue());
3076 default: assert(0 && "Cannot truncstore this type!");
3077 case MVT::i1: Opc = X86::MOV8mr; break;
3078 case MVT::f32: Opc = X86::FST32m; break;
3081 std::vector<std::pair<unsigned, unsigned> > RP;
3082 RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
3083 RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
3084 RP.push_back(std::make_pair(getRegPressure(N.getOperand(2)), 2));
3085 std::sort(RP.begin(), RP.end());
3087 Tmp1 = 0; // Silence a warning.
3088 for (unsigned i = 0; i != 3; ++i)
3089 switch (RP[2-i].second) {
3090 default: assert(0 && "Unknown operand number!");
3091 case 0: Select(N.getOperand(0)); break;
3092 case 1: Tmp1 = SelectExpr(N.getOperand(1)); break;
3093 case 2: SelectAddress(N.getOperand(2), AM); break;
3096 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Tmp1);
3102 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
3104 switch (CN->getValueType(0)) {
3105 default: assert(0 && "Invalid type for operation!");
3107 case MVT::i8: Opc = X86::MOV8mi; break;
3108 case MVT::i16: Opc = X86::MOV16mi; break;
3109 case MVT::i32: Opc = X86::MOV32mi; break;
3110 case MVT::f64: break;
3113 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
3114 Select(N.getOperand(0));
3115 SelectAddress(N.getOperand(2), AM);
3117 SelectAddress(N.getOperand(2), AM);
3118 Select(N.getOperand(0));
3120 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addImm(CN->getValue());
3123 } else if (GlobalAddressSDNode *GA =
3124 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
3125 assert(GA->getValueType(0) == MVT::i32 && "Bad pointer operand");
3127 if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
3128 Select(N.getOperand(0));
3129 SelectAddress(N.getOperand(2), AM);
3131 SelectAddress(N.getOperand(2), AM);
3132 Select(N.getOperand(0));
3134 addFullAddress(BuildMI(BB, X86::MOV32mi, 4+1),
3135 AM).addGlobalAddress(GA->getGlobal());
3139 // Check to see if this is a load/op/store combination.
3140 if (TryToFoldLoadOpStore(Node))
3143 switch (N.getOperand(1).getValueType()) {
3144 default: assert(0 && "Cannot store this type!");
3146 case MVT::i8: Opc = X86::MOV8mr; break;
3147 case MVT::i16: Opc = X86::MOV16mr; break;
3148 case MVT::i32: Opc = X86::MOV32mr; break;
3149 case MVT::f64: Opc = X86::FST64m; break;
3152 std::vector<std::pair<unsigned, unsigned> > RP;
3153 RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
3154 RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
3155 RP.push_back(std::make_pair(getRegPressure(N.getOperand(2)), 2));
3156 std::sort(RP.begin(), RP.end());
3158 Tmp1 = 0; // Silence a warning.
3159 for (unsigned i = 0; i != 3; ++i)
3160 switch (RP[2-i].second) {
3161 default: assert(0 && "Unknown operand number!");
3162 case 0: Select(N.getOperand(0)); break;
3163 case 1: Tmp1 = SelectExpr(N.getOperand(1)); break;
3164 case 2: SelectAddress(N.getOperand(2), AM); break;
3167 addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Tmp1);
3170 case ISD::ADJCALLSTACKDOWN:
3171 case ISD::ADJCALLSTACKUP:
3172 Select(N.getOperand(0));
3173 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
3175 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? X86::ADJCALLSTACKDOWN :
3176 X86::ADJCALLSTACKUP;
3177 BuildMI(BB, Opc, 1).addImm(Tmp1);
3180 Select(N.getOperand(0)); // Select the chain.
3182 (unsigned)cast<ConstantSDNode>(Node->getOperand(4))->getValue();
3183 if (Align == 0) Align = 1;
3185 // Turn the byte code into # iterations
3188 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
3189 unsigned Val = ValC->getValue() & 255;
3191 // If the value is a constant, then we can potentially use larger sets.
3192 switch (Align & 3) {
3193 case 2: // WORD aligned
3194 CountReg = MakeReg(MVT::i32);
3195 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3196 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/2);
3198 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3199 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
3201 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
3202 Opcode = X86::REP_STOSW;
3204 case 0: // DWORD aligned
3205 CountReg = MakeReg(MVT::i32);
3206 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3207 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/4);
3209 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3210 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
3212 Val = (Val << 8) | Val;
3213 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
3214 Opcode = X86::REP_STOSD;
3216 default: // BYTE aligned
3217 CountReg = SelectExpr(Node->getOperand(3));
3218 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
3219 Opcode = X86::REP_STOSB;
3223 // If it's not a constant value we are storing, just fall back. We could
3224 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
3225 unsigned ValReg = SelectExpr(Node->getOperand(2));
3226 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
3227 CountReg = SelectExpr(Node->getOperand(3));
3228 Opcode = X86::REP_STOSB;
3231 // No matter what the alignment is, we put the source in ESI, the
3232 // destination in EDI, and the count in ECX.
3233 unsigned TmpReg1 = SelectExpr(Node->getOperand(1));
3234 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
3235 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
3236 BuildMI(BB, Opcode, 0);
3240 Select(N.getOperand(0)); // Select the chain.
3242 (unsigned)cast<ConstantSDNode>(Node->getOperand(4))->getValue();
3243 if (Align == 0) Align = 1;
3245 // Turn the byte code into # iterations
3248 switch (Align & 3) {
3249 case 2: // WORD aligned
3250 CountReg = MakeReg(MVT::i32);
3251 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3252 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/2);
3254 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3255 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
3257 Opcode = X86::REP_MOVSW;
3259 case 0: // DWORD aligned
3260 CountReg = MakeReg(MVT::i32);
3261 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Node->getOperand(3))) {
3262 BuildMI(BB, X86::MOV32ri, 1, CountReg).addImm(I->getValue()/4);
3264 unsigned ByteReg = SelectExpr(Node->getOperand(3));
3265 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
3267 Opcode = X86::REP_MOVSD;
3269 default: // BYTE aligned
3270 CountReg = SelectExpr(Node->getOperand(3));
3271 Opcode = X86::REP_MOVSB;
3275 // No matter what the alignment is, we put the source in ESI, the
3276 // destination in EDI, and the count in ECX.
3277 unsigned TmpReg1 = SelectExpr(Node->getOperand(1));
3278 unsigned TmpReg2 = SelectExpr(Node->getOperand(2));
3279 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
3280 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
3281 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
3282 BuildMI(BB, Opcode, 0);
3285 assert(0 && "Should not be reached!");
3289 /// createX86PatternInstructionSelector - This pass converts an LLVM function
3290 /// into a machine code representation using pattern matching and a machine
3291 /// description file.
3293 FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
3294 return new ISel(TM);