1 //===-- X86ISelSimple.cpp - A simple instruction selector for x86 ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/Pass.h"
22 #include "llvm/CodeGen/IntrinsicLowering.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/GetElementPtrTypeIterator.h"
31 #include "llvm/Support/InstVisitor.h"
32 #include "llvm/ADT/Statistic.h"
37 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
39 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
43 cByte, cShort, cInt, cFP, cLong
47 /// getClass - Turn a primitive type into a "class" number which is based on the
48 /// size of the type, and whether or not it is floating point.
50 static inline TypeClass getClass(const Type *Ty) {
51 switch (Ty->getTypeID()) {
53 case Type::UByteTyID: return cByte; // Byte operands are class #0
55 case Type::UShortTyID: return cShort; // Short operands are class #1
58 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
61 case Type::DoubleTyID: return cFP; // Floating Point is #3
64 case Type::ULongTyID: return cLong; // Longs are class #4
66 assert(0 && "Invalid type to getClass!");
67 return cByte; // not reached
71 // getClassB - Just like getClass, but treat boolean values as bytes.
72 static inline TypeClass getClassB(const Type *Ty) {
73 if (Ty == Type::BoolTy) return cByte;
78 struct X86ISel : public FunctionPass, InstVisitor<X86ISel> {
80 MachineFunction *F; // The function we are compiling into
81 MachineBasicBlock *BB; // The current MBB we are compiling
82 int VarArgsFrameIndex; // FrameIndex for start of varargs area
83 int ReturnAddressIndex; // FrameIndex for the return address
85 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
87 // MBBMap - Mapping between LLVM BB -> Machine BB
88 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
90 // AllocaMap - Mapping from fixed sized alloca instructions to the
91 // FrameIndex for the alloca.
92 std::map<AllocaInst*, unsigned> AllocaMap;
94 X86ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
96 /// runOnFunction - Top level implementation of instruction selection for
97 /// the entire function.
99 bool runOnFunction(Function &Fn) {
100 // Lazily create a stack slot for the return address if needed.
101 ReturnAddressIndex = 0;
103 // First pass over the function, lower any unknown intrinsic functions
104 // with the IntrinsicLowering class.
105 LowerUnknownIntrinsicFunctionCalls(Fn);
107 F = &MachineFunction::construct(&Fn, TM);
109 // Create all of the machine basic blocks for the function...
110 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
111 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
115 // Copy incoming arguments off of the stack...
116 LoadArgumentsToVirtualRegs(Fn);
118 // If this is main, emit special code.
119 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
120 EmitSpecialCodeForMain();
122 // Instruction select everything except PHI nodes
125 // Select the PHI nodes
128 // Insert the FP_REG_KILL instructions into blocks that need them.
135 // We always build a machine code representation for the function
139 virtual const char *getPassName() const {
140 return "X86 Simple Instruction Selection";
143 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
144 /// the main function.
145 void EmitSpecialCodeForMain();
147 /// visitBasicBlock - This method is called when we are visiting a new basic
148 /// block. This simply creates a new MachineBasicBlock to emit code into
149 /// and adds it to the current MachineFunction. Subsequent visit* for
150 /// instructions will be invoked for all instructions in the basic block.
152 void visitBasicBlock(BasicBlock &LLVM_BB) {
153 BB = MBBMap[&LLVM_BB];
156 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
157 /// function, lowering any calls to unknown intrinsic functions into the
158 /// equivalent LLVM code.
160 void LowerUnknownIntrinsicFunctionCalls(Function &F);
162 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
163 /// from the stack into virtual registers.
165 void LoadArgumentsToVirtualRegs(Function &F);
167 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
168 /// because we have to generate our sources into the source basic blocks,
169 /// not the current one.
171 void SelectPHINodes();
173 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
174 /// that need them. This only occurs due to the floating point stackifier
175 /// not being aggressive enough to handle arbitrary global stackification.
177 void InsertFPRegKills();
179 // Visitation methods for various instructions. These methods simply emit
180 // fixed X86 code for each instruction.
183 // Control flow operators
184 void visitReturnInst(ReturnInst &RI);
185 void visitBranchInst(BranchInst &BI);
186 void visitUnreachableInst(UnreachableInst &UI) {}
192 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
193 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
195 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
196 const std::vector<ValueRecord> &Args);
197 void visitCallInst(CallInst &I);
198 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
200 // Arithmetic operators
201 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
202 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
203 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
204 void visitMul(BinaryOperator &B);
206 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
207 void visitRem(BinaryOperator &B) { visitDivRem(B); }
208 void visitDivRem(BinaryOperator &B);
211 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
212 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
213 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
215 // Comparison operators...
216 void visitSetCondInst(SetCondInst &I);
217 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
218 MachineBasicBlock *MBB,
219 MachineBasicBlock::iterator MBBI);
220 void visitSelectInst(SelectInst &SI);
223 // Memory Instructions
224 void visitLoadInst(LoadInst &I);
225 void visitStoreInst(StoreInst &I);
226 void visitGetElementPtrInst(GetElementPtrInst &I);
227 void visitAllocaInst(AllocaInst &I);
228 void visitMallocInst(MallocInst &I);
229 void visitFreeInst(FreeInst &I);
232 void visitShiftInst(ShiftInst &I);
233 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
234 void visitCastInst(CastInst &I);
235 void visitVAArgInst(VAArgInst &I);
237 void visitInstruction(Instruction &I) {
238 std::cerr << "Cannot instruction select: " << I;
242 /// promote32 - Make a value 32-bits wide, and put it somewhere.
244 void promote32(unsigned targetReg, const ValueRecord &VR);
246 /// getAddressingMode - Get the addressing mode to use to address the
247 /// specified value. The returned value should be used with addFullAddress.
248 void getAddressingMode(Value *Addr, X86AddressMode &AM);
251 /// getGEPIndex - This is used to fold GEP instructions into X86 addressing
253 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
254 std::vector<Value*> &GEPOps,
255 std::vector<const Type*> &GEPTypes,
258 /// isGEPFoldable - Return true if the specified GEP can be completely
259 /// folded into the addressing mode of a load/store or lea instruction.
260 bool isGEPFoldable(MachineBasicBlock *MBB,
261 Value *Src, User::op_iterator IdxBegin,
262 User::op_iterator IdxEnd, X86AddressMode &AM);
264 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
265 /// constant expression GEP support.
267 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
268 Value *Src, User::op_iterator IdxBegin,
269 User::op_iterator IdxEnd, unsigned TargetReg);
271 /// emitCastOperation - Common code shared between visitCastInst and
272 /// constant expression cast support.
274 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
275 Value *Src, const Type *DestTy, unsigned TargetReg);
277 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
278 /// and constant expression support.
280 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
281 MachineBasicBlock::iterator IP,
282 Value *Op0, Value *Op1,
283 unsigned OperatorClass, unsigned TargetReg);
285 /// emitBinaryFPOperation - This method handles emission of floating point
286 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
287 void emitBinaryFPOperation(MachineBasicBlock *BB,
288 MachineBasicBlock::iterator IP,
289 Value *Op0, Value *Op1,
290 unsigned OperatorClass, unsigned TargetReg);
292 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
293 Value *Op0, Value *Op1, unsigned TargetReg);
295 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
296 unsigned DestReg, const Type *DestTy,
297 unsigned Op0Reg, unsigned Op1Reg);
298 void doMultiplyConst(MachineBasicBlock *MBB,
299 MachineBasicBlock::iterator MBBI,
300 unsigned DestReg, const Type *DestTy,
301 unsigned Op0Reg, unsigned Op1Val);
303 void emitDivRemOperation(MachineBasicBlock *BB,
304 MachineBasicBlock::iterator IP,
305 Value *Op0, Value *Op1, bool isDiv,
308 /// emitSetCCOperation - Common code shared between visitSetCondInst and
309 /// constant expression support.
311 void emitSetCCOperation(MachineBasicBlock *BB,
312 MachineBasicBlock::iterator IP,
313 Value *Op0, Value *Op1, unsigned Opcode,
316 /// emitShiftOperation - Common code shared between visitShiftInst and
317 /// constant expression support.
319 void emitShiftOperation(MachineBasicBlock *MBB,
320 MachineBasicBlock::iterator IP,
321 Value *Op, Value *ShiftAmount, bool isLeftShift,
322 const Type *ResultTy, unsigned DestReg);
324 // Emit code for a 'SHLD DestReg, Op0, Op1, Amt' operation, where Amt is a
326 void doSHLDConst(MachineBasicBlock *MBB,
327 MachineBasicBlock::iterator MBBI,
328 unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg,
331 /// emitSelectOperation - Common code shared between visitSelectInst and the
332 /// constant expression support.
333 void emitSelectOperation(MachineBasicBlock *MBB,
334 MachineBasicBlock::iterator IP,
335 Value *Cond, Value *TrueVal, Value *FalseVal,
338 /// copyConstantToRegister - Output the instructions required to put the
339 /// specified constant into the specified register.
341 void copyConstantToRegister(MachineBasicBlock *MBB,
342 MachineBasicBlock::iterator MBBI,
343 Constant *C, unsigned Reg);
345 void emitUCOMr(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
346 unsigned LHS, unsigned RHS);
348 /// makeAnotherReg - This method returns the next register number we haven't
351 /// Long values are handled somewhat specially. They are always allocated
352 /// as pairs of 32 bit integer values. The register number returned is the
353 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
354 /// of the long value.
356 unsigned makeAnotherReg(const Type *Ty) {
357 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
358 "Current target doesn't have X86 reg info??");
359 const X86RegisterInfo *MRI =
360 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
361 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
362 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
363 // Create the lower part
364 F->getSSARegMap()->createVirtualRegister(RC);
365 // Create the upper part.
366 return F->getSSARegMap()->createVirtualRegister(RC)-1;
369 // Add the mapping of regnumber => reg class to MachineFunction
370 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
371 return F->getSSARegMap()->createVirtualRegister(RC);
374 /// getReg - This method turns an LLVM value into a register number.
376 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
377 unsigned getReg(Value *V) {
378 // Just append to the end of the current bb.
379 MachineBasicBlock::iterator It = BB->end();
380 return getReg(V, BB, It);
382 unsigned getReg(Value *V, MachineBasicBlock *MBB,
383 MachineBasicBlock::iterator IPt);
385 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
386 /// that is to be statically allocated with the initial stack frame
388 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
392 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
393 /// instruction in the entry block, return it. Otherwise, return a null
395 static AllocaInst *dyn_castFixedAlloca(Value *V) {
396 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
397 BasicBlock *BB = AI->getParent();
398 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
404 /// getReg - This method turns an LLVM value into a register number.
406 unsigned X86ISel::getReg(Value *V, MachineBasicBlock *MBB,
407 MachineBasicBlock::iterator IPt) {
408 // If this operand is a constant, emit the code to copy the constant into
409 // the register here...
410 if (Constant *C = dyn_cast<Constant>(V)) {
411 unsigned Reg = makeAnotherReg(V->getType());
412 copyConstantToRegister(MBB, IPt, C, Reg);
414 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
415 // Do not emit noop casts at all, unless it's a double -> float cast.
416 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()) &&
417 (CI->getType() != Type::FloatTy ||
418 CI->getOperand(0)->getType() != Type::DoubleTy))
419 return getReg(CI->getOperand(0), MBB, IPt);
420 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
421 // If the alloca address couldn't be folded into the instruction addressing,
422 // emit an explicit LEA as appropriate.
423 unsigned Reg = makeAnotherReg(V->getType());
424 unsigned FI = getFixedSizedAllocaFI(AI);
425 addFrameReference(BuildMI(*MBB, IPt, X86::LEA32r, 4, Reg), FI);
429 unsigned &Reg = RegMap[V];
431 Reg = makeAnotherReg(V->getType());
438 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
439 /// that is to be statically allocated with the initial stack frame
441 unsigned X86ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
442 // Already computed this?
443 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
444 if (I != AllocaMap.end() && I->first == AI) return I->second;
446 const Type *Ty = AI->getAllocatedType();
447 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
448 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
449 TySize *= CUI->getValue(); // Get total allocated size...
450 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
452 // Create a new stack object using the frame manager...
453 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
454 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
459 /// copyConstantToRegister - Output the instructions required to put the
460 /// specified constant into the specified register.
462 void X86ISel::copyConstantToRegister(MachineBasicBlock *MBB,
463 MachineBasicBlock::iterator IP,
464 Constant *C, unsigned R) {
465 if (isa<UndefValue>(C)) {
466 switch (getClassB(C->getType())) {
468 // FIXME: SHOULD TEACH STACKIFIER ABOUT UNDEF VALUES!
469 BuildMI(*MBB, IP, X86::FLD0, 0, R);
472 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, R+1);
475 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, R);
478 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
480 switch (CE->getOpcode()) {
481 case Instruction::GetElementPtr:
482 emitGEPOperation(MBB, IP, CE->getOperand(0),
483 CE->op_begin()+1, CE->op_end(), R);
485 case Instruction::Cast:
486 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
489 case Instruction::Xor: ++Class; // FALL THROUGH
490 case Instruction::Or: ++Class; // FALL THROUGH
491 case Instruction::And: ++Class; // FALL THROUGH
492 case Instruction::Sub: ++Class; // FALL THROUGH
493 case Instruction::Add:
494 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
498 case Instruction::Mul:
499 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
502 case Instruction::Div:
503 case Instruction::Rem:
504 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
505 CE->getOpcode() == Instruction::Div, R);
508 case Instruction::SetNE:
509 case Instruction::SetEQ:
510 case Instruction::SetLT:
511 case Instruction::SetGT:
512 case Instruction::SetLE:
513 case Instruction::SetGE:
514 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
518 case Instruction::Shl:
519 case Instruction::Shr:
520 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
521 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
524 case Instruction::Select:
525 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
526 CE->getOperand(2), R);
530 std::cerr << "Offending expr: " << *C << "\n";
531 assert(0 && "Constant expression not yet handled!\n");
535 if (C->getType()->isIntegral()) {
536 unsigned Class = getClassB(C->getType());
538 if (Class == cLong) {
539 // Copy the value into the register pair.
540 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
541 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(Val & 0xFFFFFFFF);
542 BuildMI(*MBB, IP, X86::MOV32ri, 1, R+1).addImm(Val >> 32);
546 assert(Class <= cInt && "Type not handled yet!");
548 static const unsigned IntegralOpcodeTab[] = {
549 X86::MOV8ri, X86::MOV16ri, X86::MOV32ri
552 if (C->getType() == Type::BoolTy) {
553 BuildMI(*MBB, IP, X86::MOV8ri, 1, R).addImm(C == ConstantBool::True);
555 ConstantInt *CI = cast<ConstantInt>(C);
556 BuildMI(*MBB, IP, IntegralOpcodeTab[Class],1,R).addImm(CI->getRawValue());
558 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
559 if (CFP->isExactlyValue(+0.0))
560 BuildMI(*MBB, IP, X86::FLD0, 0, R);
561 else if (CFP->isExactlyValue(+1.0))
562 BuildMI(*MBB, IP, X86::FLD1, 0, R);
563 else if (CFP->isExactlyValue(-0.0)) {
564 unsigned Tmp = makeAnotherReg(Type::DoubleTy);
565 BuildMI(*MBB, IP, X86::FLD0, 0, Tmp);
566 BuildMI(*MBB, IP, X86::FCHS, 1, R).addReg(Tmp);
567 } else if (CFP->isExactlyValue(-1.0)) {
568 unsigned Tmp = makeAnotherReg(Type::DoubleTy);
569 BuildMI(*MBB, IP, X86::FLD1, 0, Tmp);
570 BuildMI(*MBB, IP, X86::FCHS, 1, R).addReg(Tmp);
571 } else { // FIXME: PI, other native values
572 // FIXME: 2*PI -> LDPI + FADD
574 // Otherwise we need to spill the constant to memory.
575 MachineConstantPool *CP = F->getConstantPool();
577 const Type *Ty = CFP->getType();
579 // If a FP immediate is precise when represented as a float, we put it
580 // into the constant pool as a float, even if it's is statically typed as
582 if (Ty == Type::DoubleTy)
583 if (CFP->isExactlyValue((float)CFP->getValue())) {
585 CFP = cast<ConstantFP>(ConstantExpr::getCast(CFP, Ty));
588 unsigned CPI = CP->getConstantPoolIndex(CFP);
590 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
591 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m;
592 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI);
595 } else if (isa<ConstantPointerNull>(C)) {
596 // Copy zero (null pointer) to the register.
597 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(0);
598 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
599 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addGlobalAddress(GV);
601 std::cerr << "Offending constant: " << *C << "\n";
602 assert(0 && "Type not handled yet!");
606 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
607 /// the stack into virtual registers.
609 void X86ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
610 // Emit instructions to load the arguments... On entry to a function on the
611 // X86, the stack frame looks like this:
613 // [ESP] -- return address
614 // [ESP + 4] -- first argument (leftmost lexically)
615 // [ESP + 8] -- second argument, if first argument is four bytes in size
618 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
619 MachineFrameInfo *MFI = F->getFrameInfo();
621 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
623 bool ArgLive = !I->use_empty();
624 unsigned Reg = ArgLive ? getReg(*I) : 0;
625 int FI; // Frame object index
627 switch (getClassB(I->getType())) {
630 FI = MFI->CreateFixedObject(1, ArgOffset);
631 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Reg), FI);
636 FI = MFI->CreateFixedObject(2, ArgOffset);
637 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Reg), FI);
642 FI = MFI->CreateFixedObject(4, ArgOffset);
643 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
648 FI = MFI->CreateFixedObject(8, ArgOffset);
649 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
650 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg+1), FI, 4);
652 ArgOffset += 4; // longs require 4 additional bytes
657 if (I->getType() == Type::FloatTy) {
658 Opcode = X86::FLD32m;
659 FI = MFI->CreateFixedObject(4, ArgOffset);
661 Opcode = X86::FLD64m;
662 FI = MFI->CreateFixedObject(8, ArgOffset);
664 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
666 if (I->getType() == Type::DoubleTy)
667 ArgOffset += 4; // doubles require 4 additional bytes
670 assert(0 && "Unhandled argument type!");
672 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
675 // If the function takes variable number of arguments, add a frame offset for
676 // the start of the first vararg value... this is used to expand
678 if (Fn.getFunctionType()->isVarArg())
679 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
681 // Finally, inform the compiler what our live-outs will be, aka, what we will
682 // be returning in registers.
683 if (Fn.getReturnType() != Type::VoidTy)
684 switch (getClassB(Fn.getReturnType())) {
685 default: assert(0 && "Unknown type!");
689 F->addLiveOut(X86::EAX);
692 F->addLiveOut(X86::EAX);
693 F->addLiveOut(X86::EDX);
696 F->addLiveOut(X86::ST0);
701 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
702 /// the main function.
703 void X86ISel::EmitSpecialCodeForMain() {
704 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
705 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
706 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
708 // Set the high part to be 64-bit precision.
709 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
710 CWFrameIdx, 1).addImm(2);
712 // Reload the modified control word now.
713 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
716 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
717 /// because we have to generate our sources into the source basic blocks, not
720 void X86ISel::SelectPHINodes() {
721 const TargetInstrInfo &TII = *TM.getInstrInfo();
722 const Function &LF = *F->getFunction(); // The LLVM function...
723 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
724 const BasicBlock *BB = I;
725 MachineBasicBlock &MBB = *MBBMap[I];
727 // Loop over all of the PHI nodes in the LLVM basic block...
728 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
729 for (BasicBlock::const_iterator I = BB->begin(); isa<PHINode>(I); ++I) {
730 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I));
732 // Create a new machine instr PHI node, and insert it.
733 unsigned PHIReg = getReg(*PN);
734 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
735 X86::PHI, PN->getNumOperands(), PHIReg);
737 MachineInstr *LongPhiMI = 0;
738 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
739 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
740 X86::PHI, PN->getNumOperands(), PHIReg+1);
742 // PHIValues - Map of blocks to incoming virtual registers. We use this
743 // so that we only initialize one incoming value for a particular block,
744 // even if the block has multiple entries in the PHI node.
746 std::map<MachineBasicBlock*, unsigned> PHIValues;
748 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
749 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
751 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
752 PHIValues.lower_bound(PredMBB);
754 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
755 // We already inserted an initialization of the register for this
756 // predecessor. Recycle it.
757 ValReg = EntryIt->second;
760 // Get the incoming value into a virtual register.
762 Value *Val = PN->getIncomingValue(i);
764 // If this is a constant or GlobalValue, we may have to insert code
765 // into the basic block to compute it into a virtual register.
766 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val))) {
767 // Simple constants get emitted at the end of the basic block,
768 // before any terminator instructions. We "know" that the code to
769 // move a constant into a register will never clobber any flags.
770 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
772 // Because we don't want to clobber any values which might be in
773 // physical registers with the computation of this constant (which
774 // might be arbitrarily complex if it is a constant expression),
775 // just insert the computation at the top of the basic block.
776 MachineBasicBlock::iterator PI = PredMBB->begin();
778 // Skip over any PHI nodes though!
779 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
782 ValReg = getReg(Val, PredMBB, PI);
785 // Remember that we inserted a value for this PHI for this predecessor
786 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
789 PhiMI->addRegOperand(ValReg);
790 PhiMI->addMachineBasicBlockOperand(PredMBB);
792 LongPhiMI->addRegOperand(ValReg+1);
793 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
797 // Now that we emitted all of the incoming values for the PHI node, make
798 // sure to reposition the InsertPoint after the PHI that we just added.
799 // This is needed because we might have inserted a constant into this
800 // block, right after the PHI's which is before the old insert point!
801 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
807 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
808 /// compensation code on critical edges. As such, it requires that we kill all
809 /// FP registers on the exit from any blocks that either ARE critical edges, or
810 /// branch to a block that has incoming critical edges.
812 /// Note that this kill instruction will eventually be eliminated when
813 /// restrictions in the stackifier are relaxed.
815 static bool RequiresFPRegKill(const MachineBasicBlock *MBB) {
817 const BasicBlock *BB = MBB->getBasicBlock ();
818 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
819 const BasicBlock *Succ = *SI;
820 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
821 ++PI; // Block have at least one predecessory
822 if (PI != PE) { // If it has exactly one, this isn't crit edge
823 // If this block has more than one predecessor, check all of the
824 // predecessors to see if they have multiple successors. If so, then the
825 // block we are analyzing needs an FPRegKill.
826 for (PI = pred_begin(Succ); PI != PE; ++PI) {
827 const BasicBlock *Pred = *PI;
828 succ_const_iterator SI2 = succ_begin(Pred);
829 ++SI2; // There must be at least one successor of this block.
830 if (SI2 != succ_end(Pred))
831 return true; // Yes, we must insert the kill on this edge.
835 // If we got this far, there is no need to insert the kill instruction.
842 // InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
843 // need them. This only occurs due to the floating point stackifier not being
844 // aggressive enough to handle arbitrary global stackification.
846 // Currently we insert an FP_REG_KILL instruction into each block that uses or
847 // defines a floating point virtual register.
849 // When the global register allocators (like linear scan) finally update live
850 // variable analysis, we can keep floating point values in registers across
851 // portions of the CFG that do not involve critical edges. This will be a big
852 // win, but we are waiting on the global allocators before we can do this.
854 // With a bit of work, the floating point stackifier pass can be enhanced to
855 // break critical edges as needed (to make a place to put compensation code),
856 // but this will require some infrastructure improvements as well.
858 void X86ISel::InsertFPRegKills() {
859 SSARegMap &RegMap = *F->getSSARegMap();
861 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
862 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
863 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
864 MachineOperand& MO = I->getOperand(i);
865 if (MO.isRegister() && MO.getReg()) {
866 unsigned Reg = MO.getReg();
867 if (MRegisterInfo::isVirtualRegister(Reg)) {
868 unsigned RegSize = RegMap.getRegClass(Reg)->getSize();
869 if (RegSize == 10 || RegSize == 8)
874 // If we haven't found an FP register use or def in this basic block, check
875 // to see if any of our successors has an FP PHI node, which will cause a
876 // copy to be inserted into this block.
877 for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(),
878 SE = BB->succ_end(); SI != SE; ++SI) {
879 MachineBasicBlock *SBB = *SI;
880 for (MachineBasicBlock::iterator I = SBB->begin();
881 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
882 const TargetRegisterClass *RC =
883 RegMap.getRegClass(I->getOperand(0).getReg());
884 if (RC->getSize() == 10 || RC->getSize() == 8)
890 // Okay, this block uses an FP register. If the block has successors (ie,
891 // it's not an unwind/return), insert the FP_REG_KILL instruction.
892 if (BB->succ_size() && RequiresFPRegKill(BB)) {
893 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
900 void X86ISel::getAddressingMode(Value *Addr, X86AddressMode &AM) {
901 AM.BaseType = X86AddressMode::RegBase;
902 AM.Base.Reg = 0; AM.Scale = 1; AM.IndexReg = 0; AM.Disp = 0;
903 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
904 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
907 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
908 if (CE->getOpcode() == Instruction::GetElementPtr)
909 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
912 } else if (AllocaInst *AI = dyn_castFixedAlloca(Addr)) {
913 AM.BaseType = X86AddressMode::FrameIndexBase;
914 AM.Base.FrameIndex = getFixedSizedAllocaFI(AI);
916 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(Addr)) {
921 // If it's not foldable, reset addr mode.
922 AM.BaseType = X86AddressMode::RegBase;
923 AM.Base.Reg = getReg(Addr);
924 AM.Scale = 1; AM.IndexReg = 0; AM.Disp = 0;
927 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
928 // it into the conditional branch or select instruction which is the only user
929 // of the cc instruction. This is the case if the conditional branch is the
930 // only user of the setcc. We also don't handle long arguments below, so we
931 // reject them here as well.
933 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
934 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
935 if (SCI->hasOneUse()) {
936 Instruction *User = cast<Instruction>(SCI->use_back());
937 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
938 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
939 SCI->getOpcode() == Instruction::SetEQ ||
940 SCI->getOpcode() == Instruction::SetNE) &&
941 (isa<BranchInst>(User) || User->getOperand(0) == V))
947 // Return a fixed numbering for setcc instructions which does not depend on the
948 // order of the opcodes.
950 static unsigned getSetCCNumber(unsigned Opcode) {
952 default: assert(0 && "Unknown setcc instruction!");
953 case Instruction::SetEQ: return 0;
954 case Instruction::SetNE: return 1;
955 case Instruction::SetLT: return 2;
956 case Instruction::SetGE: return 3;
957 case Instruction::SetGT: return 4;
958 case Instruction::SetLE: return 5;
962 // LLVM -> X86 signed X86 unsigned
963 // ----- ---------- ------------
964 // seteq -> sete sete
965 // setne -> setne setne
966 // setlt -> setl setb
967 // setge -> setge setae
968 // setgt -> setg seta
969 // setle -> setle setbe
971 // sets // Used by comparison with 0 optimization
973 static const unsigned SetCCOpcodeTab[2][8] = {
974 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
976 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
977 X86::SETSr, X86::SETNSr },
980 /// emitUCOMr - In the future when we support processors before the P6, this
981 /// wraps the logic for emitting an FUCOMr vs FUCOMIr.
982 void X86ISel::emitUCOMr(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
983 unsigned LHS, unsigned RHS) {
984 if (0) { // for processors prior to the P6
985 BuildMI(*MBB, IP, X86::FUCOMr, 2).addReg(LHS).addReg(RHS);
986 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
987 BuildMI(*MBB, IP, X86::SAHF, 1);
989 BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(LHS).addReg(RHS);
993 // EmitComparison - This function emits a comparison of the two operands,
994 // returning the extended setcc code to use.
995 unsigned X86ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
996 MachineBasicBlock *MBB,
997 MachineBasicBlock::iterator IP) {
998 // The arguments are already supposed to be of the same type.
999 const Type *CompTy = Op0->getType();
1000 unsigned Class = getClassB(CompTy);
1002 // Special case handling of: cmp R, i
1003 if (isa<ConstantPointerNull>(Op1)) {
1004 unsigned Op0r = getReg(Op0, MBB, IP);
1005 if (OpNum < 2) // seteq/setne -> test
1006 BuildMI(*MBB, IP, X86::TEST32rr, 2).addReg(Op0r).addReg(Op0r);
1008 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(0);
1011 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1012 if (Class == cByte || Class == cShort || Class == cInt) {
1013 unsigned Op1v = CI->getRawValue();
1015 // Mask off any upper bits of the constant, if there are any...
1016 Op1v &= (1ULL << (8 << Class)) - 1;
1018 // If this is a comparison against zero, emit more efficient code. We
1019 // can't handle unsigned comparisons against zero unless they are == or
1020 // !=. These should have been strength reduced already anyway.
1021 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
1023 // If this is a comparison against zero and the LHS is an and of a
1024 // register with a constant, use the test to do the and.
1025 if (Instruction *Op0I = dyn_cast<Instruction>(Op0))
1026 if (Op0I->getOpcode() == Instruction::And && Op0->hasOneUse() &&
1027 isa<ConstantInt>(Op0I->getOperand(1))) {
1028 static const unsigned TESTTab[] = {
1029 X86::TEST8ri, X86::TEST16ri, X86::TEST32ri
1033 unsigned LHS = getReg(Op0I->getOperand(0), MBB, IP);
1035 cast<ConstantInt>(Op0I->getOperand(1))->getRawValue();
1036 BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(LHS).addImm(Imm);
1038 if (OpNum == 2) return 6; // Map jl -> js
1039 if (OpNum == 3) return 7; // Map jg -> jns
1043 unsigned Op0r = getReg(Op0, MBB, IP);
1044 static const unsigned TESTTab[] = {
1045 X86::TEST8rr, X86::TEST16rr, X86::TEST32rr
1047 BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
1049 if (OpNum == 2) return 6; // Map jl -> js
1050 if (OpNum == 3) return 7; // Map jg -> jns
1054 static const unsigned CMPTab[] = {
1055 X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
1058 unsigned Op0r = getReg(Op0, MBB, IP);
1059 BuildMI(*MBB, IP, CMPTab[Class], 2).addReg(Op0r).addImm(Op1v);
1062 unsigned Op0r = getReg(Op0, MBB, IP);
1063 assert(Class == cLong && "Unknown integer class!");
1064 unsigned LowCst = CI->getRawValue();
1065 unsigned HiCst = CI->getRawValue() >> 32;
1066 if (OpNum < 2) { // seteq, setne
1067 unsigned LoTmp = Op0r;
1069 LoTmp = makeAnotherReg(Type::IntTy);
1070 BuildMI(*MBB, IP, X86::XOR32ri, 2, LoTmp).addReg(Op0r).addImm(LowCst);
1072 unsigned HiTmp = Op0r+1;
1074 HiTmp = makeAnotherReg(Type::IntTy);
1075 BuildMI(*MBB, IP, X86::XOR32ri, 2,HiTmp).addReg(Op0r+1).addImm(HiCst);
1077 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
1078 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
1081 // Emit a sequence of code which compares the high and low parts once
1082 // each, then uses a conditional move to handle the overflow case. For
1083 // example, a setlt for long would generate code like this:
1085 // AL = lo(op1) < lo(op2) // Always unsigned comparison
1086 // BL = hi(op1) < hi(op2) // Signedness depends on operands
1087 // dest = hi(op1) == hi(op2) ? BL : AL;
1090 // FIXME: This would be much better if we had hierarchical register
1091 // classes! Until then, hardcode registers so that we can deal with
1092 // their aliases (because we don't have conditional byte moves).
1094 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(LowCst);
1095 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
1096 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r+1).addImm(HiCst);
1097 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0,X86::BL);
1098 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
1099 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
1100 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
1102 // NOTE: visitSetCondInst knows that the value is dumped into the BL
1103 // register at this point for long values...
1109 unsigned Op0r = getReg(Op0, MBB, IP);
1111 // Special case handling of comparison against +/- 0.0
1112 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
1113 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
1114 BuildMI(*MBB, IP, X86::FTST, 1).addReg(Op0r);
1115 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
1116 BuildMI(*MBB, IP, X86::SAHF, 1);
1120 unsigned Op1r = getReg(Op1, MBB, IP);
1122 default: assert(0 && "Unknown type class!");
1123 // Emit: cmp <var1>, <var2> (do the comparison). We can
1124 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
1127 BuildMI(*MBB, IP, X86::CMP8rr, 2).addReg(Op0r).addReg(Op1r);
1130 BuildMI(*MBB, IP, X86::CMP16rr, 2).addReg(Op0r).addReg(Op1r);
1133 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
1136 emitUCOMr(MBB, IP, Op0r, Op1r);
1140 if (OpNum < 2) { // seteq, setne
1141 unsigned LoTmp = makeAnotherReg(Type::IntTy);
1142 unsigned HiTmp = makeAnotherReg(Type::IntTy);
1143 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
1144 BuildMI(*MBB, IP, X86::XOR32rr, 2, LoTmp).addReg(Op0r).addReg(Op1r);
1145 BuildMI(*MBB, IP, X86::XOR32rr, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
1146 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
1147 break; // Allow the sete or setne to be generated from flags set by OR
1149 // Emit a sequence of code which compares the high and low parts once
1150 // each, then uses a conditional move to handle the overflow case. For
1151 // example, a setlt for long would generate code like this:
1153 // AL = lo(op1) < lo(op2) // Signedness depends on operands
1154 // BL = hi(op1) < hi(op2) // Always unsigned comparison
1155 // dest = hi(op1) == hi(op2) ? BL : AL;
1158 // FIXME: This would be much better if we had hierarchical register
1159 // classes! Until then, hardcode registers so that we can deal with their
1160 // aliases (because we don't have conditional byte moves).
1162 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
1163 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
1164 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r+1).addReg(Op1r+1);
1165 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
1166 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
1167 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
1168 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
1170 // NOTE: visitSetCondInst knows that the value is dumped into the BL
1171 // register at this point for long values...
1178 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
1179 /// register, then move it to wherever the result should be.
1181 void X86ISel::visitSetCondInst(SetCondInst &I) {
1182 if (canFoldSetCCIntoBranchOrSelect(&I))
1183 return; // Fold this into a branch or select.
1185 unsigned DestReg = getReg(I);
1186 MachineBasicBlock::iterator MII = BB->end();
1187 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
1191 /// emitSetCCOperation - Common code shared between visitSetCondInst and
1192 /// constant expression support.
1194 void X86ISel::emitSetCCOperation(MachineBasicBlock *MBB,
1195 MachineBasicBlock::iterator IP,
1196 Value *Op0, Value *Op1, unsigned Opcode,
1197 unsigned TargetReg) {
1198 unsigned OpNum = getSetCCNumber(Opcode);
1199 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
1201 const Type *CompTy = Op0->getType();
1202 unsigned CompClass = getClassB(CompTy);
1203 bool isSigned = CompTy->isSigned() && CompClass != cFP;
1205 if (CompClass != cLong || OpNum < 2) {
1206 // Handle normal comparisons with a setcc instruction...
1207 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
1209 // Handle long comparisons by copying the value which is already in BL into
1210 // the register we want...
1211 BuildMI(*MBB, IP, X86::MOV8rr, 1, TargetReg).addReg(X86::BL);
1215 void X86ISel::visitSelectInst(SelectInst &SI) {
1216 unsigned DestReg = getReg(SI);
1217 MachineBasicBlock::iterator MII = BB->end();
1218 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1219 SI.getFalseValue(), DestReg);
1222 /// emitSelect - Common code shared between visitSelectInst and the constant
1223 /// expression support.
1224 void X86ISel::emitSelectOperation(MachineBasicBlock *MBB,
1225 MachineBasicBlock::iterator IP,
1226 Value *Cond, Value *TrueVal, Value *FalseVal,
1228 unsigned SelectClass = getClassB(TrueVal->getType());
1230 // We don't support 8-bit conditional moves. If we have incoming constants,
1231 // transform them into 16-bit constants to avoid having a run-time conversion.
1232 if (SelectClass == cByte) {
1233 if (Constant *T = dyn_cast<Constant>(TrueVal))
1234 TrueVal = ConstantExpr::getCast(T, Type::ShortTy);
1235 if (Constant *F = dyn_cast<Constant>(FalseVal))
1236 FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
1239 unsigned TrueReg = getReg(TrueVal, MBB, IP);
1240 unsigned FalseReg = getReg(FalseVal, MBB, IP);
1241 if (TrueReg == FalseReg) {
1242 static const unsigned Opcode[] = {
1243 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
1245 BuildMI(*MBB, IP, Opcode[SelectClass], 1, DestReg).addReg(TrueReg);
1246 if (SelectClass == cLong)
1247 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(TrueReg+1);
1252 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1253 // We successfully folded the setcc into the select instruction.
1255 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1256 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
1259 const Type *CompTy = SCI->getOperand(0)->getType();
1260 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1262 // LLVM -> X86 signed X86 unsigned
1263 // ----- ---------- ------------
1264 // seteq -> cmovNE cmovNE
1265 // setne -> cmovE cmovE
1266 // setlt -> cmovGE cmovAE
1267 // setge -> cmovL cmovB
1268 // setgt -> cmovLE cmovBE
1269 // setle -> cmovG cmovA
1271 // cmovNS // Used by comparison with 0 optimization
1274 switch (SelectClass) {
1275 default: assert(0 && "Unknown value class!");
1277 // Annoyingly, we don't have a full set of floating point conditional
1279 static const unsigned OpcodeTab[2][8] = {
1280 { X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
1281 X86::FCMOVBE, X86::FCMOVA, 0, 0 },
1282 { X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
1284 Opcode = OpcodeTab[isSigned][OpNum];
1286 // If opcode == 0, we hit a case that we don't support. Output a setcc
1287 // and compare the result against zero.
1289 unsigned CompClass = getClassB(CompTy);
1291 if (CompClass != cLong || OpNum < 2) {
1292 CondReg = makeAnotherReg(Type::BoolTy);
1293 // Handle normal comparisons with a setcc instruction...
1294 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
1296 // Long comparisons end up in the BL register.
1300 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1301 Opcode = X86::FCMOVE;
1307 static const unsigned OpcodeTab[2][8] = {
1308 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
1309 X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
1310 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
1311 X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
1313 Opcode = OpcodeTab[isSigned][OpNum];
1318 static const unsigned OpcodeTab[2][8] = {
1319 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
1320 X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
1321 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
1322 X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
1324 Opcode = OpcodeTab[isSigned][OpNum];
1329 // Get the value being branched on, and use it to set the condition codes.
1330 unsigned CondReg = getReg(Cond, MBB, IP);
1331 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1332 switch (SelectClass) {
1333 default: assert(0 && "Unknown value class!");
1334 case cFP: Opcode = X86::FCMOVE; break;
1336 case cShort: Opcode = X86::CMOVE16rr; break;
1338 case cLong: Opcode = X86::CMOVE32rr; break;
1342 unsigned RealDestReg = DestReg;
1345 // Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
1346 // this, we have to promote the incoming values to 16 bits, perform a 16-bit
1347 // cmove, then truncate the result.
1348 if (SelectClass == cByte) {
1349 DestReg = makeAnotherReg(Type::ShortTy);
1350 if (getClassB(TrueVal->getType()) == cByte) {
1351 // Promote the true value, by storing it into AL, and reading from AX.
1352 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::AL).addReg(TrueReg);
1353 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::AH).addImm(0);
1354 TrueReg = makeAnotherReg(Type::ShortTy);
1355 BuildMI(*MBB, IP, X86::MOV16rr, 1, TrueReg).addReg(X86::AX);
1357 if (getClassB(FalseVal->getType()) == cByte) {
1358 // Promote the true value, by storing it into CL, and reading from CX.
1359 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(FalseReg);
1360 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::CH).addImm(0);
1361 FalseReg = makeAnotherReg(Type::ShortTy);
1362 BuildMI(*MBB, IP, X86::MOV16rr, 1, FalseReg).addReg(X86::CX);
1366 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(TrueReg).addReg(FalseReg);
1368 switch (SelectClass) {
1370 // We did the computation with 16-bit registers. Truncate back to our
1371 // result by copying into AX then copying out AL.
1372 BuildMI(*MBB, IP, X86::MOV16rr, 1, X86::AX).addReg(DestReg);
1373 BuildMI(*MBB, IP, X86::MOV8rr, 1, RealDestReg).addReg(X86::AL);
1376 // Move the upper half of the value as well.
1377 BuildMI(*MBB, IP, Opcode, 2,DestReg+1).addReg(TrueReg+1).addReg(FalseReg+1);
1384 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1385 /// operand, in the specified target register.
1387 void X86ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1388 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1390 Value *Val = VR.Val;
1391 const Type *Ty = VR.Ty;
1393 if (Constant *C = dyn_cast<Constant>(Val)) {
1394 Val = ConstantExpr::getCast(C, Type::IntTy);
1398 // If this is a simple constant, just emit a MOVri directly to avoid the
1400 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1401 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1402 BuildMI(BB, X86::MOV32ri, 1, targetReg).addImm(TheVal);
1407 // Make sure we have the register number for this value...
1408 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1410 switch (getClassB(Ty)) {
1412 // Extend value into target register (8->32)
1414 BuildMI(BB, X86::MOVZX32rr8, 1, targetReg).addReg(Reg);
1416 BuildMI(BB, X86::MOVSX32rr8, 1, targetReg).addReg(Reg);
1419 // Extend value into target register (16->32)
1421 BuildMI(BB, X86::MOVZX32rr16, 1, targetReg).addReg(Reg);
1423 BuildMI(BB, X86::MOVSX32rr16, 1, targetReg).addReg(Reg);
1426 // Move value into target register (32->32)
1427 BuildMI(BB, X86::MOV32rr, 1, targetReg).addReg(Reg);
1430 assert(0 && "Unpromotable operand class in promote32");
1434 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
1435 /// we have the following possibilities:
1437 /// ret void: No return value, simply emit a 'ret' instruction
1438 /// ret sbyte, ubyte : Extend value into EAX and return
1439 /// ret short, ushort: Extend value into EAX and return
1440 /// ret int, uint : Move value into EAX and return
1441 /// ret pointer : Move value into EAX and return
1442 /// ret long, ulong : Move value into EAX/EDX and return
1443 /// ret float/double : Top of FP stack
1445 void X86ISel::visitReturnInst(ReturnInst &I) {
1446 if (I.getNumOperands() == 0) {
1447 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
1451 Value *RetVal = I.getOperand(0);
1452 switch (getClassB(RetVal->getType())) {
1453 case cByte: // integral return values: extend or move into EAX and return
1456 promote32(X86::EAX, ValueRecord(RetVal));
1458 case cFP: { // Floats & Doubles: Return in ST(0)
1459 unsigned RetReg = getReg(RetVal);
1460 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
1464 unsigned RetReg = getReg(RetVal);
1465 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
1466 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
1470 visitInstruction(I);
1472 // Emit a 'ret' instruction
1473 BuildMI(BB, X86::RET, 0);
1476 // getBlockAfter - Return the basic block which occurs lexically after the
1478 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1479 Function::iterator I = BB; ++I; // Get iterator to next block
1480 return I != BB->getParent()->end() ? &*I : 0;
1483 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1484 /// that since code layout is frozen at this point, that if we are trying to
1485 /// jump to a block that is the immediate successor of the current block, we can
1486 /// just make a fall-through (but we don't currently).
1488 void X86ISel::visitBranchInst(BranchInst &BI) {
1489 // Update machine-CFG edges
1490 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1491 if (BI.isConditional())
1492 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
1494 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1496 if (!BI.isConditional()) { // Unconditional branch?
1497 if (BI.getSuccessor(0) != NextBB)
1498 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1502 // See if we can fold the setcc into the branch itself...
1503 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1505 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1506 // computed some other way...
1507 unsigned condReg = getReg(BI.getCondition());
1508 BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
1509 if (BI.getSuccessor(1) == NextBB) {
1510 if (BI.getSuccessor(0) != NextBB)
1511 BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1513 BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1515 if (BI.getSuccessor(0) != NextBB)
1516 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1521 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1522 MachineBasicBlock::iterator MII = BB->end();
1523 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1525 const Type *CompTy = SCI->getOperand(0)->getType();
1526 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1529 // LLVM -> X86 signed X86 unsigned
1530 // ----- ---------- ------------
1538 // js // Used by comparison with 0 optimization
1541 static const unsigned OpcodeTab[2][8] = {
1542 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1543 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1544 X86::JS, X86::JNS },
1547 if (BI.getSuccessor(0) != NextBB) {
1548 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
1549 .addMBB(MBBMap[BI.getSuccessor(0)]);
1550 if (BI.getSuccessor(1) != NextBB)
1551 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1553 // Change to the inverse condition...
1554 if (BI.getSuccessor(1) != NextBB) {
1556 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
1557 .addMBB(MBBMap[BI.getSuccessor(1)]);
1563 /// doCall - This emits an abstract call instruction, setting up the arguments
1564 /// and the return value as appropriate. For the actual function call itself,
1565 /// it inserts the specified CallMI instruction into the stream.
1567 void X86ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1568 const std::vector<ValueRecord> &Args) {
1569 // Count how many bytes are to be pushed on the stack...
1570 unsigned NumBytes = 0;
1572 if (!Args.empty()) {
1573 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1574 switch (getClassB(Args[i].Ty)) {
1575 case cByte: case cShort: case cInt:
1576 NumBytes += 4; break;
1578 NumBytes += 8; break;
1580 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1582 default: assert(0 && "Unknown class!");
1585 // Adjust the stack pointer for the new arguments...
1586 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1588 // Arguments go on the stack in reverse order, as specified by the ABI.
1589 unsigned ArgOffset = 0;
1590 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1592 switch (getClassB(Args[i].Ty)) {
1594 if (Args[i].Val && isa<ConstantBool>(Args[i].Val)) {
1595 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1596 .addImm(Args[i].Val == ConstantBool::True);
1601 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1602 // Zero/Sign extend constant, then stuff into memory.
1603 ConstantInt *Val = cast<ConstantInt>(Args[i].Val);
1604 Val = cast<ConstantInt>(ConstantExpr::getCast(Val, Type::IntTy));
1605 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1606 .addImm(Val->getRawValue() & 0xFFFFFFFF);
1608 // Promote arg to 32 bits wide into a temporary register...
1609 ArgReg = makeAnotherReg(Type::UIntTy);
1610 promote32(ArgReg, Args[i]);
1611 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1612 X86::ESP, ArgOffset).addReg(ArgReg);
1616 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1617 unsigned Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1618 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1619 X86::ESP, ArgOffset).addImm(Val);
1620 } else if (Args[i].Val && isa<ConstantPointerNull>(Args[i].Val)) {
1621 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1622 X86::ESP, ArgOffset).addImm(0);
1623 } else if (Args[i].Val && isa<GlobalValue>(Args[i].Val)) {
1624 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1625 .addGlobalAddress(cast<GlobalValue>(Args[i].Val));
1627 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1628 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1629 X86::ESP, ArgOffset).addReg(ArgReg);
1633 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1634 uint64_t Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1635 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1636 X86::ESP, ArgOffset).addImm(Val & ~0U);
1637 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1638 X86::ESP, ArgOffset+4).addImm(Val >> 32ULL);
1640 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1641 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1642 X86::ESP, ArgOffset).addReg(ArgReg);
1643 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1644 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1646 ArgOffset += 4; // 8 byte entry, not 4.
1650 if (ConstantFP *CFP = dyn_cast_or_null<ConstantFP>(Args[i].Val)) {
1651 // Store constant FP values with integer instructions to avoid having
1652 // to load the constants from the constant pool then do a store.
1653 if (CFP->getType() == Type::FloatTy) {
1658 V.F = CFP->getValue();
1659 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1660 X86::ESP, ArgOffset).addImm(V.I);
1666 V.F = CFP->getValue();
1667 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1668 X86::ESP, ArgOffset).addImm((unsigned)V.I);
1669 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1670 X86::ESP, ArgOffset+4).addImm(unsigned(V.I >> 32));
1671 ArgOffset += 4; // 8 byte entry, not 4.
1674 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1675 if (Args[i].Ty == Type::FloatTy) {
1676 addRegOffset(BuildMI(BB, X86::FST32m, 5),
1677 X86::ESP, ArgOffset).addReg(ArgReg);
1679 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1680 addRegOffset(BuildMI(BB, X86::FST64m, 5),
1681 X86::ESP, ArgOffset).addReg(ArgReg);
1682 ArgOffset += 4; // 8 byte entry, not 4.
1687 default: assert(0 && "Unknown class!");
1692 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(0);
1695 BB->push_back(CallMI);
1697 BuildMI(BB, X86::ADJCALLSTACKUP, 2).addImm(NumBytes).addImm(0);
1699 // If there is a return value, scavenge the result from the location the call
1702 if (Ret.Ty != Type::VoidTy) {
1703 unsigned DestClass = getClassB(Ret.Ty);
1704 switch (DestClass) {
1708 // Integral results are in %eax, or the appropriate portion
1710 static const unsigned regRegMove[] = {
1711 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr
1713 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1714 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1717 case cFP: // Floating-point return values live in %ST(0)
1718 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1720 case cLong: // Long values are left in EDX:EAX
1721 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg).addReg(X86::EAX);
1722 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg+1).addReg(X86::EDX);
1724 default: assert(0 && "Unknown class!");
1730 /// visitCallInst - Push args on stack and do a procedure call instruction.
1731 void X86ISel::visitCallInst(CallInst &CI) {
1732 MachineInstr *TheCall;
1733 if (Function *F = CI.getCalledFunction()) {
1734 // Is it an intrinsic function call?
1735 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1736 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1738 } else if (F->getName() == "fabs" || F->getName() == "fabsf") {
1739 if (CI.getNumOperands() == 2 && // Basic sanity checks.
1740 CI.getOperand(1)->getType()->isFloatingPoint() &&
1741 CI.getType() == CI.getOperand(1)->getType()) {
1742 unsigned op1Reg = getReg(CI.getOperand(1));
1743 unsigned DestReg = getReg(CI);
1744 BuildMI(BB, X86::FABS, 1, DestReg).addReg(op1Reg);
1747 } else if (F->getName() == "sin" && UnsafeFPMath || F->getName() == "sinf") {
1748 if (CI.getNumOperands() == 2 && // Basic sanity checks.
1749 CI.getOperand(1)->getType()->isFloatingPoint() &&
1750 CI.getType() == CI.getOperand(1)->getType()) {
1751 unsigned op1Reg = getReg(CI.getOperand(1));
1752 unsigned DestReg = getReg(CI);
1753 BuildMI(BB, X86::FSIN, 1, DestReg).addReg(op1Reg);
1757 else if (F->getName() == "cos" && UnsafeFPMath || F->getName() == "cosf") {
1758 if (CI.getNumOperands() == 2 && // Basic sanity checks.
1759 CI.getOperand(1)->getType()->isFloatingPoint() &&
1760 CI.getType() == CI.getOperand(1)->getType()) {
1761 unsigned op1Reg = getReg(CI.getOperand(1));
1762 unsigned DestReg = getReg(CI);
1763 BuildMI(BB, X86::FCOS, 1, DestReg).addReg(op1Reg);
1768 // Emit a CALL instruction with PC-relative displacement.
1769 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1770 } else { // Emit an indirect call...
1771 unsigned Reg = getReg(CI.getCalledValue());
1772 TheCall = BuildMI(X86::CALL32r, 1).addReg(Reg);
1775 std::vector<ValueRecord> Args;
1776 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1777 Args.push_back(ValueRecord(CI.getOperand(i)));
1779 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1780 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1783 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1784 /// function, lowering any calls to unknown intrinsic functions into the
1785 /// equivalent LLVM code.
1787 void X86ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1788 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1789 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1790 if (CallInst *CI = dyn_cast<CallInst>(I++))
1791 if (Function *F = CI->getCalledFunction())
1792 switch (F->getIntrinsicID()) {
1793 case Intrinsic::not_intrinsic:
1794 case Intrinsic::vastart:
1795 case Intrinsic::vacopy:
1796 case Intrinsic::vaend:
1797 case Intrinsic::returnaddress:
1798 case Intrinsic::frameaddress:
1799 case Intrinsic::memcpy:
1800 case Intrinsic::memset:
1801 case Intrinsic::isunordered:
1802 case Intrinsic::sqrt:
1803 case Intrinsic::readport:
1804 case Intrinsic::writeport:
1805 // We directly implement these intrinsics
1807 case Intrinsic::readio: {
1808 // On X86, memory operations are in-order. Lower this intrinsic
1809 // into a volatile load.
1810 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1811 CI->replaceAllUsesWith(LI);
1812 BB->getInstList().erase(CI);
1815 case Intrinsic::writeio: {
1816 // On X86, memory operations are in-order. Lower this intrinsic
1817 // into a volatile store.
1818 StoreInst *LI = new StoreInst(CI->getOperand(1),
1819 CI->getOperand(2), true, CI);
1820 CI->replaceAllUsesWith(LI);
1821 BB->getInstList().erase(CI);
1825 // All other intrinsic calls we must lower.
1826 Instruction *Before = CI->getPrev();
1827 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1828 if (Before) { // Move iterator to instruction after call
1836 void X86ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1837 unsigned TmpReg1, TmpReg2;
1839 case Intrinsic::vastart:
1840 //FIXME: store to first arg, don't return
1841 // Get the address of the first vararg value...
1842 TmpReg1 = getReg(CI);
1843 addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex);
1846 case Intrinsic::vacopy:
1847 //FIXME: copy val of second into first (which is a ptr)
1848 TmpReg1 = getReg(CI);
1849 TmpReg2 = getReg(CI.getOperand(1));
1850 BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2);
1852 case Intrinsic::vaend: return; // Noop on X86
1854 case Intrinsic::returnaddress:
1855 case Intrinsic::frameaddress:
1856 TmpReg1 = getReg(CI);
1857 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1858 if (ReturnAddressIndex == 0) {
1859 // Set up a frame object for the return address.
1860 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
1863 if (ID == Intrinsic::returnaddress) {
1864 // Just load the return address
1865 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, TmpReg1),
1866 ReturnAddressIndex);
1868 addFrameReference(BuildMI(BB, X86::LEA32r, 4, TmpReg1),
1869 ReturnAddressIndex, -4);
1872 // Values other than zero are not implemented yet.
1873 BuildMI(BB, X86::MOV32ri, 1, TmpReg1).addImm(0);
1877 case Intrinsic::isunordered:
1878 TmpReg1 = getReg(CI.getOperand(1));
1879 TmpReg2 = getReg(CI.getOperand(2));
1880 emitUCOMr(BB, BB->end(), TmpReg2, TmpReg1);
1881 TmpReg2 = getReg(CI);
1882 BuildMI(BB, X86::SETPr, 0, TmpReg2);
1885 case Intrinsic::sqrt:
1886 TmpReg1 = getReg(CI.getOperand(1));
1887 TmpReg2 = getReg(CI);
1888 BuildMI(BB, X86::FSQRT, 1, TmpReg2).addReg(TmpReg1);
1891 case Intrinsic::memcpy: {
1892 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1894 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1895 Align = AlignC->getRawValue();
1896 if (Align == 0) Align = 1;
1899 // Turn the byte code into # iterations
1902 switch (Align & 3) {
1903 case 2: // WORD aligned
1904 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1905 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1907 CountReg = makeAnotherReg(Type::IntTy);
1908 unsigned ByteReg = getReg(CI.getOperand(3));
1909 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1911 Opcode = X86::REP_MOVSW;
1913 case 0: // DWORD aligned
1914 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1915 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1917 CountReg = makeAnotherReg(Type::IntTy);
1918 unsigned ByteReg = getReg(CI.getOperand(3));
1919 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1921 Opcode = X86::REP_MOVSD;
1923 default: // BYTE aligned
1924 CountReg = getReg(CI.getOperand(3));
1925 Opcode = X86::REP_MOVSB;
1929 // No matter what the alignment is, we put the source in ESI, the
1930 // destination in EDI, and the count in ECX.
1931 TmpReg1 = getReg(CI.getOperand(1));
1932 TmpReg2 = getReg(CI.getOperand(2));
1933 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1934 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1935 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
1936 BuildMI(BB, Opcode, 0);
1939 case Intrinsic::memset: {
1940 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1942 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1943 Align = AlignC->getRawValue();
1944 if (Align == 0) Align = 1;
1947 // Turn the byte code into # iterations
1950 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1951 unsigned Val = ValC->getRawValue() & 255;
1953 // If the value is a constant, then we can potentially use larger copies.
1954 switch (Align & 3) {
1955 case 2: // WORD aligned
1956 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1957 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1959 CountReg = makeAnotherReg(Type::IntTy);
1960 unsigned ByteReg = getReg(CI.getOperand(3));
1961 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1963 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
1964 Opcode = X86::REP_STOSW;
1966 case 0: // DWORD aligned
1967 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1968 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1970 CountReg = makeAnotherReg(Type::IntTy);
1971 unsigned ByteReg = getReg(CI.getOperand(3));
1972 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1974 Val = (Val << 8) | Val;
1975 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
1976 Opcode = X86::REP_STOSD;
1978 default: // BYTE aligned
1979 CountReg = getReg(CI.getOperand(3));
1980 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
1981 Opcode = X86::REP_STOSB;
1985 // If it's not a constant value we are storing, just fall back. We could
1986 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1987 unsigned ValReg = getReg(CI.getOperand(2));
1988 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1989 CountReg = getReg(CI.getOperand(3));
1990 Opcode = X86::REP_STOSB;
1993 // No matter what the alignment is, we put the source in ESI, the
1994 // destination in EDI, and the count in ECX.
1995 TmpReg1 = getReg(CI.getOperand(1));
1996 //TmpReg2 = getReg(CI.getOperand(2));
1997 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1998 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1999 BuildMI(BB, Opcode, 0);
2003 case Intrinsic::readport: {
2004 // First, determine that the size of the operand falls within the acceptable
2005 // range for this architecture.
2007 if (getClassB(CI.getOperand(1)->getType()) != cShort) {
2008 std::cerr << "llvm.readport: Address size is not 16 bits\n";
2012 // Now, move the I/O port address into the DX register and use the IN
2013 // instruction to get the input data.
2015 unsigned Class = getClass(CI.getCalledFunction()->getReturnType());
2016 unsigned DestReg = getReg(CI);
2018 // If the port is a single-byte constant, use the immediate form.
2019 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(1)))
2020 if ((C->getRawValue() & 255) == C->getRawValue()) {
2023 BuildMI(BB, X86::IN8ri, 1).addImm((unsigned char)C->getRawValue());
2024 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
2027 BuildMI(BB, X86::IN16ri, 1).addImm((unsigned char)C->getRawValue());
2028 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
2031 BuildMI(BB, X86::IN32ri, 1).addImm((unsigned char)C->getRawValue());
2032 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
2037 unsigned Reg = getReg(CI.getOperand(1));
2038 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
2041 BuildMI(BB, X86::IN8rr, 0);
2042 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
2045 BuildMI(BB, X86::IN16rr, 0);
2046 BuildMI(BB, X86::MOV16rr, 1, DestReg).addReg(X86::AX);
2049 BuildMI(BB, X86::IN32rr, 0);
2050 BuildMI(BB, X86::MOV32rr, 1, DestReg).addReg(X86::EAX);
2053 std::cerr << "Cannot do input on this data type";
2059 case Intrinsic::writeport: {
2060 // First, determine that the size of the operand falls within the
2061 // acceptable range for this architecture.
2062 if (getClass(CI.getOperand(2)->getType()) != cShort) {
2063 std::cerr << "llvm.writeport: Address size is not 16 bits\n";
2067 unsigned Class = getClassB(CI.getOperand(1)->getType());
2068 unsigned ValReg = getReg(CI.getOperand(1));
2071 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
2074 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(ValReg);
2077 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(ValReg);
2080 std::cerr << "llvm.writeport: invalid data type for X86 target";
2085 // If the port is a single-byte constant, use the immediate form.
2086 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(2)))
2087 if ((C->getRawValue() & 255) == C->getRawValue()) {
2088 static const unsigned O[] = { X86::OUT8ir, X86::OUT16ir, X86::OUT32ir };
2089 BuildMI(BB, O[Class], 1).addImm((unsigned char)C->getRawValue());
2093 // Otherwise, move the I/O port address into the DX register and the value
2094 // to write into the AL/AX/EAX register.
2095 static const unsigned Opc[] = { X86::OUT8rr, X86::OUT16rr, X86::OUT32rr };
2096 unsigned Reg = getReg(CI.getOperand(2));
2097 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
2098 BuildMI(BB, Opc[Class], 0);
2102 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
2106 static bool isSafeToFoldLoadIntoInstruction(LoadInst &LI, Instruction &User) {
2107 if (LI.getParent() != User.getParent())
2109 BasicBlock::iterator It = &LI;
2110 // Check all of the instructions between the load and the user. We should
2111 // really use alias analysis here, but for now we just do something simple.
2112 for (++It; It != BasicBlock::iterator(&User); ++It) {
2113 switch (It->getOpcode()) {
2114 case Instruction::Free:
2115 case Instruction::Store:
2116 case Instruction::Call:
2117 case Instruction::Invoke:
2119 case Instruction::Load:
2120 if (cast<LoadInst>(It)->isVolatile() && LI.isVolatile())
2128 /// visitSimpleBinary - Implement simple binary operators for integral types...
2129 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
2132 void X86ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
2133 unsigned DestReg = getReg(B);
2134 MachineBasicBlock::iterator MI = BB->end();
2135 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
2136 unsigned Class = getClassB(B.getType());
2138 // If this is AND X, C, and it is only used by a setcc instruction, it will
2139 // be folded. There is no need to emit this instruction.
2140 if (B.hasOneUse() && OperatorClass == 2 && isa<ConstantInt>(Op1))
2141 if (Class == cByte || Class == cShort || Class == cInt) {
2142 Instruction *Use = cast<Instruction>(B.use_back());
2143 if (isa<SetCondInst>(Use) &&
2144 Use->getOperand(1) == Constant::getNullValue(B.getType())) {
2145 switch (getSetCCNumber(Use->getOpcode())) {
2150 if (B.getType()->isSigned()) return;
2155 // Special case: op Reg, load [mem]
2156 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1) && Class != cLong &&
2158 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B))
2159 if (!B.swapOperands())
2160 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
2162 if (isa<LoadInst>(Op1) && Class != cLong && Op1->hasOneUse() &&
2163 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op1), B)) {
2167 static const unsigned OpcodeTab[][3] = {
2168 // Arithmetic operators
2169 { X86::ADD8rm, X86::ADD16rm, X86::ADD32rm }, // ADD
2170 { X86::SUB8rm, X86::SUB16rm, X86::SUB32rm }, // SUB
2172 // Bitwise operators
2173 { X86::AND8rm, X86::AND16rm, X86::AND32rm }, // AND
2174 { X86:: OR8rm, X86:: OR16rm, X86:: OR32rm }, // OR
2175 { X86::XOR8rm, X86::XOR16rm, X86::XOR32rm }, // XOR
2177 Opcode = OpcodeTab[OperatorClass][Class];
2179 static const unsigned OpcodeTab[][2] = {
2180 { X86::FADD32m, X86::FADD64m }, // ADD
2181 { X86::FSUB32m, X86::FSUB64m }, // SUB
2183 const Type *Ty = Op0->getType();
2184 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
2185 Opcode = OpcodeTab[OperatorClass][Ty == Type::DoubleTy];
2188 unsigned Op0r = getReg(Op0);
2189 if (AllocaInst *AI =
2190 dyn_castFixedAlloca(cast<LoadInst>(Op1)->getOperand(0))) {
2191 unsigned FI = getFixedSizedAllocaFI(AI);
2192 addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), FI);
2196 getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), AM);
2198 addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), AM);
2203 // If this is a floating point subtract, check to see if we can fold the first
2205 if (Class == cFP && OperatorClass == 1 &&
2206 isa<LoadInst>(Op0) &&
2207 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B)) {
2208 const Type *Ty = Op0->getType();
2209 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
2210 unsigned Opcode = Ty == Type::FloatTy ? X86::FSUBR32m : X86::FSUBR64m;
2212 unsigned Op1r = getReg(Op1);
2213 if (AllocaInst *AI =
2214 dyn_castFixedAlloca(cast<LoadInst>(Op0)->getOperand(0))) {
2215 unsigned FI = getFixedSizedAllocaFI(AI);
2216 addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), FI);
2219 getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), AM);
2221 addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), AM);
2226 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
2230 /// emitBinaryFPOperation - This method handles emission of floating point
2231 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
2232 void X86ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
2233 MachineBasicBlock::iterator IP,
2234 Value *Op0, Value *Op1,
2235 unsigned OperatorClass, unsigned DestReg) {
2236 // Special case: op Reg, <const fp>
2237 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1))
2238 if (!Op1C->isExactlyValue(+0.0) && !Op1C->isExactlyValue(+1.0)) {
2239 // Create a constant pool entry for this constant.
2240 MachineConstantPool *CP = F->getConstantPool();
2241 unsigned CPI = CP->getConstantPoolIndex(Op1C);
2242 const Type *Ty = Op1->getType();
2244 static const unsigned OpcodeTab[][4] = {
2245 { X86::FADD32m, X86::FSUB32m, X86::FMUL32m, X86::FDIV32m }, // Float
2246 { X86::FADD64m, X86::FSUB64m, X86::FMUL64m, X86::FDIV64m }, // Double
2249 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
2250 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
2251 unsigned Op0r = getReg(Op0, BB, IP);
2252 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
2253 DestReg).addReg(Op0r), CPI);
2257 // Special case: R1 = op <const fp>, R2
2258 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
2259 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
2261 unsigned op1Reg = getReg(Op1, BB, IP);
2262 BuildMI(*BB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
2264 } else if (!CFP->isExactlyValue(+0.0) && !CFP->isExactlyValue(+1.0)) {
2265 // R1 = op CST, R2 --> R1 = opr R2, CST
2267 // Create a constant pool entry for this constant.
2268 MachineConstantPool *CP = F->getConstantPool();
2269 unsigned CPI = CP->getConstantPoolIndex(CFP);
2270 const Type *Ty = CFP->getType();
2272 static const unsigned OpcodeTab[][4] = {
2273 { X86::FADD32m, X86::FSUBR32m, X86::FMUL32m, X86::FDIVR32m }, // Float
2274 { X86::FADD64m, X86::FSUBR64m, X86::FMUL64m, X86::FDIVR64m }, // Double
2277 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2278 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
2279 unsigned Op1r = getReg(Op1, BB, IP);
2280 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
2281 DestReg).addReg(Op1r), CPI);
2286 static const unsigned OpcodeTab[4] = {
2287 X86::FpADD, X86::FpSUB, X86::FpMUL, X86::FpDIV
2290 unsigned Opcode = OpcodeTab[OperatorClass];
2291 unsigned Op0r = getReg(Op0, BB, IP);
2292 unsigned Op1r = getReg(Op1, BB, IP);
2293 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2296 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
2297 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
2300 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
2301 /// and constant expression support.
2303 void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
2304 MachineBasicBlock::iterator IP,
2305 Value *Op0, Value *Op1,
2306 unsigned OperatorClass,
2308 unsigned Class = getClassB(Op0->getType());
2311 assert(OperatorClass < 2 && "No logical ops for FP!");
2312 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
2316 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
2317 if (OperatorClass == 1) {
2318 static unsigned const NEGTab[] = {
2319 X86::NEG8r, X86::NEG16r, X86::NEG32r, 0, X86::NEG32r
2322 // sub 0, X -> neg X
2323 if (CI->isNullValue()) {
2324 unsigned op1Reg = getReg(Op1, MBB, IP);
2325 BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg);
2327 if (Class == cLong) {
2328 // We just emitted: Dl = neg Sl
2329 // Now emit : T = addc Sh, 0
2331 unsigned T = makeAnotherReg(Type::IntTy);
2332 BuildMI(*MBB, IP, X86::ADC32ri, 2, T).addReg(op1Reg+1).addImm(0);
2333 BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg+1).addReg(T);
2336 } else if (Op1->hasOneUse() && Class != cLong) {
2337 // sub C, X -> tmp = neg X; DestReg = add tmp, C. This is better
2338 // than copying C into a temporary register, because of register
2339 // pressure (tmp and destreg can share a register.
2340 static unsigned const ADDRITab[] = {
2341 X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri
2343 unsigned op1Reg = getReg(Op1, MBB, IP);
2344 unsigned Tmp = makeAnotherReg(Op0->getType());
2345 BuildMI(*MBB, IP, NEGTab[Class], 1, Tmp).addReg(op1Reg);
2346 BuildMI(*MBB, IP, ADDRITab[Class], 2,
2347 DestReg).addReg(Tmp).addImm(CI->getRawValue());
2352 // Special case: op Reg, <const int>
2353 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
2354 unsigned Op0r = getReg(Op0, MBB, IP);
2356 // xor X, -1 -> not X
2357 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
2358 static unsigned const NOTTab[] = {
2359 X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
2361 BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
2362 if (Class == cLong) // Invert the top part too
2363 BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
2367 // add X, -1 -> dec X
2368 if (OperatorClass == 0 && Op1C->isAllOnesValue() && Class != cLong) {
2369 // Note that we can't use dec for 64-bit decrements, because it does not
2370 // set the carry flag!
2371 static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
2372 BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
2376 // add X, 1 -> inc X
2377 if (OperatorClass == 0 && Op1C->equalsInt(1) && Class != cLong) {
2378 // Note that we can't use inc for 64-bit increments, because it does not
2379 // set the carry flag!
2380 static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
2381 BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
2385 static const unsigned OpcodeTab[][5] = {
2386 // Arithmetic operators
2387 { X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
2388 { X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
2390 // Bitwise operators
2391 { X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
2392 { X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
2393 { X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
2396 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2397 unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
2399 if (Class != cLong) {
2400 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2404 // If this is a long value and the high or low bits have a special
2405 // property, emit some special cases.
2406 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
2408 // If the constant is zero in the low 32-bits, just copy the low part
2409 // across and apply the normal 32-bit operation to the high parts. There
2410 // will be no carry or borrow into the top.
2412 if (OperatorClass != 2) // All but and...
2413 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0r);
2415 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2416 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg+1)
2417 .addReg(Op0r+1).addImm(Op1h);
2421 // If this is a logical operation and the top 32-bits are zero, just
2422 // operate on the lower 32.
2423 if (Op1h == 0 && OperatorClass > 1) {
2424 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg)
2425 .addReg(Op0r).addImm(Op1l);
2426 if (OperatorClass != 2) // All but and
2427 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(Op0r+1);
2429 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2433 // TODO: We could handle lots of other special cases here, such as AND'ing
2434 // with 0xFFFFFFFF00000000 -> noop, etc.
2436 // Otherwise, code generate the full operation with a constant.
2437 static const unsigned TopTab[] = {
2438 X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
2441 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2442 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
2443 .addReg(Op0r+1).addImm(Op1h);
2447 // Finally, handle the general case now.
2448 static const unsigned OpcodeTab[][5] = {
2449 // Arithmetic operators
2450 { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, 0, X86::ADD32rr }, // ADD
2451 { X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, 0, X86::SUB32rr }, // SUB
2453 // Bitwise operators
2454 { X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
2455 { X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
2456 { X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
2459 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2460 unsigned Op0r = getReg(Op0, MBB, IP);
2461 unsigned Op1r = getReg(Op1, MBB, IP);
2462 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2464 if (Class == cLong) { // Handle the upper 32 bits of long values...
2465 static const unsigned TopTab[] = {
2466 X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
2468 BuildMI(*MBB, IP, TopTab[OperatorClass], 2,
2469 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
2473 /// doMultiply - Emit appropriate instructions to multiply together the
2474 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
2475 /// result should be given as DestTy.
2477 void X86ISel::doMultiply(MachineBasicBlock *MBB,
2478 MachineBasicBlock::iterator MBBI,
2479 unsigned DestReg, const Type *DestTy,
2480 unsigned op0Reg, unsigned op1Reg) {
2481 unsigned Class = getClass(DestTy);
2485 BuildMI(*MBB, MBBI, Class == cInt ? X86::IMUL32rr:X86::IMUL16rr, 2, DestReg)
2486 .addReg(op0Reg).addReg(op1Reg);
2489 // Must use the MUL instruction, which forces use of AL...
2490 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, X86::AL).addReg(op0Reg);
2491 BuildMI(*MBB, MBBI, X86::MUL8r, 1).addReg(op1Reg);
2492 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
2495 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
2499 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
2500 // returns zero when the input is not exactly a power of two.
2501 static unsigned ExactLog2(unsigned Val) {
2502 if (Val == 0 || (Val & (Val-1))) return 0;
2512 /// doMultiplyConst - This function is specialized to efficiently codegen an 8,
2513 /// 16, or 32-bit integer multiply by a constant.
2514 void X86ISel::doMultiplyConst(MachineBasicBlock *MBB,
2515 MachineBasicBlock::iterator IP,
2516 unsigned DestReg, const Type *DestTy,
2517 unsigned op0Reg, unsigned ConstRHS) {
2518 static const unsigned MOVrrTab[] = {X86::MOV8rr, X86::MOV16rr, X86::MOV32rr};
2519 static const unsigned MOVriTab[] = {X86::MOV8ri, X86::MOV16ri, X86::MOV32ri};
2520 static const unsigned ADDrrTab[] = {X86::ADD8rr, X86::ADD16rr, X86::ADD32rr};
2521 static const unsigned NEGrTab[] = {X86::NEG8r , X86::NEG16r , X86::NEG32r };
2523 unsigned Class = getClass(DestTy);
2526 // Handle special cases here.
2529 TmpReg = makeAnotherReg(DestTy);
2530 BuildMI(*MBB, IP, NEGrTab[Class], 1, TmpReg).addReg(op0Reg);
2531 BuildMI(*MBB, IP, ADDrrTab[Class], 1,DestReg).addReg(TmpReg).addReg(TmpReg);
2534 BuildMI(*MBB, IP, NEGrTab[Class], 1, DestReg).addReg(op0Reg);
2537 BuildMI(*MBB, IP, MOVriTab[Class], 1, DestReg).addImm(0);
2540 BuildMI(*MBB, IP, MOVrrTab[Class], 1, DestReg).addReg(op0Reg);
2543 BuildMI(*MBB, IP, ADDrrTab[Class], 1,DestReg).addReg(op0Reg).addReg(op0Reg);
2548 if (Class == cInt) {
2550 AM.BaseType = X86AddressMode::RegBase;
2551 AM.Base.Reg = op0Reg;
2552 AM.Scale = ConstRHS-1;
2553 AM.IndexReg = op0Reg;
2555 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, DestReg), AM);
2561 if (Class == cInt) {
2562 TmpReg = makeAnotherReg(DestTy);
2564 AM.BaseType = X86AddressMode::RegBase;
2565 AM.Base.Reg = op0Reg;
2566 AM.Scale = -ConstRHS-1;
2567 AM.IndexReg = op0Reg;
2569 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TmpReg), AM);
2570 BuildMI(*MBB, IP, NEGrTab[Class], 1, DestReg).addReg(TmpReg);
2575 // If the element size is exactly a power of 2, use a shift to get it.
2576 if (unsigned Shift = ExactLog2(ConstRHS)) {
2578 default: assert(0 && "Unknown class for this function!");
2580 BuildMI(*MBB, IP, X86::SHL8ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2583 BuildMI(*MBB, IP, X86::SHL16ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2586 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2591 // If the element size is a negative power of 2, use a shift/neg to get it.
2592 if (unsigned Shift = ExactLog2(-ConstRHS)) {
2593 TmpReg = makeAnotherReg(DestTy);
2594 BuildMI(*MBB, IP, NEGrTab[Class], 1, TmpReg).addReg(op0Reg);
2596 default: assert(0 && "Unknown class for this function!");
2598 BuildMI(*MBB, IP, X86::SHL8ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2601 BuildMI(*MBB, IP, X86::SHL16ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2604 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2609 if (Class == cShort) {
2610 BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2612 } else if (Class == cInt) {
2613 BuildMI(*MBB, IP, X86::IMUL32rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2617 // Most general case, emit a normal multiply...
2618 TmpReg = makeAnotherReg(DestTy);
2619 BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS);
2621 // Emit a MUL to multiply the register holding the index by
2622 // elementSize, putting the result in OffsetReg.
2623 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
2626 /// visitMul - Multiplies are not simple binary operators because they must deal
2627 /// with the EAX register explicitly.
2629 void X86ISel::visitMul(BinaryOperator &I) {
2630 unsigned ResultReg = getReg(I);
2632 Value *Op0 = I.getOperand(0);
2633 Value *Op1 = I.getOperand(1);
2635 // Fold loads into floating point multiplies.
2636 if (getClass(Op0->getType()) == cFP) {
2637 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
2638 if (!I.swapOperands())
2639 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
2640 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2641 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2642 const Type *Ty = Op0->getType();
2643 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2644 unsigned Opcode = Ty == Type::FloatTy ? X86::FMUL32m : X86::FMUL64m;
2646 unsigned Op0r = getReg(Op0);
2647 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2648 unsigned FI = getFixedSizedAllocaFI(AI);
2649 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
2652 getAddressingMode(LI->getOperand(0), AM);
2654 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), AM);
2660 MachineBasicBlock::iterator IP = BB->end();
2661 emitMultiply(BB, IP, Op0, Op1, ResultReg);
2664 void X86ISel::emitMultiply(MachineBasicBlock *MBB,
2665 MachineBasicBlock::iterator IP,
2666 Value *Op0, Value *Op1, unsigned DestReg) {
2667 MachineBasicBlock &BB = *MBB;
2668 TypeClass Class = getClass(Op0->getType());
2670 // Simple scalar multiply?
2671 unsigned Op0Reg = getReg(Op0, &BB, IP);
2676 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2677 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
2678 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
2680 unsigned Op1Reg = getReg(Op1, &BB, IP);
2681 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
2685 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
2691 // Long value. We have to do things the hard way...
2692 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2693 unsigned CLow = CI->getRawValue();
2694 unsigned CHi = CI->getRawValue() >> 32;
2697 // If the low part of the constant is all zeros, things are simple.
2698 BuildMI(BB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2699 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
2703 // Multiply the two low parts... capturing carry into EDX
2704 unsigned OverflowReg = 0;
2706 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0Reg);
2708 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
2709 OverflowReg = makeAnotherReg(Type::UIntTy);
2710 BuildMI(BB, IP, X86::MOV32ri, 1, Op1RegL).addImm(CLow);
2711 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2712 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1RegL); // AL*BL
2714 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2715 BuildMI(BB, IP, X86::MOV32rr, 1,
2716 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2719 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2720 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
2722 unsigned AHBLplusOverflowReg;
2724 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2725 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2726 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2728 AHBLplusOverflowReg = AHBLReg;
2732 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(AHBLplusOverflowReg);
2734 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2735 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
2737 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2738 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2743 // General 64x64 multiply
2745 unsigned Op1Reg = getReg(Op1, &BB, IP);
2746 // Multiply the two low parts... capturing carry into EDX
2747 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2748 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL
2750 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
2751 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2752 BuildMI(BB, IP, X86::MOV32rr, 1,
2753 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2755 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2756 BuildMI(BB, IP, X86::IMUL32rr, 2,
2757 AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
2759 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2760 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2761 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2763 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2764 BuildMI(BB, IP, X86::IMUL32rr, 2,
2765 ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
2767 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2768 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2772 /// visitDivRem - Handle division and remainder instructions... these
2773 /// instruction both require the same instructions to be generated, they just
2774 /// select the result from a different register. Note that both of these
2775 /// instructions work differently for signed and unsigned operands.
2777 void X86ISel::visitDivRem(BinaryOperator &I) {
2778 unsigned ResultReg = getReg(I);
2779 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
2781 // Fold loads into floating point divides.
2782 if (getClass(Op0->getType()) == cFP) {
2783 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2784 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2785 const Type *Ty = Op0->getType();
2786 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2787 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIV32m : X86::FDIV64m;
2789 unsigned Op0r = getReg(Op0);
2790 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2791 unsigned FI = getFixedSizedAllocaFI(AI);
2792 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
2795 getAddressingMode(LI->getOperand(0), AM);
2797 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), AM);
2802 if (LoadInst *LI = dyn_cast<LoadInst>(Op0))
2803 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2804 const Type *Ty = Op0->getType();
2805 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2806 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIVR32m : X86::FDIVR64m;
2808 unsigned Op1r = getReg(Op1);
2809 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2810 unsigned FI = getFixedSizedAllocaFI(AI);
2811 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r), FI);
2814 getAddressingMode(LI->getOperand(0), AM);
2815 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r), AM);
2822 MachineBasicBlock::iterator IP = BB->end();
2823 emitDivRemOperation(BB, IP, Op0, Op1,
2824 I.getOpcode() == Instruction::Div, ResultReg);
2827 void X86ISel::emitDivRemOperation(MachineBasicBlock *BB,
2828 MachineBasicBlock::iterator IP,
2829 Value *Op0, Value *Op1, bool isDiv,
2830 unsigned ResultReg) {
2831 const Type *Ty = Op0->getType();
2832 unsigned Class = getClass(Ty);
2834 case cFP: // Floating point divide
2836 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
2838 } else { // Floating point remainder...
2839 unsigned Op0Reg = getReg(Op0, BB, IP);
2840 unsigned Op1Reg = getReg(Op1, BB, IP);
2841 MachineInstr *TheCall =
2842 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
2843 std::vector<ValueRecord> Args;
2844 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
2845 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
2846 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
2850 static const char *FnName[] =
2851 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
2852 unsigned Op0Reg = getReg(Op0, BB, IP);
2853 unsigned Op1Reg = getReg(Op1, BB, IP);
2854 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
2855 MachineInstr *TheCall =
2856 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
2858 std::vector<ValueRecord> Args;
2859 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
2860 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
2861 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
2864 case cByte: case cShort: case cInt:
2865 break; // Small integrals, handled below...
2866 default: assert(0 && "Unknown class!");
2869 static const unsigned MovOpcode[]={ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr };
2870 static const unsigned NEGOpcode[]={ X86::NEG8r, X86::NEG16r, X86::NEG32r };
2871 static const unsigned SAROpcode[]={ X86::SAR8ri, X86::SAR16ri, X86::SAR32ri };
2872 static const unsigned SHROpcode[]={ X86::SHR8ri, X86::SHR16ri, X86::SHR32ri };
2873 static const unsigned ADDOpcode[]={ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr };
2875 // Special case signed division by power of 2.
2876 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1))
2878 assert(Class != cLong && "This doesn't handle 64-bit divides!");
2879 int V = CI->getValue();
2881 if (V == 1) { // X /s 1 => X
2882 unsigned Op0Reg = getReg(Op0, BB, IP);
2883 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(Op0Reg);
2887 if (V == -1) { // X /s -1 => -X
2888 unsigned Op0Reg = getReg(Op0, BB, IP);
2889 BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(Op0Reg);
2893 if (V == 2 || V == -2) { // X /s 2
2894 static const unsigned CMPOpcode[] = {
2895 X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
2897 static const unsigned SBBOpcode[] = {
2898 X86::SBB8ri, X86::SBB16ri, X86::SBB32ri
2900 unsigned Op0Reg = getReg(Op0, BB, IP);
2901 unsigned SignBit = 1 << (CI->getType()->getPrimitiveSize()*8-1);
2902 BuildMI(*BB, IP, CMPOpcode[Class], 2).addReg(Op0Reg).addImm(SignBit);
2904 unsigned TmpReg = makeAnotherReg(Op0->getType());
2905 BuildMI(*BB, IP, SBBOpcode[Class], 2, TmpReg).addReg(Op0Reg).addImm(-1);
2907 unsigned TmpReg2 = V == 2 ? ResultReg : makeAnotherReg(Op0->getType());
2908 BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg2).addReg(TmpReg).addImm(1);
2910 BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(TmpReg2);
2916 if (V < 0) { // Not a positive power of 2?
2918 isNeg = true; // Maybe it's a negative power of 2.
2920 if (unsigned Log = ExactLog2(V)) {
2922 unsigned Op0Reg = getReg(Op0, BB, IP);
2923 unsigned TmpReg = makeAnotherReg(Op0->getType());
2924 BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg)
2925 .addReg(Op0Reg).addImm(Log-1);
2926 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2927 BuildMI(*BB, IP, SHROpcode[Class], 2, TmpReg2)
2928 .addReg(TmpReg).addImm(CI->getType()->getPrimitiveSizeInBits()-Log);
2929 unsigned TmpReg3 = makeAnotherReg(Op0->getType());
2930 BuildMI(*BB, IP, ADDOpcode[Class], 2, TmpReg3)
2931 .addReg(Op0Reg).addReg(TmpReg2);
2933 unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
2934 BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg4)
2935 .addReg(TmpReg3).addImm(Log);
2937 BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(TmpReg4);
2941 assert(Class != cLong && "This doesn't handle 64-bit remainder!");
2942 int V = CI->getValue();
2944 if (V == 2 || V == -2) { // X % 2, X % -2
2945 static const unsigned SExtOpcode[] = { X86::CBW, X86::CWD, X86::CDQ };
2946 static const unsigned BaseReg[] = { X86::AL , X86::AX , X86::EAX };
2947 static const unsigned SExtReg[] = { X86::AH , X86::DX , X86::EDX };
2948 static const unsigned ANDOpcode[] = {
2949 X86::AND8ri, X86::AND16ri, X86::AND32ri
2951 static const unsigned XOROpcode[] = {
2952 X86::XOR8rr, X86::XOR16rr, X86::XOR32rr
2954 static const unsigned SUBOpcode[] = {
2955 X86::SUB8rr, X86::SUB16rr, X86::SUB32rr
2958 // Sign extend result into reg of -1 or 0.
2959 unsigned Op0Reg = getReg(Op0, BB, IP);
2960 BuildMI(*BB, IP, MovOpcode[Class], 1, BaseReg[Class]).addReg(Op0Reg);
2961 BuildMI(*BB, IP, SExtOpcode[Class], 0);
2962 unsigned TmpReg0 = makeAnotherReg(Op0->getType());
2963 BuildMI(*BB, IP, MovOpcode[Class], 1, TmpReg0).addReg(SExtReg[Class]);
2965 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
2966 BuildMI(*BB, IP, ANDOpcode[Class], 2, TmpReg1).addReg(Op0Reg).addImm(1);
2968 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2969 BuildMI(*BB, IP, XOROpcode[Class], 2,
2970 TmpReg2).addReg(TmpReg1).addReg(TmpReg0);
2971 BuildMI(*BB, IP, SUBOpcode[Class], 2,
2972 ResultReg).addReg(TmpReg2).addReg(TmpReg0);
2977 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
2978 static const unsigned ClrOpcode[]={ X86::MOV8ri, X86::MOV16ri, X86::MOV32ri };
2979 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
2980 static const unsigned SExOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
2982 static const unsigned DivOpcode[][4] = {
2983 { X86::DIV8r , X86::DIV16r , X86::DIV32r , 0 }, // Unsigned division
2984 { X86::IDIV8r, X86::IDIV16r, X86::IDIV32r, 0 }, // Signed division
2987 unsigned Reg = Regs[Class];
2988 unsigned ExtReg = ExtRegs[Class];
2990 // Put the first operand into one of the A registers...
2991 unsigned Op0Reg = getReg(Op0, BB, IP);
2992 unsigned Op1Reg = getReg(Op1, BB, IP);
2993 BuildMI(*BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
2995 if (Ty->isSigned()) {
2996 // Emit a sign extension instruction.
2997 BuildMI(*BB, IP, SExOpcode[Class], 0);
2999 // Emit the appropriate divide or remainder instruction...
3000 BuildMI(*BB, IP, DivOpcode[1][Class], 1).addReg(Op1Reg);
3002 // If unsigned, emit a zeroing instruction... (reg = 0)
3003 BuildMI(*BB, IP, ClrOpcode[Class], 2, ExtReg).addImm(0);
3005 // Emit the appropriate divide or remainder instruction...
3006 BuildMI(*BB, IP, DivOpcode[0][Class], 1).addReg(Op1Reg);
3009 // Figure out which register we want to pick the result out of...
3010 unsigned DestReg = isDiv ? Reg : ExtReg;
3012 // Put the result into the destination register...
3013 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
3017 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
3018 /// for constant immediate shift values, and for constant immediate
3019 /// shift values equal to 1. Even the general case is sort of special,
3020 /// because the shift amount has to be in CL, not just any old register.
3022 void X86ISel::visitShiftInst(ShiftInst &I) {
3023 MachineBasicBlock::iterator IP = BB->end ();
3024 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
3025 I.getOpcode () == Instruction::Shl, I.getType (),
3029 /// Emit code for a 'SHLD DestReg, Op0, Op1, Amt' operation, where Amt is a
3031 void X86ISel::doSHLDConst(MachineBasicBlock *MBB,
3032 MachineBasicBlock::iterator IP,
3033 unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg,
3035 // SHLD is a very inefficient operation on every processor, try to do
3036 // somethign simpler for common values of 'Amt'.
3038 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0Reg);
3039 } else if (Amt == 1) {
3040 unsigned Tmp = makeAnotherReg(Type::UIntTy);
3041 BuildMI(*MBB, IP, X86::ADD32rr, 2, Tmp).addReg(Op1Reg).addReg(Op1Reg);
3042 BuildMI(*MBB, IP, X86::ADC32rr, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
3043 } else if (Amt == 2 || Amt == 3) {
3044 // On the P4 and Athlon it is cheaper to replace shld ..., 2|3 with a
3045 // shift/lea pair. NOTE: This should not be done on the P6 family!
3046 unsigned Tmp = makeAnotherReg(Type::UIntTy);
3047 BuildMI(*MBB, IP, X86::SHR32ri, 2, Tmp).addReg(Op1Reg).addImm(32-Amt);
3049 AM.BaseType = X86AddressMode::RegBase;
3051 AM.Scale = 1 << Amt;
3052 AM.IndexReg = Op0Reg;
3054 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 4, DestReg), AM);
3056 // NOTE: It is always cheaper on the P4 to emit SHLD as two shifts and an OR
3057 // than it is to emit a real SHLD.
3059 BuildMI(*MBB, IP, X86::SHLD32rri8, 3,
3060 DestReg).addReg(Op0Reg).addReg(Op1Reg).addImm(Amt);
3064 /// emitShiftOperation - Common code shared between visitShiftInst and
3065 /// constant expression support.
3066 void X86ISel::emitShiftOperation(MachineBasicBlock *MBB,
3067 MachineBasicBlock::iterator IP,
3068 Value *Op, Value *ShiftAmount,
3069 bool isLeftShift, const Type *ResultTy,
3071 unsigned SrcReg = getReg (Op, MBB, IP);
3072 bool isSigned = ResultTy->isSigned ();
3073 unsigned Class = getClass (ResultTy);
3075 static const unsigned ConstantOperand[][3] = {
3076 { X86::SHR8ri, X86::SHR16ri, X86::SHR32ri }, // SHR
3077 { X86::SAR8ri, X86::SAR16ri, X86::SAR32ri }, // SAR
3078 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri }, // SHL
3079 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri }, // SAL = SHL
3082 static const unsigned NonConstantOperand[][3] = {
3083 { X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL }, // SHR
3084 { X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL }, // SAR
3085 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SHL
3086 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SAL = SHL
3089 // Longs, as usual, are handled specially.
3090 if (Class == cLong) {
3091 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
3092 unsigned Amount = CUI->getValue();
3093 if (Amount == 1 && isLeftShift) { // X << 1 == X+X
3094 BuildMI(*MBB, IP, X86::ADD32rr, 2,
3095 DestReg).addReg(SrcReg).addReg(SrcReg);
3096 BuildMI(*MBB, IP, X86::ADC32rr, 2,
3097 DestReg+1).addReg(SrcReg+1).addReg(SrcReg+1);
3098 } else if (Amount < 32) {
3099 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
3101 doSHLDConst(MBB, IP, DestReg+1, SrcReg+1, SrcReg, Amount);
3102 BuildMI(*MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addImm(Amount);
3104 BuildMI(*MBB, IP, X86::SHRD32rri8, 3,
3105 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount);
3106 BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount);
3108 } else if (Amount == 32) {
3110 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg);
3111 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
3113 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg+1);
3115 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
3117 BuildMI(*MBB, IP, X86::SAR32ri, 2,
3118 DestReg+1).addReg(SrcReg).addImm(31);
3121 } else { // Shifting more than 32 bits
3124 BuildMI(*MBB, IP, X86::SHL32ri, 2,
3125 DestReg + 1).addReg(SrcReg).addImm(Amount);
3126 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
3128 BuildMI(*MBB, IP, isSigned ? X86::SAR32ri : X86::SHR32ri, 2,
3129 DestReg).addReg(SrcReg+1).addImm(Amount);
3131 BuildMI(*MBB, IP, X86::SAR32ri, 2,
3132 DestReg+1).addReg(SrcReg+1).addImm(31);
3134 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
3138 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3139 if (!isLeftShift && isSigned) {
3140 // If this is a SHR of a Long, then we need to do funny sign extension
3141 // stuff. TmpReg gets the value to use as the high-part if we are
3142 // shifting more than 32 bits.
3143 BuildMI(*MBB, IP, X86::SAR32ri, 2, TmpReg).addReg(SrcReg).addImm(31);
3145 // Other shifts use a fixed zero value if the shift is more than 32
3147 BuildMI(*MBB, IP, X86::MOV32ri, 1, TmpReg).addImm(0);
3150 // Initialize CL with the shift amount...
3151 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
3152 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
3154 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
3155 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
3157 // TmpReg2 = shld inHi, inLo
3158 BuildMI(*MBB, IP, X86::SHLD32rrCL,2,TmpReg2).addReg(SrcReg+1)
3160 // TmpReg3 = shl inLo, CL
3161 BuildMI(*MBB, IP, X86::SHL32rCL, 1, TmpReg3).addReg(SrcReg);
3163 // Set the flags to indicate whether the shift was by more than 32 bits.
3164 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
3166 // DestHi = (>32) ? TmpReg3 : TmpReg2;
3167 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
3168 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
3169 // DestLo = (>32) ? TmpReg : TmpReg3;
3170 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
3171 DestReg).addReg(TmpReg3).addReg(TmpReg);
3173 // TmpReg2 = shrd inLo, inHi
3174 BuildMI(*MBB, IP, X86::SHRD32rrCL,2,TmpReg2).addReg(SrcReg)
3176 // TmpReg3 = s[ah]r inHi, CL
3177 BuildMI(*MBB, IP, isSigned ? X86::SAR32rCL : X86::SHR32rCL, 1, TmpReg3)
3180 // Set the flags to indicate whether the shift was by more than 32 bits.
3181 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
3183 // DestLo = (>32) ? TmpReg3 : TmpReg2;
3184 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
3185 DestReg).addReg(TmpReg2).addReg(TmpReg3);
3187 // DestHi = (>32) ? TmpReg : TmpReg3;
3188 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
3189 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
3195 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
3196 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
3197 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
3199 if (CUI->getValue() == 1 && isLeftShift) { // X << 1 -> X+X
3200 static const int AddOpC[] = { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr };
3201 BuildMI(*MBB, IP, AddOpC[Class], 2,DestReg).addReg(SrcReg).addReg(SrcReg);
3203 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
3204 BuildMI(*MBB, IP, Opc[Class], 2,
3205 DestReg).addReg(SrcReg).addImm(CUI->getValue());
3207 } else { // The shift amount is non-constant.
3208 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
3209 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
3211 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
3212 BuildMI(*MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
3217 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
3218 /// instruction. The load and store instructions are the only place where we
3219 /// need to worry about the memory layout of the target machine.
3221 void X86ISel::visitLoadInst(LoadInst &I) {
3222 // Check to see if this load instruction is going to be folded into a binary
3223 // instruction, like add. If so, we don't want to emit it. Wouldn't a real
3224 // pattern matching instruction selector be nice?
3225 unsigned Class = getClassB(I.getType());
3226 if (I.hasOneUse()) {
3227 Instruction *User = cast<Instruction>(I.use_back());
3228 switch (User->getOpcode()) {
3229 case Instruction::Cast:
3230 // If this is a cast from a signed-integer type to a floating point type,
3231 // fold the cast here.
3232 if (getClassB(User->getType()) == cFP &&
3233 (I.getType() == Type::ShortTy || I.getType() == Type::IntTy ||
3234 I.getType() == Type::LongTy)) {
3235 unsigned DestReg = getReg(User);
3236 static const unsigned Opcode[] = {
3237 0/*BYTE*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m
3240 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
3241 unsigned FI = getFixedSizedAllocaFI(AI);
3242 addFrameReference(BuildMI(BB, Opcode[Class], 4, DestReg), FI);
3245 getAddressingMode(I.getOperand(0), AM);
3246 addFullAddress(BuildMI(BB, Opcode[Class], 4, DestReg), AM);
3254 case Instruction::Add:
3255 case Instruction::Sub:
3256 case Instruction::And:
3257 case Instruction::Or:
3258 case Instruction::Xor:
3259 if (Class == cLong) User = 0;
3261 case Instruction::Mul:
3262 case Instruction::Div:
3263 if (Class != cFP) User = 0;
3264 break; // Folding only implemented for floating point.
3265 default: User = 0; break;
3269 // Okay, we found a user. If the load is the first operand and there is
3270 // no second operand load, reverse the operand ordering. Note that this
3271 // can fail for a subtract (ie, no change will be made).
3272 bool Swapped = false;
3273 if (!isa<LoadInst>(User->getOperand(1)))
3274 Swapped = !cast<BinaryOperator>(User)->swapOperands();
3276 // Okay, now that everything is set up, if this load is used by the second
3277 // operand, and if there are no instructions that invalidate the load
3278 // before the binary operator, eliminate the load.
3279 if (User->getOperand(1) == &I &&
3280 isSafeToFoldLoadIntoInstruction(I, *User))
3281 return; // Eliminate the load!
3283 // If this is a floating point sub or div, we won't be able to swap the
3284 // operands, but we will still be able to eliminate the load.
3285 if (Class == cFP && User->getOperand(0) == &I &&
3286 !isa<LoadInst>(User->getOperand(1)) &&
3287 (User->getOpcode() == Instruction::Sub ||
3288 User->getOpcode() == Instruction::Div) &&
3289 isSafeToFoldLoadIntoInstruction(I, *User))
3290 return; // Eliminate the load!
3292 // If we swapped the operands to the instruction, but couldn't fold the
3293 // load anyway, swap them back. We don't want to break add X, int
3295 if (Swapped) cast<BinaryOperator>(User)->swapOperands();
3299 static const unsigned Opcodes[] = {
3300 X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m, X86::MOV32rm
3302 unsigned Opcode = Opcodes[Class];
3303 if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m;
3305 unsigned DestReg = getReg(I);
3307 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
3308 unsigned FI = getFixedSizedAllocaFI(AI);
3309 if (Class == cLong) {
3310 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg), FI);
3311 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), FI, 4);
3313 addFrameReference(BuildMI(BB, Opcode, 4, DestReg), FI);
3317 getAddressingMode(I.getOperand(0), AM);
3319 if (Class == cLong) {
3320 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg), AM);
3322 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), AM);
3324 addFullAddress(BuildMI(BB, Opcode, 4, DestReg), AM);
3329 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
3332 void X86ISel::visitStoreInst(StoreInst &I) {
3334 getAddressingMode(I.getOperand(1), AM);
3336 const Type *ValTy = I.getOperand(0)->getType();
3337 unsigned Class = getClassB(ValTy);
3339 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
3340 uint64_t Val = CI->getRawValue();
3341 if (Class == cLong) {
3342 addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(Val & ~0U);
3344 addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(Val>>32);
3346 static const unsigned Opcodes[] = {
3347 X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
3349 unsigned Opcode = Opcodes[Class];
3350 addFullAddress(BuildMI(BB, Opcode, 5), AM).addImm(Val);
3352 } else if (isa<ConstantPointerNull>(I.getOperand(0))) {
3353 addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(0);
3354 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(I.getOperand(0))) {
3355 addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addGlobalAddress(GV);
3356 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
3357 addFullAddress(BuildMI(BB, X86::MOV8mi, 5), AM).addImm(CB->getValue());
3358 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) {
3359 // Store constant FP values with integer instructions to avoid having to
3360 // load the constants from the constant pool then do a store.
3361 if (CFP->getType() == Type::FloatTy) {
3366 V.F = CFP->getValue();
3367 addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(V.I);
3373 V.F = CFP->getValue();
3374 addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm((unsigned)V.I);
3376 addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(
3377 unsigned(V.I >> 32));
3380 } else if (Class == cLong) {
3381 unsigned ValReg = getReg(I.getOperand(0));
3382 addFullAddress(BuildMI(BB, X86::MOV32mr, 5), AM).addReg(ValReg);
3384 addFullAddress(BuildMI(BB, X86::MOV32mr, 5), AM).addReg(ValReg+1);
3386 // FIXME: stop emitting these two instructions:
3387 // movl $global,%eax
3389 // when one instruction will suffice. That includes when the global
3390 // has an offset applied to it.
3391 unsigned ValReg = getReg(I.getOperand(0));
3392 static const unsigned Opcodes[] = {
3393 X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST32m
3395 unsigned Opcode = Opcodes[Class];
3396 if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
3398 addFullAddress(BuildMI(BB, Opcode, 1+4), AM).addReg(ValReg);
3403 /// visitCastInst - Here we have various kinds of copying with or without sign
3404 /// extension going on.
3406 void X86ISel::visitCastInst(CastInst &CI) {
3407 Value *Op = CI.getOperand(0);
3409 unsigned SrcClass = getClassB(Op->getType());
3410 unsigned DestClass = getClassB(CI.getType());
3411 // Noop casts are not emitted: getReg will return the source operand as the
3412 // register to use for any uses of the noop cast.
3413 if (DestClass == SrcClass) {
3414 // The only detail in this plan is that casts from double -> float are
3415 // truncating operations that we have to codegen through memory (despite
3416 // the fact that the source/dest registers are the same class).
3417 if (CI.getType() != Type::FloatTy || Op->getType() != Type::DoubleTy)
3421 // If this is a cast from a 32-bit integer to a Long type, and the only uses
3422 // of the case are GEP instructions, then the cast does not need to be
3423 // generated explicitly, it will be folded into the GEP.
3424 if (DestClass == cLong && SrcClass == cInt) {
3425 bool AllUsesAreGEPs = true;
3426 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
3427 if (!isa<GetElementPtrInst>(*I)) {
3428 AllUsesAreGEPs = false;
3432 // No need to codegen this cast if all users are getelementptr instrs...
3433 if (AllUsesAreGEPs) return;
3436 // If this cast converts a load from a short,int, or long integer to a FP
3437 // value, we will have folded this cast away.
3438 if (DestClass == cFP && isa<LoadInst>(Op) && Op->hasOneUse() &&
3439 (Op->getType() == Type::ShortTy || Op->getType() == Type::IntTy ||
3440 Op->getType() == Type::LongTy))
3444 unsigned DestReg = getReg(CI);
3445 MachineBasicBlock::iterator MI = BB->end();
3446 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
3449 /// emitCastOperation - Common code shared between visitCastInst and constant
3450 /// expression cast support.
3452 void X86ISel::emitCastOperation(MachineBasicBlock *BB,
3453 MachineBasicBlock::iterator IP,
3454 Value *Src, const Type *DestTy,
3456 const Type *SrcTy = Src->getType();
3457 unsigned SrcClass = getClassB(SrcTy);
3458 unsigned DestClass = getClassB(DestTy);
3459 unsigned SrcReg = getReg(Src, BB, IP);
3461 // Implement casts to bool by using compare on the operand followed by set if
3462 // not zero on the result.
3463 if (DestTy == Type::BoolTy) {
3466 BuildMI(*BB, IP, X86::TEST8rr, 2).addReg(SrcReg).addReg(SrcReg);
3469 BuildMI(*BB, IP, X86::TEST16rr, 2).addReg(SrcReg).addReg(SrcReg);
3472 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg).addReg(SrcReg);
3475 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3476 BuildMI(*BB, IP, X86::OR32rr, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
3480 BuildMI(*BB, IP, X86::FTST, 1).addReg(SrcReg);
3481 BuildMI(*BB, IP, X86::FNSTSW8r, 0);
3482 BuildMI(*BB, IP, X86::SAHF, 1);
3486 // If the zero flag is not set, then the value is true, set the byte to
3488 BuildMI(*BB, IP, X86::SETNEr, 1, DestReg);
3492 static const unsigned RegRegMove[] = {
3493 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
3496 // Implement casts between values of the same type class (as determined by
3497 // getClass) by using a register-to-register move.
3498 if (SrcClass == DestClass) {
3499 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
3500 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
3501 } else if (SrcClass == cFP) {
3502 if (SrcTy == Type::FloatTy) { // double -> float
3503 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
3504 BuildMI(*BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
3505 } else { // float -> double
3506 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
3507 "Unknown cFP member!");
3508 // Truncate from double to float by storing to memory as short, then
3510 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
3511 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
3512 addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5),
3513 FrameIdx).addReg(SrcReg);
3514 addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx);
3516 } else if (SrcClass == cLong) {
3517 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
3518 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg+1);
3520 assert(0 && "Cannot handle this type of cast instruction!");
3526 // Handle cast of SMALLER int to LARGER int using a move with sign extension
3527 // or zero extension, depending on whether the source type was signed.
3528 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
3529 SrcClass < DestClass) {
3530 bool isLong = DestClass == cLong;
3531 if (isLong) DestClass = cInt;
3533 static const unsigned Opc[][4] = {
3534 { X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s
3535 { X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u
3538 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
3539 BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
3540 DestReg).addReg(SrcReg);
3542 if (isLong) { // Handle upper 32 bits as appropriate...
3543 if (isUnsigned) // Zero out top bits...
3544 BuildMI(*BB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
3545 else // Sign extend bottom half...
3546 BuildMI(*BB, IP, X86::SAR32ri, 2, DestReg+1).addReg(DestReg).addImm(31);
3551 // Special case long -> int ...
3552 if (SrcClass == cLong && DestClass == cInt) {
3553 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
3557 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
3558 // move out of AX or AL.
3559 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
3560 && SrcClass > DestClass) {
3561 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
3562 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
3563 BuildMI(*BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
3567 // Handle casts from integer to floating point now...
3568 if (DestClass == cFP) {
3569 // Promote the integer to a type supported by FLD. We do this because there
3570 // are no unsigned FLD instructions, so we must promote an unsigned value to
3571 // a larger signed value, then use FLD on the larger value.
3573 const Type *PromoteType = 0;
3574 unsigned PromoteOpcode = 0;
3575 unsigned RealDestReg = DestReg;
3576 switch (SrcTy->getTypeID()) {
3577 case Type::BoolTyID:
3578 case Type::SByteTyID:
3579 // We don't have the facilities for directly loading byte sized data from
3580 // memory (even signed). Promote it to 16 bits.
3581 PromoteType = Type::ShortTy;
3582 PromoteOpcode = X86::MOVSX16rr8;
3584 case Type::UByteTyID:
3585 PromoteType = Type::ShortTy;
3586 PromoteOpcode = X86::MOVZX16rr8;
3588 case Type::UShortTyID:
3589 PromoteType = Type::IntTy;
3590 PromoteOpcode = X86::MOVZX32rr16;
3592 case Type::ULongTyID:
3593 case Type::UIntTyID:
3594 // Don't fild into the read destination.
3595 DestReg = makeAnotherReg(Type::DoubleTy);
3597 default: // No promotion needed...
3602 unsigned TmpReg = makeAnotherReg(PromoteType);
3603 BuildMI(*BB, IP, PromoteOpcode, 1, TmpReg).addReg(SrcReg);
3604 SrcTy = PromoteType;
3605 SrcClass = getClass(PromoteType);
3609 // Spill the integer to memory and reload it from there...
3611 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
3613 if (SrcClass == cLong) {
3614 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3615 FrameIdx).addReg(SrcReg);
3616 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3617 FrameIdx, 4).addReg(SrcReg+1);
3619 static const unsigned Op1[] = { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr };
3620 addFrameReference(BuildMI(*BB, IP, Op1[SrcClass], 5),
3621 FrameIdx).addReg(SrcReg);
3624 static const unsigned Op2[] =
3625 { 0/*byte*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m };
3626 addFrameReference(BuildMI(*BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
3628 if (SrcTy == Type::UIntTy) {
3629 // If this is a cast from uint -> double, we need to be careful about if
3630 // the "sign" bit is set. If so, we don't want to make a negative number,
3631 // we want to make a positive number. Emit code to add an offset if the
3634 // Compute whether the sign bit is set by shifting the reg right 31 bits.
3635 unsigned IsNeg = makeAnotherReg(Type::IntTy);
3636 BuildMI(*BB, IP, X86::SHR32ri, 2, IsNeg).addReg(SrcReg).addImm(31);
3638 // Create a CP value that has the offset in one word and 0 in the other.
3639 static ConstantInt *TheOffset = ConstantUInt::get(Type::ULongTy,
3640 0x4f80000000000000ULL);
3641 unsigned CPI = F->getConstantPool()->getConstantPoolIndex(TheOffset);
3642 BuildMI(*BB, IP, X86::FADD32m, 5, RealDestReg).addReg(DestReg)
3643 .addConstantPoolIndex(CPI).addZImm(4).addReg(IsNeg).addSImm(0);
3645 } else if (SrcTy == Type::ULongTy) {
3646 // We need special handling for unsigned 64-bit integer sources. If the
3647 // input number has the "sign bit" set, then we loaded it incorrectly as a
3648 // negative 64-bit number. In this case, add an offset value.
3650 // Emit a test instruction to see if the dynamic input value was signed.
3651 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg+1).addReg(SrcReg+1);
3653 // If the sign bit is set, get a pointer to an offset, otherwise get a
3654 // pointer to a zero.
3655 MachineConstantPool *CP = F->getConstantPool();
3656 unsigned Zero = makeAnotherReg(Type::IntTy);
3657 Constant *Null = Constant::getNullValue(Type::UIntTy);
3658 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
3659 CP->getConstantPoolIndex(Null));
3660 unsigned Offset = makeAnotherReg(Type::IntTy);
3661 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
3663 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset),
3664 CP->getConstantPoolIndex(OffsetCst));
3665 unsigned Addr = makeAnotherReg(Type::IntTy);
3666 BuildMI(*BB, IP, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
3668 // Load the constant for an add. FIXME: this could make an 'fadd' that
3669 // reads directly from memory, but we don't support these yet.
3670 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
3671 addDirectMem(BuildMI(*BB, IP, X86::FLD32m, 4, ConstReg), Addr);
3673 BuildMI(*BB, IP, X86::FpADD, 2, RealDestReg)
3674 .addReg(ConstReg).addReg(DestReg);
3680 // Handle casts from floating point to integer now...
3681 if (SrcClass == cFP) {
3682 // Change the floating point control register to use "round towards zero"
3683 // mode when truncating to an integer value.
3685 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
3686 addFrameReference(BuildMI(*BB, IP, X86::FNSTCW16m, 4), CWFrameIdx);
3688 // Load the old value of the high byte of the control word...
3689 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
3690 addFrameReference(BuildMI(*BB, IP, X86::MOV8rm, 4, HighPartOfCW),
3693 // Set the high part to be round to zero...
3694 addFrameReference(BuildMI(*BB, IP, X86::MOV8mi, 5),
3695 CWFrameIdx, 1).addImm(12);
3697 // Reload the modified control word now...
3698 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3700 // Restore the memory image of control word to original value
3701 addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5),
3702 CWFrameIdx, 1).addReg(HighPartOfCW);
3704 // We don't have the facilities for directly storing byte sized data to
3705 // memory. Promote it to 16 bits. We also must promote unsigned values to
3706 // larger classes because we only have signed FP stores.
3707 unsigned StoreClass = DestClass;
3708 const Type *StoreTy = DestTy;
3709 if (StoreClass == cByte || DestTy->isUnsigned())
3710 switch (StoreClass) {
3711 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
3712 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
3713 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
3714 // The following treatment of cLong may not be perfectly right,
3715 // but it survives chains of casts of the form
3716 // double->ulong->double.
3717 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
3718 default: assert(0 && "Unknown store class!");
3721 // Spill the integer to memory and reload it from there...
3723 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
3725 static const unsigned Op1[] =
3726 { 0, X86::FIST16m, X86::FIST32m, 0, X86::FISTP64m };
3727 addFrameReference(BuildMI(*BB, IP, Op1[StoreClass], 5),
3728 FrameIdx).addReg(SrcReg);
3730 if (DestClass == cLong) {
3731 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg), FrameIdx);
3732 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg+1),
3735 static const unsigned Op2[] = { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm };
3736 addFrameReference(BuildMI(*BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
3739 // Reload the original control word now...
3740 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3744 // Anything we haven't handled already, we can't (yet) handle at all.
3745 assert(0 && "Unhandled cast instruction!");
3749 void X86ISel::visitVAArgInst(VAArgInst &I) {
3750 unsigned VAListPtr = getReg(I.getOperand(0));
3751 unsigned DestReg = getReg(I);
3752 unsigned VAList = makeAnotherReg(Type::IntTy);
3753 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, VAList), VAListPtr);
3755 switch (I.getType()->getTypeID()) {
3758 assert(0 && "Error: bad type for va_next instruction!");
3760 case Type::PointerTyID:
3761 case Type::UIntTyID:
3764 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3766 case Type::ULongTyID:
3767 case Type::LongTyID:
3769 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3770 addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4);
3772 case Type::DoubleTyID:
3774 addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList);
3777 // Increment the VAList pointer...
3778 unsigned NP = makeAnotherReg(Type::IntTy);
3779 BuildMI(BB, X86::ADD32ri, 2, NP).addReg(VAList).addSImm(Size);
3780 addDirectMem(BuildMI(BB, X86::MOV32rm, 5), VAListPtr).addReg(VAList);
3783 /// visitGetElementPtrInst - instruction-select GEP instructions
3785 void X86ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
3786 // If this GEP instruction will be folded into all of its users, we don't need
3787 // to explicitly calculate it!
3789 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), AM)) {
3790 // Check all of the users of the instruction to see if they are loads and
3792 bool AllWillFold = true;
3793 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
3794 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
3795 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
3796 cast<Instruction>(*UI)->getOperand(0) == &I) {
3797 AllWillFold = false;
3801 // If the instruction is foldable, and will be folded into all users, don't
3803 if (AllWillFold) return;
3806 unsigned outputReg = getReg(I);
3807 emitGEPOperation(BB, BB->end(), I.getOperand(0),
3808 I.op_begin()+1, I.op_end(), outputReg);
3811 /// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
3812 /// GEPTypes (the derived types being stepped through at each level). On return
3813 /// from this function, if some indexes of the instruction are representable as
3814 /// an X86 lea instruction, the machine operands are put into the Ops
3815 /// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
3816 /// lists. Otherwise, GEPOps.size() is returned. If this returns a an
3817 /// addressing mode that only partially consumes the input, the BaseReg input of
3818 /// the addressing mode must be left free.
3820 /// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
3822 void X86ISel::getGEPIndex(MachineBasicBlock *MBB,
3823 MachineBasicBlock::iterator IP,
3824 std::vector<Value*> &GEPOps,
3825 std::vector<const Type*> &GEPTypes,
3826 X86AddressMode &AM) {
3827 const TargetData &TD = TM.getTargetData();
3829 // Clear out the state we are working with...
3830 AM.BaseType = X86AddressMode::RegBase;
3831 AM.Base.Reg = 0; // No base register
3832 AM.Scale = 1; // Unit scale
3833 AM.IndexReg = 0; // No index register
3834 AM.Disp = 0; // No displacement
3836 // While there are GEP indexes that can be folded into the current address,
3837 // keep processing them.
3838 while (!GEPTypes.empty()) {
3839 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
3840 // It's a struct access. CUI is the index into the structure,
3841 // which names the field. This index must have unsigned type.
3842 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
3844 // Use the TargetData structure to pick out what the layout of the
3845 // structure is in memory. Since the structure index must be constant, we
3846 // can get its value and use it to find the right byte offset from the
3847 // StructLayout class's list of structure member offsets.
3848 AM.Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
3849 GEPOps.pop_back(); // Consume a GEP operand
3850 GEPTypes.pop_back();
3852 // It's an array or pointer access: [ArraySize x ElementType].
3853 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3854 Value *idx = GEPOps.back();
3856 // idx is the index into the array. Unlike with structure
3857 // indices, we may not know its actual value at code-generation
3860 // If idx is a constant, fold it into the offset.
3861 unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
3862 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
3863 AM.Disp += TypeSize*CSI->getValue();
3864 } else if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(idx)) {
3865 AM.Disp += TypeSize*CUI->getValue();
3867 // If the index reg is already taken, we can't handle this index.
3868 if (AM.IndexReg) return;
3870 // If this is a size that we can handle, then add the index as
3872 case 1: case 2: case 4: case 8:
3873 // These are all acceptable scales on X86.
3874 AM.Scale = TypeSize;
3877 // Otherwise, we can't handle this scale
3881 if (CastInst *CI = dyn_cast<CastInst>(idx))
3882 if (CI->getOperand(0)->getType() == Type::IntTy ||
3883 CI->getOperand(0)->getType() == Type::UIntTy)
3884 idx = CI->getOperand(0);
3886 AM.IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
3889 GEPOps.pop_back(); // Consume a GEP operand
3890 GEPTypes.pop_back();
3894 // GEPTypes is empty, which means we have a single operand left. Set it as
3895 // the base register.
3897 assert(AM.Base.Reg == 0);
3899 if (AllocaInst *AI = dyn_castFixedAlloca(GEPOps.back())) {
3900 AM.BaseType = X86AddressMode::FrameIndexBase;
3901 AM.Base.FrameIndex = getFixedSizedAllocaFI(AI);
3906 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps.back())) {
3912 AM.Base.Reg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
3913 GEPOps.pop_back(); // Consume the last GEP operand
3917 /// isGEPFoldable - Return true if the specified GEP can be completely
3918 /// folded into the addressing mode of a load/store or lea instruction.
3919 bool X86ISel::isGEPFoldable(MachineBasicBlock *MBB,
3920 Value *Src, User::op_iterator IdxBegin,
3921 User::op_iterator IdxEnd, X86AddressMode &AM) {
3923 std::vector<Value*> GEPOps;
3924 GEPOps.resize(IdxEnd-IdxBegin+1);
3926 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3928 std::vector<const Type*>
3929 GEPTypes(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3930 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3932 MachineBasicBlock::iterator IP;
3933 if (MBB) IP = MBB->end();
3934 getGEPIndex(MBB, IP, GEPOps, GEPTypes, AM);
3936 // We can fold it away iff the getGEPIndex call eliminated all operands.
3937 return GEPOps.empty();
3940 void X86ISel::emitGEPOperation(MachineBasicBlock *MBB,
3941 MachineBasicBlock::iterator IP,
3942 Value *Src, User::op_iterator IdxBegin,
3943 User::op_iterator IdxEnd, unsigned TargetReg) {
3944 const TargetData &TD = TM.getTargetData();
3946 // If this is a getelementptr null, with all constant integer indices, just
3947 // replace it with TargetReg = 42.
3948 if (isa<ConstantPointerNull>(Src)) {
3949 User::op_iterator I = IdxBegin;
3950 for (; I != IdxEnd; ++I)
3951 if (!isa<ConstantInt>(*I))
3953 if (I == IdxEnd) { // All constant indices
3954 unsigned Offset = TD.getIndexedOffset(Src->getType(),
3955 std::vector<Value*>(IdxBegin, IdxEnd));
3956 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addImm(Offset);
3961 std::vector<Value*> GEPOps;
3962 GEPOps.resize(IdxEnd-IdxBegin+1);
3964 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3966 std::vector<const Type*> GEPTypes;
3967 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3968 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3970 // Keep emitting instructions until we consume the entire GEP instruction.
3971 while (!GEPOps.empty()) {
3972 unsigned OldSize = GEPOps.size();
3974 getGEPIndex(MBB, IP, GEPOps, GEPTypes, AM);
3976 if (GEPOps.size() != OldSize) {
3977 // getGEPIndex consumed some of the input. Build an LEA instruction here.
3978 unsigned NextTarget = 0;
3979 if (!GEPOps.empty()) {
3980 assert(AM.Base.Reg == 0 &&
3981 "getGEPIndex should have left the base register open for chaining!");
3982 NextTarget = AM.Base.Reg = makeAnotherReg(Type::UIntTy);
3985 if (AM.BaseType == X86AddressMode::RegBase &&
3986 AM.IndexReg == 0 && AM.Disp == 0 && !AM.GV)
3987 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(AM.Base.Reg);
3988 else if (AM.BaseType == X86AddressMode::RegBase && AM.Base.Reg == 0 &&
3989 AM.IndexReg == 0 && AM.Disp == 0)
3990 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(AM.GV);
3992 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg), AM);
3994 TargetReg = NextTarget;
3995 } else if (GEPTypes.empty()) {
3996 // The getGEPIndex operation didn't want to build an LEA. Check to see if
3997 // all operands are consumed but the base pointer. If so, just load it
3998 // into the register.
3999 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
4000 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(GV);
4002 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
4003 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
4005 break; // we are now done
4008 // It's an array or pointer access: [ArraySize x ElementType].
4009 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
4010 Value *idx = GEPOps.back();
4011 GEPOps.pop_back(); // Consume a GEP operand
4012 GEPTypes.pop_back();
4014 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
4015 // operand on X86. Handle this case directly now...
4016 if (CastInst *CI = dyn_cast<CastInst>(idx))
4017 if (CI->getOperand(0)->getType() == Type::IntTy ||
4018 CI->getOperand(0)->getType() == Type::UIntTy)
4019 idx = CI->getOperand(0);
4021 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
4022 // must find the size of the pointed-to type (Not coincidentally, the next
4023 // type is the type of the elements in the array).
4024 const Type *ElTy = SqTy->getElementType();
4025 unsigned elementSize = TD.getTypeSize(ElTy);
4027 // If idxReg is a constant, we don't need to perform the multiply!
4028 if (ConstantInt *CSI = dyn_cast<ConstantInt>(idx)) {
4029 if (!CSI->isNullValue()) {
4030 unsigned Offset = elementSize*CSI->getRawValue();
4031 unsigned Reg = makeAnotherReg(Type::UIntTy);
4032 BuildMI(*MBB, IP, X86::ADD32ri, 2, TargetReg)
4033 .addReg(Reg).addImm(Offset);
4034 --IP; // Insert the next instruction before this one.
4035 TargetReg = Reg; // Codegen the rest of the GEP into this
4037 } else if (elementSize == 1) {
4038 // If the element size is 1, we don't have to multiply, just add
4039 unsigned idxReg = getReg(idx, MBB, IP);
4040 unsigned Reg = makeAnotherReg(Type::UIntTy);
4041 BuildMI(*MBB, IP, X86::ADD32rr, 2,TargetReg).addReg(Reg).addReg(idxReg);
4042 --IP; // Insert the next instruction before this one.
4043 TargetReg = Reg; // Codegen the rest of the GEP into this
4045 unsigned idxReg = getReg(idx, MBB, IP);
4046 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
4048 // Make sure we can back the iterator up to point to the first
4049 // instruction emitted.
4050 MachineBasicBlock::iterator BeforeIt = IP;
4051 if (IP == MBB->begin())
4052 BeforeIt = MBB->end();
4055 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
4057 // Emit an ADD to add OffsetReg to the basePtr.
4058 unsigned Reg = makeAnotherReg(Type::UIntTy);
4059 BuildMI(*MBB, IP, X86::ADD32rr, 2, TargetReg)
4060 .addReg(Reg).addReg(OffsetReg);
4062 // Step to the first instruction of the multiply.
4063 if (BeforeIt == MBB->end())
4068 TargetReg = Reg; // Codegen the rest of the GEP into this
4074 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
4075 /// frame manager, otherwise do it the hard way.
4077 void X86ISel::visitAllocaInst(AllocaInst &I) {
4078 // If this is a fixed size alloca in the entry block for the function, we
4079 // statically stack allocate the space, so we don't need to do anything here.
4081 if (dyn_castFixedAlloca(&I)) return;
4083 // Find the data size of the alloca inst's getAllocatedType.
4084 const Type *Ty = I.getAllocatedType();
4085 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
4087 // Create a register to hold the temporary result of multiplying the type size
4088 // constant by the variable amount.
4089 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
4090 unsigned SrcReg1 = getReg(I.getArraySize());
4092 // TotalSizeReg = mul <numelements>, <TypeSize>
4093 MachineBasicBlock::iterator MBBI = BB->end();
4094 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
4096 // AddedSize = add <TotalSizeReg>, 15
4097 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
4098 BuildMI(BB, X86::ADD32ri, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
4100 // AlignedSize = and <AddedSize>, ~15
4101 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
4102 BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15);
4104 // Subtract size from stack pointer, thereby allocating some space.
4105 BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
4107 // Put a pointer to the space into the result register, by copying
4108 // the stack pointer.
4109 BuildMI(BB, X86::MOV32rr, 1, getReg(I)).addReg(X86::ESP);
4111 // Inform the Frame Information that we have just allocated a variable-sized
4113 F->getFrameInfo()->CreateVariableSizedObject();
4116 /// visitMallocInst - Malloc instructions are code generated into direct calls
4117 /// to the library malloc.
4119 void X86ISel::visitMallocInst(MallocInst &I) {
4120 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
4123 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
4124 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
4126 Arg = makeAnotherReg(Type::UIntTy);
4127 unsigned Op0Reg = getReg(I.getOperand(0));
4128 MachineBasicBlock::iterator MBBI = BB->end();
4129 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
4132 std::vector<ValueRecord> Args;
4133 Args.push_back(ValueRecord(Arg, Type::UIntTy));
4134 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
4135 1).addExternalSymbol("malloc", true);
4136 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
4140 /// visitFreeInst - Free instructions are code gen'd to call the free libc
4143 void X86ISel::visitFreeInst(FreeInst &I) {
4144 std::vector<ValueRecord> Args;
4145 Args.push_back(ValueRecord(I.getOperand(0)));
4146 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
4147 1).addExternalSymbol("free", true);
4148 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
4151 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
4152 /// into a machine code representation is a very simple peep-hole fashion. The
4153 /// generated code sucks but the implementation is nice and simple.
4155 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
4156 return new X86ISel(TM);