1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 target
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/Instructions.h"
12 #include "llvm/DerivedTypes.h"
13 #include "llvm/Constants.h"
14 #include "llvm/Pass.h"
15 #include "llvm/Intrinsics.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/SSARegMap.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/InstVisitor.h"
25 /// BMI - A special BuildMI variant that takes an iterator to insert the
26 /// instruction at as well as a basic block. This is the version for when you
27 /// have a destination register in mind.
28 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
29 MachineBasicBlock::iterator &I,
30 int Opcode, unsigned NumOperands,
32 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
33 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
34 I = MBB->insert(I, MI)+1;
35 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
38 /// BMI - A special BuildMI variant that takes an iterator to insert the
39 /// instruction at as well as a basic block.
40 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
41 MachineBasicBlock::iterator &I,
42 int Opcode, unsigned NumOperands) {
43 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
44 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
45 I = MBB->insert(I, MI)+1;
46 return MachineInstrBuilder(MI);
51 struct ISel : public FunctionPass, InstVisitor<ISel> {
53 MachineFunction *F; // The function we are compiling into
54 MachineBasicBlock *BB; // The current MBB we are compiling
55 int VarArgsFrameIndex; // FrameIndex for start of varargs area
57 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
59 // MBBMap - Mapping between LLVM BB -> Machine BB
60 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
62 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
64 /// runOnFunction - Top level implementation of instruction selection for
65 /// the entire function.
67 bool runOnFunction(Function &Fn) {
68 F = &MachineFunction::construct(&Fn, TM);
70 // Create all of the machine basic blocks for the function...
71 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
72 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
76 // Copy incoming arguments off of the stack...
77 LoadArgumentsToVirtualRegs(Fn);
79 // Instruction select everything except PHI nodes
82 // Select the PHI nodes
88 return false; // We never modify the LLVM itself.
91 virtual const char *getPassName() const {
92 return "X86 Simple Instruction Selection";
95 /// visitBasicBlock - This method is called when we are visiting a new basic
96 /// block. This simply creates a new MachineBasicBlock to emit code into
97 /// and adds it to the current MachineFunction. Subsequent visit* for
98 /// instructions will be invoked for all instructions in the basic block.
100 void visitBasicBlock(BasicBlock &LLVM_BB) {
101 BB = MBBMap[&LLVM_BB];
104 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
105 /// from the stack into virtual registers.
107 void LoadArgumentsToVirtualRegs(Function &F);
109 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
110 /// because we have to generate our sources into the source basic blocks,
111 /// not the current one.
113 void SelectPHINodes();
115 // Visitation methods for various instructions. These methods simply emit
116 // fixed X86 code for each instruction.
119 // Control flow operators
120 void visitReturnInst(ReturnInst &RI);
121 void visitBranchInst(BranchInst &BI);
126 ValueRecord(unsigned R, const Type *T) : Reg(R), Ty(T) {}
128 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
129 const std::vector<ValueRecord> &Args);
130 void visitCallInst(CallInst &I);
131 void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
133 // Arithmetic operators
134 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
135 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
136 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
137 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
138 unsigned DestReg, const Type *DestTy,
139 unsigned Op0Reg, unsigned Op1Reg);
140 void visitMul(BinaryOperator &B);
142 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
143 void visitRem(BinaryOperator &B) { visitDivRem(B); }
144 void visitDivRem(BinaryOperator &B);
147 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
148 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
149 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
151 // Comparison operators...
152 void visitSetCondInst(SetCondInst &I);
153 bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
155 // Memory Instructions
156 MachineInstr *doFPLoad(MachineBasicBlock *MBB,
157 MachineBasicBlock::iterator &MBBI,
158 const Type *Ty, unsigned DestReg);
159 void visitLoadInst(LoadInst &I);
160 void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg);
161 void visitStoreInst(StoreInst &I);
162 void visitGetElementPtrInst(GetElementPtrInst &I);
163 void visitAllocaInst(AllocaInst &I);
164 void visitMallocInst(MallocInst &I);
165 void visitFreeInst(FreeInst &I);
168 void visitShiftInst(ShiftInst &I);
169 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
170 void visitCastInst(CastInst &I);
171 void visitVarArgInst(VarArgInst &I);
173 void visitInstruction(Instruction &I) {
174 std::cerr << "Cannot instruction select: " << I;
178 /// promote32 - Make a value 32-bits wide, and put it somewhere.
180 void promote32(unsigned targetReg, const ValueRecord &VR);
182 /// EmitByteSwap - Byteswap SrcReg into DestReg.
184 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
186 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
187 /// constant expression GEP support.
189 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
190 Value *Src, User::op_iterator IdxBegin,
191 User::op_iterator IdxEnd, unsigned TargetReg);
193 /// emitCastOperation - Common code shared between visitCastInst and
194 /// constant expression cast support.
195 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
196 Value *Src, const Type *DestTy, unsigned TargetReg);
198 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
199 /// and constant expression support.
200 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
201 MachineBasicBlock::iterator &IP,
202 Value *Op0, Value *Op1,
203 unsigned OperatorClass, unsigned TargetReg);
205 /// copyConstantToRegister - Output the instructions required to put the
206 /// specified constant into the specified register.
208 void copyConstantToRegister(MachineBasicBlock *MBB,
209 MachineBasicBlock::iterator &MBBI,
210 Constant *C, unsigned Reg);
212 /// makeAnotherReg - This method returns the next register number we haven't
215 /// Long values are handled somewhat specially. They are always allocated
216 /// as pairs of 32 bit integer values. The register number returned is the
217 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
218 /// of the long value.
220 unsigned makeAnotherReg(const Type *Ty) {
221 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
222 const TargetRegisterClass *RC =
223 TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
224 // Create the lower part
225 F->getSSARegMap()->createVirtualRegister(RC);
226 // Create the upper part.
227 return F->getSSARegMap()->createVirtualRegister(RC)-1;
230 // Add the mapping of regnumber => reg class to MachineFunction
231 const TargetRegisterClass *RC =
232 TM.getRegisterInfo()->getRegClassForType(Ty);
233 return F->getSSARegMap()->createVirtualRegister(RC);
236 /// getReg - This method turns an LLVM value into a register number. This
237 /// is guaranteed to produce the same register number for a particular value
238 /// every time it is queried.
240 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
241 unsigned getReg(Value *V) {
242 // Just append to the end of the current bb.
243 MachineBasicBlock::iterator It = BB->end();
244 return getReg(V, BB, It);
246 unsigned getReg(Value *V, MachineBasicBlock *MBB,
247 MachineBasicBlock::iterator &IPt) {
248 unsigned &Reg = RegMap[V];
250 Reg = makeAnotherReg(V->getType());
254 // If this operand is a constant, emit the code to copy the constant into
255 // the register here...
257 if (Constant *C = dyn_cast<Constant>(V)) {
258 copyConstantToRegister(MBB, IPt, C, Reg);
259 RegMap.erase(V); // Assign a new name to this constant if ref'd again
260 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
261 // Move the address of the global into the register
262 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
263 RegMap.erase(V); // Assign a new name to this address if ref'd again
271 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
275 cByte, cShort, cInt, cFP, cLong
278 /// getClass - Turn a primitive type into a "class" number which is based on the
279 /// size of the type, and whether or not it is floating point.
281 static inline TypeClass getClass(const Type *Ty) {
282 switch (Ty->getPrimitiveID()) {
283 case Type::SByteTyID:
284 case Type::UByteTyID: return cByte; // Byte operands are class #0
285 case Type::ShortTyID:
286 case Type::UShortTyID: return cShort; // Short operands are class #1
289 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
291 case Type::FloatTyID:
292 case Type::DoubleTyID: return cFP; // Floating Point is #3
295 case Type::ULongTyID: return cLong; // Longs are class #4
297 assert(0 && "Invalid type to getClass!");
298 return cByte; // not reached
302 // getClassB - Just like getClass, but treat boolean values as bytes.
303 static inline TypeClass getClassB(const Type *Ty) {
304 if (Ty == Type::BoolTy) return cByte;
309 /// copyConstantToRegister - Output the instructions required to put the
310 /// specified constant into the specified register.
312 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
313 MachineBasicBlock::iterator &IP,
314 Constant *C, unsigned R) {
315 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
317 switch (CE->getOpcode()) {
318 case Instruction::GetElementPtr:
319 emitGEPOperation(MBB, IP, CE->getOperand(0),
320 CE->op_begin()+1, CE->op_end(), R);
322 case Instruction::Cast:
323 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
326 case Instruction::Xor: ++Class; // FALL THROUGH
327 case Instruction::Or: ++Class; // FALL THROUGH
328 case Instruction::And: ++Class; // FALL THROUGH
329 case Instruction::Sub: ++Class; // FALL THROUGH
330 case Instruction::Add:
331 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
336 std::cerr << "Offending expr: " << C << "\n";
337 assert(0 && "Constant expressions not yet handled!\n");
341 if (C->getType()->isIntegral()) {
342 unsigned Class = getClassB(C->getType());
344 if (Class == cLong) {
345 // Copy the value into the register pair.
347 if (C->getType()->isSigned())
348 Val = cast<ConstantSInt>(C)->getValue();
350 Val = cast<ConstantUInt>(C)->getValue();
352 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
353 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
357 assert(Class <= cInt && "Type not handled yet!");
359 static const unsigned IntegralOpcodeTab[] = {
360 X86::MOVir8, X86::MOVir16, X86::MOVir32
363 if (C->getType() == Type::BoolTy) {
364 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
365 } else if (C->getType()->isSigned()) {
366 ConstantSInt *CSI = cast<ConstantSInt>(C);
367 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CSI->getValue());
369 ConstantUInt *CUI = cast<ConstantUInt>(C);
370 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
372 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
373 double Value = CFP->getValue();
375 BMI(MBB, IP, X86::FLD0, 0, R);
376 else if (Value == +1.0)
377 BMI(MBB, IP, X86::FLD1, 0, R);
379 // Otherwise we need to spill the constant to memory...
380 MachineConstantPool *CP = F->getConstantPool();
381 unsigned CPI = CP->getConstantPoolIndex(CFP);
382 addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI);
385 } else if (isa<ConstantPointerNull>(C)) {
386 // Copy zero (null pointer) to the register.
387 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
388 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
389 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
390 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
392 std::cerr << "Offending constant: " << C << "\n";
393 assert(0 && "Type not handled yet!");
397 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
398 /// the stack into virtual registers.
400 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
401 // Emit instructions to load the arguments... On entry to a function on the
402 // X86, the stack frame looks like this:
404 // [ESP] -- return address
405 // [ESP + 4] -- first argument (leftmost lexically)
406 // [ESP + 8] -- second argument, if first argument is four bytes in size
409 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
410 MachineFrameInfo *MFI = F->getFrameInfo();
412 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
413 unsigned Reg = getReg(*I);
415 int FI; // Frame object index
416 switch (getClassB(I->getType())) {
418 FI = MFI->CreateFixedObject(1, ArgOffset);
419 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
422 FI = MFI->CreateFixedObject(2, ArgOffset);
423 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
426 FI = MFI->CreateFixedObject(4, ArgOffset);
427 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
430 FI = MFI->CreateFixedObject(8, ArgOffset);
431 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
432 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
433 ArgOffset += 4; // longs require 4 additional bytes
437 if (I->getType() == Type::FloatTy) {
438 Opcode = X86::FLDr32;
439 FI = MFI->CreateFixedObject(4, ArgOffset);
441 Opcode = X86::FLDr64;
442 FI = MFI->CreateFixedObject(8, ArgOffset);
443 ArgOffset += 4; // doubles require 4 additional bytes
445 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
448 assert(0 && "Unhandled argument type!");
450 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
453 // If the function takes variable number of arguments, add a frame offset for
454 // the start of the first vararg value... this is used to expand
456 if (Fn.getFunctionType()->isVarArg())
457 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
461 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
462 /// because we have to generate our sources into the source basic blocks, not
465 void ISel::SelectPHINodes() {
466 const TargetInstrInfo &TII = TM.getInstrInfo();
467 const Function &LF = *F->getFunction(); // The LLVM function...
468 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
469 const BasicBlock *BB = I;
470 MachineBasicBlock *MBB = MBBMap[I];
472 // Loop over all of the PHI nodes in the LLVM basic block...
473 unsigned NumPHIs = 0;
474 for (BasicBlock::const_iterator I = BB->begin();
475 PHINode *PN = (PHINode*)dyn_cast<PHINode>(I); ++I) {
477 // Create a new machine instr PHI node, and insert it.
478 unsigned PHIReg = getReg(*PN);
479 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
480 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
482 MachineInstr *LongPhiMI = 0;
483 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
484 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
485 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
488 // PHIValues - Map of blocks to incoming virtual registers. We use this
489 // so that we only initialize one incoming value for a particular block,
490 // even if the block has multiple entries in the PHI node.
492 std::map<MachineBasicBlock*, unsigned> PHIValues;
494 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
495 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
497 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
498 PHIValues.lower_bound(PredMBB);
500 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
501 // We already inserted an initialization of the register for this
502 // predecessor. Recycle it.
503 ValReg = EntryIt->second;
506 // Get the incoming value into a virtual register. If it is not
507 // already available in a virtual register, insert the computation
510 MachineBasicBlock::iterator PI = PredMBB->end();
511 while (PI != PredMBB->begin() &&
512 TII.isTerminatorInstr((*(PI-1))->getOpcode()))
514 ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
516 // Remember that we inserted a value for this PHI for this predecessor
517 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
520 PhiMI->addRegOperand(ValReg);
521 PhiMI->addMachineBasicBlockOperand(PredMBB);
523 LongPhiMI->addRegOperand(ValReg+1);
524 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
531 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
532 // the conditional branch instruction which is the only user of the cc
533 // instruction. This is the case if the conditional branch is the only user of
534 // the setcc, and if the setcc is in the same basic block as the conditional
535 // branch. We also don't handle long arguments below, so we reject them here as
538 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
539 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
540 if (SCI->use_size() == 1 && isa<BranchInst>(SCI->use_back()) &&
541 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
542 const Type *Ty = SCI->getOperand(0)->getType();
543 if (Ty != Type::LongTy && Ty != Type::ULongTy)
549 // Return a fixed numbering for setcc instructions which does not depend on the
550 // order of the opcodes.
552 static unsigned getSetCCNumber(unsigned Opcode) {
554 default: assert(0 && "Unknown setcc instruction!");
555 case Instruction::SetEQ: return 0;
556 case Instruction::SetNE: return 1;
557 case Instruction::SetLT: return 2;
558 case Instruction::SetGE: return 3;
559 case Instruction::SetGT: return 4;
560 case Instruction::SetLE: return 5;
564 // LLVM -> X86 signed X86 unsigned
565 // ----- ---------- ------------
566 // seteq -> sete sete
567 // setne -> setne setne
568 // setlt -> setl setb
569 // setge -> setge setae
570 // setgt -> setg seta
571 // setle -> setle setbe
572 static const unsigned SetCCOpcodeTab[2][6] = {
573 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
574 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
577 bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
579 // The arguments are already supposed to be of the same type.
580 const Type *CompTy = Op0->getType();
581 bool isSigned = CompTy->isSigned();
582 unsigned reg1 = getReg(Op0);
583 unsigned reg2 = getReg(Op1);
585 unsigned Class = getClassB(CompTy);
587 default: assert(0 && "Unknown type class!");
588 // Emit: cmp <var1>, <var2> (do the comparison). We can
589 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
592 BuildMI(BB, X86::CMPrr8, 2).addReg(reg1).addReg(reg2);
595 BuildMI(BB, X86::CMPrr16, 2).addReg(reg1).addReg(reg2);
598 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
601 BuildMI(BB, X86::FpUCOM, 2).addReg(reg1).addReg(reg2);
602 BuildMI(BB, X86::FNSTSWr8, 0);
603 BuildMI(BB, X86::SAHF, 1);
604 isSigned = false; // Compare with unsigned operators
608 if (OpNum < 2) { // seteq, setne
609 unsigned LoTmp = makeAnotherReg(Type::IntTy);
610 unsigned HiTmp = makeAnotherReg(Type::IntTy);
611 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
612 BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(reg1).addReg(reg2);
613 BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(reg1+1).addReg(reg2+1);
614 BuildMI(BB, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
615 break; // Allow the sete or setne to be generated from flags set by OR
617 // Emit a sequence of code which compares the high and low parts once
618 // each, then uses a conditional move to handle the overflow case. For
619 // example, a setlt for long would generate code like this:
621 // AL = lo(op1) < lo(op2) // Signedness depends on operands
622 // BL = hi(op1) < hi(op2) // Always unsigned comparison
623 // dest = hi(op1) == hi(op2) ? AL : BL;
626 // FIXME: This would be much better if we had hierarchical register
627 // classes! Until then, hardcode registers so that we can deal with their
628 // aliases (because we don't have conditional byte moves).
630 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
631 BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
632 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1+1).addReg(reg2+1);
633 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
634 BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
635 // NOTE: visitSetCondInst knows that the value is dumped into the BL
636 // register at this point for long values...
644 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
645 /// register, then move it to wherever the result should be.
647 void ISel::visitSetCondInst(SetCondInst &I) {
648 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
650 unsigned OpNum = getSetCCNumber(I.getOpcode());
651 unsigned DestReg = getReg(I);
652 bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
655 if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
656 // Handle normal comparisons with a setcc instruction...
657 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
659 // Handle long comparisons by copying the value which is already in BL into
660 // the register we want...
661 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
665 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
666 /// operand, in the specified target register.
667 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
668 bool isUnsigned = VR.Ty->isUnsigned();
669 switch (getClassB(VR.Ty)) {
671 // Extend value into target register (8->32)
673 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(VR.Reg);
675 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(VR.Reg);
678 // Extend value into target register (16->32)
680 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(VR.Reg);
682 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(VR.Reg);
685 // Move value into target register (32->32)
686 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(VR.Reg);
689 assert(0 && "Unpromotable operand class in promote32");
693 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
694 /// we have the following possibilities:
696 /// ret void: No return value, simply emit a 'ret' instruction
697 /// ret sbyte, ubyte : Extend value into EAX and return
698 /// ret short, ushort: Extend value into EAX and return
699 /// ret int, uint : Move value into EAX and return
700 /// ret pointer : Move value into EAX and return
701 /// ret long, ulong : Move value into EAX/EDX and return
702 /// ret float/double : Top of FP stack
704 void ISel::visitReturnInst(ReturnInst &I) {
705 if (I.getNumOperands() == 0) {
706 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
710 Value *RetVal = I.getOperand(0);
711 unsigned RetReg = getReg(RetVal);
712 switch (getClassB(RetVal->getType())) {
713 case cByte: // integral return values: extend or move into EAX and return
716 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
717 // Declare that EAX is live on exit
718 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
720 case cFP: // Floats & Doubles: Return in ST(0)
721 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
722 // Declare that top-of-stack is live on exit
723 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
726 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
727 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
728 // Declare that EAX & EDX are live on exit
729 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP);
734 // Emit a 'ret' instruction
735 BuildMI(BB, X86::RET, 0);
738 // getBlockAfter - Return the basic block which occurs lexically after the
740 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
741 Function::iterator I = BB; ++I; // Get iterator to next block
742 return I != BB->getParent()->end() ? &*I : 0;
745 /// visitBranchInst - Handle conditional and unconditional branches here. Note
746 /// that since code layout is frozen at this point, that if we are trying to
747 /// jump to a block that is the immediate successor of the current block, we can
748 /// just make a fall-through (but we don't currently).
750 void ISel::visitBranchInst(BranchInst &BI) {
751 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
753 if (!BI.isConditional()) { // Unconditional branch?
754 if (BI.getSuccessor(0) != NextBB)
755 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
759 // See if we can fold the setcc into the branch itself...
760 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
762 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
763 // computed some other way...
764 unsigned condReg = getReg(BI.getCondition());
765 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
766 if (BI.getSuccessor(1) == NextBB) {
767 if (BI.getSuccessor(0) != NextBB)
768 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
770 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
772 if (BI.getSuccessor(0) != NextBB)
773 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
778 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
779 bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
782 // LLVM -> X86 signed X86 unsigned
783 // ----- ---------- ------------
790 static const unsigned OpcodeTab[2][6] = {
791 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
792 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
795 if (BI.getSuccessor(0) != NextBB) {
796 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
797 if (BI.getSuccessor(1) != NextBB)
798 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
800 // Change to the inverse condition...
801 if (BI.getSuccessor(1) != NextBB) {
803 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
809 /// doCall - This emits an abstract call instruction, setting up the arguments
810 /// and the return value as appropriate. For the actual function call itself,
811 /// it inserts the specified CallMI instruction into the stream.
813 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
814 const std::vector<ValueRecord> &Args) {
816 // Count how many bytes are to be pushed on the stack...
817 unsigned NumBytes = 0;
820 for (unsigned i = 0, e = Args.size(); i != e; ++i)
821 switch (getClassB(Args[i].Ty)) {
822 case cByte: case cShort: case cInt:
823 NumBytes += 4; break;
825 NumBytes += 8; break;
827 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
829 default: assert(0 && "Unknown class!");
832 // Adjust the stack pointer for the new arguments...
833 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
835 // Arguments go on the stack in reverse order, as specified by the ABI.
836 unsigned ArgOffset = 0;
837 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
838 unsigned ArgReg = Args[i].Reg;
839 switch (getClassB(Args[i].Ty)) {
842 // Promote arg to 32 bits wide into a temporary register...
843 unsigned R = makeAnotherReg(Type::UIntTy);
844 promote32(R, Args[i]);
845 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
846 X86::ESP, ArgOffset).addReg(R);
850 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
851 X86::ESP, ArgOffset).addReg(ArgReg);
854 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
855 X86::ESP, ArgOffset).addReg(ArgReg);
856 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
857 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
858 ArgOffset += 4; // 8 byte entry, not 4.
862 if (Args[i].Ty == Type::FloatTy) {
863 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
864 X86::ESP, ArgOffset).addReg(ArgReg);
866 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
867 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
868 X86::ESP, ArgOffset).addReg(ArgReg);
869 ArgOffset += 4; // 8 byte entry, not 4.
873 default: assert(0 && "Unknown class!");
878 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
881 BB->push_back(CallMI);
883 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
885 // If there is a return value, scavenge the result from the location the call
888 if (Ret.Ty != Type::VoidTy) {
889 unsigned DestClass = getClassB(Ret.Ty);
894 // Integral results are in %eax, or the appropriate portion
896 static const unsigned regRegMove[] = {
897 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
899 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
900 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
903 case cFP: // Floating-point return values live in %ST(0)
904 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
906 case cLong: // Long values are left in EDX:EAX
907 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
908 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
910 default: assert(0 && "Unknown class!");
916 /// visitCallInst - Push args on stack and do a procedure call instruction.
917 void ISel::visitCallInst(CallInst &CI) {
918 MachineInstr *TheCall;
919 if (Function *F = CI.getCalledFunction()) {
920 // Is it an intrinsic function call?
921 if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
922 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
926 // Emit a CALL instruction with PC-relative displacement.
927 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
928 } else { // Emit an indirect call...
929 unsigned Reg = getReg(CI.getCalledValue());
930 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
933 std::vector<ValueRecord> Args;
934 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
935 Args.push_back(ValueRecord(getReg(CI.getOperand(i)),
936 CI.getOperand(i)->getType()));
938 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
939 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
942 void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
943 unsigned TmpReg1, TmpReg2;
945 case LLVMIntrinsic::va_start:
946 // Get the address of the first vararg value...
947 TmpReg1 = makeAnotherReg(Type::UIntTy);
948 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
949 TmpReg2 = getReg(CI.getOperand(1));
950 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
953 case LLVMIntrinsic::va_end: return; // Noop on X86
954 case LLVMIntrinsic::va_copy:
955 TmpReg1 = getReg(CI.getOperand(2)); // Get existing va_list
956 TmpReg2 = getReg(CI.getOperand(1)); // Get va_list* to store into
957 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
960 default: assert(0 && "Unknown intrinsic for X86!");
965 /// visitSimpleBinary - Implement simple binary operators for integral types...
966 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
968 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
969 unsigned DestReg = getReg(B);
970 MachineBasicBlock::iterator MI = BB->end();
971 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
972 OperatorClass, DestReg);
975 /// visitSimpleBinary - Implement simple binary operators for integral types...
976 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
979 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
980 /// and constant expression support.
981 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
982 MachineBasicBlock::iterator &IP,
983 Value *Op0, Value *Op1,
984 unsigned OperatorClass,unsigned TargetReg){
985 unsigned Class = getClassB(Op0->getType());
986 if (!isa<ConstantInt>(Op1) || Class == cLong) {
987 static const unsigned OpcodeTab[][4] = {
988 // Arithmetic operators
989 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
990 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
993 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
994 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
995 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
999 if (Class == cLong) {
1001 Class = cInt; // Bottom 32 bits are handled just like ints
1004 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1005 assert(Opcode && "Floating point arguments to logical inst?");
1006 unsigned Op0r = getReg(Op0, BB, IP);
1007 unsigned Op1r = getReg(Op1, BB, IP);
1008 BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
1010 if (isLong) { // Handle the upper 32 bits of long values...
1011 static const unsigned TopTab[] = {
1012 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1014 BMI(BB, IP, TopTab[OperatorClass], 2,
1015 TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
1018 // Special case: op Reg, <const>
1019 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1021 static const unsigned OpcodeTab[][3] = {
1022 // Arithmetic operators
1023 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1024 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1026 // Bitwise operators
1027 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1028 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1029 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1032 assert(Class < 3 && "General code handles 64-bit integer types!");
1033 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1034 unsigned Op0r = getReg(Op0, BB, IP);
1036 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(Op1C))
1037 Op1v = CSI->getValue();
1039 Op1v = cast<ConstantUInt>(Op1C)->getValue();
1041 // Mask off any upper bits of the constant, if there are any...
1042 Op1v &= (1ULL << (8 << Class)) - 1;
1043 BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
1047 /// doMultiply - Emit appropriate instructions to multiply together the
1048 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1049 /// result should be given as DestTy.
1051 /// FIXME: doMultiply should use one of the two address IMUL instructions!
1053 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1054 unsigned DestReg, const Type *DestTy,
1055 unsigned op0Reg, unsigned op1Reg) {
1056 unsigned Class = getClass(DestTy);
1058 case cFP: // Floating point multiply
1059 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1062 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1065 case cInt: // Small integerals, handled below...
1069 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1070 static const unsigned MulOpcode[]={ X86::MULr8 , X86::MULr16 , X86::MULr32 };
1071 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1072 unsigned Reg = Regs[Class];
1074 // Emit a MOV to put the first operand into the appropriately-sized
1076 BMI(MBB, MBBI, MovOpcode[Class], 1, Reg).addReg(op0Reg);
1078 // Emit the appropriate multiply instruction.
1079 BMI(MBB, MBBI, MulOpcode[Class], 1).addReg(op1Reg);
1081 // Emit another MOV to put the result into the destination register.
1082 BMI(MBB, MBBI, MovOpcode[Class], 1, DestReg).addReg(Reg);
1085 /// visitMul - Multiplies are not simple binary operators because they must deal
1086 /// with the EAX register explicitly.
1088 void ISel::visitMul(BinaryOperator &I) {
1089 unsigned Op0Reg = getReg(I.getOperand(0));
1090 unsigned Op1Reg = getReg(I.getOperand(1));
1091 unsigned DestReg = getReg(I);
1093 // Simple scalar multiply?
1094 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1095 MachineBasicBlock::iterator MBBI = BB->end();
1096 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1098 // Long value. We have to do things the hard way...
1099 // Multiply the two low parts... capturing carry into EDX
1100 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1101 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1103 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1104 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1105 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1107 MachineBasicBlock::iterator MBBI = BB->end();
1108 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1109 doMultiply(BB, MBBI, AHBLReg, Type::UIntTy, Op0Reg+1, Op1Reg); // AH*BL
1111 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1112 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1113 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1116 unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
1117 doMultiply(BB, MBBI, ALBHReg, Type::UIntTy, Op0Reg, Op1Reg+1); // AL*BH
1119 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1120 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1125 /// visitDivRem - Handle division and remainder instructions... these
1126 /// instruction both require the same instructions to be generated, they just
1127 /// select the result from a different register. Note that both of these
1128 /// instructions work differently for signed and unsigned operands.
1130 void ISel::visitDivRem(BinaryOperator &I) {
1131 unsigned Class = getClass(I.getType());
1132 unsigned Op0Reg = getReg(I.getOperand(0));
1133 unsigned Op1Reg = getReg(I.getOperand(1));
1134 unsigned ResultReg = getReg(I);
1137 case cFP: // Floating point divide
1138 if (I.getOpcode() == Instruction::Div)
1139 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1140 else { // Floating point remainder...
1141 MachineInstr *TheCall =
1142 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1143 std::vector<ValueRecord> Args;
1144 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1145 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1146 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1150 static const char *FnName[] =
1151 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1153 unsigned NameIdx = I.getType()->isUnsigned()*2;
1154 NameIdx += I.getOpcode() == Instruction::Div;
1155 MachineInstr *TheCall =
1156 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1158 std::vector<ValueRecord> Args;
1159 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1160 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1161 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1164 case cByte: case cShort: case cInt:
1165 break; // Small integerals, handled below...
1166 default: assert(0 && "Unknown class!");
1169 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1170 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1171 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
1172 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1173 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1175 static const unsigned DivOpcode[][4] = {
1176 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1177 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1180 bool isSigned = I.getType()->isSigned();
1181 unsigned Reg = Regs[Class];
1182 unsigned ExtReg = ExtRegs[Class];
1184 // Put the first operand into one of the A registers...
1185 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1188 // Emit a sign extension instruction...
1189 BuildMI(BB, ExtOpcode[Class], 0);
1191 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1192 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1195 // Emit the appropriate divide or remainder instruction...
1196 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1198 // Figure out which register we want to pick the result out of...
1199 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1201 // Put the result into the destination register...
1202 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1206 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1207 /// for constant immediate shift values, and for constant immediate
1208 /// shift values equal to 1. Even the general case is sort of special,
1209 /// because the shift amount has to be in CL, not just any old register.
1211 void ISel::visitShiftInst(ShiftInst &I) {
1212 unsigned SrcReg = getReg(I.getOperand(0));
1213 unsigned DestReg = getReg(I);
1214 bool isLeftShift = I.getOpcode() == Instruction::Shl;
1215 bool isSigned = I.getType()->isSigned();
1216 unsigned Class = getClass(I.getType());
1218 static const unsigned ConstantOperand[][4] = {
1219 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1220 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1221 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1222 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1225 static const unsigned NonConstantOperand[][4] = {
1226 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1227 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1228 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1229 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1232 // Longs, as usual, are handled specially...
1233 if (Class == cLong) {
1234 // If we have a constant shift, we can generate much more efficient code
1235 // than otherwise...
1237 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1238 unsigned Amount = CUI->getValue();
1240 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1242 BuildMI(BB, Opc[3], 3,
1243 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1244 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1246 BuildMI(BB, Opc[3], 3,
1247 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1248 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1250 } else { // Shifting more than 32 bits
1253 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1254 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1256 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1257 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1258 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1262 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1264 if (!isLeftShift && isSigned) {
1265 // If this is a SHR of a Long, then we need to do funny sign extension
1266 // stuff. TmpReg gets the value to use as the high-part if we are
1267 // shifting more than 32 bits.
1268 BuildMI(BB, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1270 // Other shifts use a fixed zero value if the shift is more than 32
1272 BuildMI(BB, X86::MOVir32, 1, TmpReg).addZImm(0);
1275 // Initialize CL with the shift amount...
1276 unsigned ShiftAmount = getReg(I.getOperand(1));
1277 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmount);
1279 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1280 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1282 // TmpReg2 = shld inHi, inLo
1283 BuildMI(BB, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1284 // TmpReg3 = shl inLo, CL
1285 BuildMI(BB, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1287 // Set the flags to indicate whether the shift was by more than 32 bits.
1288 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1290 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1291 BuildMI(BB, X86::CMOVNErr32, 2,
1292 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1293 // DestLo = (>32) ? TmpReg : TmpReg3;
1294 BuildMI(BB, X86::CMOVNErr32, 2, DestReg).addReg(TmpReg3).addReg(TmpReg);
1296 // TmpReg2 = shrd inLo, inHi
1297 BuildMI(BB, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1298 // TmpReg3 = s[ah]r inHi, CL
1299 BuildMI(BB, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1302 // Set the flags to indicate whether the shift was by more than 32 bits.
1303 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1305 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1306 BuildMI(BB, X86::CMOVNErr32, 2,
1307 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1309 // DestHi = (>32) ? TmpReg : TmpReg3;
1310 BuildMI(BB, X86::CMOVNErr32, 2,
1311 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1317 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1318 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1319 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1321 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1322 BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1323 } else { // The shift amount is non-constant.
1324 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
1326 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1327 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1332 /// doFPLoad - This method is used to load an FP value from memory using the
1333 /// current endianness. NOTE: This method returns a partially constructed load
1334 /// instruction which needs to have the memory source filled in still.
1336 MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB,
1337 MachineBasicBlock::iterator &MBBI,
1338 const Type *Ty, unsigned DestReg) {
1339 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1340 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
1342 if (TM.getTargetData().isLittleEndian()) // fast path...
1343 return BMI(MBB, MBBI, LoadOpcode, 4, DestReg);
1345 // If we are big-endian, start by creating an LEA instruction to represent the
1346 // address of the memory location to load from...
1348 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1349 MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg);
1351 // Allocate a temporary stack slot to transform the value into...
1352 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1354 // Perform the bswaps 32 bits at a time...
1355 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1356 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1357 addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1358 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1359 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1360 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5),
1361 FrameIdx, Offset).addReg(TmpReg2);
1363 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1364 TmpReg1 = makeAnotherReg(Type::UIntTy);
1365 TmpReg2 = makeAnotherReg(Type::UIntTy);
1367 addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1368 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1369 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1370 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2);
1373 // Now we can reload the final byteswapped result into the final destination.
1374 addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx);
1378 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1380 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1381 // Emit the byte swap instruction...
1384 // No byteswap necessary for 8 bit value...
1385 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1388 // Use the 32 bit bswap instruction to do a 32 bit swap...
1389 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1393 // For 16 bit we have to use an xchg instruction, because there is no
1394 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1395 // into AX to do the xchg.
1397 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1398 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1399 .addReg(X86::AH, MOTy::UseAndDef);
1400 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1402 default: assert(0 && "Cannot byteswap this class!");
1407 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1408 /// instruction. The load and store instructions are the only place where we
1409 /// need to worry about the memory layout of the target machine.
1411 void ISel::visitLoadInst(LoadInst &I) {
1412 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1413 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1414 unsigned SrcAddrReg = getReg(I.getOperand(0));
1415 unsigned DestReg = getReg(I);
1417 unsigned Class = getClass(I.getType());
1420 MachineBasicBlock::iterator MBBI = BB->end();
1421 addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg);
1424 case cLong: case cInt: case cShort: case cByte:
1425 break; // Integers of various sizes handled below
1426 default: assert(0 && "Unknown memory class!");
1429 // We need to adjust the input pointer if we are emulating a big-endian
1430 // long-pointer target. On these systems, the pointer that we are interested
1431 // in is in the upper part of the eight byte memory image of the pointer. It
1432 // also happens to be byte-swapped, but this will be handled later.
1434 if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
1435 unsigned R = makeAnotherReg(Type::UIntTy);
1436 BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
1440 unsigned IReg = DestReg;
1441 if (!isLittleEndian) // If big endian we need an intermediate stage
1442 DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy);
1444 static const unsigned Opcode[] = {
1445 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
1447 addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
1449 // Handle long values now...
1450 if (Class == cLong) {
1451 if (isLittleEndian) {
1452 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1454 EmitByteSwap(IReg+1, DestReg, cInt);
1455 unsigned TempReg = makeAnotherReg(Type::IntTy);
1456 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4);
1457 EmitByteSwap(IReg, TempReg, cInt);
1462 if (!isLittleEndian)
1463 EmitByteSwap(IReg, DestReg, Class);
1467 /// doFPStore - This method is used to store an FP value to memory using the
1468 /// current endianness.
1470 void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) {
1471 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1472 unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
1474 if (TM.getTargetData().isLittleEndian()) { // fast path...
1475 addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg);
1479 // Allocate a temporary stack slot to transform the value into...
1480 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1481 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1482 addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx);
1484 // Store the value into a temporary stack slot...
1485 addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg);
1487 // Perform the bswaps 32 bits at a time...
1488 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1489 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1490 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1491 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1492 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1493 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1494 DestAddrReg, Offset).addReg(TmpReg2);
1496 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1497 TmpReg1 = makeAnotherReg(Type::UIntTy);
1498 TmpReg2 = makeAnotherReg(Type::UIntTy);
1500 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1501 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1502 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1503 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2);
1508 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1511 void ISel::visitStoreInst(StoreInst &I) {
1512 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1513 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1514 unsigned ValReg = getReg(I.getOperand(0));
1515 unsigned AddressReg = getReg(I.getOperand(1));
1517 unsigned Class = getClass(I.getOperand(0)->getType());
1520 if (isLittleEndian) {
1521 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1522 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4),
1523 AddressReg, 4).addReg(ValReg+1);
1525 unsigned T1 = makeAnotherReg(Type::IntTy);
1526 unsigned T2 = makeAnotherReg(Type::IntTy);
1527 EmitByteSwap(T1, ValReg , cInt);
1528 EmitByteSwap(T2, ValReg+1, cInt);
1529 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2);
1530 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1);
1534 doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg);
1536 case cInt: case cShort: case cByte:
1537 break; // Integers of various sizes handled below
1538 default: assert(0 && "Unknown memory class!");
1541 if (!isLittleEndian && hasLongPointers &&
1542 isa<PointerType>(I.getOperand(0)->getType())) {
1543 unsigned R = makeAnotherReg(Type::UIntTy);
1544 BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
1548 if (!isLittleEndian && Class != cByte) {
1549 unsigned R = makeAnotherReg(I.getOperand(0)->getType());
1550 EmitByteSwap(R, ValReg, Class);
1554 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1555 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
1559 /// visitCastInst - Here we have various kinds of copying with or without
1560 /// sign extension going on.
1561 void ISel::visitCastInst(CastInst &CI) {
1562 unsigned DestReg = getReg(CI);
1563 MachineBasicBlock::iterator MI = BB->end();
1564 emitCastOperation(BB, MI, CI.getOperand(0), CI.getType(), DestReg);
1567 /// emitCastOperation - Common code shared between visitCastInst and
1568 /// constant expression cast support.
1569 void ISel::emitCastOperation(MachineBasicBlock *BB,
1570 MachineBasicBlock::iterator &IP,
1571 Value *Src, const Type *DestTy,
1573 unsigned SrcReg = getReg(Src, BB, IP);
1574 const Type *SrcTy = Src->getType();
1575 unsigned SrcClass = getClassB(SrcTy);
1576 unsigned DestClass = getClassB(DestTy);
1578 // Implement casts to bool by using compare on the operand followed by set if
1579 // not zero on the result.
1580 if (DestTy == Type::BoolTy) {
1583 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1586 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1589 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1592 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1593 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1597 assert(0 && "FIXME: implement cast FP to bool");
1601 // If the zero flag is not set, then the value is true, set the byte to
1603 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1607 static const unsigned RegRegMove[] = {
1608 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1611 // Implement casts between values of the same type class (as determined by
1612 // getClass) by using a register-to-register move.
1613 if (SrcClass == DestClass) {
1614 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1615 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1616 } else if (SrcClass == cFP) {
1617 if (SrcTy == Type::FloatTy) { // double -> float
1618 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1619 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1620 } else { // float -> double
1621 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1622 "Unknown cFP member!");
1623 // Truncate from double to float by storing to memory as short, then
1625 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1626 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1627 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1628 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1630 } else if (SrcClass == cLong) {
1631 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1632 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1634 assert(0 && "Cannot handle this type of cast instruction!");
1640 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1641 // or zero extension, depending on whether the source type was signed.
1642 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1643 SrcClass < DestClass) {
1644 bool isLong = DestClass == cLong;
1645 if (isLong) DestClass = cInt;
1647 static const unsigned Opc[][4] = {
1648 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1649 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1652 bool isUnsigned = SrcTy->isUnsigned();
1653 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1654 DestReg).addReg(SrcReg);
1656 if (isLong) { // Handle upper 32 bits as appropriate...
1657 if (isUnsigned) // Zero out top bits...
1658 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1659 else // Sign extend bottom half...
1660 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1665 // Special case long -> int ...
1666 if (SrcClass == cLong && DestClass == cInt) {
1667 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1671 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1672 // move out of AX or AL.
1673 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1674 && SrcClass > DestClass) {
1675 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1676 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1677 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1681 // Handle casts from integer to floating point now...
1682 if (DestClass == cFP) {
1683 // Promote the integer to a type supported by FLD. We do this because there
1684 // are no unsigned FLD instructions, so we must promote an unsigned value to
1685 // a larger signed value, then use FLD on the larger value.
1687 const Type *PromoteType = 0;
1688 unsigned PromoteOpcode;
1689 switch (SrcTy->getPrimitiveID()) {
1690 case Type::BoolTyID:
1691 case Type::SByteTyID:
1692 // We don't have the facilities for directly loading byte sized data from
1693 // memory (even signed). Promote it to 16 bits.
1694 PromoteType = Type::ShortTy;
1695 PromoteOpcode = X86::MOVSXr16r8;
1697 case Type::UByteTyID:
1698 PromoteType = Type::ShortTy;
1699 PromoteOpcode = X86::MOVZXr16r8;
1701 case Type::UShortTyID:
1702 PromoteType = Type::IntTy;
1703 PromoteOpcode = X86::MOVZXr32r16;
1705 case Type::UIntTyID: {
1706 // Make a 64 bit temporary... and zero out the top of it...
1707 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1708 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1709 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1710 SrcTy = Type::LongTy;
1715 case Type::ULongTyID:
1716 assert("FIXME: not implemented: cast ulong X to fp type!");
1717 default: // No promotion needed...
1722 unsigned TmpReg = makeAnotherReg(PromoteType);
1723 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1724 1, TmpReg).addReg(SrcReg);
1725 SrcTy = PromoteType;
1726 SrcClass = getClass(PromoteType);
1730 // Spill the integer to memory and reload it from there...
1732 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1734 if (SrcClass == cLong) {
1735 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1736 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1737 FrameIdx, 4).addReg(SrcReg+1);
1739 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1740 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1743 static const unsigned Op2[] =
1744 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1745 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1749 // Handle casts from floating point to integer now...
1750 if (SrcClass == cFP) {
1751 // Change the floating point control register to use "round towards zero"
1752 // mode when truncating to an integer value.
1754 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1755 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1757 // Load the old value of the high byte of the control word...
1758 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1759 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1761 // Set the high part to be round to zero...
1762 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1764 // Reload the modified control word now...
1765 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1767 // Restore the memory image of control word to original value
1768 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1769 CWFrameIdx, 1).addReg(HighPartOfCW);
1771 // We don't have the facilities for directly storing byte sized data to
1772 // memory. Promote it to 16 bits. We also must promote unsigned values to
1773 // larger classes because we only have signed FP stores.
1774 unsigned StoreClass = DestClass;
1775 const Type *StoreTy = DestTy;
1776 if (StoreClass == cByte || DestTy->isUnsigned())
1777 switch (StoreClass) {
1778 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1779 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1780 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1782 assert(0 &&"FIXME not implemented: cast FP to unsigned long long");
1784 default: assert(0 && "Unknown store class!");
1787 // Spill the integer to memory and reload it from there...
1789 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1791 static const unsigned Op1[] =
1792 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1793 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1795 if (DestClass == cLong) {
1796 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1797 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1799 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1800 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1803 // Reload the original control word now...
1804 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1808 // Anything we haven't handled already, we can't (yet) handle at all.
1809 assert(0 && "Unhandled cast instruction!");
1813 /// visitVarArgInst - Implement the va_arg instruction...
1815 void ISel::visitVarArgInst(VarArgInst &I) {
1816 unsigned SrcReg = getReg(I.getOperand(0));
1817 unsigned DestReg = getReg(I);
1819 // Load the va_list into a register...
1820 unsigned VAList = makeAnotherReg(Type::UIntTy);
1821 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, VAList), SrcReg);
1824 switch (I.getType()->getPrimitiveID()) {
1827 assert(0 && "Error: bad type for va_arg instruction!");
1829 case Type::PointerTyID:
1830 case Type::UIntTyID:
1833 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1835 case Type::ULongTyID:
1836 case Type::LongTyID:
1838 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1839 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
1841 case Type::DoubleTyID:
1843 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
1847 // Increment the VAList pointer...
1848 unsigned NextVAList = makeAnotherReg(Type::UIntTy);
1849 BuildMI(BB, X86::ADDri32, 2, NextVAList).addReg(VAList).addZImm(Size);
1851 // Update the VAList in memory...
1852 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), SrcReg).addReg(NextVAList);
1856 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1857 // returns zero when the input is not exactly a power of two.
1858 static unsigned ExactLog2(unsigned Val) {
1859 if (Val == 0) return 0;
1862 if (Val & 1) return 0;
1869 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
1870 unsigned outputReg = getReg(I);
1871 MachineBasicBlock::iterator MI = BB->end();
1872 emitGEPOperation(BB, MI, I.getOperand(0),
1873 I.op_begin()+1, I.op_end(), outputReg);
1876 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
1877 MachineBasicBlock::iterator &IP,
1878 Value *Src, User::op_iterator IdxBegin,
1879 User::op_iterator IdxEnd, unsigned TargetReg) {
1880 const TargetData &TD = TM.getTargetData();
1881 const Type *Ty = Src->getType();
1882 unsigned BaseReg = getReg(Src, MBB, IP);
1884 // GEPs have zero or more indices; we must perform a struct access
1885 // or array access for each one.
1886 for (GetElementPtrInst::op_iterator oi = IdxBegin,
1887 oe = IdxEnd; oi != oe; ++oi) {
1889 unsigned NextReg = BaseReg;
1890 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1891 // It's a struct access. idx is the index into the structure,
1892 // which names the field. This index must have ubyte type.
1893 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
1894 assert(CUI->getType() == Type::UByteTy
1895 && "Funny-looking structure index in GEP");
1896 // Use the TargetData structure to pick out what the layout of
1897 // the structure is in memory. Since the structure index must
1898 // be constant, we can get its value and use it to find the
1899 // right byte offset from the StructLayout class's list of
1900 // structure member offsets.
1901 unsigned idxValue = CUI->getValue();
1902 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
1904 NextReg = makeAnotherReg(Type::UIntTy);
1905 // Emit an ADD to add FieldOff to the basePtr.
1906 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1908 // The next type is the member of the structure selected by the
1910 Ty = StTy->getElementTypes()[idxValue];
1911 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
1912 // It's an array or pointer access: [ArraySize x ElementType].
1914 // idx is the index into the array. Unlike with structure
1915 // indices, we may not know its actual value at code-generation
1917 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
1919 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
1920 // must find the size of the pointed-to type (Not coincidentally, the next
1921 // type is the type of the elements in the array).
1922 Ty = SqTy->getElementType();
1923 unsigned elementSize = TD.getTypeSize(Ty);
1925 // If idxReg is a constant, we don't need to perform the multiply!
1926 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
1927 if (!CSI->isNullValue()) {
1928 unsigned Offset = elementSize*CSI->getValue();
1929 NextReg = makeAnotherReg(Type::UIntTy);
1930 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
1932 } else if (elementSize == 1) {
1933 // If the element size is 1, we don't have to multiply, just add
1934 unsigned idxReg = getReg(idx, MBB, IP);
1935 NextReg = makeAnotherReg(Type::UIntTy);
1936 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
1938 unsigned idxReg = getReg(idx, MBB, IP);
1939 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
1940 if (unsigned Shift = ExactLog2(elementSize)) {
1941 // If the element size is exactly a power of 2, use a shift to get it.
1942 BMI(MBB, IP, X86::SHLir32, 2,
1943 OffsetReg).addReg(idxReg).addZImm(Shift-1);
1945 // Most general case, emit a multiply...
1946 unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
1947 BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
1949 // Emit a MUL to multiply the register holding the index by
1950 // elementSize, putting the result in OffsetReg.
1951 doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
1953 // Emit an ADD to add OffsetReg to the basePtr.
1954 NextReg = makeAnotherReg(Type::UIntTy);
1955 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
1958 // Now that we are here, further indices refer to subtypes of this
1959 // one, so we don't need to worry about BaseReg itself, anymore.
1962 // After we have processed all the indices, the result is left in
1963 // BaseReg. Move it to the register where we were expected to
1964 // put the answer. A 32-bit move should do it, because we are in
1966 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
1970 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
1971 /// frame manager, otherwise do it the hard way.
1973 void ISel::visitAllocaInst(AllocaInst &I) {
1974 // Find the data size of the alloca inst's getAllocatedType.
1975 const Type *Ty = I.getAllocatedType();
1976 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1978 // If this is a fixed size alloca in the entry block for the function,
1979 // statically stack allocate the space.
1981 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
1982 if (I.getParent() == I.getParent()->getParent()->begin()) {
1983 TySize *= CUI->getValue(); // Get total allocated size...
1984 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
1986 // Create a new stack object using the frame manager...
1987 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
1988 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
1993 // Create a register to hold the temporary result of multiplying the type size
1994 // constant by the variable amount.
1995 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
1996 unsigned SrcReg1 = getReg(I.getArraySize());
1997 unsigned SizeReg = makeAnotherReg(Type::UIntTy);
1998 BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
2000 // TotalSizeReg = mul <numelements>, <TypeSize>
2001 MachineBasicBlock::iterator MBBI = BB->end();
2002 doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
2004 // AddedSize = add <TotalSizeReg>, 15
2005 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2006 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2008 // AlignedSize = and <AddedSize>, ~15
2009 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2010 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2012 // Subtract size from stack pointer, thereby allocating some space.
2013 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2015 // Put a pointer to the space into the result register, by copying
2016 // the stack pointer.
2017 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2019 // Inform the Frame Information that we have just allocated a variable-sized
2021 F->getFrameInfo()->CreateVariableSizedObject();
2024 /// visitMallocInst - Malloc instructions are code generated into direct calls
2025 /// to the library malloc.
2027 void ISel::visitMallocInst(MallocInst &I) {
2028 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2031 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2032 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2034 Arg = makeAnotherReg(Type::UIntTy);
2035 unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
2036 unsigned Op1Reg = getReg(I.getOperand(0));
2037 MachineBasicBlock::iterator MBBI = BB->end();
2038 doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
2043 std::vector<ValueRecord> Args;
2044 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2045 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2046 1).addExternalSymbol("malloc", true);
2047 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2051 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2054 void ISel::visitFreeInst(FreeInst &I) {
2055 std::vector<ValueRecord> Args;
2056 Args.push_back(ValueRecord(getReg(I.getOperand(0)),
2057 I.getOperand(0)->getType()));
2058 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2059 1).addExternalSymbol("free", true);
2060 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2064 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
2065 /// into a machine code representation is a very simple peep-hole fashion. The
2066 /// generated code sucks but the implementation is nice and simple.
2068 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
2069 return new ISel(TM);