1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Support/InstVisitor.h"
23 #include "llvm/Target/MRegisterInfo.h"
26 using namespace MOTy; // Get Use, Def, UseAndDef
29 struct ISel : public FunctionPass, InstVisitor<ISel> {
31 MachineFunction *F; // The function we are compiling into
32 MachineBasicBlock *BB; // The current MBB we are compiling
35 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
37 ISel(TargetMachine &tm)
38 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
40 /// runOnFunction - Top level implementation of instruction selection for
41 /// the entire function.
43 bool runOnFunction(Function &Fn) {
44 F = &MachineFunction::construct(&Fn, TM);
48 return false; // We never modify the LLVM itself.
51 /// visitBasicBlock - This method is called when we are visiting a new basic
52 /// block. This simply creates a new MachineBasicBlock to emit code into
53 /// and adds it to the current MachineFunction. Subsequent visit* for
54 /// instructions will be invoked for all instructions in the basic block.
56 void visitBasicBlock(BasicBlock &LLVM_BB) {
57 BB = new MachineBasicBlock(&LLVM_BB);
58 // FIXME: Use the auto-insert form when it's available
59 F->getBasicBlockList().push_back(BB);
62 // Visitation methods for various instructions. These methods simply emit
63 // fixed X86 code for each instruction.
65 void visitReturnInst(ReturnInst &RI);
66 void visitBranchInst(BranchInst &BI);
68 // Arithmetic operators
69 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
70 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
71 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
72 void visitMul(BinaryOperator &B);
74 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
75 void visitRem(BinaryOperator &B) { visitDivRem(B); }
76 void visitDivRem(BinaryOperator &B);
79 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
80 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
81 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
83 // Binary comparison operators
84 void visitSetCCInst(SetCondInst &I, unsigned OpNum);
85 void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
86 void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
87 void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
88 void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
89 void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
90 void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
92 // Memory Instructions
93 void visitLoadInst(LoadInst &I);
94 void visitStoreInst(StoreInst &I);
97 void visitShiftInst(ShiftInst &I);
98 void visitPHINode(PHINode &I);
100 void visitInstruction(Instruction &I) {
101 std::cerr << "Cannot instruction select: " << I;
106 /// copyConstantToRegister - Output the instructions required to put the
107 /// specified constant into the specified register.
109 void copyConstantToRegister(Constant *C, unsigned Reg);
111 /// getReg - This method turns an LLVM value into a register number. This
112 /// is guaranteed to produce the same register number for a particular value
113 /// every time it is queried.
115 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
116 unsigned getReg(Value *V) {
117 unsigned &Reg = RegMap[V];
122 // Add the mapping of regnumber => reg class to MachineFunction
124 TM.getRegisterInfo()->getRegClassForType(V->getType()));
127 // If this operand is a constant, emit the code to copy the constant into
128 // the register here...
130 if (Constant *C = dyn_cast<Constant>(V))
131 copyConstantToRegister(C, Reg);
138 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
142 cByte, cShort, cInt, cLong, cFloat, cDouble
145 /// getClass - Turn a primitive type into a "class" number which is based on the
146 /// size of the type, and whether or not it is floating point.
148 static inline TypeClass getClass(const Type *Ty) {
149 switch (Ty->getPrimitiveID()) {
150 case Type::SByteTyID:
151 case Type::UByteTyID: return cByte; // Byte operands are class #0
152 case Type::ShortTyID:
153 case Type::UShortTyID: return cShort; // Short operands are class #1
156 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
159 case Type::ULongTyID: return cLong; // Longs are class #3
160 case Type::FloatTyID: return cFloat; // Float is class #4
161 case Type::DoubleTyID: return cDouble; // Doubles are class #5
163 assert(0 && "Invalid type to getClass!");
164 return cByte; // not reached
169 /// copyConstantToRegister - Output the instructions required to put the
170 /// specified constant into the specified register.
172 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
173 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
175 if (C->getType()->isIntegral()) {
176 unsigned Class = getClass(C->getType());
177 assert(Class != 3 && "Type not handled yet!");
179 static const unsigned IntegralOpcodeTab[] = {
180 X86::MOVir8, X86::MOVir16, X86::MOVir32
183 if (C->getType()->isSigned()) {
184 ConstantSInt *CSI = cast<ConstantSInt>(C);
185 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
187 ConstantUInt *CUI = cast<ConstantUInt>(C);
188 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
191 assert(0 && "Type not handled yet!");
196 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
197 /// register, then move it to wherever the result should be.
198 /// We handle FP setcc instructions by pushing them, doing a
199 /// compare-and-pop-twice, and then copying the concodes to the main
200 /// processor's concodes (I didn't make this up, it's in the Intel manual)
202 void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
203 // The arguments are already supposed to be of the same type.
204 const Type *CompTy = I.getOperand(0)->getType();
205 unsigned reg1 = getReg(I.getOperand(0));
206 unsigned reg2 = getReg(I.getOperand(1));
208 unsigned Class = getClass(CompTy);
210 // Emit: cmp <var1>, <var2> (do the comparison). We can
211 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
214 BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
217 BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
220 BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
223 // Push the variables on the stack with fldl opcodes.
224 // FIXME: assuming var1, var2 are in memory, if not, spill to
226 case cFloat: // Floats
227 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
228 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
230 case cDouble: // Doubles
231 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
232 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
239 if (CompTy->isFloatingPoint()) {
240 // (Non-trapping) compare and pop twice.
241 BuildMI (BB, X86::FUCOMPP, 0);
242 // Move fp status word (concodes) to ax.
243 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
244 // Load real concodes from ax.
245 BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
248 // Emit setOp instruction (extract concode; clobbers ax),
249 // using the following mapping:
250 // LLVM -> X86 signed X86 unsigned
252 // seteq -> sete sete
253 // setne -> setne setne
254 // setlt -> setl setb
255 // setgt -> setg seta
256 // setle -> setle setbe
257 // setge -> setge setae
259 static const unsigned OpcodeTab[2][6] = {
260 { X86::SETE, X86::SETNE, X86::SETB, X86::SETA, X86::SETBE, X86::SETAE },
261 { X86::SETE, X86::SETNE, X86::SETL, X86::SETG, X86::SETLE, X86::SETGE },
264 BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
266 // Put it in the result using a move.
267 BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
271 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
272 /// we have the following possibilities:
274 /// ret void: No return value, simply emit a 'ret' instruction
275 /// ret sbyte, ubyte : Extend value into EAX and return
276 /// ret short, ushort: Extend value into EAX and return
277 /// ret int, uint : Move value into EAX and return
278 /// ret pointer : Move value into EAX and return
279 /// ret long, ulong : Move value into EAX/EDX and return
280 /// ret float/double : Top of FP stack
282 void ISel::visitReturnInst (ReturnInst &I) {
283 if (I.getNumOperands() == 0) {
284 // Emit a 'ret' instruction
285 BuildMI(BB, X86::RET, 0);
289 unsigned val = getReg(I.getOperand(0));
290 unsigned Class = getClass(I.getOperand(0)->getType());
291 bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
294 // ret sbyte, ubyte: Extend value into EAX and return
296 BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
298 BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
301 // ret short, ushort: Extend value into EAX and return
303 BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
305 BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
308 // ret int, uint, ptr: Move value into EAX and return
310 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
313 // ret float/double: top of FP stack
315 case cFloat: // Floats
316 BuildMI(BB, X86::FLDr4, 1).addReg(val);
318 case cDouble: // Doubles
319 BuildMI(BB, X86::FLDr8, 1).addReg(val);
322 // ret long: use EAX(least significant 32 bits)/EDX (most
323 // significant 32)...uh, I think so Brain, but how do i call
324 // up the two parts of the value from inside this mouse
330 // Emit a 'ret' instruction
331 BuildMI(BB, X86::RET, 0);
334 /// visitBranchInst - Handle conditional and unconditional branches here. Note
335 /// that since code layout is frozen at this point, that if we are trying to
336 /// jump to a block that is the immediate successor of the current block, we can
337 /// just make a fall-through. (but we don't currently).
340 ISel::visitBranchInst (BranchInst & BI)
342 if (BI.isConditional ())
344 BasicBlock *ifTrue = BI.getSuccessor (0);
345 BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
347 // simplest thing I can think of: compare condition with zero,
348 // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
350 unsigned int condReg = getReg (BI.getCondition ());
351 BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
352 BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
353 BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
355 else // unconditional branch
357 BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
362 /// visitSimpleBinary - Implement simple binary operators for integral types...
363 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
366 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
367 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
370 unsigned Class = getClass(B.getType());
371 if (Class > 2) // FIXME: Handle longs
374 static const unsigned OpcodeTab[][4] = {
375 // Arithmetic operators
376 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
377 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
380 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
381 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
382 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
385 unsigned Opcode = OpcodeTab[OperatorClass][Class];
386 unsigned Op0r = getReg(B.getOperand(0));
387 unsigned Op1r = getReg(B.getOperand(1));
388 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
391 /// visitMul - Multiplies are not simple binary operators because they must deal
392 /// with the EAX register explicitly.
394 void ISel::visitMul(BinaryOperator &I) {
395 unsigned Class = getClass(I.getType());
396 if (Class > 2) // FIXME: Handle longs
399 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
400 static const unsigned Clobbers[] ={ X86::AH , X86::DX , X86::EDX };
401 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
402 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
404 unsigned Reg = Regs[Class];
405 unsigned Clobber = Clobbers[Class];
406 unsigned Op0Reg = getReg(I.getOperand(0));
407 unsigned Op1Reg = getReg(I.getOperand(1));
409 // Put the first operand into one of the A registers...
410 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
412 // Emit the appropriate multiply instruction...
413 BuildMI(BB, MulOpcode[Class], 3)
414 .addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber);
416 // Put the result into the destination register...
417 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
421 /// visitDivRem - Handle division and remainder instructions... these
422 /// instruction both require the same instructions to be generated, they just
423 /// select the result from a different register. Note that both of these
424 /// instructions work differently for signed and unsigned operands.
426 void ISel::visitDivRem(BinaryOperator &I) {
427 unsigned Class = getClass(I.getType());
428 if (Class > 2) // FIXME: Handle longs
431 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
432 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
433 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
434 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
435 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
437 static const unsigned DivOpcode[][4] = {
438 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
439 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
442 bool isSigned = I.getType()->isSigned();
443 unsigned Reg = Regs[Class];
444 unsigned ExtReg = ExtRegs[Class];
445 unsigned Op0Reg = getReg(I.getOperand(0));
446 unsigned Op1Reg = getReg(I.getOperand(1));
448 // Put the first operand into one of the A registers...
449 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
452 // Emit a sign extension instruction...
453 BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
455 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
456 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
459 // Emit the appropriate divide or remainder instruction...
460 BuildMI(BB, DivOpcode[isSigned][Class], 2)
461 .addReg(Reg, UseAndDef).addReg(ExtReg, UseAndDef).addReg(Op1Reg);
463 // Figure out which register we want to pick the result out of...
464 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
466 // Put the result into the destination register...
467 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
471 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
472 /// for constant immediate shift values, and for constant immediate
473 /// shift values equal to 1. Even the general case is sort of special,
474 /// because the shift amount has to be in CL, not just any old register.
476 void ISel::visitShiftInst (ShiftInst &I) {
477 unsigned Op0r = getReg (I.getOperand(0));
478 unsigned DestReg = getReg(I);
479 bool isLeftShift = I.getOpcode() == Instruction::Shl;
480 bool isOperandSigned = I.getType()->isUnsigned();
481 unsigned OperandClass = getClass(I.getType());
483 if (OperandClass > 2)
484 visitInstruction(I); // Can't handle longs yet!
486 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
488 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
489 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
490 unsigned char shAmt = CUI->getValue();
492 static const unsigned ConstantOperand[][4] = {
493 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
494 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
495 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
496 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
499 const unsigned *OpTab = // Figure out the operand table to use
500 ConstantOperand[isLeftShift*2+isOperandSigned];
502 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
503 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
507 // The shift amount is non-constant.
509 // In fact, you can only shift with a variable shift amount if
510 // that amount is already in the CL register, so we have to put it
514 // Emit: move cl, shiftAmount (put the shift amount in CL.)
515 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
517 // This is a shift right (SHR).
518 static const unsigned NonConstantOperand[][4] = {
519 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
520 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
521 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
522 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
525 const unsigned *OpTab = // Figure out the operand table to use
526 NonConstantOperand[isLeftShift*2+isOperandSigned];
528 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
533 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
536 void ISel::visitLoadInst(LoadInst &I) {
537 unsigned Class = getClass(I.getType());
538 if (Class > 2) // FIXME: Handle longs and others...
541 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
543 unsigned AddressReg = getReg(I.getOperand(0));
544 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
548 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
551 void ISel::visitStoreInst(StoreInst &I) {
552 unsigned Class = getClass(I.getOperand(0)->getType());
553 if (Class > 2) // FIXME: Handle longs and others...
556 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
558 unsigned ValReg = getReg(I.getOperand(0));
559 unsigned AddressReg = getReg(I.getOperand(1));
560 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
564 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
566 void ISel::visitPHINode(PHINode &PN) {
567 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
569 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
570 // FIXME: This will put constants after the PHI nodes in the block, which
571 // is invalid. They should be put inline into the PHI node eventually.
573 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
574 MI->addPCDispOperand(PN.getIncomingBlock(i));
579 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
580 /// into a machine code representation is a very simple peep-hole fashion. The
581 /// generated code sucks but the implementation is nice and simple.
583 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {