1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Support/InstVisitor.h"
24 #include "llvm/Target/MRegisterInfo.h"
27 using namespace MOTy; // Get Use, Def, UseAndDef
30 /// BMI - A special BuildMI variant that takes an iterator to insert the
31 /// instruction at as well as a basic block.
32 inline static MachineInstrBuilder BMI(MachineBasicBlock *BB,
33 MachineBasicBlock::iterator &I,
37 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
38 I = ++BB->insert(I, MI);
39 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
44 struct ISel : public FunctionPass, InstVisitor<ISel> {
46 MachineFunction *F; // The function we are compiling into
47 MachineBasicBlock *BB; // The current MBB we are compiling
50 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
52 // MBBMap - Mapping between LLVM BB -> Machine BB
53 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
55 ISel(TargetMachine &tm)
56 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
58 /// runOnFunction - Top level implementation of instruction selection for
59 /// the entire function.
61 bool runOnFunction(Function &Fn) {
62 F = &MachineFunction::construct(&Fn, TM);
64 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
65 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
67 // Instruction select everything except PHI nodes
70 // Select the PHI nodes
75 CurReg = MRegisterInfo::FirstVirtualRegister;
77 return false; // We never modify the LLVM itself.
80 /// visitBasicBlock - This method is called when we are visiting a new basic
81 /// block. This simply creates a new MachineBasicBlock to emit code into
82 /// and adds it to the current MachineFunction. Subsequent visit* for
83 /// instructions will be invoked for all instructions in the basic block.
85 void visitBasicBlock(BasicBlock &LLVM_BB) {
86 BB = MBBMap[&LLVM_BB];
90 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
91 /// because we have to generate our sources into the source basic blocks,
92 /// not the current one.
94 void SelectPHINodes();
96 // Visitation methods for various instructions. These methods simply emit
97 // fixed X86 code for each instruction.
100 // Control flow operators
101 void visitReturnInst(ReturnInst &RI);
102 void visitBranchInst(BranchInst &BI);
103 void visitCallInst(CallInst &I);
105 // Arithmetic operators
106 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
107 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
108 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
109 void doMultiply(unsigned destReg, const Type *resultType,
110 unsigned op0Reg, unsigned op1Reg);
111 void visitMul(BinaryOperator &B);
113 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
114 void visitRem(BinaryOperator &B) { visitDivRem(B); }
115 void visitDivRem(BinaryOperator &B);
118 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
119 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
120 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
122 // Binary comparison operators
123 void visitSetCCInst(SetCondInst &I, unsigned OpNum);
124 void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
125 void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
126 void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
127 void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
128 void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
129 void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
131 // Memory Instructions
132 void visitLoadInst(LoadInst &I);
133 void visitStoreInst(StoreInst &I);
134 void visitGetElementPtrInst(GetElementPtrInst &I);
135 void visitMallocInst(MallocInst &I);
136 void visitFreeInst(FreeInst &I);
137 void visitAllocaInst(AllocaInst &I);
140 void visitShiftInst(ShiftInst &I);
141 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
142 void visitCastInst(CastInst &I);
144 void visitInstruction(Instruction &I) {
145 std::cerr << "Cannot instruction select: " << I;
149 /// promote32 - Make a value 32-bits wide, and put it somewhere.
150 void promote32 (const unsigned targetReg, Value *v);
152 // emitGEPOperation - Common code shared between visitGetElementPtrInst and
153 // constant expression GEP support.
155 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
156 Value *Src, User::op_iterator IdxBegin,
157 User::op_iterator IdxEnd, unsigned TargetReg);
159 /// copyConstantToRegister - Output the instructions required to put the
160 /// specified constant into the specified register.
162 void copyConstantToRegister(Constant *C, unsigned Reg,
163 MachineBasicBlock *MBB,
164 MachineBasicBlock::iterator MBBI);
166 /// makeAnotherReg - This method returns the next register number
167 /// we haven't yet used.
168 unsigned makeAnotherReg(const Type *Ty) {
169 // Add the mapping of regnumber => reg class to MachineFunction
170 F->addRegMap(CurReg, TM.getRegisterInfo()->getRegClassForType(Ty));
174 /// getReg - This method turns an LLVM value into a register number. This
175 /// is guaranteed to produce the same register number for a particular value
176 /// every time it is queried.
178 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
179 unsigned getReg(Value *V, MachineBasicBlock *BB = 0) {
180 MachineBasicBlock::iterator IPt;
181 if (BB == 0) { // Should we just append to the end of the current bb?
184 } else { // Otherwise, insert before the branch or ret instr...
188 unsigned &Reg = RegMap[V];
190 Reg = makeAnotherReg(V->getType());
194 // If this operand is a constant, emit the code to copy the constant into
195 // the register here...
197 if (Constant *C = dyn_cast<Constant>(V)) {
198 copyConstantToRegister(C, Reg, BB, IPt);
199 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
200 // Move the address of the global into the register
201 BMI(BB, IPt, X86::MOVir32, 1, Reg).addReg(GV);
202 } else if (Argument *A = dyn_cast<Argument>(V)) {
203 // Find the position of the argument in the argument list.
204 const Function *f = F->getFunction ();
205 // The function's arguments look like this:
206 // [EBP] -- copy of old EBP
207 // [EBP + 4] -- return address
208 // [EBP + 8] -- first argument (leftmost lexically)
209 // So we want to start with counter = 2.
210 int counter = 2, argPos = -1;
211 for (Function::const_aiterator ai = f->abegin (), ae = f->aend ();
215 break; // Only need to find it once. ;-)
220 && "Argument not found in current function's argument list");
221 // Load it out of the stack frame at EBP + 4*argPos.
222 addRegOffset(BMI(BB, IPt, X86::MOVmr32, 4, Reg), X86::EBP, 4*argPos);
230 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
234 cByte, cShort, cInt, cLong, cFloat, cDouble
237 /// getClass - Turn a primitive type into a "class" number which is based on the
238 /// size of the type, and whether or not it is floating point.
240 static inline TypeClass getClass(const Type *Ty) {
241 switch (Ty->getPrimitiveID()) {
242 case Type::SByteTyID:
243 case Type::UByteTyID: return cByte; // Byte operands are class #0
244 case Type::ShortTyID:
245 case Type::UShortTyID: return cShort; // Short operands are class #1
248 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
251 case Type::ULongTyID: //return cLong; // Longs are class #3
252 return cInt; // FIXME: LONGS ARE TREATED AS INTS!
254 case Type::FloatTyID: return cFloat; // Float is class #4
255 case Type::DoubleTyID: return cDouble; // Doubles are class #5
257 assert(0 && "Invalid type to getClass!");
258 return cByte; // not reached
263 /// copyConstantToRegister - Output the instructions required to put the
264 /// specified constant into the specified register.
266 void ISel::copyConstantToRegister(Constant *C, unsigned R,
267 MachineBasicBlock *BB,
268 MachineBasicBlock::iterator IP) {
269 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
270 if (CE->getOpcode() == Instruction::GetElementPtr) {
271 emitGEPOperation(BB, IP, CE->getOperand(0),
272 CE->op_begin()+1, CE->op_end(), R);
276 std::cerr << "Offending expr: " << C << "\n";
277 assert (0 && "Constant expressions not yet handled!\n");
280 if (C->getType()->isIntegral()) {
281 unsigned Class = getClass(C->getType());
282 assert(Class != 3 && "Type not handled yet!");
284 static const unsigned IntegralOpcodeTab[] = {
285 X86::MOVir8, X86::MOVir16, X86::MOVir32
288 if (C->getType()->isSigned()) {
289 ConstantSInt *CSI = cast<ConstantSInt>(C);
290 BMI(BB, IP, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
292 ConstantUInt *CUI = cast<ConstantUInt>(C);
293 BMI(BB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
295 } else if (isa <ConstantPointerNull> (C)) {
296 // Copy zero (null pointer) to the register.
297 BMI(BB, IP, X86::MOVir32, 1, R).addZImm(0);
298 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
299 unsigned SrcReg = getReg(CPR->getValue());
300 BMI(BB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
302 std::cerr << "Offending constant: " << C << "\n";
303 assert(0 && "Type not handled yet!");
307 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
308 /// because we have to generate our sources into the source basic blocks, not
311 void ISel::SelectPHINodes() {
312 const Function &LF = *F->getFunction(); // The LLVM function...
313 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
314 const BasicBlock *BB = I;
315 MachineBasicBlock *MBB = MBBMap[I];
317 // Loop over all of the PHI nodes in the LLVM basic block...
318 unsigned NumPHIs = 0;
319 for (BasicBlock::const_iterator I = BB->begin();
320 PHINode *PN = (PHINode*)dyn_cast<PHINode>(&*I); ++I) {
321 // Create a new machine instr PHI node, and insert it.
322 MachineInstr *MI = BuildMI(X86::PHI, PN->getNumOperands(), getReg(*PN));
323 MBB->insert(MBB->begin()+NumPHIs++, MI); // Insert it at the top of the BB
325 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
326 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
328 // Get the incoming value into a virtual register. If it is not already
329 // available in a virtual register, insert the computation code into
331 MI->addRegOperand(getReg(PN->getIncomingValue(i), PredMBB));
333 // FIXME: Pass in the MachineBasicBlocks instead of the basic blocks...
334 MI->addPCDispOperand(PN->getIncomingBlock(i)); // PredMBB
342 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
343 /// register, then move it to wherever the result should be.
344 /// We handle FP setcc instructions by pushing them, doing a
345 /// compare-and-pop-twice, and then copying the concodes to the main
346 /// processor's concodes (I didn't make this up, it's in the Intel manual)
348 void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
349 // The arguments are already supposed to be of the same type.
350 const Type *CompTy = I.getOperand(0)->getType();
351 unsigned reg1 = getReg(I.getOperand(0));
352 unsigned reg2 = getReg(I.getOperand(1));
354 unsigned Class = getClass(CompTy);
356 // Emit: cmp <var1>, <var2> (do the comparison). We can
357 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
360 BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
363 BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
366 BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
369 // Push the variables on the stack with fldl opcodes.
370 // FIXME: assuming var1, var2 are in memory, if not, spill to
372 case cFloat: // Floats
373 BuildMI (BB, X86::FLDr32, 1).addReg (reg1);
374 BuildMI (BB, X86::FLDr32, 1).addReg (reg2);
376 case cDouble: // Doubles
377 BuildMI (BB, X86::FLDr64, 1).addReg (reg1);
378 BuildMI (BB, X86::FLDr64, 1).addReg (reg2);
385 if (CompTy->isFloatingPoint()) {
386 // (Non-trapping) compare and pop twice.
387 BuildMI (BB, X86::FUCOMPP, 0);
388 // Move fp status word (concodes) to ax.
389 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
390 // Load real concodes from ax.
391 BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
394 // Emit setOp instruction (extract concode; clobbers ax),
395 // using the following mapping:
396 // LLVM -> X86 signed X86 unsigned
398 // seteq -> sete sete
399 // setne -> setne setne
400 // setlt -> setl setb
401 // setgt -> setg seta
402 // setle -> setle setbe
403 // setge -> setge setae
405 static const unsigned OpcodeTab[2][6] = {
406 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
407 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
410 BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
412 // Put it in the result using a move.
413 BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
416 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
417 /// operand, in the specified target register.
419 ISel::promote32 (unsigned targetReg, Value *v)
421 unsigned vReg = getReg (v);
422 unsigned Class = getClass (v->getType ());
423 bool isUnsigned = v->getType ()->isUnsigned ();
424 assert (((Class == cByte) || (Class == cShort) || (Class == cInt))
425 && "Unpromotable operand class in promote32");
429 // Extend value into target register (8->32)
431 BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg);
433 BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg);
436 // Extend value into target register (16->32)
438 BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg);
440 BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg);
443 // Move value into target register (32->32)
444 BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg);
449 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
450 /// we have the following possibilities:
452 /// ret void: No return value, simply emit a 'ret' instruction
453 /// ret sbyte, ubyte : Extend value into EAX and return
454 /// ret short, ushort: Extend value into EAX and return
455 /// ret int, uint : Move value into EAX and return
456 /// ret pointer : Move value into EAX and return
457 /// ret long, ulong : Move value into EAX/EDX and return
458 /// ret float/double : Top of FP stack
461 ISel::visitReturnInst (ReturnInst &I)
463 if (I.getNumOperands () == 0)
465 // Emit a 'ret' instruction
466 BuildMI (BB, X86::RET, 0);
469 Value *rv = I.getOperand (0);
470 unsigned Class = getClass (rv->getType ());
473 // integral return values: extend or move into EAX and return.
477 promote32 (X86::EAX, rv);
479 // ret float/double: top of FP stack
481 case cFloat: // Floats
482 BuildMI (BB, X86::FLDr32, 1).addReg (getReg (rv));
484 case cDouble: // Doubles
485 BuildMI (BB, X86::FLDr64, 1).addReg (getReg (rv));
488 // ret long: use EAX(least significant 32 bits)/EDX (most
489 // significant 32)...uh, I think so Brain, but how do i call
490 // up the two parts of the value from inside this mouse
493 visitInstruction (I);
495 // Emit a 'ret' instruction
496 BuildMI (BB, X86::RET, 0);
499 /// visitBranchInst - Handle conditional and unconditional branches here. Note
500 /// that since code layout is frozen at this point, that if we are trying to
501 /// jump to a block that is the immediate successor of the current block, we can
502 /// just make a fall-through. (but we don't currently).
505 ISel::visitBranchInst (BranchInst & BI)
507 if (BI.isConditional ())
509 BasicBlock *ifTrue = BI.getSuccessor (0);
510 BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
512 // simplest thing I can think of: compare condition with zero,
513 // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
515 unsigned int condReg = getReg (BI.getCondition ());
516 BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
517 BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
518 BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
520 else // unconditional branch
522 BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
526 /// visitCallInst - Push args on stack and do a procedure call instruction.
528 ISel::visitCallInst (CallInst & CI)
530 // keep a counter of how many bytes we pushed on the stack
531 unsigned bytesPushed = 0;
533 // Push the arguments on the stack in reverse order, as specified by
535 for (unsigned i = CI.getNumOperands()-1; i >= 1; --i)
537 Value *v = CI.getOperand (i);
538 switch (getClass (v->getType ()))
542 // Promote V to 32 bits wide, and move the result into EAX,
544 promote32 (X86::EAX, v);
545 BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
550 unsigned Reg = getReg(v);
551 BuildMI (BB, X86::PUSHr32, 1).addReg(Reg);
556 // FIXME: long/ulong/double args not handled.
557 visitInstruction (CI);
561 // Emit a CALL instruction with PC-relative displacement.
562 BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ());
564 // Adjust the stack by `bytesPushed' amount if non-zero
566 BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed);
568 // If there is a return value, scavenge the result from the location the call
571 if (CI.getType() != Type::VoidTy) {
572 unsigned resultTypeClass = getClass (CI.getType ());
573 switch (resultTypeClass) {
577 // Integral results are in %eax, or the appropriate portion
579 static const unsigned regRegMove[] = {
580 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
582 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
583 BuildMI (BB, regRegMove[resultTypeClass], 1,
584 getReg (CI)).addReg (AReg[resultTypeClass]);
588 // Floating-point return values live in %st(0) (i.e., the top of
589 // the FP stack.) The general way to approach this is to do a
590 // FSTP to save the top of the FP stack on the real stack, then
591 // do a MOV to load the top of the real stack into the target
593 visitInstruction (CI); // FIXME: add the right args for the calls below
594 // BuildMI (BB, X86::FSTPm32, 0);
595 // BuildMI (BB, X86::MOVmr32, 0);
598 std::cerr << "Cannot get return value for call of type '"
599 << *CI.getType() << "'\n";
600 visitInstruction(CI);
605 /// visitSimpleBinary - Implement simple binary operators for integral types...
606 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
609 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
610 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
613 unsigned Class = getClass(B.getType());
614 if (Class > 2) // FIXME: Handle longs
617 static const unsigned OpcodeTab[][4] = {
618 // Arithmetic operators
619 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
620 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
623 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
624 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
625 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
628 unsigned Opcode = OpcodeTab[OperatorClass][Class];
629 unsigned Op0r = getReg(B.getOperand(0));
630 unsigned Op1r = getReg(B.getOperand(1));
631 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
634 /// doMultiply - Emit appropriate instructions to multiply together
635 /// the registers op0Reg and op1Reg, and put the result in destReg.
636 /// The type of the result should be given as resultType.
638 ISel::doMultiply(unsigned destReg, const Type *resultType,
639 unsigned op0Reg, unsigned op1Reg)
641 unsigned Class = getClass (resultType);
644 assert (Class <= 2 && "Someday, we will learn how to multiply"
645 "longs and floating-point numbers. This is not that day.");
647 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
648 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
649 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
650 unsigned Reg = Regs[Class];
652 // Emit a MOV to put the first operand into the appropriately-sized
654 BuildMI (BB, MovOpcode[Class], 1, Reg).addReg (op0Reg);
656 // Emit the appropriate multiply instruction.
657 BuildMI (BB, MulOpcode[Class], 1).addReg (op1Reg);
659 // Emit another MOV to put the result into the destination register.
660 BuildMI (BB, MovOpcode[Class], 1, destReg).addReg (Reg);
663 /// visitMul - Multiplies are not simple binary operators because they must deal
664 /// with the EAX register explicitly.
666 void ISel::visitMul(BinaryOperator &I) {
667 doMultiply (getReg (I), I.getType (),
668 getReg (I.getOperand (0)), getReg (I.getOperand (1)));
672 /// visitDivRem - Handle division and remainder instructions... these
673 /// instruction both require the same instructions to be generated, they just
674 /// select the result from a different register. Note that both of these
675 /// instructions work differently for signed and unsigned operands.
677 void ISel::visitDivRem(BinaryOperator &I) {
678 unsigned Class = getClass(I.getType());
679 if (Class > 2) // FIXME: Handle longs
682 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
683 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
684 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
685 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
686 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
688 static const unsigned DivOpcode[][4] = {
689 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
690 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
693 bool isSigned = I.getType()->isSigned();
694 unsigned Reg = Regs[Class];
695 unsigned ExtReg = ExtRegs[Class];
696 unsigned Op0Reg = getReg(I.getOperand(0));
697 unsigned Op1Reg = getReg(I.getOperand(1));
699 // Put the first operand into one of the A registers...
700 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
703 // Emit a sign extension instruction...
704 BuildMI(BB, ExtOpcode[Class], 0);
706 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
707 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
710 // Emit the appropriate divide or remainder instruction...
711 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
713 // Figure out which register we want to pick the result out of...
714 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
716 // Put the result into the destination register...
717 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
721 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
722 /// for constant immediate shift values, and for constant immediate
723 /// shift values equal to 1. Even the general case is sort of special,
724 /// because the shift amount has to be in CL, not just any old register.
726 void ISel::visitShiftInst (ShiftInst &I) {
727 unsigned Op0r = getReg (I.getOperand(0));
728 unsigned DestReg = getReg(I);
729 bool isLeftShift = I.getOpcode() == Instruction::Shl;
730 bool isOperandSigned = I.getType()->isUnsigned();
731 unsigned OperandClass = getClass(I.getType());
733 if (OperandClass > 2)
734 visitInstruction(I); // Can't handle longs yet!
736 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
738 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
739 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
740 unsigned char shAmt = CUI->getValue();
742 static const unsigned ConstantOperand[][4] = {
743 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
744 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
745 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
746 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
749 const unsigned *OpTab = // Figure out the operand table to use
750 ConstantOperand[isLeftShift*2+isOperandSigned];
752 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
753 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
757 // The shift amount is non-constant.
759 // In fact, you can only shift with a variable shift amount if
760 // that amount is already in the CL register, so we have to put it
764 // Emit: move cl, shiftAmount (put the shift amount in CL.)
765 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
767 // This is a shift right (SHR).
768 static const unsigned NonConstantOperand[][4] = {
769 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
770 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
771 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
772 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
775 const unsigned *OpTab = // Figure out the operand table to use
776 NonConstantOperand[isLeftShift*2+isOperandSigned];
778 BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
783 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
786 void ISel::visitLoadInst(LoadInst &I) {
787 unsigned Class = getClass(I.getType());
788 if (Class > 2) // FIXME: Handle longs and others...
791 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
793 unsigned AddressReg = getReg(I.getOperand(0));
794 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
798 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
801 void ISel::visitStoreInst(StoreInst &I) {
802 unsigned Class = getClass(I.getOperand(0)->getType());
803 if (Class > 2) // FIXME: Handle longs and others...
806 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
808 unsigned ValReg = getReg(I.getOperand(0));
809 unsigned AddressReg = getReg(I.getOperand(1));
810 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
814 /// visitCastInst - Here we have various kinds of copying with or without
815 /// sign extension going on.
817 ISel::visitCastInst (CastInst &CI)
819 const Type *targetType = CI.getType ();
820 Value *operand = CI.getOperand (0);
821 unsigned int operandReg = getReg (operand);
822 const Type *sourceType = operand->getType ();
823 unsigned int destReg = getReg (CI);
825 // Currently we handle:
829 // 2) cast {sbyte, ubyte} to {sbyte, ubyte}
830 // cast {short, ushort} to {ushort, short}
831 // cast {int, uint, ptr} to {int, uint, ptr}
833 // 3) cast {sbyte, ubyte} to {ushort, short}
834 // cast {sbyte, ubyte} to {int, uint, ptr}
835 // cast {short, ushort} to {int, uint, ptr}
837 // 4) cast {int, uint, ptr} to {short, ushort}
838 // cast {int, uint, ptr} to {sbyte, ubyte}
839 // cast {short, ushort} to {sbyte, ubyte}
841 // 1) Implement casts to bool by using compare on the operand followed
842 // by set if not zero on the result.
843 if (targetType == Type::BoolTy)
845 BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
846 BuildMI (BB, X86::SETNEr, 1, destReg);
849 // 2) Implement casts between values of the same type class (as determined
850 // by getClass) by using a register-to-register move.
851 unsigned int srcClass = getClass (sourceType);
852 unsigned int targClass = getClass (targetType);
853 static const unsigned regRegMove[] = {
854 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
856 if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass))
858 BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg);
861 // 3) Handle cast of SMALLER int to LARGER int using a move with sign
862 // extension or zero extension, depending on whether the source type
864 if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass))
866 static const unsigned ops[] = {
867 X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16,
868 X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16
870 unsigned srcSigned = sourceType->isSigned ();
871 BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1,
872 destReg).addReg (operandReg);
875 // 4) Handle cast of LARGER int to SMALLER int using a move to EAX
876 // followed by a move out of AX or AL.
877 if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass))
879 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
880 BuildMI (BB, regRegMove[srcClass], 1,
881 AReg[srcClass]).addReg (operandReg);
882 BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]);
885 // Anything we haven't handled already, we can't (yet) handle at all.
887 // FP to integral casts can be handled with FISTP to store onto the
888 // stack while converting to integer, followed by a MOV to load from
889 // the stack into the result register. Integral to FP casts can be
890 // handled with MOV to store onto the stack, followed by a FILD to
891 // load from the stack while converting to FP. For the moment, I
892 // can't quite get straight in my head how to borrow myself some
893 // stack space and write on it. Otherwise, this would be trivial.
894 visitInstruction (CI);
897 /// visitGetElementPtrInst - I don't know, most programs don't have
898 /// getelementptr instructions, right? That means we can put off
899 /// implementing this, right? Right. This method emits machine
900 /// instructions to perform type-safe pointer arithmetic. I am
901 /// guessing this could be cleaned up somewhat to use fewer temporary
904 ISel::visitGetElementPtrInst (GetElementPtrInst &I)
906 emitGEPOperation(BB, BB->end(), I.getOperand(0),
907 I.op_begin()+1, I.op_end(), getReg(I));
910 void ISel::emitGEPOperation(MachineBasicBlock *BB,
911 MachineBasicBlock::iterator IP,
912 Value *Src, User::op_iterator IdxBegin,
913 User::op_iterator IdxEnd, unsigned TargetReg) {
914 const TargetData &TD = TM.getTargetData();
915 const Type *Ty = Src->getType();
916 unsigned basePtrReg = getReg(Src);
918 // GEPs have zero or more indices; we must perform a struct access
919 // or array access for each one.
920 for (GetElementPtrInst::op_iterator oi = IdxBegin,
921 oe = IdxEnd; oi != oe; ++oi) {
923 unsigned nextBasePtrReg = makeAnotherReg(Type::UIntTy);
924 if (const StructType *StTy = dyn_cast <StructType> (Ty)) {
925 // It's a struct access. idx is the index into the structure,
926 // which names the field. This index must have ubyte type.
927 const ConstantUInt *CUI = cast <ConstantUInt> (idx);
928 assert (CUI->getType () == Type::UByteTy
929 && "Funny-looking structure index in GEP");
930 // Use the TargetData structure to pick out what the layout of
931 // the structure is in memory. Since the structure index must
932 // be constant, we can get its value and use it to find the
933 // right byte offset from the StructLayout class's list of
934 // structure member offsets.
935 unsigned idxValue = CUI->getValue ();
936 unsigned memberOffset =
937 TD.getStructLayout (StTy)->MemberOffsets[idxValue];
938 // Emit an ADD to add memberOffset to the basePtr.
939 BuildMI (BB, X86::ADDri32, 2,
940 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
941 // The next type is the member of the structure selected by the
943 Ty = StTy->getElementTypes ()[idxValue];
944 } else if (const SequentialType *SqTy = cast <SequentialType> (Ty)) {
945 // It's an array or pointer access: [ArraySize x ElementType].
946 const Type *typeOfSequentialTypeIndex = SqTy->getIndexType ();
947 // idx is the index into the array. Unlike with structure
948 // indices, we may not know its actual value at code-generation
950 assert (idx->getType () == typeOfSequentialTypeIndex
951 && "Funny-looking array index in GEP");
952 // We want to add basePtrReg to (idxReg * sizeof
953 // ElementType). First, we must find the size of the pointed-to
954 // type. (Not coincidentally, the next type is the type of the
955 // elements in the array.)
956 Ty = SqTy->getElementType ();
957 unsigned elementSize = TD.getTypeSize (Ty);
958 unsigned elementSizeReg = makeAnotherReg(Type::UIntTy);
959 copyConstantToRegister(ConstantInt::get(typeOfSequentialTypeIndex,
960 elementSize), elementSizeReg,
963 unsigned idxReg = getReg (idx);
964 // Emit a MUL to multiply the register holding the index by
965 // elementSize, putting the result in memberOffsetReg.
966 unsigned memberOffsetReg = makeAnotherReg(Type::UIntTy);
967 doMultiply (memberOffsetReg, typeOfSequentialTypeIndex,
968 elementSizeReg, idxReg);
969 // Emit an ADD to add memberOffsetReg to the basePtr.
970 BuildMI (BB, X86::ADDrr32, 2,
971 nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg);
973 // Now that we are here, further indices refer to subtypes of this
974 // one, so we don't need to worry about basePtrReg itself, anymore.
975 basePtrReg = nextBasePtrReg;
977 // After we have processed all the indices, the result is left in
978 // basePtrReg. Move it to the register where we were expected to
979 // put the answer. A 32-bit move should do it, because we are in
981 BuildMI (BB, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg);
985 /// visitMallocInst - I know that personally, whenever I want to remember
986 /// something, I have to clear off some space in my brain.
988 ISel::visitMallocInst (MallocInst &I)
990 // We assume that by this point, malloc instructions have been
991 // lowered to calls, and dlsym will magically find malloc for us.
992 // So we do not want to see malloc instructions here.
993 visitInstruction (I);
997 /// visitFreeInst - same story as MallocInst
999 ISel::visitFreeInst (FreeInst &I)
1001 // We assume that by this point, free instructions have been
1002 // lowered to calls, and dlsym will magically find free for us.
1003 // So we do not want to see free instructions here.
1004 visitInstruction (I);
1008 /// visitAllocaInst - I want some stack space. Come on, man, I said I
1009 /// want some freakin' stack space.
1011 ISel::visitAllocaInst (AllocaInst &I)
1013 // Find the data size of the alloca inst's getAllocatedType.
1014 const Type *allocatedType = I.getAllocatedType ();
1015 const TargetData &TD = TM.DataLayout;
1016 unsigned allocatedTypeSize = TD.getTypeSize (allocatedType);
1017 // Keep stack 32-bit aligned.
1018 unsigned int allocatedTypeWords = allocatedTypeSize / 4;
1019 if (allocatedTypeSize % 4 != 0) { allocatedTypeWords++; }
1020 // Subtract size from stack pointer, thereby allocating some space.
1021 BuildMI (BB, X86::SUBri32, 1, X86::ESP).addZImm (allocatedTypeWords * 4);
1022 // Put a pointer to the space into the result register, by copying
1023 // the stack pointer.
1024 BuildMI (BB, X86::MOVrr32, 1, getReg (I)).addReg (X86::ESP);
1028 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
1029 /// into a machine code representation is a very simple peep-hole fashion. The
1030 /// generated code sucks but the implementation is nice and simple.
1032 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
1033 return new ISel(TM);