1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Support/InstVisitor.h"
24 #include "llvm/Target/MRegisterInfo.h"
27 using namespace MOTy; // Get Use, Def, UseAndDef
30 /// BMI - A special BuildMI variant that takes an iterator to insert the
31 /// instruction at as well as a basic block.
32 /// this is the version for when you have a destination register in mind.
33 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
34 MachineBasicBlock::iterator &I,
38 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
39 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
40 I = ++MBB->insert(I, MI);
41 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
44 /// BMI - A special BuildMI variant that takes an iterator to insert the
45 /// instruction at as well as a basic block.
46 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
47 MachineBasicBlock::iterator &I,
49 unsigned NumOperands) {
50 assert(I > MBB->begin() && I <= MBB->end() && "Bad iterator!");
51 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
52 I = ++MBB->insert(I, MI);
53 return MachineInstrBuilder(MI);
58 struct ISel : public FunctionPass, InstVisitor<ISel> {
60 MachineFunction *F; // The function we are compiling into
61 MachineBasicBlock *BB; // The current MBB we are compiling
64 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
66 // MBBMap - Mapping between LLVM BB -> Machine BB
67 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
69 ISel(TargetMachine &tm)
70 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
72 /// runOnFunction - Top level implementation of instruction selection for
73 /// the entire function.
75 bool runOnFunction(Function &Fn) {
76 F = &MachineFunction::construct(&Fn, TM);
78 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
79 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
81 // Instruction select everything except PHI nodes
84 // Select the PHI nodes
89 CurReg = MRegisterInfo::FirstVirtualRegister;
91 return false; // We never modify the LLVM itself.
94 virtual const char *getPassName() const {
95 return "X86 Simple Instruction Selection";
98 /// visitBasicBlock - This method is called when we are visiting a new basic
99 /// block. This simply creates a new MachineBasicBlock to emit code into
100 /// and adds it to the current MachineFunction. Subsequent visit* for
101 /// instructions will be invoked for all instructions in the basic block.
103 void visitBasicBlock(BasicBlock &LLVM_BB) {
104 BB = MBBMap[&LLVM_BB];
108 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
109 /// because we have to generate our sources into the source basic blocks,
110 /// not the current one.
112 void SelectPHINodes();
114 // Visitation methods for various instructions. These methods simply emit
115 // fixed X86 code for each instruction.
118 // Control flow operators
119 void visitReturnInst(ReturnInst &RI);
120 void visitBranchInst(BranchInst &BI);
121 void visitCallInst(CallInst &I);
123 // Arithmetic operators
124 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
125 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
126 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
127 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
128 unsigned destReg, const Type *resultType,
129 unsigned op0Reg, unsigned op1Reg);
130 void visitMul(BinaryOperator &B);
132 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
133 void visitRem(BinaryOperator &B) { visitDivRem(B); }
134 void visitDivRem(BinaryOperator &B);
137 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
138 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
139 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
141 // Binary comparison operators
142 void visitSetCCInst(SetCondInst &I, unsigned OpNum);
143 void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
144 void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
145 void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
146 void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
147 void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
148 void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
150 // Memory Instructions
151 void visitLoadInst(LoadInst &I);
152 void visitStoreInst(StoreInst &I);
153 void visitGetElementPtrInst(GetElementPtrInst &I);
154 void visitMallocInst(MallocInst &I);
155 void visitFreeInst(FreeInst &I);
156 void visitAllocaInst(AllocaInst &I);
159 void visitShiftInst(ShiftInst &I);
160 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
161 void visitCastInst(CastInst &I);
163 void visitInstruction(Instruction &I) {
164 std::cerr << "Cannot instruction select: " << I;
168 /// promote32 - Make a value 32-bits wide, and put it somewhere.
169 void promote32 (const unsigned targetReg, Value *v);
171 // emitGEPOperation - Common code shared between visitGetElementPtrInst and
172 // constant expression GEP support.
174 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
175 Value *Src, User::op_iterator IdxBegin,
176 User::op_iterator IdxEnd, unsigned TargetReg);
178 /// copyConstantToRegister - Output the instructions required to put the
179 /// specified constant into the specified register.
181 void copyConstantToRegister(MachineBasicBlock *MBB,
182 MachineBasicBlock::iterator &MBBI,
183 Constant *C, unsigned Reg);
185 /// makeAnotherReg - This method returns the next register number
186 /// we haven't yet used.
187 unsigned makeAnotherReg(const Type *Ty) {
188 // Add the mapping of regnumber => reg class to MachineFunction
189 F->addRegMap(CurReg, TM.getRegisterInfo()->getRegClassForType(Ty));
193 /// getReg - This method turns an LLVM value into a register number. This
194 /// is guaranteed to produce the same register number for a particular value
195 /// every time it is queried.
197 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
198 unsigned getReg(Value *V) {
199 // Just append to the end of the current bb.
200 MachineBasicBlock::iterator It = BB->end();
201 return getReg(V, BB, It);
203 unsigned getReg(Value *V, MachineBasicBlock *MBB,
204 MachineBasicBlock::iterator &IPt) {
205 unsigned &Reg = RegMap[V];
207 Reg = makeAnotherReg(V->getType());
211 // If this operand is a constant, emit the code to copy the constant into
212 // the register here...
214 if (Constant *C = dyn_cast<Constant>(V)) {
215 copyConstantToRegister(MBB, IPt, C, Reg);
216 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
217 // Move the address of the global into the register
218 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addReg(GV);
219 } else if (Argument *A = dyn_cast<Argument>(V)) {
220 // Find the position of the argument in the argument list.
221 const Function *f = F->getFunction ();
222 // The function's arguments look like this:
223 // [EBP] -- copy of old EBP
224 // [EBP + 4] -- return address
225 // [EBP + 8] -- first argument (leftmost lexically)
226 // So we want to start with counter = 2.
227 int counter = 2, argPos = -1;
228 for (Function::const_aiterator ai = f->abegin (), ae = f->aend ();
232 break; // Only need to find it once. ;-)
237 && "Argument not found in current function's argument list");
238 // Load it out of the stack frame at EBP + 4*argPos.
239 addRegOffset(BMI(MBB, IPt, X86::MOVmr32, 4, Reg), X86::EBP, 4*argPos);
247 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
251 cByte, cShort, cInt, cLong, cFloat, cDouble
254 /// getClass - Turn a primitive type into a "class" number which is based on the
255 /// size of the type, and whether or not it is floating point.
257 static inline TypeClass getClass(const Type *Ty) {
258 switch (Ty->getPrimitiveID()) {
259 case Type::SByteTyID:
260 case Type::UByteTyID: return cByte; // Byte operands are class #0
261 case Type::ShortTyID:
262 case Type::UShortTyID: return cShort; // Short operands are class #1
265 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
268 case Type::ULongTyID: //return cLong; // Longs are class #3
269 return cInt; // FIXME: LONGS ARE TREATED AS INTS!
271 case Type::FloatTyID: return cFloat; // Float is class #4
272 case Type::DoubleTyID: return cDouble; // Doubles are class #5
274 assert(0 && "Invalid type to getClass!");
275 return cByte; // not reached
279 // getClassB - Just like getClass, but treat boolean values as bytes.
280 static inline TypeClass getClassB(const Type *Ty) {
281 if (Ty == Type::BoolTy) return cByte;
286 /// copyConstantToRegister - Output the instructions required to put the
287 /// specified constant into the specified register.
289 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
290 MachineBasicBlock::iterator &IP,
291 Constant *C, unsigned R) {
292 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
293 if (CE->getOpcode() == Instruction::GetElementPtr) {
294 emitGEPOperation(MBB, IP, CE->getOperand(0),
295 CE->op_begin()+1, CE->op_end(), R);
299 std::cerr << "Offending expr: " << C << "\n";
300 assert (0 && "Constant expressions not yet handled!\n");
303 if (C->getType()->isIntegral()) {
304 unsigned Class = getClassB(C->getType());
305 assert(Class != 3 && "Type not handled yet!");
307 static const unsigned IntegralOpcodeTab[] = {
308 X86::MOVir8, X86::MOVir16, X86::MOVir32
311 if (C->getType() == Type::BoolTy) {
312 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
313 } else if (C->getType()->isSigned()) {
314 ConstantSInt *CSI = cast<ConstantSInt>(C);
315 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
317 ConstantUInt *CUI = cast<ConstantUInt>(C);
318 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
320 } else if (isa<ConstantPointerNull>(C)) {
321 // Copy zero (null pointer) to the register.
322 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
323 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
324 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
325 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
327 std::cerr << "Offending constant: " << C << "\n";
328 assert(0 && "Type not handled yet!");
332 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
333 /// because we have to generate our sources into the source basic blocks, not
336 void ISel::SelectPHINodes() {
337 const Function &LF = *F->getFunction(); // The LLVM function...
338 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
339 const BasicBlock *BB = I;
340 MachineBasicBlock *MBB = MBBMap[I];
342 // Loop over all of the PHI nodes in the LLVM basic block...
343 unsigned NumPHIs = 0;
344 for (BasicBlock::const_iterator I = BB->begin();
345 PHINode *PN = (PHINode*)dyn_cast<PHINode>(&*I); ++I) {
346 // Create a new machine instr PHI node, and insert it.
347 MachineInstr *MI = BuildMI(X86::PHI, PN->getNumOperands(), getReg(*PN));
348 MBB->insert(MBB->begin()+NumPHIs++, MI); // Insert it at the top of the BB
350 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
351 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
353 // Get the incoming value into a virtual register. If it is not already
354 // available in a virtual register, insert the computation code into
358 MachineBasicBlock::iterator PI = PredMBB->begin();
359 while ((*PI)->getOpcode() == X86::PHI) ++PI;
361 MI->addRegOperand(getReg(PN->getIncomingValue(i), PredMBB, PI));
362 MI->addMachineBasicBlockOperand(PredMBB);
370 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
371 /// register, then move it to wherever the result should be.
372 /// We handle FP setcc instructions by pushing them, doing a
373 /// compare-and-pop-twice, and then copying the concodes to the main
374 /// processor's concodes (I didn't make this up, it's in the Intel manual)
376 void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
377 // The arguments are already supposed to be of the same type.
378 const Type *CompTy = I.getOperand(0)->getType();
379 unsigned reg1 = getReg(I.getOperand(0));
380 unsigned reg2 = getReg(I.getOperand(1));
382 unsigned Class = getClass(CompTy);
384 // Emit: cmp <var1>, <var2> (do the comparison). We can
385 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
388 BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
391 BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
394 BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
397 // Push the variables on the stack with fldl opcodes.
398 // FIXME: assuming var1, var2 are in memory, if not, spill to
400 case cFloat: // Floats
401 BuildMI (BB, X86::FLDr32, 1).addReg (reg1);
402 BuildMI (BB, X86::FLDr32, 1).addReg (reg2);
404 case cDouble: // Doubles
405 BuildMI (BB, X86::FLDr64, 1).addReg (reg1);
406 BuildMI (BB, X86::FLDr64, 1).addReg (reg2);
413 if (CompTy->isFloatingPoint()) {
414 // (Non-trapping) compare and pop twice.
415 BuildMI (BB, X86::FUCOMPP, 0);
416 // Move fp status word (concodes) to ax.
417 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
418 // Load real concodes from ax.
419 BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
422 // Emit setOp instruction (extract concode; clobbers ax),
423 // using the following mapping:
424 // LLVM -> X86 signed X86 unsigned
426 // seteq -> sete sete
427 // setne -> setne setne
428 // setlt -> setl setb
429 // setgt -> setg seta
430 // setle -> setle setbe
431 // setge -> setge setae
433 static const unsigned OpcodeTab[2][6] = {
434 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
435 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
438 BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
440 // Put it in the result using a move.
441 BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
444 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
445 /// operand, in the specified target register.
447 ISel::promote32 (unsigned targetReg, Value *v)
449 unsigned vReg = getReg (v);
450 unsigned Class = getClass (v->getType ());
451 bool isUnsigned = v->getType ()->isUnsigned ();
452 assert (((Class == cByte) || (Class == cShort) || (Class == cInt))
453 && "Unpromotable operand class in promote32");
457 // Extend value into target register (8->32)
459 BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg);
461 BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg);
464 // Extend value into target register (16->32)
466 BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg);
468 BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg);
471 // Move value into target register (32->32)
472 BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg);
477 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
478 /// we have the following possibilities:
480 /// ret void: No return value, simply emit a 'ret' instruction
481 /// ret sbyte, ubyte : Extend value into EAX and return
482 /// ret short, ushort: Extend value into EAX and return
483 /// ret int, uint : Move value into EAX and return
484 /// ret pointer : Move value into EAX and return
485 /// ret long, ulong : Move value into EAX/EDX and return
486 /// ret float/double : Top of FP stack
489 ISel::visitReturnInst (ReturnInst &I)
491 if (I.getNumOperands () == 0)
493 // Emit a 'ret' instruction
494 BuildMI (BB, X86::RET, 0);
497 Value *rv = I.getOperand (0);
498 unsigned Class = getClass (rv->getType ());
501 // integral return values: extend or move into EAX and return.
505 promote32 (X86::EAX, rv);
507 // ret float/double: top of FP stack
509 case cFloat: // Floats
510 BuildMI (BB, X86::FLDr32, 1).addReg (getReg (rv));
512 case cDouble: // Doubles
513 BuildMI (BB, X86::FLDr64, 1).addReg (getReg (rv));
516 // ret long: use EAX(least significant 32 bits)/EDX (most
517 // significant 32)...uh, I think so Brain, but how do i call
518 // up the two parts of the value from inside this mouse
521 visitInstruction (I);
523 // Emit a 'ret' instruction
524 BuildMI (BB, X86::RET, 0);
527 /// visitBranchInst - Handle conditional and unconditional branches here. Note
528 /// that since code layout is frozen at this point, that if we are trying to
529 /// jump to a block that is the immediate successor of the current block, we can
530 /// just make a fall-through. (but we don't currently).
533 ISel::visitBranchInst (BranchInst & BI)
535 if (BI.isConditional ())
537 BasicBlock *ifTrue = BI.getSuccessor (0);
538 BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
540 // simplest thing I can think of: compare condition with zero,
541 // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
543 unsigned int condReg = getReg (BI.getCondition ());
544 BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
545 BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
546 BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
548 else // unconditional branch
550 BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
554 /// visitCallInst - Push args on stack and do a procedure call instruction.
556 ISel::visitCallInst (CallInst & CI)
558 // keep a counter of how many bytes we pushed on the stack
559 unsigned bytesPushed = 0;
561 // Push the arguments on the stack in reverse order, as specified by
563 for (unsigned i = CI.getNumOperands()-1; i >= 1; --i)
565 Value *v = CI.getOperand (i);
566 switch (getClass (v->getType ()))
570 // Promote V to 32 bits wide, and move the result into EAX,
572 promote32 (X86::EAX, v);
573 BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
578 unsigned Reg = getReg(v);
579 BuildMI (BB, X86::PUSHr32, 1).addReg(Reg);
584 // FIXME: long/ulong/double args not handled.
585 visitInstruction (CI);
590 if (Function *F = CI.getCalledFunction()) {
591 // Emit a CALL instruction with PC-relative displacement.
592 BuildMI(BB, X86::CALLpcrel32, 1).addPCDisp(F);
594 unsigned Reg = getReg(CI.getCalledValue());
595 BuildMI(BB, X86::CALLr32, 1).addReg(Reg);
598 // Adjust the stack by `bytesPushed' amount if non-zero
600 BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed);
602 // If there is a return value, scavenge the result from the location the call
605 if (CI.getType() != Type::VoidTy) {
606 unsigned resultTypeClass = getClass (CI.getType ());
607 switch (resultTypeClass) {
611 // Integral results are in %eax, or the appropriate portion
613 static const unsigned regRegMove[] = {
614 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
616 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
617 BuildMI (BB, regRegMove[resultTypeClass], 1,
618 getReg (CI)).addReg (AReg[resultTypeClass]);
622 // Floating-point return values live in %st(0) (i.e., the top of
623 // the FP stack.) The general way to approach this is to do a
624 // FSTP to save the top of the FP stack on the real stack, then
625 // do a MOV to load the top of the real stack into the target
627 visitInstruction (CI); // FIXME: add the right args for the calls below
628 // BuildMI (BB, X86::FSTPm32, 0);
629 // BuildMI (BB, X86::MOVmr32, 0);
632 std::cerr << "Cannot get return value for call of type '"
633 << *CI.getType() << "'\n";
634 visitInstruction(CI);
639 /// visitSimpleBinary - Implement simple binary operators for integral types...
640 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
643 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
644 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
647 unsigned Class = getClass(B.getType());
648 if (Class > 2) // FIXME: Handle longs
651 static const unsigned OpcodeTab[][4] = {
652 // Arithmetic operators
653 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
654 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
657 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
658 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
659 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
662 unsigned Opcode = OpcodeTab[OperatorClass][Class];
663 unsigned Op0r = getReg(B.getOperand(0));
664 unsigned Op1r = getReg(B.getOperand(1));
665 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
668 /// doMultiply - Emit appropriate instructions to multiply together
669 /// the registers op0Reg and op1Reg, and put the result in destReg.
670 /// The type of the result should be given as resultType.
671 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
672 unsigned destReg, const Type *resultType,
673 unsigned op0Reg, unsigned op1Reg) {
674 unsigned Class = getClass (resultType);
677 assert (Class <= 2 && "Someday, we will learn how to multiply"
678 "longs and floating-point numbers. This is not that day.");
680 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
681 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
682 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
683 unsigned Reg = Regs[Class];
685 // Emit a MOV to put the first operand into the appropriately-sized
687 BMI(MBB, MBBI, MovOpcode[Class], 1, Reg).addReg (op0Reg);
689 // Emit the appropriate multiply instruction.
690 BMI(MBB, MBBI, MulOpcode[Class], 1).addReg (op1Reg);
692 // Emit another MOV to put the result into the destination register.
693 BMI(MBB, MBBI, MovOpcode[Class], 1, destReg).addReg (Reg);
696 /// visitMul - Multiplies are not simple binary operators because they must deal
697 /// with the EAX register explicitly.
699 void ISel::visitMul(BinaryOperator &I) {
700 unsigned DestReg = getReg(I);
701 unsigned Op0Reg = getReg(I.getOperand(0));
702 unsigned Op1Reg = getReg(I.getOperand(1));
703 MachineBasicBlock::iterator MBBI = BB->end();
704 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
708 /// visitDivRem - Handle division and remainder instructions... these
709 /// instruction both require the same instructions to be generated, they just
710 /// select the result from a different register. Note that both of these
711 /// instructions work differently for signed and unsigned operands.
713 void ISel::visitDivRem(BinaryOperator &I) {
714 unsigned Class = getClass(I.getType());
715 if (Class > 2) // FIXME: Handle longs
718 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
719 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
720 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
721 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
722 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
724 static const unsigned DivOpcode[][4] = {
725 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
726 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
729 bool isSigned = I.getType()->isSigned();
730 unsigned Reg = Regs[Class];
731 unsigned ExtReg = ExtRegs[Class];
732 unsigned Op0Reg = getReg(I.getOperand(0));
733 unsigned Op1Reg = getReg(I.getOperand(1));
735 // Put the first operand into one of the A registers...
736 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
739 // Emit a sign extension instruction...
740 BuildMI(BB, ExtOpcode[Class], 0);
742 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
743 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
746 // Emit the appropriate divide or remainder instruction...
747 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
749 // Figure out which register we want to pick the result out of...
750 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
752 // Put the result into the destination register...
753 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
757 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
758 /// for constant immediate shift values, and for constant immediate
759 /// shift values equal to 1. Even the general case is sort of special,
760 /// because the shift amount has to be in CL, not just any old register.
762 void ISel::visitShiftInst (ShiftInst &I) {
763 unsigned Op0r = getReg (I.getOperand(0));
764 unsigned DestReg = getReg(I);
765 bool isLeftShift = I.getOpcode() == Instruction::Shl;
766 bool isOperandSigned = I.getType()->isUnsigned();
767 unsigned OperandClass = getClass(I.getType());
769 if (OperandClass > 2)
770 visitInstruction(I); // Can't handle longs yet!
772 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
774 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
775 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
776 unsigned char shAmt = CUI->getValue();
778 static const unsigned ConstantOperand[][4] = {
779 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
780 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
781 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
782 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
785 const unsigned *OpTab = // Figure out the operand table to use
786 ConstantOperand[isLeftShift*2+isOperandSigned];
788 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
789 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
793 // The shift amount is non-constant.
795 // In fact, you can only shift with a variable shift amount if
796 // that amount is already in the CL register, so we have to put it
800 // Emit: move cl, shiftAmount (put the shift amount in CL.)
801 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
803 // This is a shift right (SHR).
804 static const unsigned NonConstantOperand[][4] = {
805 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
806 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
807 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
808 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
811 const unsigned *OpTab = // Figure out the operand table to use
812 NonConstantOperand[isLeftShift*2+isOperandSigned];
814 BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
819 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
822 void ISel::visitLoadInst(LoadInst &I) {
823 unsigned Class = getClass(I.getType());
824 if (Class > 2) // FIXME: Handle longs and others...
827 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
829 unsigned AddressReg = getReg(I.getOperand(0));
830 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
834 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
837 void ISel::visitStoreInst(StoreInst &I) {
838 unsigned Class = getClass(I.getOperand(0)->getType());
839 if (Class > 2) // FIXME: Handle longs and others...
842 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
844 unsigned ValReg = getReg(I.getOperand(0));
845 unsigned AddressReg = getReg(I.getOperand(1));
846 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
850 /// visitCastInst - Here we have various kinds of copying with or without
851 /// sign extension going on.
853 ISel::visitCastInst (CastInst &CI)
855 const Type *targetType = CI.getType ();
856 Value *operand = CI.getOperand (0);
857 unsigned int operandReg = getReg (operand);
858 const Type *sourceType = operand->getType ();
859 unsigned int destReg = getReg (CI);
861 // Currently we handle:
865 // 2) cast {sbyte, ubyte} to {sbyte, ubyte}
866 // cast {short, ushort} to {ushort, short}
867 // cast {int, uint, ptr} to {int, uint, ptr}
869 // 3) cast {sbyte, ubyte} to {ushort, short}
870 // cast {sbyte, ubyte} to {int, uint, ptr}
871 // cast {short, ushort} to {int, uint, ptr}
873 // 4) cast {int, uint, ptr} to {short, ushort}
874 // cast {int, uint, ptr} to {sbyte, ubyte}
875 // cast {short, ushort} to {sbyte, ubyte}
877 // 1) Implement casts to bool by using compare on the operand followed
878 // by set if not zero on the result.
879 if (targetType == Type::BoolTy)
881 BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
882 BuildMI (BB, X86::SETNEr, 1, destReg);
886 // 2) Implement casts between values of the same type class (as determined
887 // by getClass) by using a register-to-register move.
888 unsigned srcClass = getClassB (sourceType);
889 unsigned targClass = getClass (targetType);
890 static const unsigned regRegMove[] = {
891 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
893 if ((srcClass < cLong) && (targClass < cLong) && (srcClass == targClass))
895 BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg);
898 // 3) Handle cast of SMALLER int to LARGER int using a move with sign
899 // extension or zero extension, depending on whether the source type
901 if ((srcClass < cLong) && (targClass < cLong) && (srcClass < targClass))
903 static const unsigned ops[] = {
904 X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16,
905 X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16
907 unsigned srcSigned = sourceType->isSigned ();
908 BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1,
909 destReg).addReg (operandReg);
912 // 4) Handle cast of LARGER int to SMALLER int using a move to EAX
913 // followed by a move out of AX or AL.
914 if ((srcClass < cLong) && (targClass < cLong) && (srcClass > targClass))
916 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
917 BuildMI (BB, regRegMove[srcClass], 1,
918 AReg[srcClass]).addReg (operandReg);
919 BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]);
922 // Anything we haven't handled already, we can't (yet) handle at all.
924 // FP to integral casts can be handled with FISTP to store onto the
925 // stack while converting to integer, followed by a MOV to load from
926 // the stack into the result register. Integral to FP casts can be
927 // handled with MOV to store onto the stack, followed by a FILD to
928 // load from the stack while converting to FP. For the moment, I
929 // can't quite get straight in my head how to borrow myself some
930 // stack space and write on it. Otherwise, this would be trivial.
931 visitInstruction (CI);
934 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
935 // returns zero when the input is not exactly a power of two.
936 static unsigned ExactLog2(unsigned Val) {
937 if (Val == 0) return 0;
940 if (Val & 1) return 0;
947 /// visitGetElementPtrInst - I don't know, most programs don't have
948 /// getelementptr instructions, right? That means we can put off
949 /// implementing this, right? Right. This method emits machine
950 /// instructions to perform type-safe pointer arithmetic. I am
951 /// guessing this could be cleaned up somewhat to use fewer temporary
954 ISel::visitGetElementPtrInst (GetElementPtrInst &I)
956 unsigned outputReg = getReg (I);
957 MachineBasicBlock::iterator MI = BB->end();
958 emitGEPOperation(BB, MI, I.getOperand(0),
959 I.op_begin()+1, I.op_end(), outputReg);
962 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
963 MachineBasicBlock::iterator &IP,
964 Value *Src, User::op_iterator IdxBegin,
965 User::op_iterator IdxEnd, unsigned TargetReg) {
966 const TargetData &TD = TM.getTargetData();
967 const Type *Ty = Src->getType();
968 unsigned basePtrReg = getReg(Src, MBB, IP);
970 // GEPs have zero or more indices; we must perform a struct access
971 // or array access for each one.
972 for (GetElementPtrInst::op_iterator oi = IdxBegin,
973 oe = IdxEnd; oi != oe; ++oi) {
975 unsigned nextBasePtrReg = makeAnotherReg(Type::UIntTy);
976 if (const StructType *StTy = dyn_cast <StructType> (Ty)) {
977 // It's a struct access. idx is the index into the structure,
978 // which names the field. This index must have ubyte type.
979 const ConstantUInt *CUI = cast <ConstantUInt> (idx);
980 assert (CUI->getType () == Type::UByteTy
981 && "Funny-looking structure index in GEP");
982 // Use the TargetData structure to pick out what the layout of
983 // the structure is in memory. Since the structure index must
984 // be constant, we can get its value and use it to find the
985 // right byte offset from the StructLayout class's list of
986 // structure member offsets.
987 unsigned idxValue = CUI->getValue ();
988 unsigned memberOffset =
989 TD.getStructLayout (StTy)->MemberOffsets[idxValue];
990 // Emit an ADD to add memberOffset to the basePtr.
991 BMI(MBB, IP, X86::ADDri32, 2,
992 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
993 // The next type is the member of the structure selected by the
995 Ty = StTy->getElementTypes ()[idxValue];
996 } else if (const SequentialType *SqTy = cast <SequentialType>(Ty)) {
997 // It's an array or pointer access: [ArraySize x ElementType].
999 // idx is the index into the array. Unlike with structure
1000 // indices, we may not know its actual value at code-generation
1002 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
1004 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
1005 // must find the size of the pointed-to type (Not coincidentally, the next
1006 // type is the type of the elements in the array).
1007 Ty = SqTy->getElementType();
1008 unsigned elementSize = TD.getTypeSize(Ty);
1010 // If idxReg is a constant, we don't need to perform the multiply!
1011 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
1012 if (CSI->isNullValue()) {
1013 BMI(MBB, IP, X86::MOVrr32, 1, nextBasePtrReg).addReg(basePtrReg);
1015 unsigned Offset = elementSize*CSI->getValue();
1017 BMI(MBB, IP, X86::ADDri32, 2,
1018 nextBasePtrReg).addReg(basePtrReg).addZImm(Offset);
1020 } else if (elementSize == 1) {
1021 // If the element size is 1, we don't have to multiply, just add
1022 unsigned idxReg = getReg(idx, MBB, IP);
1023 BMI(MBB, IP, X86::ADDrr32, 2,
1024 nextBasePtrReg).addReg(basePtrReg).addReg(idxReg);
1026 unsigned idxReg = getReg(idx, MBB, IP);
1027 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
1028 if (unsigned Shift = ExactLog2(elementSize)) {
1029 // If the element size is exactly a power of 2, use a shift to get it.
1031 BMI(MBB, IP, X86::SHLir32, 2,
1032 OffsetReg).addReg(idxReg).addZImm(Shift-1);
1034 // Most general case, emit a multiply...
1035 unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
1036 BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
1038 // Emit a MUL to multiply the register holding the index by
1039 // elementSize, putting the result in OffsetReg.
1040 doMultiply(MBB, IP, OffsetReg, Type::LongTy, idxReg, elementSizeReg);
1042 // Emit an ADD to add OffsetReg to the basePtr.
1043 BMI(MBB, IP, X86::ADDrr32, 2,
1044 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
1047 // Now that we are here, further indices refer to subtypes of this
1048 // one, so we don't need to worry about basePtrReg itself, anymore.
1049 basePtrReg = nextBasePtrReg;
1051 // After we have processed all the indices, the result is left in
1052 // basePtrReg. Move it to the register where we were expected to
1053 // put the answer. A 32-bit move should do it, because we are in
1055 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg);
1059 /// visitMallocInst - I know that personally, whenever I want to remember
1060 /// something, I have to clear off some space in my brain.
1062 ISel::visitMallocInst (MallocInst &I)
1064 // We assume that by this point, malloc instructions have been
1065 // lowered to calls, and dlsym will magically find malloc for us.
1066 // So we do not want to see malloc instructions here.
1067 visitInstruction (I);
1071 /// visitFreeInst - same story as MallocInst
1073 ISel::visitFreeInst (FreeInst &I)
1075 // We assume that by this point, free instructions have been
1076 // lowered to calls, and dlsym will magically find free for us.
1077 // So we do not want to see free instructions here.
1078 visitInstruction (I);
1082 /// visitAllocaInst - I want some stack space. Come on, man, I said I
1083 /// want some freakin' stack space.
1085 ISel::visitAllocaInst (AllocaInst &I)
1087 // Find the data size of the alloca inst's getAllocatedType.
1088 const Type *allocatedType = I.getAllocatedType ();
1089 const TargetData &TD = TM.DataLayout;
1090 unsigned allocatedTypeSize = TD.getTypeSize (allocatedType);
1091 // Keep stack 32-bit aligned.
1092 unsigned int allocatedTypeWords = allocatedTypeSize / 4;
1093 if (allocatedTypeSize % 4 != 0) { allocatedTypeWords++; }
1094 // Subtract size from stack pointer, thereby allocating some space.
1095 BuildMI(BB, X86::SUBri32, 2,
1096 X86::ESP).addReg(X86::ESP).addZImm(allocatedTypeWords * 4);
1097 // Put a pointer to the space into the result register, by copying
1098 // the stack pointer.
1099 BuildMI (BB, X86::MOVrr32, 1, getReg (I)).addReg (X86::ESP);
1103 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
1104 /// into a machine code representation is a very simple peep-hole fashion. The
1105 /// generated code sucks but the implementation is nice and simple.
1107 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
1108 return new ISel(TM);