1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "llvm/Function.h"
10 #include "llvm/iTerminators.h"
11 #include "llvm/iOther.h"
12 #include "llvm/iPHINode.h"
13 #include "llvm/Type.h"
14 #include "llvm/Constants.h"
15 #include "llvm/Pass.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/Support/InstVisitor.h"
22 struct ISel : public FunctionPass, InstVisitor<ISel> {
24 MachineFunction *F; // The function we are compiling into
25 MachineBasicBlock *BB; // The current MBB we are compiling
28 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
30 ISel(TargetMachine &tm)
31 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
33 /// runOnFunction - Top level implementation of instruction selection for
34 /// the entire function.
36 bool runOnFunction(Function &Fn) {
37 F = &MachineFunction::construct(&Fn, TM);
41 return false; // We never modify the LLVM itself.
44 /// visitBasicBlock - This method is called when we are visiting a new basic
45 /// block. This simply creates a new MachineBasicBlock to emit code into
46 /// and adds it to the current MachineFunction. Subsequent visit* for
47 /// instructions will be invoked for all instructions in the basic block.
49 void visitBasicBlock(BasicBlock &LLVM_BB) {
50 BB = new MachineBasicBlock(&LLVM_BB);
51 // FIXME: Use the auto-insert form when it's available
52 F->getBasicBlockList().push_back(BB);
55 // Visitation methods for various instructions. These methods simply emit
56 // fixed X86 code for each instruction.
58 void visitReturnInst(ReturnInst &RI);
59 void visitBranchInst(BranchInst &BI);
61 // Arithmetic operators
62 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
63 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
66 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
67 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
68 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
69 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
71 // Binary comparison operators
74 void visitShiftInst(ShiftInst &I);
75 void visitPHINode(PHINode &I);
77 void visitInstruction(Instruction &I) {
78 std::cerr << "Cannot instruction select: " << I;
83 /// copyConstantToRegister - Output the instructions required to put the
84 /// specified constant into the specified register.
86 void copyConstantToRegister(Constant *C, unsigned Reg);
88 /// getReg - This method turns an LLVM value into a register number. This
89 /// is guaranteed to produce the same register number for a particular value
90 /// every time it is queried.
92 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
93 unsigned getReg(Value *V) {
94 unsigned &Reg = RegMap[V];
98 // If this operand is a constant, emit the code to copy the constant into
99 // the register here...
101 if (Constant *C = dyn_cast<Constant>(V))
102 copyConstantToRegister(C, Reg);
109 /// getClass - Turn a primitive type into a "class" number which is based on the
110 /// size of the type, and whether or not it is floating point.
112 static inline unsigned getClass(const Type *Ty) {
113 switch (Ty->getPrimitiveID()) {
114 case Type::SByteTyID:
115 case Type::UByteTyID: return 0; // Byte operands are class #0
116 case Type::ShortTyID:
117 case Type::UShortTyID: return 1; // Short operands are class #1
120 case Type::PointerTyID: return 2; // Int's and pointers are class #2
123 case Type::ULongTyID: return 3; // Longs are class #3
124 case Type::FloatTyID: return 4; // Float is class #4
125 case Type::DoubleTyID: return 5; // Doubles are class #5
127 assert(0 && "Invalid type to getClass!");
128 return 0; // not reached
132 /// copyConstantToRegister - Output the instructions required to put the
133 /// specified constant into the specified register.
135 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
136 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
138 if (C->getType()->isIntegral()) {
139 unsigned Class = getClass(C->getType());
140 assert(Class != 3 && "Type not handled yet!");
142 static const unsigned IntegralOpcodeTab[] = {
143 X86::MOVir8, X86::MOVir16, X86::MOVir32
146 if (C->getType()->isSigned()) {
147 ConstantSInt *CSI = cast<ConstantSInt>(C);
148 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
150 ConstantUInt *CUI = cast<ConstantUInt>(C);
151 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
154 assert(0 && "Type not handled yet!");
160 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
161 /// we have the following possibilities:
163 /// ret void: No return value, simply emit a 'ret' instruction
164 /// ret sbyte, ubyte : Extend value into EAX and return
165 /// ret short, ushort: Extend value into EAX and return
166 /// ret int, uint : Move value into EAX and return
167 /// ret pointer : Move value into EAX and return
168 /// ret long, ulong : Move value into EAX/EDX (?) and return
169 /// ret float/double : ? Top of FP stack? XMM0?
171 void ISel::visitReturnInst(ReturnInst &I) {
172 if (I.getNumOperands() != 0) { // Not 'ret void'?
173 // Move result into a hard register... then emit a ret
174 visitInstruction(I); // abort
177 // Emit a simple 'ret' instruction... appending it to the end of the basic
179 BuildMI(BB, X86::RET, 0);
182 /// visitBranchInst - Handle conditional and unconditional branches here. Note
183 /// that since code layout is frozen at this point, that if we are trying to
184 /// jump to a block that is the immediate successor of the current block, we can
185 /// just make a fall-through. (but we don't currently).
187 void ISel::visitBranchInst(BranchInst &BI) {
188 if (BI.isConditional()) // Only handles unconditional branches so far...
189 visitInstruction(BI);
191 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
195 /// visitSimpleBinary - Implement simple binary operators for integral types...
196 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
199 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
200 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
203 unsigned Class = getClass(B.getType());
204 if (Class > 2) // FIXME: Handle longs
207 static const unsigned OpcodeTab[][4] = {
208 // Arithmetic operators
209 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
210 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
213 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
214 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
215 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
218 unsigned Opcode = OpcodeTab[OperatorClass][Class];
219 unsigned Op0r = getReg(B.getOperand(0));
220 unsigned Op1r = getReg(B.getOperand(1));
221 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
226 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
227 /// for constant immediate shift values, and for constant immediate
228 /// shift values equal to 1. Even the general case is sort of special,
229 /// because the shift amount has to be in CL, not just any old register.
232 ISel::visitShiftInst (ShiftInst & I)
234 unsigned Op0r = getReg (I.getOperand (0));
235 unsigned DestReg = getReg (I);
236 bool isLeftShift = I.getOpcode() == Instruction::Shl;
237 bool isOperandSigned = I.getType()->isUnsigned();
238 unsigned OperandClass = getClass(I.getType());
240 if (OperandClass > 2)
241 visitInstruction(I); // Can't handle longs yet!
243 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
245 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
246 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
247 unsigned char shAmt = CUI->getValue();
249 static const unsigned ConstantOperand[][4] = {
250 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
251 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
252 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
253 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
256 const unsigned *OpTab = // Figure out the operand table to use
257 ConstantOperand[isLeftShift*2+isOperandSigned];
259 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
260 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
264 // The shift amount is non-constant.
266 // In fact, you can only shift with a variable shift amount if
267 // that amount is already in the CL register, so we have to put it
271 // Emit: move cl, shiftAmount (put the shift amount in CL.)
272 BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg(getReg(I.getOperand(1)));
274 // This is a shift right (SHR).
275 static const unsigned NonConstantOperand[][4] = {
276 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
277 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
278 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
279 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
282 const unsigned *OpTab = // Figure out the operand table to use
283 NonConstantOperand[isLeftShift*2+isOperandSigned];
285 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
289 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
291 void ISel::visitPHINode(PHINode &PN) {
292 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
294 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
295 // FIXME: This will put constants after the PHI nodes in the block, which
296 // is invalid. They should be put inline into the PHI node eventually.
298 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
299 MI->addPCDispOperand(PN.getIncomingBlock(i));
304 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
305 /// into a machine code representation is a very simple peep-hole fashion. The
306 /// generated code sucks but the implementation is nice and simple.
308 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {