1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 target
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/Instructions.h"
12 #include "llvm/DerivedTypes.h"
13 #include "llvm/Constants.h"
14 #include "llvm/Pass.h"
15 #include "llvm/Intrinsics.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/SSARegMap.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/InstVisitor.h"
25 /// BMI - A special BuildMI variant that takes an iterator to insert the
26 /// instruction at as well as a basic block. This is the version for when you
27 /// have a destination register in mind.
28 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
29 MachineBasicBlock::iterator &I,
30 int Opcode, unsigned NumOperands,
32 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
33 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
34 I = MBB->insert(I, MI)+1;
35 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
38 /// BMI - A special BuildMI variant that takes an iterator to insert the
39 /// instruction at as well as a basic block.
40 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
41 MachineBasicBlock::iterator &I,
42 int Opcode, unsigned NumOperands) {
43 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
44 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
45 I = MBB->insert(I, MI)+1;
46 return MachineInstrBuilder(MI);
51 struct ISel : public FunctionPass, InstVisitor<ISel> {
53 MachineFunction *F; // The function we are compiling into
54 MachineBasicBlock *BB; // The current MBB we are compiling
55 int VarArgsFrameIndex; // FrameIndex for start of varargs area
57 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
59 // MBBMap - Mapping between LLVM BB -> Machine BB
60 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
62 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
64 /// runOnFunction - Top level implementation of instruction selection for
65 /// the entire function.
67 bool runOnFunction(Function &Fn) {
68 F = &MachineFunction::construct(&Fn, TM);
70 // Create all of the machine basic blocks for the function...
71 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
72 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
76 // Copy incoming arguments off of the stack...
77 LoadArgumentsToVirtualRegs(Fn);
79 // Instruction select everything except PHI nodes
82 // Select the PHI nodes
88 // We always build a machine code representation for the function
92 virtual const char *getPassName() const {
93 return "X86 Simple Instruction Selection";
96 /// visitBasicBlock - This method is called when we are visiting a new basic
97 /// block. This simply creates a new MachineBasicBlock to emit code into
98 /// and adds it to the current MachineFunction. Subsequent visit* for
99 /// instructions will be invoked for all instructions in the basic block.
101 void visitBasicBlock(BasicBlock &LLVM_BB) {
102 BB = MBBMap[&LLVM_BB];
105 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
106 /// from the stack into virtual registers.
108 void LoadArgumentsToVirtualRegs(Function &F);
110 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
111 /// because we have to generate our sources into the source basic blocks,
112 /// not the current one.
114 void SelectPHINodes();
116 // Visitation methods for various instructions. These methods simply emit
117 // fixed X86 code for each instruction.
120 // Control flow operators
121 void visitReturnInst(ReturnInst &RI);
122 void visitBranchInst(BranchInst &BI);
128 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
129 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
131 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
132 const std::vector<ValueRecord> &Args);
133 void visitCallInst(CallInst &I);
134 void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
136 // Arithmetic operators
137 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
138 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
139 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
140 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
141 unsigned DestReg, const Type *DestTy,
142 unsigned Op0Reg, unsigned Op1Reg);
143 void doMultiplyConst(MachineBasicBlock *MBB,
144 MachineBasicBlock::iterator &MBBI,
145 unsigned DestReg, const Type *DestTy,
146 unsigned Op0Reg, unsigned Op1Val);
147 void visitMul(BinaryOperator &B);
149 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
150 void visitRem(BinaryOperator &B) { visitDivRem(B); }
151 void visitDivRem(BinaryOperator &B);
154 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
155 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
156 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
158 // Comparison operators...
159 void visitSetCondInst(SetCondInst &I);
160 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
161 MachineBasicBlock *MBB,
162 MachineBasicBlock::iterator &MBBI);
164 // Memory Instructions
165 void visitLoadInst(LoadInst &I);
166 void visitStoreInst(StoreInst &I);
167 void visitGetElementPtrInst(GetElementPtrInst &I);
168 void visitAllocaInst(AllocaInst &I);
169 void visitMallocInst(MallocInst &I);
170 void visitFreeInst(FreeInst &I);
173 void visitShiftInst(ShiftInst &I);
174 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
175 void visitCastInst(CastInst &I);
176 void visitVANextInst(VANextInst &I);
177 void visitVAArgInst(VAArgInst &I);
179 void visitInstruction(Instruction &I) {
180 std::cerr << "Cannot instruction select: " << I;
184 /// promote32 - Make a value 32-bits wide, and put it somewhere.
186 void promote32(unsigned targetReg, const ValueRecord &VR);
188 /// EmitByteSwap - Byteswap SrcReg into DestReg.
190 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
192 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
193 /// constant expression GEP support.
195 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
196 Value *Src, User::op_iterator IdxBegin,
197 User::op_iterator IdxEnd, unsigned TargetReg);
199 /// emitCastOperation - Common code shared between visitCastInst and
200 /// constant expression cast support.
201 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
202 Value *Src, const Type *DestTy, unsigned TargetReg);
204 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
205 /// and constant expression support.
206 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
207 MachineBasicBlock::iterator &IP,
208 Value *Op0, Value *Op1,
209 unsigned OperatorClass, unsigned TargetReg);
211 /// emitSetCCOperation - Common code shared between visitSetCondInst and
212 /// constant expression support.
213 void emitSetCCOperation(MachineBasicBlock *BB,
214 MachineBasicBlock::iterator &IP,
215 Value *Op0, Value *Op1, unsigned Opcode,
219 /// copyConstantToRegister - Output the instructions required to put the
220 /// specified constant into the specified register.
222 void copyConstantToRegister(MachineBasicBlock *MBB,
223 MachineBasicBlock::iterator &MBBI,
224 Constant *C, unsigned Reg);
226 /// makeAnotherReg - This method returns the next register number we haven't
229 /// Long values are handled somewhat specially. They are always allocated
230 /// as pairs of 32 bit integer values. The register number returned is the
231 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
232 /// of the long value.
234 unsigned makeAnotherReg(const Type *Ty) {
235 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
236 "Current target doesn't have X86 reg info??");
237 const X86RegisterInfo *MRI =
238 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
239 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
240 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
241 // Create the lower part
242 F->getSSARegMap()->createVirtualRegister(RC);
243 // Create the upper part.
244 return F->getSSARegMap()->createVirtualRegister(RC)-1;
247 // Add the mapping of regnumber => reg class to MachineFunction
248 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
249 return F->getSSARegMap()->createVirtualRegister(RC);
252 /// getReg - This method turns an LLVM value into a register number. This
253 /// is guaranteed to produce the same register number for a particular value
254 /// every time it is queried.
256 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
257 unsigned getReg(Value *V) {
258 // Just append to the end of the current bb.
259 MachineBasicBlock::iterator It = BB->end();
260 return getReg(V, BB, It);
262 unsigned getReg(Value *V, MachineBasicBlock *MBB,
263 MachineBasicBlock::iterator &IPt) {
264 unsigned &Reg = RegMap[V];
266 Reg = makeAnotherReg(V->getType());
270 // If this operand is a constant, emit the code to copy the constant into
271 // the register here...
273 if (Constant *C = dyn_cast<Constant>(V)) {
274 copyConstantToRegister(MBB, IPt, C, Reg);
275 RegMap.erase(V); // Assign a new name to this constant if ref'd again
276 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
277 // Move the address of the global into the register
278 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
279 RegMap.erase(V); // Assign a new name to this address if ref'd again
287 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
291 cByte, cShort, cInt, cFP, cLong
294 /// getClass - Turn a primitive type into a "class" number which is based on the
295 /// size of the type, and whether or not it is floating point.
297 static inline TypeClass getClass(const Type *Ty) {
298 switch (Ty->getPrimitiveID()) {
299 case Type::SByteTyID:
300 case Type::UByteTyID: return cByte; // Byte operands are class #0
301 case Type::ShortTyID:
302 case Type::UShortTyID: return cShort; // Short operands are class #1
305 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
307 case Type::FloatTyID:
308 case Type::DoubleTyID: return cFP; // Floating Point is #3
311 case Type::ULongTyID: return cLong; // Longs are class #4
313 assert(0 && "Invalid type to getClass!");
314 return cByte; // not reached
318 // getClassB - Just like getClass, but treat boolean values as bytes.
319 static inline TypeClass getClassB(const Type *Ty) {
320 if (Ty == Type::BoolTy) return cByte;
325 /// copyConstantToRegister - Output the instructions required to put the
326 /// specified constant into the specified register.
328 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
329 MachineBasicBlock::iterator &IP,
330 Constant *C, unsigned R) {
331 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
333 switch (CE->getOpcode()) {
334 case Instruction::GetElementPtr:
335 emitGEPOperation(MBB, IP, CE->getOperand(0),
336 CE->op_begin()+1, CE->op_end(), R);
338 case Instruction::Cast:
339 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
342 case Instruction::Xor: ++Class; // FALL THROUGH
343 case Instruction::Or: ++Class; // FALL THROUGH
344 case Instruction::And: ++Class; // FALL THROUGH
345 case Instruction::Sub: ++Class; // FALL THROUGH
346 case Instruction::Add:
347 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
351 case Instruction::SetNE:
352 case Instruction::SetEQ:
353 case Instruction::SetLT:
354 case Instruction::SetGT:
355 case Instruction::SetLE:
356 case Instruction::SetGE:
357 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
362 std::cerr << "Offending expr: " << C << "\n";
363 assert(0 && "Constant expression not yet handled!\n");
367 if (C->getType()->isIntegral()) {
368 unsigned Class = getClassB(C->getType());
370 if (Class == cLong) {
371 // Copy the value into the register pair.
372 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
373 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
374 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
378 assert(Class <= cInt && "Type not handled yet!");
380 static const unsigned IntegralOpcodeTab[] = {
381 X86::MOVir8, X86::MOVir16, X86::MOVir32
384 if (C->getType() == Type::BoolTy) {
385 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
387 ConstantInt *CI = cast<ConstantInt>(C);
388 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
390 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
391 double Value = CFP->getValue();
393 BMI(MBB, IP, X86::FLD0, 0, R);
394 else if (Value == +1.0)
395 BMI(MBB, IP, X86::FLD1, 0, R);
397 // Otherwise we need to spill the constant to memory...
398 MachineConstantPool *CP = F->getConstantPool();
399 unsigned CPI = CP->getConstantPoolIndex(CFP);
400 const Type *Ty = CFP->getType();
402 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
403 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
404 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
407 } else if (isa<ConstantPointerNull>(C)) {
408 // Copy zero (null pointer) to the register.
409 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
410 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
411 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
412 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
414 std::cerr << "Offending constant: " << C << "\n";
415 assert(0 && "Type not handled yet!");
419 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
420 /// the stack into virtual registers.
422 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
423 // Emit instructions to load the arguments... On entry to a function on the
424 // X86, the stack frame looks like this:
426 // [ESP] -- return address
427 // [ESP + 4] -- first argument (leftmost lexically)
428 // [ESP + 8] -- second argument, if first argument is four bytes in size
431 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
432 MachineFrameInfo *MFI = F->getFrameInfo();
434 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
435 unsigned Reg = getReg(*I);
437 int FI; // Frame object index
438 switch (getClassB(I->getType())) {
440 FI = MFI->CreateFixedObject(1, ArgOffset);
441 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
444 FI = MFI->CreateFixedObject(2, ArgOffset);
445 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
448 FI = MFI->CreateFixedObject(4, ArgOffset);
449 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
452 FI = MFI->CreateFixedObject(8, ArgOffset);
453 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
454 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
455 ArgOffset += 4; // longs require 4 additional bytes
459 if (I->getType() == Type::FloatTy) {
460 Opcode = X86::FLDr32;
461 FI = MFI->CreateFixedObject(4, ArgOffset);
463 Opcode = X86::FLDr64;
464 FI = MFI->CreateFixedObject(8, ArgOffset);
465 ArgOffset += 4; // doubles require 4 additional bytes
467 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
470 assert(0 && "Unhandled argument type!");
472 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
475 // If the function takes variable number of arguments, add a frame offset for
476 // the start of the first vararg value... this is used to expand
478 if (Fn.getFunctionType()->isVarArg())
479 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
483 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
484 /// because we have to generate our sources into the source basic blocks, not
487 void ISel::SelectPHINodes() {
488 const TargetInstrInfo &TII = TM.getInstrInfo();
489 const Function &LF = *F->getFunction(); // The LLVM function...
490 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
491 const BasicBlock *BB = I;
492 MachineBasicBlock *MBB = MBBMap[I];
494 // Loop over all of the PHI nodes in the LLVM basic block...
495 unsigned NumPHIs = 0;
496 for (BasicBlock::const_iterator I = BB->begin();
497 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
499 // Create a new machine instr PHI node, and insert it.
500 unsigned PHIReg = getReg(*PN);
501 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
502 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
504 MachineInstr *LongPhiMI = 0;
505 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
506 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
507 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
510 // PHIValues - Map of blocks to incoming virtual registers. We use this
511 // so that we only initialize one incoming value for a particular block,
512 // even if the block has multiple entries in the PHI node.
514 std::map<MachineBasicBlock*, unsigned> PHIValues;
516 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
517 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
519 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
520 PHIValues.lower_bound(PredMBB);
522 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
523 // We already inserted an initialization of the register for this
524 // predecessor. Recycle it.
525 ValReg = EntryIt->second;
528 // Get the incoming value into a virtual register.
530 Value *Val = PN->getIncomingValue(i);
532 // If this is a constant or GlobalValue, we may have to insert code
533 // into the basic block to compute it into a virtual register.
534 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
535 // Because we don't want to clobber any values which might be in
536 // physical registers with the computation of this constant (which
537 // might be arbitrarily complex if it is a constant expression),
538 // just insert the computation at the top of the basic block.
539 MachineBasicBlock::iterator PI = PredMBB->begin();
541 // Skip over any PHI nodes though!
542 while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
545 ValReg = getReg(Val, PredMBB, PI);
547 ValReg = getReg(Val);
550 // Remember that we inserted a value for this PHI for this predecessor
551 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
554 PhiMI->addRegOperand(ValReg);
555 PhiMI->addMachineBasicBlockOperand(PredMBB);
557 LongPhiMI->addRegOperand(ValReg+1);
558 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
565 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
566 // the conditional branch instruction which is the only user of the cc
567 // instruction. This is the case if the conditional branch is the only user of
568 // the setcc, and if the setcc is in the same basic block as the conditional
569 // branch. We also don't handle long arguments below, so we reject them here as
572 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
573 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
574 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
575 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
576 const Type *Ty = SCI->getOperand(0)->getType();
577 if (Ty != Type::LongTy && Ty != Type::ULongTy)
583 // Return a fixed numbering for setcc instructions which does not depend on the
584 // order of the opcodes.
586 static unsigned getSetCCNumber(unsigned Opcode) {
588 default: assert(0 && "Unknown setcc instruction!");
589 case Instruction::SetEQ: return 0;
590 case Instruction::SetNE: return 1;
591 case Instruction::SetLT: return 2;
592 case Instruction::SetGE: return 3;
593 case Instruction::SetGT: return 4;
594 case Instruction::SetLE: return 5;
598 // LLVM -> X86 signed X86 unsigned
599 // ----- ---------- ------------
600 // seteq -> sete sete
601 // setne -> setne setne
602 // setlt -> setl setb
603 // setge -> setge setae
604 // setgt -> setg seta
605 // setle -> setle setbe
607 // sets // Used by comparison with 0 optimization
609 static const unsigned SetCCOpcodeTab[2][8] = {
610 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
612 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
613 X86::SETSr, X86::SETNSr },
616 // EmitComparison - This function emits a comparison of the two operands,
617 // returning the extended setcc code to use.
618 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
619 MachineBasicBlock *MBB,
620 MachineBasicBlock::iterator &IP) {
621 // The arguments are already supposed to be of the same type.
622 const Type *CompTy = Op0->getType();
623 unsigned Class = getClassB(CompTy);
624 unsigned Op0r = getReg(Op0, MBB, IP);
626 // Special case handling of: cmp R, i
627 if (Class == cByte || Class == cShort || Class == cInt)
628 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
629 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
631 // Mask off any upper bits of the constant, if there are any...
632 Op1v &= (1ULL << (8 << Class)) - 1;
634 // If this is a comparison against zero, emit more efficient code. We
635 // can't handle unsigned comparisons against zero unless they are == or
636 // !=. These should have been strength reduced already anyway.
637 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
638 static const unsigned TESTTab[] = {
639 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
641 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
643 if (OpNum == 2) return 6; // Map jl -> js
644 if (OpNum == 3) return 7; // Map jg -> jns
648 static const unsigned CMPTab[] = {
649 X86::CMPri8, X86::CMPri16, X86::CMPri32
652 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
656 unsigned Op1r = getReg(Op1, MBB, IP);
658 default: assert(0 && "Unknown type class!");
659 // Emit: cmp <var1>, <var2> (do the comparison). We can
660 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
663 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
666 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
669 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
672 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
673 BMI(MBB, IP, X86::FNSTSWr8, 0);
674 BMI(MBB, IP, X86::SAHF, 1);
678 if (OpNum < 2) { // seteq, setne
679 unsigned LoTmp = makeAnotherReg(Type::IntTy);
680 unsigned HiTmp = makeAnotherReg(Type::IntTy);
681 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
682 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
683 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
684 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
685 break; // Allow the sete or setne to be generated from flags set by OR
687 // Emit a sequence of code which compares the high and low parts once
688 // each, then uses a conditional move to handle the overflow case. For
689 // example, a setlt for long would generate code like this:
691 // AL = lo(op1) < lo(op2) // Signedness depends on operands
692 // BL = hi(op1) < hi(op2) // Always unsigned comparison
693 // dest = hi(op1) == hi(op2) ? AL : BL;
696 // FIXME: This would be much better if we had hierarchical register
697 // classes! Until then, hardcode registers so that we can deal with their
698 // aliases (because we don't have conditional byte moves).
700 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
701 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
702 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
703 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
704 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
705 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
706 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
707 // NOTE: visitSetCondInst knows that the value is dumped into the BL
708 // register at this point for long values...
716 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
717 /// register, then move it to wherever the result should be.
719 void ISel::visitSetCondInst(SetCondInst &I) {
720 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
722 unsigned DestReg = getReg(I);
723 MachineBasicBlock::iterator MII = BB->end();
724 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
728 /// emitSetCCOperation - Common code shared between visitSetCondInst and
729 /// constant expression support.
730 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
731 MachineBasicBlock::iterator &IP,
732 Value *Op0, Value *Op1, unsigned Opcode,
733 unsigned TargetReg) {
734 unsigned OpNum = getSetCCNumber(Opcode);
735 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
737 const Type *CompTy = Op0->getType();
738 unsigned CompClass = getClassB(CompTy);
739 bool isSigned = CompTy->isSigned() && CompClass != cFP;
741 if (CompClass != cLong || OpNum < 2) {
742 // Handle normal comparisons with a setcc instruction...
743 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
745 // Handle long comparisons by copying the value which is already in BL into
746 // the register we want...
747 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
754 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
755 /// operand, in the specified target register.
756 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
757 bool isUnsigned = VR.Ty->isUnsigned();
759 // Make sure we have the register number for this value...
760 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
762 switch (getClassB(VR.Ty)) {
764 // Extend value into target register (8->32)
766 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
768 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
771 // Extend value into target register (16->32)
773 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
775 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
778 // Move value into target register (32->32)
779 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
782 assert(0 && "Unpromotable operand class in promote32");
786 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
787 /// we have the following possibilities:
789 /// ret void: No return value, simply emit a 'ret' instruction
790 /// ret sbyte, ubyte : Extend value into EAX and return
791 /// ret short, ushort: Extend value into EAX and return
792 /// ret int, uint : Move value into EAX and return
793 /// ret pointer : Move value into EAX and return
794 /// ret long, ulong : Move value into EAX/EDX and return
795 /// ret float/double : Top of FP stack
797 void ISel::visitReturnInst(ReturnInst &I) {
798 if (I.getNumOperands() == 0) {
799 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
803 Value *RetVal = I.getOperand(0);
804 unsigned RetReg = getReg(RetVal);
805 switch (getClassB(RetVal->getType())) {
806 case cByte: // integral return values: extend or move into EAX and return
809 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
810 // Declare that EAX is live on exit
811 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
813 case cFP: // Floats & Doubles: Return in ST(0)
814 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
815 // Declare that top-of-stack is live on exit
816 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
819 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
820 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
821 // Declare that EAX & EDX are live on exit
822 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP);
827 // Emit a 'ret' instruction
828 BuildMI(BB, X86::RET, 0);
831 // getBlockAfter - Return the basic block which occurs lexically after the
833 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
834 Function::iterator I = BB; ++I; // Get iterator to next block
835 return I != BB->getParent()->end() ? &*I : 0;
838 /// visitBranchInst - Handle conditional and unconditional branches here. Note
839 /// that since code layout is frozen at this point, that if we are trying to
840 /// jump to a block that is the immediate successor of the current block, we can
841 /// just make a fall-through (but we don't currently).
843 void ISel::visitBranchInst(BranchInst &BI) {
844 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
846 if (!BI.isConditional()) { // Unconditional branch?
847 if (BI.getSuccessor(0) != NextBB)
848 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
852 // See if we can fold the setcc into the branch itself...
853 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
855 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
856 // computed some other way...
857 unsigned condReg = getReg(BI.getCondition());
858 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
859 if (BI.getSuccessor(1) == NextBB) {
860 if (BI.getSuccessor(0) != NextBB)
861 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
863 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
865 if (BI.getSuccessor(0) != NextBB)
866 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
871 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
872 MachineBasicBlock::iterator MII = BB->end();
873 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB, MII);
875 const Type *CompTy = SCI->getOperand(0)->getType();
876 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
879 // LLVM -> X86 signed X86 unsigned
880 // ----- ---------- ------------
888 // js // Used by comparison with 0 optimization
891 static const unsigned OpcodeTab[2][8] = {
892 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
893 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
897 if (BI.getSuccessor(0) != NextBB) {
898 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
899 if (BI.getSuccessor(1) != NextBB)
900 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
902 // Change to the inverse condition...
903 if (BI.getSuccessor(1) != NextBB) {
905 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
911 /// doCall - This emits an abstract call instruction, setting up the arguments
912 /// and the return value as appropriate. For the actual function call itself,
913 /// it inserts the specified CallMI instruction into the stream.
915 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
916 const std::vector<ValueRecord> &Args) {
918 // Count how many bytes are to be pushed on the stack...
919 unsigned NumBytes = 0;
922 for (unsigned i = 0, e = Args.size(); i != e; ++i)
923 switch (getClassB(Args[i].Ty)) {
924 case cByte: case cShort: case cInt:
925 NumBytes += 4; break;
927 NumBytes += 8; break;
929 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
931 default: assert(0 && "Unknown class!");
934 // Adjust the stack pointer for the new arguments...
935 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
937 // Arguments go on the stack in reverse order, as specified by the ABI.
938 unsigned ArgOffset = 0;
939 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
940 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
941 switch (getClassB(Args[i].Ty)) {
944 // Promote arg to 32 bits wide into a temporary register...
945 unsigned R = makeAnotherReg(Type::UIntTy);
946 promote32(R, Args[i]);
947 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
948 X86::ESP, ArgOffset).addReg(R);
952 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
953 X86::ESP, ArgOffset).addReg(ArgReg);
956 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
957 X86::ESP, ArgOffset).addReg(ArgReg);
958 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
959 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
960 ArgOffset += 4; // 8 byte entry, not 4.
964 if (Args[i].Ty == Type::FloatTy) {
965 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
966 X86::ESP, ArgOffset).addReg(ArgReg);
968 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
969 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
970 X86::ESP, ArgOffset).addReg(ArgReg);
971 ArgOffset += 4; // 8 byte entry, not 4.
975 default: assert(0 && "Unknown class!");
980 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
983 BB->push_back(CallMI);
985 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
987 // If there is a return value, scavenge the result from the location the call
990 if (Ret.Ty != Type::VoidTy) {
991 unsigned DestClass = getClassB(Ret.Ty);
996 // Integral results are in %eax, or the appropriate portion
998 static const unsigned regRegMove[] = {
999 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1001 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1002 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1005 case cFP: // Floating-point return values live in %ST(0)
1006 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1008 case cLong: // Long values are left in EDX:EAX
1009 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1010 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1012 default: assert(0 && "Unknown class!");
1018 /// visitCallInst - Push args on stack and do a procedure call instruction.
1019 void ISel::visitCallInst(CallInst &CI) {
1020 MachineInstr *TheCall;
1021 if (Function *F = CI.getCalledFunction()) {
1022 // Is it an intrinsic function call?
1023 if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
1024 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1028 // Emit a CALL instruction with PC-relative displacement.
1029 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1030 } else { // Emit an indirect call...
1031 unsigned Reg = getReg(CI.getCalledValue());
1032 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1035 std::vector<ValueRecord> Args;
1036 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1037 Args.push_back(ValueRecord(CI.getOperand(i)));
1039 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1040 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1044 void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
1045 unsigned TmpReg1, TmpReg2;
1047 case LLVMIntrinsic::va_start:
1048 // Get the address of the first vararg value...
1049 TmpReg1 = getReg(CI);
1050 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1053 case LLVMIntrinsic::va_copy:
1054 TmpReg1 = getReg(CI);
1055 TmpReg2 = getReg(CI.getOperand(1));
1056 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1058 case LLVMIntrinsic::va_end: return; // Noop on X86
1060 case LLVMIntrinsic::longjmp:
1061 case LLVMIntrinsic::siglongjmp:
1062 BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true);
1065 case LLVMIntrinsic::setjmp:
1066 case LLVMIntrinsic::sigsetjmp:
1067 // Setjmp always returns zero...
1068 BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0);
1070 default: assert(0 && "Unknown intrinsic for X86!");
1075 /// visitSimpleBinary - Implement simple binary operators for integral types...
1076 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1078 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1079 unsigned DestReg = getReg(B);
1080 MachineBasicBlock::iterator MI = BB->end();
1081 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1082 OperatorClass, DestReg);
1085 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1086 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1089 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1090 /// and constant expression support.
1092 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1093 MachineBasicBlock::iterator &IP,
1094 Value *Op0, Value *Op1,
1095 unsigned OperatorClass, unsigned DestReg) {
1096 unsigned Class = getClassB(Op0->getType());
1098 // sub 0, X -> neg X
1099 if (OperatorClass == 1 && Class != cLong)
1100 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1101 if (CI->isNullValue()) {
1102 unsigned op1Reg = getReg(Op1, MBB, IP);
1104 default: assert(0 && "Unknown class for this function!");
1106 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1109 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1112 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1117 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1118 static const unsigned OpcodeTab[][4] = {
1119 // Arithmetic operators
1120 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1121 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1123 // Bitwise operators
1124 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1125 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1126 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1129 bool isLong = false;
1130 if (Class == cLong) {
1132 Class = cInt; // Bottom 32 bits are handled just like ints
1135 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1136 assert(Opcode && "Floating point arguments to logical inst?");
1137 unsigned Op0r = getReg(Op0, MBB, IP);
1138 unsigned Op1r = getReg(Op1, MBB, IP);
1139 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1141 if (isLong) { // Handle the upper 32 bits of long values...
1142 static const unsigned TopTab[] = {
1143 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1145 BMI(MBB, IP, TopTab[OperatorClass], 2,
1146 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1151 // Special case: op Reg, <const>
1152 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1153 unsigned Op0r = getReg(Op0, MBB, IP);
1155 // xor X, -1 -> not X
1156 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1157 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1158 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1162 // add X, -1 -> dec X
1163 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1164 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1165 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1169 // add X, 1 -> inc X
1170 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1171 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1172 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1176 static const unsigned OpcodeTab[][3] = {
1177 // Arithmetic operators
1178 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1179 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1181 // Bitwise operators
1182 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1183 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1184 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1187 assert(Class < 3 && "General code handles 64-bit integer types!");
1188 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1189 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1191 // Mask off any upper bits of the constant, if there are any...
1192 Op1v &= (1ULL << (8 << Class)) - 1;
1193 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1196 /// doMultiply - Emit appropriate instructions to multiply together the
1197 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1198 /// result should be given as DestTy.
1200 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1201 unsigned DestReg, const Type *DestTy,
1202 unsigned op0Reg, unsigned op1Reg) {
1203 unsigned Class = getClass(DestTy);
1205 case cFP: // Floating point multiply
1206 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1210 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1211 .addReg(op0Reg).addReg(op1Reg);
1214 // Must use the MUL instruction, which forces use of AL...
1215 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1216 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1217 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1220 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1224 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1225 // returns zero when the input is not exactly a power of two.
1226 static unsigned ExactLog2(unsigned Val) {
1227 if (Val == 0) return 0;
1230 if (Val & 1) return 0;
1237 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1238 MachineBasicBlock::iterator &IP,
1239 unsigned DestReg, const Type *DestTy,
1240 unsigned op0Reg, unsigned ConstRHS) {
1241 unsigned Class = getClass(DestTy);
1243 // If the element size is exactly a power of 2, use a shift to get it.
1244 if (unsigned Shift = ExactLog2(ConstRHS)) {
1246 default: assert(0 && "Unknown class for this function!");
1248 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1251 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1254 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1259 if (Class == cShort) {
1260 BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1262 } else if (Class == cInt) {
1263 BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1267 // Most general case, emit a normal multiply...
1268 static const unsigned MOVirTab[] = {
1269 X86::MOVir8, X86::MOVir16, X86::MOVir32
1272 unsigned TmpReg = makeAnotherReg(DestTy);
1273 BMI(MBB, IP, MOVirTab[Class], 1, TmpReg).addZImm(ConstRHS);
1275 // Emit a MUL to multiply the register holding the index by
1276 // elementSize, putting the result in OffsetReg.
1277 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1280 /// visitMul - Multiplies are not simple binary operators because they must deal
1281 /// with the EAX register explicitly.
1283 void ISel::visitMul(BinaryOperator &I) {
1284 unsigned Op0Reg = getReg(I.getOperand(0));
1285 unsigned DestReg = getReg(I);
1287 // Simple scalar multiply?
1288 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1289 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1290 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1291 MachineBasicBlock::iterator MBBI = BB->end();
1292 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1294 unsigned Op1Reg = getReg(I.getOperand(1));
1295 MachineBasicBlock::iterator MBBI = BB->end();
1296 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1299 unsigned Op1Reg = getReg(I.getOperand(1));
1301 // Long value. We have to do things the hard way...
1302 // Multiply the two low parts... capturing carry into EDX
1303 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1304 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1306 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1307 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1308 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1310 MachineBasicBlock::iterator MBBI = BB->end();
1311 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1312 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1314 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1315 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1316 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1319 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1320 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1322 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1323 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1328 /// visitDivRem - Handle division and remainder instructions... these
1329 /// instruction both require the same instructions to be generated, they just
1330 /// select the result from a different register. Note that both of these
1331 /// instructions work differently for signed and unsigned operands.
1333 void ISel::visitDivRem(BinaryOperator &I) {
1334 unsigned Class = getClass(I.getType());
1335 unsigned Op0Reg, Op1Reg, ResultReg = getReg(I);
1338 case cFP: // Floating point divide
1339 if (I.getOpcode() == Instruction::Div) {
1340 Op0Reg = getReg(I.getOperand(0));
1341 Op1Reg = getReg(I.getOperand(1));
1342 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1343 } else { // Floating point remainder...
1344 MachineInstr *TheCall =
1345 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1346 std::vector<ValueRecord> Args;
1347 Args.push_back(ValueRecord(I.getOperand(0)));
1348 Args.push_back(ValueRecord(I.getOperand(1)));
1349 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1353 static const char *FnName[] =
1354 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1356 unsigned NameIdx = I.getType()->isUnsigned()*2;
1357 NameIdx += I.getOpcode() == Instruction::Div;
1358 MachineInstr *TheCall =
1359 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1361 std::vector<ValueRecord> Args;
1362 Args.push_back(ValueRecord(I.getOperand(0)));
1363 Args.push_back(ValueRecord(I.getOperand(1)));
1364 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1367 case cByte: case cShort: case cInt:
1368 break; // Small integrals, handled below...
1369 default: assert(0 && "Unknown class!");
1372 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1373 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1374 static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
1375 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1376 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1378 static const unsigned DivOpcode[][4] = {
1379 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1380 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1383 bool isSigned = I.getType()->isSigned();
1384 unsigned Reg = Regs[Class];
1385 unsigned ExtReg = ExtRegs[Class];
1387 // Put the first operand into one of the A registers...
1388 Op0Reg = getReg(I.getOperand(0));
1389 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1392 // Emit a sign extension instruction...
1393 unsigned ShiftResult = makeAnotherReg(I.getType());
1394 BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1395 BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1397 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1398 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1401 // Emit the appropriate divide or remainder instruction...
1402 Op1Reg = getReg(I.getOperand(1));
1403 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1405 // Figure out which register we want to pick the result out of...
1406 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1408 // Put the result into the destination register...
1409 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1413 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1414 /// for constant immediate shift values, and for constant immediate
1415 /// shift values equal to 1. Even the general case is sort of special,
1416 /// because the shift amount has to be in CL, not just any old register.
1418 void ISel::visitShiftInst(ShiftInst &I) {
1419 unsigned SrcReg = getReg(I.getOperand(0));
1420 unsigned DestReg = getReg(I);
1421 bool isLeftShift = I.getOpcode() == Instruction::Shl;
1422 bool isSigned = I.getType()->isSigned();
1423 unsigned Class = getClass(I.getType());
1425 static const unsigned ConstantOperand[][4] = {
1426 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1427 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1428 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1429 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1432 static const unsigned NonConstantOperand[][4] = {
1433 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1434 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1435 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1436 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1439 // Longs, as usual, are handled specially...
1440 if (Class == cLong) {
1441 // If we have a constant shift, we can generate much more efficient code
1442 // than otherwise...
1444 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1445 unsigned Amount = CUI->getValue();
1447 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1449 BuildMI(BB, Opc[3], 3,
1450 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1451 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1453 BuildMI(BB, Opc[3], 3,
1454 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1455 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1457 } else { // Shifting more than 32 bits
1460 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1461 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1463 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1464 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1465 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1469 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1471 if (!isLeftShift && isSigned) {
1472 // If this is a SHR of a Long, then we need to do funny sign extension
1473 // stuff. TmpReg gets the value to use as the high-part if we are
1474 // shifting more than 32 bits.
1475 BuildMI(BB, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1477 // Other shifts use a fixed zero value if the shift is more than 32
1479 BuildMI(BB, X86::MOVir32, 1, TmpReg).addZImm(0);
1482 // Initialize CL with the shift amount...
1483 unsigned ShiftAmount = getReg(I.getOperand(1));
1484 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmount);
1486 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1487 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1489 // TmpReg2 = shld inHi, inLo
1490 BuildMI(BB, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1491 // TmpReg3 = shl inLo, CL
1492 BuildMI(BB, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1494 // Set the flags to indicate whether the shift was by more than 32 bits.
1495 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1497 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1498 BuildMI(BB, X86::CMOVNErr32, 2,
1499 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1500 // DestLo = (>32) ? TmpReg : TmpReg3;
1501 BuildMI(BB, X86::CMOVNErr32, 2, DestReg).addReg(TmpReg3).addReg(TmpReg);
1503 // TmpReg2 = shrd inLo, inHi
1504 BuildMI(BB, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1505 // TmpReg3 = s[ah]r inHi, CL
1506 BuildMI(BB, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1509 // Set the flags to indicate whether the shift was by more than 32 bits.
1510 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1512 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1513 BuildMI(BB, X86::CMOVNErr32, 2,
1514 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1516 // DestHi = (>32) ? TmpReg : TmpReg3;
1517 BuildMI(BB, X86::CMOVNErr32, 2,
1518 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1524 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1525 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1526 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1528 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1529 BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1530 } else { // The shift amount is non-constant.
1531 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
1533 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1534 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1539 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1541 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1542 // Emit the byte swap instruction...
1545 // No byteswap necessary for 8 bit value...
1546 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1549 // Use the 32 bit bswap instruction to do a 32 bit swap...
1550 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1554 // For 16 bit we have to use an xchg instruction, because there is no
1555 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1556 // into AX to do the xchg.
1558 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1559 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1560 .addReg(X86::AH, MOTy::UseAndDef);
1561 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1563 default: assert(0 && "Cannot byteswap this class!");
1568 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1569 /// instruction. The load and store instructions are the only place where we
1570 /// need to worry about the memory layout of the target machine.
1572 void ISel::visitLoadInst(LoadInst &I) {
1573 unsigned SrcAddrReg = getReg(I.getOperand(0));
1574 unsigned DestReg = getReg(I);
1576 unsigned Class = getClassB(I.getType());
1579 MachineBasicBlock::iterator MBBI = BB->end();
1580 assert(I.getType() == Type::FloatTy || I.getType() == Type::DoubleTy &&
1581 "Unknown FP type!");
1582 unsigned Opc = I.getType() == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
1583 addDirectMem(BMI(BB, MBBI, Opc, 4, DestReg), SrcAddrReg);
1586 case cLong: case cInt: case cShort: case cByte:
1587 break; // Integers of various sizes handled below
1588 default: assert(0 && "Unknown memory class!");
1591 unsigned IReg = DestReg;
1593 static const unsigned Opcode[] = {
1594 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
1596 addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
1598 // Handle long values now...
1600 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1603 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1606 void ISel::visitStoreInst(StoreInst &I) {
1607 unsigned ValReg = getReg(I.getOperand(0));
1608 unsigned AddressReg = getReg(I.getOperand(1));
1610 const Type *ValTy = I.getOperand(0)->getType();
1611 unsigned Class = getClassB(ValTy);
1614 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1615 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
1618 unsigned StoreOpcode = ValTy == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
1619 addDirectMem(BuildMI(BB, StoreOpcode, 5), AddressReg).addReg(ValReg);
1622 case cInt: case cShort: case cByte:
1623 break; // Integers of various sizes handled below
1624 default: assert(0 && "Unknown memory class!");
1627 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1628 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
1632 /// visitCastInst - Here we have various kinds of copying with or without
1633 /// sign extension going on.
1634 void ISel::visitCastInst(CastInst &CI) {
1635 Value *Op = CI.getOperand(0);
1636 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1637 // of the case are GEP instructions, then the cast does not need to be
1638 // generated explicitly, it will be folded into the GEP.
1639 if (CI.getType() == Type::LongTy &&
1640 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1641 bool AllUsesAreGEPs = true;
1642 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1643 if (!isa<GetElementPtrInst>(*I)) {
1644 AllUsesAreGEPs = false;
1648 // No need to codegen this cast if all users are getelementptr instrs...
1649 if (AllUsesAreGEPs) return;
1652 unsigned DestReg = getReg(CI);
1653 MachineBasicBlock::iterator MI = BB->end();
1654 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1657 /// emitCastOperation - Common code shared between visitCastInst and
1658 /// constant expression cast support.
1659 void ISel::emitCastOperation(MachineBasicBlock *BB,
1660 MachineBasicBlock::iterator &IP,
1661 Value *Src, const Type *DestTy,
1663 unsigned SrcReg = getReg(Src, BB, IP);
1664 const Type *SrcTy = Src->getType();
1665 unsigned SrcClass = getClassB(SrcTy);
1666 unsigned DestClass = getClassB(DestTy);
1668 // Implement casts to bool by using compare on the operand followed by set if
1669 // not zero on the result.
1670 if (DestTy == Type::BoolTy) {
1673 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1676 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1679 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1682 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1683 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1687 assert(0 && "FIXME: implement cast FP to bool");
1691 // If the zero flag is not set, then the value is true, set the byte to
1693 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1697 static const unsigned RegRegMove[] = {
1698 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1701 // Implement casts between values of the same type class (as determined by
1702 // getClass) by using a register-to-register move.
1703 if (SrcClass == DestClass) {
1704 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1705 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1706 } else if (SrcClass == cFP) {
1707 if (SrcTy == Type::FloatTy) { // double -> float
1708 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1709 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1710 } else { // float -> double
1711 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1712 "Unknown cFP member!");
1713 // Truncate from double to float by storing to memory as short, then
1715 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1716 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1717 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1718 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1720 } else if (SrcClass == cLong) {
1721 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1722 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1724 assert(0 && "Cannot handle this type of cast instruction!");
1730 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1731 // or zero extension, depending on whether the source type was signed.
1732 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1733 SrcClass < DestClass) {
1734 bool isLong = DestClass == cLong;
1735 if (isLong) DestClass = cInt;
1737 static const unsigned Opc[][4] = {
1738 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1739 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1742 bool isUnsigned = SrcTy->isUnsigned();
1743 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1744 DestReg).addReg(SrcReg);
1746 if (isLong) { // Handle upper 32 bits as appropriate...
1747 if (isUnsigned) // Zero out top bits...
1748 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1749 else // Sign extend bottom half...
1750 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1755 // Special case long -> int ...
1756 if (SrcClass == cLong && DestClass == cInt) {
1757 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1761 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1762 // move out of AX or AL.
1763 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1764 && SrcClass > DestClass) {
1765 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1766 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1767 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1771 // Handle casts from integer to floating point now...
1772 if (DestClass == cFP) {
1773 // Promote the integer to a type supported by FLD. We do this because there
1774 // are no unsigned FLD instructions, so we must promote an unsigned value to
1775 // a larger signed value, then use FLD on the larger value.
1777 const Type *PromoteType = 0;
1778 unsigned PromoteOpcode;
1779 switch (SrcTy->getPrimitiveID()) {
1780 case Type::BoolTyID:
1781 case Type::SByteTyID:
1782 // We don't have the facilities for directly loading byte sized data from
1783 // memory (even signed). Promote it to 16 bits.
1784 PromoteType = Type::ShortTy;
1785 PromoteOpcode = X86::MOVSXr16r8;
1787 case Type::UByteTyID:
1788 PromoteType = Type::ShortTy;
1789 PromoteOpcode = X86::MOVZXr16r8;
1791 case Type::UShortTyID:
1792 PromoteType = Type::IntTy;
1793 PromoteOpcode = X86::MOVZXr32r16;
1795 case Type::UIntTyID: {
1796 // Make a 64 bit temporary... and zero out the top of it...
1797 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1798 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1799 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1800 SrcTy = Type::LongTy;
1805 case Type::ULongTyID:
1806 assert("FIXME: not implemented: cast ulong X to fp type!");
1807 default: // No promotion needed...
1812 unsigned TmpReg = makeAnotherReg(PromoteType);
1813 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1814 1, TmpReg).addReg(SrcReg);
1815 SrcTy = PromoteType;
1816 SrcClass = getClass(PromoteType);
1820 // Spill the integer to memory and reload it from there...
1822 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1824 if (SrcClass == cLong) {
1825 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1826 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1827 FrameIdx, 4).addReg(SrcReg+1);
1829 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1830 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1833 static const unsigned Op2[] =
1834 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1835 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1839 // Handle casts from floating point to integer now...
1840 if (SrcClass == cFP) {
1841 // Change the floating point control register to use "round towards zero"
1842 // mode when truncating to an integer value.
1844 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1845 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1847 // Load the old value of the high byte of the control word...
1848 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1849 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1851 // Set the high part to be round to zero...
1852 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1854 // Reload the modified control word now...
1855 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1857 // Restore the memory image of control word to original value
1858 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1859 CWFrameIdx, 1).addReg(HighPartOfCW);
1861 // We don't have the facilities for directly storing byte sized data to
1862 // memory. Promote it to 16 bits. We also must promote unsigned values to
1863 // larger classes because we only have signed FP stores.
1864 unsigned StoreClass = DestClass;
1865 const Type *StoreTy = DestTy;
1866 if (StoreClass == cByte || DestTy->isUnsigned())
1867 switch (StoreClass) {
1868 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1869 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1870 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1871 // The following treatment of cLong may not be perfectly right,
1872 // but it survives chains of casts of the form
1873 // double->ulong->double.
1874 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
1875 default: assert(0 && "Unknown store class!");
1878 // Spill the integer to memory and reload it from there...
1880 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1882 static const unsigned Op1[] =
1883 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1884 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1886 if (DestClass == cLong) {
1887 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1888 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1890 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1891 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1894 // Reload the original control word now...
1895 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1899 // Anything we haven't handled already, we can't (yet) handle at all.
1900 assert(0 && "Unhandled cast instruction!");
1904 /// visitVANextInst - Implement the va_next instruction...
1906 void ISel::visitVANextInst(VANextInst &I) {
1907 unsigned VAList = getReg(I.getOperand(0));
1908 unsigned DestReg = getReg(I);
1911 switch (I.getArgType()->getPrimitiveID()) {
1914 assert(0 && "Error: bad type for va_next instruction!");
1916 case Type::PointerTyID:
1917 case Type::UIntTyID:
1921 case Type::ULongTyID:
1922 case Type::LongTyID:
1923 case Type::DoubleTyID:
1928 // Increment the VAList pointer...
1929 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
1932 void ISel::visitVAArgInst(VAArgInst &I) {
1933 unsigned VAList = getReg(I.getOperand(0));
1934 unsigned DestReg = getReg(I);
1936 switch (I.getType()->getPrimitiveID()) {
1939 assert(0 && "Error: bad type for va_next instruction!");
1941 case Type::PointerTyID:
1942 case Type::UIntTyID:
1944 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1946 case Type::ULongTyID:
1947 case Type::LongTyID:
1948 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1949 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
1951 case Type::DoubleTyID:
1952 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
1958 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
1959 unsigned outputReg = getReg(I);
1960 MachineBasicBlock::iterator MI = BB->end();
1961 emitGEPOperation(BB, MI, I.getOperand(0),
1962 I.op_begin()+1, I.op_end(), outputReg);
1965 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
1966 MachineBasicBlock::iterator &IP,
1967 Value *Src, User::op_iterator IdxBegin,
1968 User::op_iterator IdxEnd, unsigned TargetReg) {
1969 const TargetData &TD = TM.getTargetData();
1970 const Type *Ty = Src->getType();
1971 unsigned BaseReg = getReg(Src, MBB, IP);
1973 // GEPs have zero or more indices; we must perform a struct access
1974 // or array access for each one.
1975 for (GetElementPtrInst::op_iterator oi = IdxBegin,
1976 oe = IdxEnd; oi != oe; ++oi) {
1978 unsigned NextReg = BaseReg;
1979 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1980 // It's a struct access. idx is the index into the structure,
1981 // which names the field. This index must have ubyte type.
1982 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
1983 assert(CUI->getType() == Type::UByteTy
1984 && "Funny-looking structure index in GEP");
1985 // Use the TargetData structure to pick out what the layout of
1986 // the structure is in memory. Since the structure index must
1987 // be constant, we can get its value and use it to find the
1988 // right byte offset from the StructLayout class's list of
1989 // structure member offsets.
1990 unsigned idxValue = CUI->getValue();
1991 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
1993 NextReg = makeAnotherReg(Type::UIntTy);
1994 // Emit an ADD to add FieldOff to the basePtr.
1995 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1997 // The next type is the member of the structure selected by the
1999 Ty = StTy->getElementTypes()[idxValue];
2000 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
2001 // It's an array or pointer access: [ArraySize x ElementType].
2003 // idx is the index into the array. Unlike with structure
2004 // indices, we may not know its actual value at code-generation
2006 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2008 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2009 // operand on X86. Handle this case directly now...
2010 if (CastInst *CI = dyn_cast<CastInst>(idx))
2011 if (CI->getOperand(0)->getType() == Type::IntTy ||
2012 CI->getOperand(0)->getType() == Type::UIntTy)
2013 idx = CI->getOperand(0);
2015 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2016 // must find the size of the pointed-to type (Not coincidentally, the next
2017 // type is the type of the elements in the array).
2018 Ty = SqTy->getElementType();
2019 unsigned elementSize = TD.getTypeSize(Ty);
2021 // If idxReg is a constant, we don't need to perform the multiply!
2022 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2023 if (!CSI->isNullValue()) {
2024 unsigned Offset = elementSize*CSI->getValue();
2025 NextReg = makeAnotherReg(Type::UIntTy);
2026 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
2028 } else if (elementSize == 1) {
2029 // If the element size is 1, we don't have to multiply, just add
2030 unsigned idxReg = getReg(idx, MBB, IP);
2031 NextReg = makeAnotherReg(Type::UIntTy);
2032 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
2034 unsigned idxReg = getReg(idx, MBB, IP);
2035 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2037 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2039 // Emit an ADD to add OffsetReg to the basePtr.
2040 NextReg = makeAnotherReg(Type::UIntTy);
2041 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
2044 // Now that we are here, further indices refer to subtypes of this
2045 // one, so we don't need to worry about BaseReg itself, anymore.
2048 // After we have processed all the indices, the result is left in
2049 // BaseReg. Move it to the register where we were expected to
2050 // put the answer. A 32-bit move should do it, because we are in
2052 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2056 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2057 /// frame manager, otherwise do it the hard way.
2059 void ISel::visitAllocaInst(AllocaInst &I) {
2060 // Find the data size of the alloca inst's getAllocatedType.
2061 const Type *Ty = I.getAllocatedType();
2062 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2064 // If this is a fixed size alloca in the entry block for the function,
2065 // statically stack allocate the space.
2067 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2068 if (I.getParent() == I.getParent()->getParent()->begin()) {
2069 TySize *= CUI->getValue(); // Get total allocated size...
2070 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2072 // Create a new stack object using the frame manager...
2073 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2074 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2079 // Create a register to hold the temporary result of multiplying the type size
2080 // constant by the variable amount.
2081 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2082 unsigned SrcReg1 = getReg(I.getArraySize());
2084 // TotalSizeReg = mul <numelements>, <TypeSize>
2085 MachineBasicBlock::iterator MBBI = BB->end();
2086 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2088 // AddedSize = add <TotalSizeReg>, 15
2089 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2090 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2092 // AlignedSize = and <AddedSize>, ~15
2093 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2094 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2096 // Subtract size from stack pointer, thereby allocating some space.
2097 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2099 // Put a pointer to the space into the result register, by copying
2100 // the stack pointer.
2101 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2103 // Inform the Frame Information that we have just allocated a variable-sized
2105 F->getFrameInfo()->CreateVariableSizedObject();
2108 /// visitMallocInst - Malloc instructions are code generated into direct calls
2109 /// to the library malloc.
2111 void ISel::visitMallocInst(MallocInst &I) {
2112 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2115 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2116 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2118 Arg = makeAnotherReg(Type::UIntTy);
2119 unsigned Op0Reg = getReg(I.getOperand(0));
2120 MachineBasicBlock::iterator MBBI = BB->end();
2121 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2124 std::vector<ValueRecord> Args;
2125 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2126 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2127 1).addExternalSymbol("malloc", true);
2128 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2132 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2135 void ISel::visitFreeInst(FreeInst &I) {
2136 std::vector<ValueRecord> Args;
2137 Args.push_back(ValueRecord(I.getOperand(0)));
2138 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2139 1).addExternalSymbol("free", true);
2140 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2144 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2145 /// into a machine code representation is a very simple peep-hole fashion. The
2146 /// generated code sucks but the implementation is nice and simple.
2148 FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) {
2149 return new ISel(TM);