1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/GetElementPtrTypeIterator.h"
31 #include "llvm/Support/InstVisitor.h"
32 #include "llvm/Support/CFG.h"
37 /// BMI - A special BuildMI variant that takes an iterator to insert the
38 /// instruction at as well as a basic block. This is the version for when you
39 /// have a destination register in mind.
40 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
41 MachineBasicBlock::iterator I,
42 int Opcode, unsigned NumOperands,
44 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
46 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
49 /// BMI - A special BuildMI variant that takes an iterator to insert the
50 /// instruction at as well as a basic block.
51 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
52 MachineBasicBlock::iterator I,
53 int Opcode, unsigned NumOperands) {
54 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
56 return MachineInstrBuilder(MI);
61 struct ISel : public FunctionPass, InstVisitor<ISel> {
63 MachineFunction *F; // The function we are compiling into
64 MachineBasicBlock *BB; // The current MBB we are compiling
65 int VarArgsFrameIndex; // FrameIndex for start of varargs area
66 int ReturnAddressIndex; // FrameIndex for the return address
68 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
70 // MBBMap - Mapping between LLVM BB -> Machine BB
71 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
73 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
75 /// runOnFunction - Top level implementation of instruction selection for
76 /// the entire function.
78 bool runOnFunction(Function &Fn) {
79 // First pass over the function, lower any unknown intrinsic functions
80 // with the IntrinsicLowering class.
81 LowerUnknownIntrinsicFunctionCalls(Fn);
83 F = &MachineFunction::construct(&Fn, TM);
85 // Create all of the machine basic blocks for the function...
86 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
87 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
91 // Set up a frame object for the return address. This is used by the
92 // llvm.returnaddress & llvm.frameaddress intrinisics.
93 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
95 // Copy incoming arguments off of the stack...
96 LoadArgumentsToVirtualRegs(Fn);
98 // Instruction select everything except PHI nodes
101 // Select the PHI nodes
107 // We always build a machine code representation for the function
111 virtual const char *getPassName() const {
112 return "X86 Simple Instruction Selection";
115 /// visitBasicBlock - This method is called when we are visiting a new basic
116 /// block. This simply creates a new MachineBasicBlock to emit code into
117 /// and adds it to the current MachineFunction. Subsequent visit* for
118 /// instructions will be invoked for all instructions in the basic block.
120 void visitBasicBlock(BasicBlock &LLVM_BB) {
121 BB = MBBMap[&LLVM_BB];
124 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
125 /// function, lowering any calls to unknown intrinsic functions into the
126 /// equivalent LLVM code.
127 void LowerUnknownIntrinsicFunctionCalls(Function &F);
129 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
130 /// from the stack into virtual registers.
132 void LoadArgumentsToVirtualRegs(Function &F);
134 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
135 /// because we have to generate our sources into the source basic blocks,
136 /// not the current one.
138 void SelectPHINodes();
140 // Visitation methods for various instructions. These methods simply emit
141 // fixed X86 code for each instruction.
144 // Control flow operators
145 void visitReturnInst(ReturnInst &RI);
146 void visitBranchInst(BranchInst &BI);
152 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
153 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
155 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
156 const std::vector<ValueRecord> &Args);
157 void visitCallInst(CallInst &I);
158 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
160 // Arithmetic operators
161 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
162 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
163 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
164 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
165 unsigned DestReg, const Type *DestTy,
166 unsigned Op0Reg, unsigned Op1Reg);
167 void doMultiplyConst(MachineBasicBlock *MBB,
168 MachineBasicBlock::iterator &MBBI,
169 unsigned DestReg, const Type *DestTy,
170 unsigned Op0Reg, unsigned Op1Val);
171 void visitMul(BinaryOperator &B);
173 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
174 void visitRem(BinaryOperator &B) { visitDivRem(B); }
175 void visitDivRem(BinaryOperator &B);
178 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
179 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
180 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
182 // Comparison operators...
183 void visitSetCondInst(SetCondInst &I);
184 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
185 MachineBasicBlock *MBB,
186 MachineBasicBlock::iterator &MBBI);
188 // Memory Instructions
189 void visitLoadInst(LoadInst &I);
190 void visitStoreInst(StoreInst &I);
191 void visitGetElementPtrInst(GetElementPtrInst &I);
192 void visitAllocaInst(AllocaInst &I);
193 void visitMallocInst(MallocInst &I);
194 void visitFreeInst(FreeInst &I);
197 void visitShiftInst(ShiftInst &I);
198 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
199 void visitCastInst(CastInst &I);
200 void visitVANextInst(VANextInst &I);
201 void visitVAArgInst(VAArgInst &I);
203 void visitInstruction(Instruction &I) {
204 std::cerr << "Cannot instruction select: " << I;
208 /// promote32 - Make a value 32-bits wide, and put it somewhere.
210 void promote32(unsigned targetReg, const ValueRecord &VR);
212 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
213 /// constant expression GEP support.
215 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
216 Value *Src, User::op_iterator IdxBegin,
217 User::op_iterator IdxEnd, unsigned TargetReg);
219 /// emitCastOperation - Common code shared between visitCastInst and
220 /// constant expression cast support.
221 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
222 Value *Src, const Type *DestTy, unsigned TargetReg);
224 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
225 /// and constant expression support.
226 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
227 MachineBasicBlock::iterator &IP,
228 Value *Op0, Value *Op1,
229 unsigned OperatorClass, unsigned TargetReg);
231 void emitDivRemOperation(MachineBasicBlock *BB,
232 MachineBasicBlock::iterator &IP,
233 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
234 const Type *Ty, unsigned TargetReg);
236 /// emitSetCCOperation - Common code shared between visitSetCondInst and
237 /// constant expression support.
238 void emitSetCCOperation(MachineBasicBlock *BB,
239 MachineBasicBlock::iterator &IP,
240 Value *Op0, Value *Op1, unsigned Opcode,
243 /// emitShiftOperation - Common code shared between visitShiftInst and
244 /// constant expression support.
245 void emitShiftOperation(MachineBasicBlock *MBB,
246 MachineBasicBlock::iterator &IP,
247 Value *Op, Value *ShiftAmount, bool isLeftShift,
248 const Type *ResultTy, unsigned DestReg);
251 /// copyConstantToRegister - Output the instructions required to put the
252 /// specified constant into the specified register.
254 void copyConstantToRegister(MachineBasicBlock *MBB,
255 MachineBasicBlock::iterator &MBBI,
256 Constant *C, unsigned Reg);
258 /// makeAnotherReg - This method returns the next register number we haven't
261 /// Long values are handled somewhat specially. They are always allocated
262 /// as pairs of 32 bit integer values. The register number returned is the
263 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
264 /// of the long value.
266 unsigned makeAnotherReg(const Type *Ty) {
267 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
268 "Current target doesn't have X86 reg info??");
269 const X86RegisterInfo *MRI =
270 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
271 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
272 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
273 // Create the lower part
274 F->getSSARegMap()->createVirtualRegister(RC);
275 // Create the upper part.
276 return F->getSSARegMap()->createVirtualRegister(RC)-1;
279 // Add the mapping of regnumber => reg class to MachineFunction
280 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
281 return F->getSSARegMap()->createVirtualRegister(RC);
284 /// getReg - This method turns an LLVM value into a register number. This
285 /// is guaranteed to produce the same register number for a particular value
286 /// every time it is queried.
288 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
289 unsigned getReg(Value *V) {
290 // Just append to the end of the current bb.
291 MachineBasicBlock::iterator It = BB->end();
292 return getReg(V, BB, It);
294 unsigned getReg(Value *V, MachineBasicBlock *MBB,
295 MachineBasicBlock::iterator &IPt) {
296 unsigned &Reg = RegMap[V];
298 Reg = makeAnotherReg(V->getType());
302 // If this operand is a constant, emit the code to copy the constant into
303 // the register here...
305 if (Constant *C = dyn_cast<Constant>(V)) {
306 copyConstantToRegister(MBB, IPt, C, Reg);
307 RegMap.erase(V); // Assign a new name to this constant if ref'd again
308 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
309 // Move the address of the global into the register
310 BMI(MBB, IPt, X86::MOVri32, 1, Reg).addGlobalAddress(GV);
311 RegMap.erase(V); // Assign a new name to this address if ref'd again
319 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
323 cByte, cShort, cInt, cFP, cLong
326 /// getClass - Turn a primitive type into a "class" number which is based on the
327 /// size of the type, and whether or not it is floating point.
329 static inline TypeClass getClass(const Type *Ty) {
330 switch (Ty->getPrimitiveID()) {
331 case Type::SByteTyID:
332 case Type::UByteTyID: return cByte; // Byte operands are class #0
333 case Type::ShortTyID:
334 case Type::UShortTyID: return cShort; // Short operands are class #1
337 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
339 case Type::FloatTyID:
340 case Type::DoubleTyID: return cFP; // Floating Point is #3
343 case Type::ULongTyID: return cLong; // Longs are class #4
345 assert(0 && "Invalid type to getClass!");
346 return cByte; // not reached
350 // getClassB - Just like getClass, but treat boolean values as bytes.
351 static inline TypeClass getClassB(const Type *Ty) {
352 if (Ty == Type::BoolTy) return cByte;
357 /// copyConstantToRegister - Output the instructions required to put the
358 /// specified constant into the specified register.
360 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
361 MachineBasicBlock::iterator &IP,
362 Constant *C, unsigned R) {
363 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
365 switch (CE->getOpcode()) {
366 case Instruction::GetElementPtr:
367 emitGEPOperation(MBB, IP, CE->getOperand(0),
368 CE->op_begin()+1, CE->op_end(), R);
370 case Instruction::Cast:
371 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
374 case Instruction::Xor: ++Class; // FALL THROUGH
375 case Instruction::Or: ++Class; // FALL THROUGH
376 case Instruction::And: ++Class; // FALL THROUGH
377 case Instruction::Sub: ++Class; // FALL THROUGH
378 case Instruction::Add:
379 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
383 case Instruction::Mul: {
384 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
385 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
386 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
389 case Instruction::Div:
390 case Instruction::Rem: {
391 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
392 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
393 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
394 CE->getOpcode() == Instruction::Div,
399 case Instruction::SetNE:
400 case Instruction::SetEQ:
401 case Instruction::SetLT:
402 case Instruction::SetGT:
403 case Instruction::SetLE:
404 case Instruction::SetGE:
405 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
409 case Instruction::Shl:
410 case Instruction::Shr:
411 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
412 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
416 std::cerr << "Offending expr: " << C << "\n";
417 assert(0 && "Constant expression not yet handled!\n");
421 if (C->getType()->isIntegral()) {
422 unsigned Class = getClassB(C->getType());
424 if (Class == cLong) {
425 // Copy the value into the register pair.
426 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
427 BMI(MBB, IP, X86::MOVri32, 1, R).addZImm(Val & 0xFFFFFFFF);
428 BMI(MBB, IP, X86::MOVri32, 1, R+1).addZImm(Val >> 32);
432 assert(Class <= cInt && "Type not handled yet!");
434 static const unsigned IntegralOpcodeTab[] = {
435 X86::MOVri8, X86::MOVri16, X86::MOVri32
438 if (C->getType() == Type::BoolTy) {
439 BMI(MBB, IP, X86::MOVri8, 1, R).addZImm(C == ConstantBool::True);
441 ConstantInt *CI = cast<ConstantInt>(C);
442 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
444 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
445 if (CFP->isExactlyValue(+0.0))
446 BMI(MBB, IP, X86::FLD0, 0, R);
447 else if (CFP->isExactlyValue(+1.0))
448 BMI(MBB, IP, X86::FLD1, 0, R);
450 // Otherwise we need to spill the constant to memory...
451 MachineConstantPool *CP = F->getConstantPool();
452 unsigned CPI = CP->getConstantPoolIndex(CFP);
453 const Type *Ty = CFP->getType();
455 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
456 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
457 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
460 } else if (isa<ConstantPointerNull>(C)) {
461 // Copy zero (null pointer) to the register.
462 BMI(MBB, IP, X86::MOVri32, 1, R).addZImm(0);
463 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
464 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
465 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
467 std::cerr << "Offending constant: " << C << "\n";
468 assert(0 && "Type not handled yet!");
472 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
473 /// the stack into virtual registers.
475 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
476 // Emit instructions to load the arguments... On entry to a function on the
477 // X86, the stack frame looks like this:
479 // [ESP] -- return address
480 // [ESP + 4] -- first argument (leftmost lexically)
481 // [ESP + 8] -- second argument, if first argument is four bytes in size
484 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
485 MachineFrameInfo *MFI = F->getFrameInfo();
487 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
488 unsigned Reg = getReg(*I);
490 int FI; // Frame object index
491 switch (getClassB(I->getType())) {
493 FI = MFI->CreateFixedObject(1, ArgOffset);
494 addFrameReference(BuildMI(BB, X86::MOVrm8, 4, Reg), FI);
497 FI = MFI->CreateFixedObject(2, ArgOffset);
498 addFrameReference(BuildMI(BB, X86::MOVrm16, 4, Reg), FI);
501 FI = MFI->CreateFixedObject(4, ArgOffset);
502 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg), FI);
505 FI = MFI->CreateFixedObject(8, ArgOffset);
506 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg), FI);
507 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg+1), FI, 4);
508 ArgOffset += 4; // longs require 4 additional bytes
512 if (I->getType() == Type::FloatTy) {
513 Opcode = X86::FLDr32;
514 FI = MFI->CreateFixedObject(4, ArgOffset);
516 Opcode = X86::FLDr64;
517 FI = MFI->CreateFixedObject(8, ArgOffset);
518 ArgOffset += 4; // doubles require 4 additional bytes
520 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
523 assert(0 && "Unhandled argument type!");
525 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
528 // If the function takes variable number of arguments, add a frame offset for
529 // the start of the first vararg value... this is used to expand
531 if (Fn.getFunctionType()->isVarArg())
532 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
536 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
537 /// because we have to generate our sources into the source basic blocks, not
540 void ISel::SelectPHINodes() {
541 const TargetInstrInfo &TII = TM.getInstrInfo();
542 const Function &LF = *F->getFunction(); // The LLVM function...
543 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
544 const BasicBlock *BB = I;
545 MachineBasicBlock *MBB = MBBMap[I];
547 // Loop over all of the PHI nodes in the LLVM basic block...
548 MachineInstr* instr = MBB->begin();
549 for (BasicBlock::const_iterator I = BB->begin();
550 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
552 // Create a new machine instr PHI node, and insert it.
553 unsigned PHIReg = getReg(*PN);
554 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
555 MBB->insert(instr, PhiMI);
557 MachineInstr *LongPhiMI = 0;
558 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
559 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
560 MBB->insert(instr, LongPhiMI);
563 // PHIValues - Map of blocks to incoming virtual registers. We use this
564 // so that we only initialize one incoming value for a particular block,
565 // even if the block has multiple entries in the PHI node.
567 std::map<MachineBasicBlock*, unsigned> PHIValues;
569 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
570 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
572 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
573 PHIValues.lower_bound(PredMBB);
575 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
576 // We already inserted an initialization of the register for this
577 // predecessor. Recycle it.
578 ValReg = EntryIt->second;
581 // Get the incoming value into a virtual register.
583 Value *Val = PN->getIncomingValue(i);
585 // If this is a constant or GlobalValue, we may have to insert code
586 // into the basic block to compute it into a virtual register.
587 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
588 // Because we don't want to clobber any values which might be in
589 // physical registers with the computation of this constant (which
590 // might be arbitrarily complex if it is a constant expression),
591 // just insert the computation at the top of the basic block.
592 MachineBasicBlock::iterator PI = PredMBB->begin();
594 // Skip over any PHI nodes though!
595 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
598 ValReg = getReg(Val, PredMBB, PI);
600 ValReg = getReg(Val);
603 // Remember that we inserted a value for this PHI for this predecessor
604 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
607 PhiMI->addRegOperand(ValReg);
608 PhiMI->addMachineBasicBlockOperand(PredMBB);
610 LongPhiMI->addRegOperand(ValReg+1);
611 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
618 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
619 // the conditional branch instruction which is the only user of the cc
620 // instruction. This is the case if the conditional branch is the only user of
621 // the setcc, and if the setcc is in the same basic block as the conditional
622 // branch. We also don't handle long arguments below, so we reject them here as
625 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
626 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
627 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
628 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
629 const Type *Ty = SCI->getOperand(0)->getType();
630 if (Ty != Type::LongTy && Ty != Type::ULongTy)
636 // Return a fixed numbering for setcc instructions which does not depend on the
637 // order of the opcodes.
639 static unsigned getSetCCNumber(unsigned Opcode) {
641 default: assert(0 && "Unknown setcc instruction!");
642 case Instruction::SetEQ: return 0;
643 case Instruction::SetNE: return 1;
644 case Instruction::SetLT: return 2;
645 case Instruction::SetGE: return 3;
646 case Instruction::SetGT: return 4;
647 case Instruction::SetLE: return 5;
651 // LLVM -> X86 signed X86 unsigned
652 // ----- ---------- ------------
653 // seteq -> sete sete
654 // setne -> setne setne
655 // setlt -> setl setb
656 // setge -> setge setae
657 // setgt -> setg seta
658 // setle -> setle setbe
660 // sets // Used by comparison with 0 optimization
662 static const unsigned SetCCOpcodeTab[2][8] = {
663 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
665 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
666 X86::SETSr, X86::SETNSr },
669 // EmitComparison - This function emits a comparison of the two operands,
670 // returning the extended setcc code to use.
671 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
672 MachineBasicBlock *MBB,
673 MachineBasicBlock::iterator &IP) {
674 // The arguments are already supposed to be of the same type.
675 const Type *CompTy = Op0->getType();
676 unsigned Class = getClassB(CompTy);
677 unsigned Op0r = getReg(Op0, MBB, IP);
679 // Special case handling of: cmp R, i
680 if (Class == cByte || Class == cShort || Class == cInt)
681 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
682 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
684 // Mask off any upper bits of the constant, if there are any...
685 Op1v &= (1ULL << (8 << Class)) - 1;
687 // If this is a comparison against zero, emit more efficient code. We
688 // can't handle unsigned comparisons against zero unless they are == or
689 // !=. These should have been strength reduced already anyway.
690 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
691 static const unsigned TESTTab[] = {
692 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
694 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
696 if (OpNum == 2) return 6; // Map jl -> js
697 if (OpNum == 3) return 7; // Map jg -> jns
701 static const unsigned CMPTab[] = {
702 X86::CMPri8, X86::CMPri16, X86::CMPri32
705 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
709 // Special case handling of comparison against +/- 0.0
710 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
711 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
712 BMI(MBB, IP, X86::FTST, 1).addReg(Op0r);
713 BMI(MBB, IP, X86::FNSTSWr8, 0);
714 BMI(MBB, IP, X86::SAHF, 1);
718 unsigned Op1r = getReg(Op1, MBB, IP);
720 default: assert(0 && "Unknown type class!");
721 // Emit: cmp <var1>, <var2> (do the comparison). We can
722 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
725 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
728 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
731 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
734 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
735 BMI(MBB, IP, X86::FNSTSWr8, 0);
736 BMI(MBB, IP, X86::SAHF, 1);
740 if (OpNum < 2) { // seteq, setne
741 unsigned LoTmp = makeAnotherReg(Type::IntTy);
742 unsigned HiTmp = makeAnotherReg(Type::IntTy);
743 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
744 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
745 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
746 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
747 break; // Allow the sete or setne to be generated from flags set by OR
749 // Emit a sequence of code which compares the high and low parts once
750 // each, then uses a conditional move to handle the overflow case. For
751 // example, a setlt for long would generate code like this:
753 // AL = lo(op1) < lo(op2) // Signedness depends on operands
754 // BL = hi(op1) < hi(op2) // Always unsigned comparison
755 // dest = hi(op1) == hi(op2) ? AL : BL;
758 // FIXME: This would be much better if we had hierarchical register
759 // classes! Until then, hardcode registers so that we can deal with their
760 // aliases (because we don't have conditional byte moves).
762 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
763 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
764 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
765 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
766 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
767 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
768 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
769 // NOTE: visitSetCondInst knows that the value is dumped into the BL
770 // register at this point for long values...
778 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
779 /// register, then move it to wherever the result should be.
781 void ISel::visitSetCondInst(SetCondInst &I) {
782 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
784 unsigned DestReg = getReg(I);
785 MachineBasicBlock::iterator MII = BB->end();
786 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
790 /// emitSetCCOperation - Common code shared between visitSetCondInst and
791 /// constant expression support.
792 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
793 MachineBasicBlock::iterator &IP,
794 Value *Op0, Value *Op1, unsigned Opcode,
795 unsigned TargetReg) {
796 unsigned OpNum = getSetCCNumber(Opcode);
797 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
799 const Type *CompTy = Op0->getType();
800 unsigned CompClass = getClassB(CompTy);
801 bool isSigned = CompTy->isSigned() && CompClass != cFP;
803 if (CompClass != cLong || OpNum < 2) {
804 // Handle normal comparisons with a setcc instruction...
805 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
807 // Handle long comparisons by copying the value which is already in BL into
808 // the register we want...
809 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
816 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
817 /// operand, in the specified target register.
818 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
819 bool isUnsigned = VR.Ty->isUnsigned();
821 // Make sure we have the register number for this value...
822 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
824 switch (getClassB(VR.Ty)) {
826 // Extend value into target register (8->32)
828 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
830 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
833 // Extend value into target register (16->32)
835 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
837 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
840 // Move value into target register (32->32)
841 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
844 assert(0 && "Unpromotable operand class in promote32");
848 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
849 /// we have the following possibilities:
851 /// ret void: No return value, simply emit a 'ret' instruction
852 /// ret sbyte, ubyte : Extend value into EAX and return
853 /// ret short, ushort: Extend value into EAX and return
854 /// ret int, uint : Move value into EAX and return
855 /// ret pointer : Move value into EAX and return
856 /// ret long, ulong : Move value into EAX/EDX and return
857 /// ret float/double : Top of FP stack
859 void ISel::visitReturnInst(ReturnInst &I) {
860 if (I.getNumOperands() == 0) {
862 BuildMI(BB, X86::FP_REG_KILL, 0);
864 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
868 Value *RetVal = I.getOperand(0);
869 unsigned RetReg = getReg(RetVal);
870 switch (getClassB(RetVal->getType())) {
871 case cByte: // integral return values: extend or move into EAX and return
874 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
875 // Declare that EAX is live on exit
876 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
878 case cFP: // Floats & Doubles: Return in ST(0)
879 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
880 // Declare that top-of-stack is live on exit
881 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
884 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
885 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
886 // Declare that EAX & EDX are live on exit
887 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
893 // Emit a 'ret' instruction
895 BuildMI(BB, X86::FP_REG_KILL, 0);
897 BuildMI(BB, X86::RET, 0);
900 // getBlockAfter - Return the basic block which occurs lexically after the
902 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
903 Function::iterator I = BB; ++I; // Get iterator to next block
904 return I != BB->getParent()->end() ? &*I : 0;
907 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
908 /// compensation code on critical edges. As such, it requires that we kill all
909 /// FP registers on the exit from any blocks that either ARE critical edges, or
910 /// branch to a block that has incoming critical edges.
912 /// Note that this kill instruction will eventually be eliminated when
913 /// restrictions in the stackifier are relaxed.
915 static bool RequiresFPRegKill(const BasicBlock *BB) {
917 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
918 const BasicBlock *Succ = *SI;
919 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
920 ++PI; // Block have at least one predecessory
921 if (PI != PE) { // If it has exactly one, this isn't crit edge
922 // If this block has more than one predecessor, check all of the
923 // predecessors to see if they have multiple successors. If so, then the
924 // block we are analyzing needs an FPRegKill.
925 for (PI = pred_begin(Succ); PI != PE; ++PI) {
926 const BasicBlock *Pred = *PI;
927 succ_const_iterator SI2 = succ_begin(Pred);
928 ++SI2; // There must be at least one successor of this block.
929 if (SI2 != succ_end(Pred))
930 return true; // Yes, we must insert the kill on this edge.
934 // If we got this far, there is no need to insert the kill instruction.
941 /// visitBranchInst - Handle conditional and unconditional branches here. Note
942 /// that since code layout is frozen at this point, that if we are trying to
943 /// jump to a block that is the immediate successor of the current block, we can
944 /// just make a fall-through (but we don't currently).
946 void ISel::visitBranchInst(BranchInst &BI) {
947 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
949 if (!BI.isConditional()) { // Unconditional branch?
950 if (RequiresFPRegKill(BI.getParent()))
951 BuildMI(BB, X86::FP_REG_KILL, 0);
952 if (BI.getSuccessor(0) != NextBB)
953 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
957 // See if we can fold the setcc into the branch itself...
958 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
960 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
961 // computed some other way...
962 unsigned condReg = getReg(BI.getCondition());
963 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
964 if (RequiresFPRegKill(BI.getParent()))
965 BuildMI(BB, X86::FP_REG_KILL, 0);
966 if (BI.getSuccessor(1) == NextBB) {
967 if (BI.getSuccessor(0) != NextBB)
968 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
970 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
972 if (BI.getSuccessor(0) != NextBB)
973 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
978 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
979 MachineBasicBlock::iterator MII = BB->end();
980 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
982 const Type *CompTy = SCI->getOperand(0)->getType();
983 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
986 // LLVM -> X86 signed X86 unsigned
987 // ----- ---------- ------------
995 // js // Used by comparison with 0 optimization
998 static const unsigned OpcodeTab[2][8] = {
999 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1000 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1001 X86::JS, X86::JNS },
1004 if (RequiresFPRegKill(BI.getParent()))
1005 BuildMI(BB, X86::FP_REG_KILL, 0);
1006 if (BI.getSuccessor(0) != NextBB) {
1007 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1008 if (BI.getSuccessor(1) != NextBB)
1009 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1011 // Change to the inverse condition...
1012 if (BI.getSuccessor(1) != NextBB) {
1014 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1020 /// doCall - This emits an abstract call instruction, setting up the arguments
1021 /// and the return value as appropriate. For the actual function call itself,
1022 /// it inserts the specified CallMI instruction into the stream.
1024 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1025 const std::vector<ValueRecord> &Args) {
1027 // Count how many bytes are to be pushed on the stack...
1028 unsigned NumBytes = 0;
1030 if (!Args.empty()) {
1031 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1032 switch (getClassB(Args[i].Ty)) {
1033 case cByte: case cShort: case cInt:
1034 NumBytes += 4; break;
1036 NumBytes += 8; break;
1038 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1040 default: assert(0 && "Unknown class!");
1043 // Adjust the stack pointer for the new arguments...
1044 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
1046 // Arguments go on the stack in reverse order, as specified by the ABI.
1047 unsigned ArgOffset = 0;
1048 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1049 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1050 switch (getClassB(Args[i].Ty)) {
1053 // Promote arg to 32 bits wide into a temporary register...
1054 unsigned R = makeAnotherReg(Type::UIntTy);
1055 promote32(R, Args[i]);
1056 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1057 X86::ESP, ArgOffset).addReg(R);
1061 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1062 X86::ESP, ArgOffset).addReg(ArgReg);
1065 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1066 X86::ESP, ArgOffset).addReg(ArgReg);
1067 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1068 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1069 ArgOffset += 4; // 8 byte entry, not 4.
1073 if (Args[i].Ty == Type::FloatTy) {
1074 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
1075 X86::ESP, ArgOffset).addReg(ArgReg);
1077 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1078 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
1079 X86::ESP, ArgOffset).addReg(ArgReg);
1080 ArgOffset += 4; // 8 byte entry, not 4.
1084 default: assert(0 && "Unknown class!");
1089 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
1092 BB->push_back(CallMI);
1094 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
1096 // If there is a return value, scavenge the result from the location the call
1099 if (Ret.Ty != Type::VoidTy) {
1100 unsigned DestClass = getClassB(Ret.Ty);
1101 switch (DestClass) {
1105 // Integral results are in %eax, or the appropriate portion
1107 static const unsigned regRegMove[] = {
1108 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1110 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1111 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1114 case cFP: // Floating-point return values live in %ST(0)
1115 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1117 case cLong: // Long values are left in EDX:EAX
1118 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1119 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1121 default: assert(0 && "Unknown class!");
1127 /// visitCallInst - Push args on stack and do a procedure call instruction.
1128 void ISel::visitCallInst(CallInst &CI) {
1129 MachineInstr *TheCall;
1130 if (Function *F = CI.getCalledFunction()) {
1131 // Is it an intrinsic function call?
1132 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1133 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1137 // Emit a CALL instruction with PC-relative displacement.
1138 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1139 } else { // Emit an indirect call...
1140 unsigned Reg = getReg(CI.getCalledValue());
1141 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1144 std::vector<ValueRecord> Args;
1145 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1146 Args.push_back(ValueRecord(CI.getOperand(i)));
1148 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1149 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1153 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1154 /// function, lowering any calls to unknown intrinsic functions into the
1155 /// equivalent LLVM code.
1156 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1157 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1158 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1159 if (CallInst *CI = dyn_cast<CallInst>(I++))
1160 if (Function *F = CI->getCalledFunction())
1161 switch (F->getIntrinsicID()) {
1162 case Intrinsic::not_intrinsic:
1163 case Intrinsic::va_start:
1164 case Intrinsic::va_copy:
1165 case Intrinsic::va_end:
1166 case Intrinsic::returnaddress:
1167 case Intrinsic::frameaddress:
1168 case Intrinsic::memcpy:
1169 case Intrinsic::memset:
1170 // We directly implement these intrinsics
1173 // All other intrinsic calls we must lower.
1174 Instruction *Before = CI->getPrev();
1175 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1176 if (Before) { // Move iterator to instruction after call
1185 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1186 unsigned TmpReg1, TmpReg2;
1188 case Intrinsic::va_start:
1189 // Get the address of the first vararg value...
1190 TmpReg1 = getReg(CI);
1191 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1194 case Intrinsic::va_copy:
1195 TmpReg1 = getReg(CI);
1196 TmpReg2 = getReg(CI.getOperand(1));
1197 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1199 case Intrinsic::va_end: return; // Noop on X86
1201 case Intrinsic::returnaddress:
1202 case Intrinsic::frameaddress:
1203 TmpReg1 = getReg(CI);
1204 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1205 if (ID == Intrinsic::returnaddress) {
1206 // Just load the return address
1207 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, TmpReg1),
1208 ReturnAddressIndex);
1210 addFrameReference(BuildMI(BB, X86::LEAr32, 4, TmpReg1),
1211 ReturnAddressIndex, -4);
1214 // Values other than zero are not implemented yet.
1215 BuildMI(BB, X86::MOVri32, 1, TmpReg1).addZImm(0);
1219 case Intrinsic::memcpy: {
1220 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1222 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1223 Align = AlignC->getRawValue();
1224 if (Align == 0) Align = 1;
1227 // Turn the byte code into # iterations
1231 switch (Align & 3) {
1232 case 2: // WORD aligned
1233 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1234 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1236 CountReg = makeAnotherReg(Type::IntTy);
1237 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(1);
1239 Opcode = X86::REP_MOVSW;
1241 case 0: // DWORD aligned
1242 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1243 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1245 CountReg = makeAnotherReg(Type::IntTy);
1246 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(2);
1248 Opcode = X86::REP_MOVSD;
1250 case 1: // BYTE aligned
1251 case 3: // BYTE aligned
1252 CountReg = getReg(CI.getOperand(3));
1253 Opcode = X86::REP_MOVSB;
1257 // No matter what the alignment is, we put the source in ESI, the
1258 // destination in EDI, and the count in ECX.
1259 TmpReg1 = getReg(CI.getOperand(1));
1260 TmpReg2 = getReg(CI.getOperand(2));
1261 BuildMI(BB, X86::MOVrr32, 1, X86::ECX).addReg(CountReg);
1262 BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
1263 BuildMI(BB, X86::MOVrr32, 1, X86::ESI).addReg(TmpReg2);
1264 BuildMI(BB, Opcode, 0);
1267 case Intrinsic::memset: {
1268 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1270 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1271 Align = AlignC->getRawValue();
1272 if (Align == 0) Align = 1;
1275 // Turn the byte code into # iterations
1279 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1280 unsigned Val = ValC->getRawValue() & 255;
1282 // If the value is a constant, then we can potentially use larger copies.
1283 switch (Align & 3) {
1284 case 2: // WORD aligned
1285 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1286 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1288 CountReg = makeAnotherReg(Type::IntTy);
1289 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(1);
1291 BuildMI(BB, X86::MOVri16, 1, X86::AX).addZImm((Val << 8) | Val);
1292 Opcode = X86::REP_STOSW;
1294 case 0: // DWORD aligned
1295 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1296 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1298 CountReg = makeAnotherReg(Type::IntTy);
1299 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(2);
1301 Val = (Val << 8) | Val;
1302 BuildMI(BB, X86::MOVri32, 1, X86::EAX).addZImm((Val << 16) | Val);
1303 Opcode = X86::REP_STOSD;
1305 case 1: // BYTE aligned
1306 case 3: // BYTE aligned
1307 CountReg = getReg(CI.getOperand(3));
1308 BuildMI(BB, X86::MOVri8, 1, X86::AL).addZImm(Val);
1309 Opcode = X86::REP_STOSB;
1313 // If it's not a constant value we are storing, just fall back. We could
1314 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1315 unsigned ValReg = getReg(CI.getOperand(2));
1316 BuildMI(BB, X86::MOVrr8, 1, X86::AL).addReg(ValReg);
1317 CountReg = getReg(CI.getOperand(3));
1318 Opcode = X86::REP_STOSB;
1321 // No matter what the alignment is, we put the source in ESI, the
1322 // destination in EDI, and the count in ECX.
1323 TmpReg1 = getReg(CI.getOperand(1));
1324 //TmpReg2 = getReg(CI.getOperand(2));
1325 BuildMI(BB, X86::MOVrr32, 1, X86::ECX).addReg(CountReg);
1326 BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
1327 BuildMI(BB, Opcode, 0);
1331 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1336 /// visitSimpleBinary - Implement simple binary operators for integral types...
1337 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1339 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1340 unsigned DestReg = getReg(B);
1341 MachineBasicBlock::iterator MI = BB->end();
1342 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1343 OperatorClass, DestReg);
1346 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1347 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1350 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1351 /// and constant expression support.
1353 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1354 MachineBasicBlock::iterator &IP,
1355 Value *Op0, Value *Op1,
1356 unsigned OperatorClass, unsigned DestReg) {
1357 unsigned Class = getClassB(Op0->getType());
1359 // sub 0, X -> neg X
1360 if (OperatorClass == 1 && Class != cLong)
1361 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1362 if (CI->isNullValue()) {
1363 unsigned op1Reg = getReg(Op1, MBB, IP);
1365 default: assert(0 && "Unknown class for this function!");
1367 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1370 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1373 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1377 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1378 if (CFP->isExactlyValue(-0.0)) {
1380 unsigned op1Reg = getReg(Op1, MBB, IP);
1381 BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1385 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1386 static const unsigned OpcodeTab[][4] = {
1387 // Arithmetic operators
1388 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1389 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1391 // Bitwise operators
1392 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1393 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1394 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1397 bool isLong = false;
1398 if (Class == cLong) {
1400 Class = cInt; // Bottom 32 bits are handled just like ints
1403 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1404 assert(Opcode && "Floating point arguments to logical inst?");
1405 unsigned Op0r = getReg(Op0, MBB, IP);
1406 unsigned Op1r = getReg(Op1, MBB, IP);
1407 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1409 if (isLong) { // Handle the upper 32 bits of long values...
1410 static const unsigned TopTab[] = {
1411 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1413 BMI(MBB, IP, TopTab[OperatorClass], 2,
1414 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1419 // Special case: op Reg, <const>
1420 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1421 unsigned Op0r = getReg(Op0, MBB, IP);
1423 // xor X, -1 -> not X
1424 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1425 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1426 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1430 // add X, -1 -> dec X
1431 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1432 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1433 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1437 // add X, 1 -> inc X
1438 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1439 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1440 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1444 static const unsigned OpcodeTab[][3] = {
1445 // Arithmetic operators
1446 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1447 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1449 // Bitwise operators
1450 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1451 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1452 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1455 assert(Class < 3 && "General code handles 64-bit integer types!");
1456 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1457 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1459 // Mask off any upper bits of the constant, if there are any...
1460 Op1v &= (1ULL << (8 << Class)) - 1;
1461 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1464 /// doMultiply - Emit appropriate instructions to multiply together the
1465 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1466 /// result should be given as DestTy.
1468 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1469 unsigned DestReg, const Type *DestTy,
1470 unsigned op0Reg, unsigned op1Reg) {
1471 unsigned Class = getClass(DestTy);
1473 case cFP: // Floating point multiply
1474 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1478 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1479 .addReg(op0Reg).addReg(op1Reg);
1482 // Must use the MUL instruction, which forces use of AL...
1483 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1484 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1485 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1488 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1492 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1493 // returns zero when the input is not exactly a power of two.
1494 static unsigned ExactLog2(unsigned Val) {
1495 if (Val == 0) return 0;
1498 if (Val & 1) return 0;
1505 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1506 MachineBasicBlock::iterator &IP,
1507 unsigned DestReg, const Type *DestTy,
1508 unsigned op0Reg, unsigned ConstRHS) {
1509 unsigned Class = getClass(DestTy);
1511 // If the element size is exactly a power of 2, use a shift to get it.
1512 if (unsigned Shift = ExactLog2(ConstRHS)) {
1514 default: assert(0 && "Unknown class for this function!");
1516 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1519 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1522 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1527 if (Class == cShort) {
1528 BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1530 } else if (Class == cInt) {
1531 BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1535 // Most general case, emit a normal multiply...
1536 static const unsigned MOVriTab[] = {
1537 X86::MOVri8, X86::MOVri16, X86::MOVri32
1540 unsigned TmpReg = makeAnotherReg(DestTy);
1541 BMI(MBB, IP, MOVriTab[Class], 1, TmpReg).addZImm(ConstRHS);
1543 // Emit a MUL to multiply the register holding the index by
1544 // elementSize, putting the result in OffsetReg.
1545 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1548 /// visitMul - Multiplies are not simple binary operators because they must deal
1549 /// with the EAX register explicitly.
1551 void ISel::visitMul(BinaryOperator &I) {
1552 unsigned Op0Reg = getReg(I.getOperand(0));
1553 unsigned DestReg = getReg(I);
1555 // Simple scalar multiply?
1556 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1557 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1558 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1559 MachineBasicBlock::iterator MBBI = BB->end();
1560 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1562 unsigned Op1Reg = getReg(I.getOperand(1));
1563 MachineBasicBlock::iterator MBBI = BB->end();
1564 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1567 unsigned Op1Reg = getReg(I.getOperand(1));
1569 // Long value. We have to do things the hard way...
1570 // Multiply the two low parts... capturing carry into EDX
1571 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1572 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1574 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1575 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1576 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1578 MachineBasicBlock::iterator MBBI = BB->end();
1579 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1580 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1582 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1583 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1584 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1587 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1588 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1590 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1591 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1596 /// visitDivRem - Handle division and remainder instructions... these
1597 /// instruction both require the same instructions to be generated, they just
1598 /// select the result from a different register. Note that both of these
1599 /// instructions work differently for signed and unsigned operands.
1601 void ISel::visitDivRem(BinaryOperator &I) {
1602 unsigned Op0Reg = getReg(I.getOperand(0));
1603 unsigned Op1Reg = getReg(I.getOperand(1));
1604 unsigned ResultReg = getReg(I);
1606 MachineBasicBlock::iterator IP = BB->end();
1607 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1608 I.getType(), ResultReg);
1611 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1612 MachineBasicBlock::iterator &IP,
1613 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1614 const Type *Ty, unsigned ResultReg) {
1615 unsigned Class = getClass(Ty);
1617 case cFP: // Floating point divide
1619 BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1620 } else { // Floating point remainder...
1621 MachineInstr *TheCall =
1622 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1623 std::vector<ValueRecord> Args;
1624 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1625 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1626 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1630 static const char *FnName[] =
1631 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1633 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1634 MachineInstr *TheCall =
1635 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1637 std::vector<ValueRecord> Args;
1638 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1639 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1640 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1643 case cByte: case cShort: case cInt:
1644 break; // Small integrals, handled below...
1645 default: assert(0 && "Unknown class!");
1648 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1649 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1650 static const unsigned SarOpcode[]={ X86::SARri8, X86::SARri16, X86::SARri32 };
1651 static const unsigned ClrOpcode[]={ X86::MOVri8, X86::MOVri16, X86::MOVri32 };
1652 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1654 static const unsigned DivOpcode[][4] = {
1655 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1656 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1659 bool isSigned = Ty->isSigned();
1660 unsigned Reg = Regs[Class];
1661 unsigned ExtReg = ExtRegs[Class];
1663 // Put the first operand into one of the A registers...
1664 BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1667 // Emit a sign extension instruction...
1668 unsigned ShiftResult = makeAnotherReg(Ty);
1669 BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1670 BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1672 // If unsigned, emit a zeroing instruction... (reg = 0)
1673 BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0);
1676 // Emit the appropriate divide or remainder instruction...
1677 BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1679 // Figure out which register we want to pick the result out of...
1680 unsigned DestReg = isDiv ? Reg : ExtReg;
1682 // Put the result into the destination register...
1683 BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1687 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1688 /// for constant immediate shift values, and for constant immediate
1689 /// shift values equal to 1. Even the general case is sort of special,
1690 /// because the shift amount has to be in CL, not just any old register.
1692 void ISel::visitShiftInst(ShiftInst &I) {
1693 MachineBasicBlock::iterator IP = BB->end ();
1694 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1695 I.getOpcode () == Instruction::Shl, I.getType (),
1699 /// emitShiftOperation - Common code shared between visitShiftInst and
1700 /// constant expression support.
1701 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1702 MachineBasicBlock::iterator &IP,
1703 Value *Op, Value *ShiftAmount, bool isLeftShift,
1704 const Type *ResultTy, unsigned DestReg) {
1705 unsigned SrcReg = getReg (Op, MBB, IP);
1706 bool isSigned = ResultTy->isSigned ();
1707 unsigned Class = getClass (ResultTy);
1709 static const unsigned ConstantOperand[][4] = {
1710 { X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDri32 }, // SHR
1711 { X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDri32 }, // SAR
1712 { X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SHL
1713 { X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SAL = SHL
1716 static const unsigned NonConstantOperand[][4] = {
1717 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1718 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1719 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1720 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1723 // Longs, as usual, are handled specially...
1724 if (Class == cLong) {
1725 // If we have a constant shift, we can generate much more efficient code
1726 // than otherwise...
1728 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1729 unsigned Amount = CUI->getValue();
1731 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1733 BMI(MBB, IP, Opc[3], 3,
1734 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1735 BMI(MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1737 BMI(MBB, IP, Opc[3], 3,
1738 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1739 BMI(MBB, IP, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1741 } else { // Shifting more than 32 bits
1744 BMI(MBB, IP, X86::SHLri32, 2,
1745 DestReg + 1).addReg(SrcReg).addZImm(Amount);
1746 BMI(MBB, IP, X86::MOVri32, 1,
1747 DestReg).addZImm(0);
1749 unsigned Opcode = isSigned ? X86::SARri32 : X86::SHRri32;
1750 BMI(MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1751 BMI(MBB, IP, X86::MOVri32, 1, DestReg+1).addZImm(0);
1755 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1757 if (!isLeftShift && isSigned) {
1758 // If this is a SHR of a Long, then we need to do funny sign extension
1759 // stuff. TmpReg gets the value to use as the high-part if we are
1760 // shifting more than 32 bits.
1761 BMI(MBB, IP, X86::SARri32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1763 // Other shifts use a fixed zero value if the shift is more than 32
1765 BMI(MBB, IP, X86::MOVri32, 1, TmpReg).addZImm(0);
1768 // Initialize CL with the shift amount...
1769 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
1770 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1772 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1773 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1775 // TmpReg2 = shld inHi, inLo
1776 BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1777 // TmpReg3 = shl inLo, CL
1778 BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1780 // Set the flags to indicate whether the shift was by more than 32 bits.
1781 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1783 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1784 BMI(MBB, IP, X86::CMOVNErr32, 2,
1785 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1786 // DestLo = (>32) ? TmpReg : TmpReg3;
1787 BMI(MBB, IP, X86::CMOVNErr32, 2,
1788 DestReg).addReg(TmpReg3).addReg(TmpReg);
1790 // TmpReg2 = shrd inLo, inHi
1791 BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1792 // TmpReg3 = s[ah]r inHi, CL
1793 BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1796 // Set the flags to indicate whether the shift was by more than 32 bits.
1797 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1799 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1800 BMI(MBB, IP, X86::CMOVNErr32, 2,
1801 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1803 // DestHi = (>32) ? TmpReg : TmpReg3;
1804 BMI(MBB, IP, X86::CMOVNErr32, 2,
1805 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1811 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1812 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1813 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1815 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1816 BMI(MBB, IP, Opc[Class], 2,
1817 DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1818 } else { // The shift amount is non-constant.
1819 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
1820 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1822 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1823 BMI(MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
1828 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1829 /// instruction. The load and store instructions are the only place where we
1830 /// need to worry about the memory layout of the target machine.
1832 void ISel::visitLoadInst(LoadInst &I) {
1833 unsigned SrcAddrReg = getReg(I.getOperand(0));
1834 unsigned DestReg = getReg(I);
1836 unsigned Class = getClassB(I.getType());
1838 if (Class == cLong) {
1839 addDirectMem(BuildMI(BB, X86::MOVrm32, 4, DestReg), SrcAddrReg);
1840 addRegOffset(BuildMI(BB, X86::MOVrm32, 4, DestReg+1), SrcAddrReg, 4);
1844 static const unsigned Opcodes[] = {
1845 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr32
1847 unsigned Opcode = Opcodes[Class];
1848 if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
1849 addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
1852 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1855 void ISel::visitStoreInst(StoreInst &I) {
1856 unsigned ValReg = getReg(I.getOperand(0));
1857 unsigned AddressReg = getReg(I.getOperand(1));
1859 const Type *ValTy = I.getOperand(0)->getType();
1860 unsigned Class = getClassB(ValTy);
1862 if (Class == cLong) {
1863 addDirectMem(BuildMI(BB, X86::MOVmr32, 1+4), AddressReg).addReg(ValReg);
1864 addRegOffset(BuildMI(BB, X86::MOVmr32, 1+4), AddressReg,4).addReg(ValReg+1);
1868 static const unsigned Opcodes[] = {
1869 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTr32
1871 unsigned Opcode = Opcodes[Class];
1872 if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
1873 addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
1877 /// visitCastInst - Here we have various kinds of copying with or without
1878 /// sign extension going on.
1879 void ISel::visitCastInst(CastInst &CI) {
1880 Value *Op = CI.getOperand(0);
1881 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1882 // of the case are GEP instructions, then the cast does not need to be
1883 // generated explicitly, it will be folded into the GEP.
1884 if (CI.getType() == Type::LongTy &&
1885 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1886 bool AllUsesAreGEPs = true;
1887 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1888 if (!isa<GetElementPtrInst>(*I)) {
1889 AllUsesAreGEPs = false;
1893 // No need to codegen this cast if all users are getelementptr instrs...
1894 if (AllUsesAreGEPs) return;
1897 unsigned DestReg = getReg(CI);
1898 MachineBasicBlock::iterator MI = BB->end();
1899 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1902 /// emitCastOperation - Common code shared between visitCastInst and
1903 /// constant expression cast support.
1904 void ISel::emitCastOperation(MachineBasicBlock *BB,
1905 MachineBasicBlock::iterator &IP,
1906 Value *Src, const Type *DestTy,
1908 unsigned SrcReg = getReg(Src, BB, IP);
1909 const Type *SrcTy = Src->getType();
1910 unsigned SrcClass = getClassB(SrcTy);
1911 unsigned DestClass = getClassB(DestTy);
1913 // Implement casts to bool by using compare on the operand followed by set if
1914 // not zero on the result.
1915 if (DestTy == Type::BoolTy) {
1918 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1921 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1924 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1927 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1928 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1932 assert(0 && "FIXME: implement cast FP to bool");
1936 // If the zero flag is not set, then the value is true, set the byte to
1938 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1942 static const unsigned RegRegMove[] = {
1943 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1946 // Implement casts between values of the same type class (as determined by
1947 // getClass) by using a register-to-register move.
1948 if (SrcClass == DestClass) {
1949 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1950 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1951 } else if (SrcClass == cFP) {
1952 if (SrcTy == Type::FloatTy) { // double -> float
1953 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1954 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1955 } else { // float -> double
1956 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1957 "Unknown cFP member!");
1958 // Truncate from double to float by storing to memory as short, then
1960 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1961 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1962 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1963 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1965 } else if (SrcClass == cLong) {
1966 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1967 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1969 assert(0 && "Cannot handle this type of cast instruction!");
1975 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1976 // or zero extension, depending on whether the source type was signed.
1977 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1978 SrcClass < DestClass) {
1979 bool isLong = DestClass == cLong;
1980 if (isLong) DestClass = cInt;
1982 static const unsigned Opc[][4] = {
1983 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1984 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1987 bool isUnsigned = SrcTy->isUnsigned();
1988 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1989 DestReg).addReg(SrcReg);
1991 if (isLong) { // Handle upper 32 bits as appropriate...
1992 if (isUnsigned) // Zero out top bits...
1993 BMI(BB, IP, X86::MOVri32, 1, DestReg+1).addZImm(0);
1994 else // Sign extend bottom half...
1995 BMI(BB, IP, X86::SARri32, 2, DestReg+1).addReg(DestReg).addZImm(31);
2000 // Special case long -> int ...
2001 if (SrcClass == cLong && DestClass == cInt) {
2002 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
2006 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
2007 // move out of AX or AL.
2008 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2009 && SrcClass > DestClass) {
2010 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
2011 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
2012 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
2016 // Handle casts from integer to floating point now...
2017 if (DestClass == cFP) {
2018 // Promote the integer to a type supported by FLD. We do this because there
2019 // are no unsigned FLD instructions, so we must promote an unsigned value to
2020 // a larger signed value, then use FLD on the larger value.
2022 const Type *PromoteType = 0;
2023 unsigned PromoteOpcode;
2024 switch (SrcTy->getPrimitiveID()) {
2025 case Type::BoolTyID:
2026 case Type::SByteTyID:
2027 // We don't have the facilities for directly loading byte sized data from
2028 // memory (even signed). Promote it to 16 bits.
2029 PromoteType = Type::ShortTy;
2030 PromoteOpcode = X86::MOVSXr16r8;
2032 case Type::UByteTyID:
2033 PromoteType = Type::ShortTy;
2034 PromoteOpcode = X86::MOVZXr16r8;
2036 case Type::UShortTyID:
2037 PromoteType = Type::IntTy;
2038 PromoteOpcode = X86::MOVZXr32r16;
2040 case Type::UIntTyID: {
2041 // Make a 64 bit temporary... and zero out the top of it...
2042 unsigned TmpReg = makeAnotherReg(Type::LongTy);
2043 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
2044 BMI(BB, IP, X86::MOVri32, 1, TmpReg+1).addZImm(0);
2045 SrcTy = Type::LongTy;
2050 case Type::ULongTyID:
2051 assert("FIXME: not implemented: cast ulong X to fp type!");
2052 default: // No promotion needed...
2057 unsigned TmpReg = makeAnotherReg(PromoteType);
2058 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
2059 1, TmpReg).addReg(SrcReg);
2060 SrcTy = PromoteType;
2061 SrcClass = getClass(PromoteType);
2065 // Spill the integer to memory and reload it from there...
2067 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2069 if (SrcClass == cLong) {
2070 addFrameReference(BMI(BB, IP, X86::MOVmr32, 5), FrameIdx).addReg(SrcReg);
2071 addFrameReference(BMI(BB, IP, X86::MOVmr32, 5),
2072 FrameIdx, 4).addReg(SrcReg+1);
2074 static const unsigned Op1[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
2075 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
2078 static const unsigned Op2[] =
2079 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
2080 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
2084 // Handle casts from floating point to integer now...
2085 if (SrcClass == cFP) {
2086 // Change the floating point control register to use "round towards zero"
2087 // mode when truncating to an integer value.
2089 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
2090 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
2092 // Load the old value of the high byte of the control word...
2093 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
2094 addFrameReference(BMI(BB, IP, X86::MOVrm8, 4, HighPartOfCW), CWFrameIdx, 1);
2096 // Set the high part to be round to zero...
2097 addFrameReference(BMI(BB, IP, X86::MOVmi8, 5), CWFrameIdx, 1).addZImm(12);
2099 // Reload the modified control word now...
2100 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2102 // Restore the memory image of control word to original value
2103 addFrameReference(BMI(BB, IP, X86::MOVmr8, 5),
2104 CWFrameIdx, 1).addReg(HighPartOfCW);
2106 // We don't have the facilities for directly storing byte sized data to
2107 // memory. Promote it to 16 bits. We also must promote unsigned values to
2108 // larger classes because we only have signed FP stores.
2109 unsigned StoreClass = DestClass;
2110 const Type *StoreTy = DestTy;
2111 if (StoreClass == cByte || DestTy->isUnsigned())
2112 switch (StoreClass) {
2113 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
2114 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
2115 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
2116 // The following treatment of cLong may not be perfectly right,
2117 // but it survives chains of casts of the form
2118 // double->ulong->double.
2119 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
2120 default: assert(0 && "Unknown store class!");
2123 // Spill the integer to memory and reload it from there...
2125 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
2127 static const unsigned Op1[] =
2128 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
2129 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
2131 if (DestClass == cLong) {
2132 addFrameReference(BMI(BB, IP, X86::MOVrm32, 4, DestReg), FrameIdx);
2133 addFrameReference(BMI(BB, IP, X86::MOVrm32, 4, DestReg+1), FrameIdx, 4);
2135 static const unsigned Op2[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
2136 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
2139 // Reload the original control word now...
2140 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2144 // Anything we haven't handled already, we can't (yet) handle at all.
2145 assert(0 && "Unhandled cast instruction!");
2149 /// visitVANextInst - Implement the va_next instruction...
2151 void ISel::visitVANextInst(VANextInst &I) {
2152 unsigned VAList = getReg(I.getOperand(0));
2153 unsigned DestReg = getReg(I);
2156 switch (I.getArgType()->getPrimitiveID()) {
2159 assert(0 && "Error: bad type for va_next instruction!");
2161 case Type::PointerTyID:
2162 case Type::UIntTyID:
2166 case Type::ULongTyID:
2167 case Type::LongTyID:
2168 case Type::DoubleTyID:
2173 // Increment the VAList pointer...
2174 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
2177 void ISel::visitVAArgInst(VAArgInst &I) {
2178 unsigned VAList = getReg(I.getOperand(0));
2179 unsigned DestReg = getReg(I);
2181 switch (I.getType()->getPrimitiveID()) {
2184 assert(0 && "Error: bad type for va_next instruction!");
2186 case Type::PointerTyID:
2187 case Type::UIntTyID:
2189 addDirectMem(BuildMI(BB, X86::MOVrm32, 4, DestReg), VAList);
2191 case Type::ULongTyID:
2192 case Type::LongTyID:
2193 addDirectMem(BuildMI(BB, X86::MOVrm32, 4, DestReg), VAList);
2194 addRegOffset(BuildMI(BB, X86::MOVrm32, 4, DestReg+1), VAList, 4);
2196 case Type::DoubleTyID:
2197 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
2203 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2204 unsigned outputReg = getReg(I);
2205 emitGEPOperation(BB, BB->end(), I.getOperand(0),
2206 I.op_begin()+1, I.op_end(), outputReg);
2209 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2210 MachineBasicBlock::iterator IP,
2211 Value *Src, User::op_iterator IdxBegin,
2212 User::op_iterator IdxEnd, unsigned TargetReg) {
2213 const TargetData &TD = TM.getTargetData();
2215 std::vector<Value*> GEPOps;
2216 GEPOps.resize(IdxEnd-IdxBegin+1);
2218 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2220 std::vector<const Type*> GEPTypes;
2221 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2222 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2224 // Keep emitting instructions until we consume the entire GEP instruction.
2225 while (!GEPOps.empty()) {
2226 unsigned OldSize = GEPOps.size();
2228 if (GEPTypes.empty()) {
2229 // The getGEPIndex operation didn't want to build an LEA. Check to see if
2230 // all operands are consumed but the base pointer. If so, just load it
2231 // into the register.
2232 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
2233 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2234 return; // we are now done
2235 } else if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
2236 // It's a struct access. CUI is the index into the structure,
2237 // which names the field. This index must have unsigned type.
2238 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
2239 GEPOps.pop_back(); // Consume a GEP operand
2240 GEPTypes.pop_back();
2242 // Use the TargetData structure to pick out what the layout of the
2243 // structure is in memory. Since the structure index must be constant, we
2244 // can get its value and use it to find the right byte offset from the
2245 // StructLayout class's list of structure member offsets.
2246 unsigned idxValue = CUI->getValue();
2247 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
2249 unsigned Reg = makeAnotherReg(Type::UIntTy);
2250 // Emit an ADD to add FieldOff to the basePtr.
2251 BMI(MBB, IP, X86::ADDri32, 2, TargetReg).addReg(Reg).addZImm(FieldOff);
2252 --IP; // Insert the next instruction before this one.
2253 TargetReg = Reg; // Codegen the rest of the GEP into this
2257 // It's an array or pointer access: [ArraySize x ElementType].
2258 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2259 Value *idx = GEPOps.back();
2260 GEPOps.pop_back(); // Consume a GEP operand
2261 GEPTypes.pop_back();
2263 // idx is the index into the array. Unlike with structure
2264 // indices, we may not know its actual value at code-generation
2266 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2268 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2269 // operand on X86. Handle this case directly now...
2270 if (CastInst *CI = dyn_cast<CastInst>(idx))
2271 if (CI->getOperand(0)->getType() == Type::IntTy ||
2272 CI->getOperand(0)->getType() == Type::UIntTy)
2273 idx = CI->getOperand(0);
2275 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2276 // must find the size of the pointed-to type (Not coincidentally, the next
2277 // type is the type of the elements in the array).
2278 const Type *ElTy = SqTy->getElementType();
2279 unsigned elementSize = TD.getTypeSize(ElTy);
2281 // If idxReg is a constant, we don't need to perform the multiply!
2282 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2283 if (!CSI->isNullValue()) {
2284 unsigned Offset = elementSize*CSI->getValue();
2285 unsigned Reg = makeAnotherReg(Type::UIntTy);
2286 BMI(MBB, IP, X86::ADDri32, 2, TargetReg).addReg(Reg).addZImm(Offset);
2287 --IP; // Insert the next instruction before this one.
2288 TargetReg = Reg; // Codegen the rest of the GEP into this
2290 } else if (elementSize == 1) {
2291 // If the element size is 1, we don't have to multiply, just add
2292 unsigned idxReg = getReg(idx, MBB, IP);
2293 unsigned Reg = makeAnotherReg(Type::UIntTy);
2294 BMI(MBB, IP, X86::ADDrr32, 2, TargetReg).addReg(Reg).addReg(idxReg);
2295 --IP; // Insert the next instruction before this one.
2296 TargetReg = Reg; // Codegen the rest of the GEP into this
2298 unsigned idxReg = getReg(idx, MBB, IP);
2299 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2301 // Make sure we can back the iterator up to point to the first
2302 // instruction emitted.
2303 MachineBasicBlock::iterator BeforeIt = IP;
2304 if (IP == MBB->begin())
2305 BeforeIt = MBB->end();
2308 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2310 // Emit an ADD to add OffsetReg to the basePtr.
2311 unsigned Reg = makeAnotherReg(Type::UIntTy);
2312 BMI(MBB, IP, X86::ADDrr32, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
2314 // Step to the first instruction of the multiply.
2315 if (BeforeIt == MBB->end())
2320 TargetReg = Reg; // Codegen the rest of the GEP into this
2327 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2328 /// frame manager, otherwise do it the hard way.
2330 void ISel::visitAllocaInst(AllocaInst &I) {
2331 // Find the data size of the alloca inst's getAllocatedType.
2332 const Type *Ty = I.getAllocatedType();
2333 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2335 // If this is a fixed size alloca in the entry block for the function,
2336 // statically stack allocate the space.
2338 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2339 if (I.getParent() == I.getParent()->getParent()->begin()) {
2340 TySize *= CUI->getValue(); // Get total allocated size...
2341 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2343 // Create a new stack object using the frame manager...
2344 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2345 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2350 // Create a register to hold the temporary result of multiplying the type size
2351 // constant by the variable amount.
2352 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2353 unsigned SrcReg1 = getReg(I.getArraySize());
2355 // TotalSizeReg = mul <numelements>, <TypeSize>
2356 MachineBasicBlock::iterator MBBI = BB->end();
2357 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2359 // AddedSize = add <TotalSizeReg>, 15
2360 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2361 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2363 // AlignedSize = and <AddedSize>, ~15
2364 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2365 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2367 // Subtract size from stack pointer, thereby allocating some space.
2368 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2370 // Put a pointer to the space into the result register, by copying
2371 // the stack pointer.
2372 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2374 // Inform the Frame Information that we have just allocated a variable-sized
2376 F->getFrameInfo()->CreateVariableSizedObject();
2379 /// visitMallocInst - Malloc instructions are code generated into direct calls
2380 /// to the library malloc.
2382 void ISel::visitMallocInst(MallocInst &I) {
2383 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2386 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2387 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2389 Arg = makeAnotherReg(Type::UIntTy);
2390 unsigned Op0Reg = getReg(I.getOperand(0));
2391 MachineBasicBlock::iterator MBBI = BB->end();
2392 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2395 std::vector<ValueRecord> Args;
2396 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2397 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2398 1).addExternalSymbol("malloc", true);
2399 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2403 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2406 void ISel::visitFreeInst(FreeInst &I) {
2407 std::vector<ValueRecord> Args;
2408 Args.push_back(ValueRecord(I.getOperand(0)));
2409 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2410 1).addExternalSymbol("free", true);
2411 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2414 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2415 /// into a machine code representation is a very simple peep-hole fashion. The
2416 /// generated code sucks but the implementation is nice and simple.
2418 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
2419 return new ISel(TM);