1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/GetElementPtrTypeIterator.h"
30 #include "llvm/Support/InstVisitor.h"
31 #include "llvm/Support/CFG.h"
32 #include "Support/Statistic.h"
37 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
39 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
43 cByte, cShort, cInt, cFP, cLong
47 /// getClass - Turn a primitive type into a "class" number which is based on the
48 /// size of the type, and whether or not it is floating point.
50 static inline TypeClass getClass(const Type *Ty) {
51 switch (Ty->getPrimitiveID()) {
53 case Type::UByteTyID: return cByte; // Byte operands are class #0
55 case Type::UShortTyID: return cShort; // Short operands are class #1
58 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
61 case Type::DoubleTyID: return cFP; // Floating Point is #3
64 case Type::ULongTyID: return cLong; // Longs are class #4
66 assert(0 && "Invalid type to getClass!");
67 return cByte; // not reached
71 // getClassB - Just like getClass, but treat boolean values as bytes.
72 static inline TypeClass getClassB(const Type *Ty) {
73 if (Ty == Type::BoolTy) return cByte;
78 struct ISel : public FunctionPass, InstVisitor<ISel> {
80 MachineFunction *F; // The function we are compiling into
81 MachineBasicBlock *BB; // The current MBB we are compiling
82 int VarArgsFrameIndex; // FrameIndex for start of varargs area
83 int ReturnAddressIndex; // FrameIndex for the return address
85 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
87 // MBBMap - Mapping between LLVM BB -> Machine BB
88 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
90 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
92 /// runOnFunction - Top level implementation of instruction selection for
93 /// the entire function.
95 bool runOnFunction(Function &Fn) {
96 // First pass over the function, lower any unknown intrinsic functions
97 // with the IntrinsicLowering class.
98 LowerUnknownIntrinsicFunctionCalls(Fn);
100 F = &MachineFunction::construct(&Fn, TM);
102 // Create all of the machine basic blocks for the function...
103 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
104 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
108 // Set up a frame object for the return address. This is used by the
109 // llvm.returnaddress & llvm.frameaddress intrinisics.
110 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
112 // Copy incoming arguments off of the stack...
113 LoadArgumentsToVirtualRegs(Fn);
115 // Instruction select everything except PHI nodes
118 // Select the PHI nodes
121 // Insert the FP_REG_KILL instructions into blocks that need them.
127 // We always build a machine code representation for the function
131 virtual const char *getPassName() const {
132 return "X86 Simple Instruction Selection";
135 /// visitBasicBlock - This method is called when we are visiting a new basic
136 /// block. This simply creates a new MachineBasicBlock to emit code into
137 /// and adds it to the current MachineFunction. Subsequent visit* for
138 /// instructions will be invoked for all instructions in the basic block.
140 void visitBasicBlock(BasicBlock &LLVM_BB) {
141 BB = MBBMap[&LLVM_BB];
144 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
145 /// function, lowering any calls to unknown intrinsic functions into the
146 /// equivalent LLVM code.
148 void LowerUnknownIntrinsicFunctionCalls(Function &F);
150 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
151 /// from the stack into virtual registers.
153 void LoadArgumentsToVirtualRegs(Function &F);
155 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
156 /// because we have to generate our sources into the source basic blocks,
157 /// not the current one.
159 void SelectPHINodes();
161 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
162 /// that need them. This only occurs due to the floating point stackifier
163 /// not being aggressive enough to handle arbitrary global stackification.
165 void InsertFPRegKills();
167 // Visitation methods for various instructions. These methods simply emit
168 // fixed X86 code for each instruction.
171 // Control flow operators
172 void visitReturnInst(ReturnInst &RI);
173 void visitBranchInst(BranchInst &BI);
179 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
180 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
182 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
183 const std::vector<ValueRecord> &Args);
184 void visitCallInst(CallInst &I);
185 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
187 // Arithmetic operators
188 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
189 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
190 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
191 void visitMul(BinaryOperator &B);
193 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
194 void visitRem(BinaryOperator &B) { visitDivRem(B); }
195 void visitDivRem(BinaryOperator &B);
198 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
199 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
200 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
202 // Comparison operators...
203 void visitSetCondInst(SetCondInst &I);
204 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
205 MachineBasicBlock *MBB,
206 MachineBasicBlock::iterator MBBI);
207 void visitSelectInst(SelectInst &SI);
210 // Memory Instructions
211 void visitLoadInst(LoadInst &I);
212 void visitStoreInst(StoreInst &I);
213 void visitGetElementPtrInst(GetElementPtrInst &I);
214 void visitAllocaInst(AllocaInst &I);
215 void visitMallocInst(MallocInst &I);
216 void visitFreeInst(FreeInst &I);
219 void visitShiftInst(ShiftInst &I);
220 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
221 void visitCastInst(CastInst &I);
222 void visitVANextInst(VANextInst &I);
223 void visitVAArgInst(VAArgInst &I);
225 void visitInstruction(Instruction &I) {
226 std::cerr << "Cannot instruction select: " << I;
230 /// promote32 - Make a value 32-bits wide, and put it somewhere.
232 void promote32(unsigned targetReg, const ValueRecord &VR);
234 /// getAddressingMode - Get the addressing mode to use to address the
235 /// specified value. The returned value should be used with addFullAddress.
236 void getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
237 unsigned &IndexReg, unsigned &Disp);
240 /// getGEPIndex - This is used to fold GEP instructions into X86 addressing
242 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
243 std::vector<Value*> &GEPOps,
244 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
245 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
247 /// isGEPFoldable - Return true if the specified GEP can be completely
248 /// folded into the addressing mode of a load/store or lea instruction.
249 bool isGEPFoldable(MachineBasicBlock *MBB,
250 Value *Src, User::op_iterator IdxBegin,
251 User::op_iterator IdxEnd, unsigned &BaseReg,
252 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
254 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
255 /// constant expression GEP support.
257 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
258 Value *Src, User::op_iterator IdxBegin,
259 User::op_iterator IdxEnd, unsigned TargetReg);
261 /// emitCastOperation - Common code shared between visitCastInst and
262 /// constant expression cast support.
264 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
265 Value *Src, const Type *DestTy, unsigned TargetReg);
267 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
268 /// and constant expression support.
270 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
271 MachineBasicBlock::iterator IP,
272 Value *Op0, Value *Op1,
273 unsigned OperatorClass, unsigned TargetReg);
275 /// emitBinaryFPOperation - This method handles emission of floating point
276 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
277 void emitBinaryFPOperation(MachineBasicBlock *BB,
278 MachineBasicBlock::iterator IP,
279 Value *Op0, Value *Op1,
280 unsigned OperatorClass, unsigned TargetReg);
282 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
283 Value *Op0, Value *Op1, unsigned TargetReg);
285 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
286 unsigned DestReg, const Type *DestTy,
287 unsigned Op0Reg, unsigned Op1Reg);
288 void doMultiplyConst(MachineBasicBlock *MBB,
289 MachineBasicBlock::iterator MBBI,
290 unsigned DestReg, const Type *DestTy,
291 unsigned Op0Reg, unsigned Op1Val);
293 void emitDivRemOperation(MachineBasicBlock *BB,
294 MachineBasicBlock::iterator IP,
295 Value *Op0, Value *Op1, bool isDiv,
298 /// emitSetCCOperation - Common code shared between visitSetCondInst and
299 /// constant expression support.
301 void emitSetCCOperation(MachineBasicBlock *BB,
302 MachineBasicBlock::iterator IP,
303 Value *Op0, Value *Op1, unsigned Opcode,
306 /// emitShiftOperation - Common code shared between visitShiftInst and
307 /// constant expression support.
309 void emitShiftOperation(MachineBasicBlock *MBB,
310 MachineBasicBlock::iterator IP,
311 Value *Op, Value *ShiftAmount, bool isLeftShift,
312 const Type *ResultTy, unsigned DestReg);
314 /// emitSelectOperation - Common code shared between visitSelectInst and the
315 /// constant expression support.
316 void emitSelectOperation(MachineBasicBlock *MBB,
317 MachineBasicBlock::iterator IP,
318 Value *Cond, Value *TrueVal, Value *FalseVal,
321 /// copyConstantToRegister - Output the instructions required to put the
322 /// specified constant into the specified register.
324 void copyConstantToRegister(MachineBasicBlock *MBB,
325 MachineBasicBlock::iterator MBBI,
326 Constant *C, unsigned Reg);
328 /// makeAnotherReg - This method returns the next register number we haven't
331 /// Long values are handled somewhat specially. They are always allocated
332 /// as pairs of 32 bit integer values. The register number returned is the
333 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
334 /// of the long value.
336 unsigned makeAnotherReg(const Type *Ty) {
337 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
338 "Current target doesn't have X86 reg info??");
339 const X86RegisterInfo *MRI =
340 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
341 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
342 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
343 // Create the lower part
344 F->getSSARegMap()->createVirtualRegister(RC);
345 // Create the upper part.
346 return F->getSSARegMap()->createVirtualRegister(RC)-1;
349 // Add the mapping of regnumber => reg class to MachineFunction
350 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
351 return F->getSSARegMap()->createVirtualRegister(RC);
354 /// getReg - This method turns an LLVM value into a register number. This
355 /// is guaranteed to produce the same register number for a particular value
356 /// every time it is queried.
358 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
359 unsigned getReg(Value *V) {
360 // Just append to the end of the current bb.
361 MachineBasicBlock::iterator It = BB->end();
362 return getReg(V, BB, It);
364 unsigned getReg(Value *V, MachineBasicBlock *MBB,
365 MachineBasicBlock::iterator IPt) {
366 // If this operand is a constant, emit the code to copy the constant into
367 // the register here...
369 if (Constant *C = dyn_cast<Constant>(V)) {
370 unsigned Reg = makeAnotherReg(V->getType());
371 copyConstantToRegister(MBB, IPt, C, Reg);
373 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
374 unsigned Reg = makeAnotherReg(V->getType());
375 // Move the address of the global into the register
376 BuildMI(*MBB, IPt, X86::MOV32ri, 1, Reg).addGlobalAddress(GV);
378 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
379 // Do not emit noop casts at all.
380 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
381 return getReg(CI->getOperand(0), MBB, IPt);
384 unsigned &Reg = RegMap[V];
386 Reg = makeAnotherReg(V->getType());
395 /// copyConstantToRegister - Output the instructions required to put the
396 /// specified constant into the specified register.
398 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
399 MachineBasicBlock::iterator IP,
400 Constant *C, unsigned R) {
401 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
403 switch (CE->getOpcode()) {
404 case Instruction::GetElementPtr:
405 emitGEPOperation(MBB, IP, CE->getOperand(0),
406 CE->op_begin()+1, CE->op_end(), R);
408 case Instruction::Cast:
409 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
412 case Instruction::Xor: ++Class; // FALL THROUGH
413 case Instruction::Or: ++Class; // FALL THROUGH
414 case Instruction::And: ++Class; // FALL THROUGH
415 case Instruction::Sub: ++Class; // FALL THROUGH
416 case Instruction::Add:
417 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
421 case Instruction::Mul:
422 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
425 case Instruction::Div:
426 case Instruction::Rem:
427 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
428 CE->getOpcode() == Instruction::Div, R);
431 case Instruction::SetNE:
432 case Instruction::SetEQ:
433 case Instruction::SetLT:
434 case Instruction::SetGT:
435 case Instruction::SetLE:
436 case Instruction::SetGE:
437 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
441 case Instruction::Shl:
442 case Instruction::Shr:
443 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
444 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
447 case Instruction::Select:
448 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
449 CE->getOperand(2), R);
453 std::cerr << "Offending expr: " << C << "\n";
454 assert(0 && "Constant expression not yet handled!\n");
458 if (C->getType()->isIntegral()) {
459 unsigned Class = getClassB(C->getType());
461 if (Class == cLong) {
462 // Copy the value into the register pair.
463 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
464 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(Val & 0xFFFFFFFF);
465 BuildMI(*MBB, IP, X86::MOV32ri, 1, R+1).addImm(Val >> 32);
469 assert(Class <= cInt && "Type not handled yet!");
471 static const unsigned IntegralOpcodeTab[] = {
472 X86::MOV8ri, X86::MOV16ri, X86::MOV32ri
475 if (C->getType() == Type::BoolTy) {
476 BuildMI(*MBB, IP, X86::MOV8ri, 1, R).addImm(C == ConstantBool::True);
478 ConstantInt *CI = cast<ConstantInt>(C);
479 BuildMI(*MBB, IP, IntegralOpcodeTab[Class],1,R).addImm(CI->getRawValue());
481 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
482 if (CFP->isExactlyValue(+0.0))
483 BuildMI(*MBB, IP, X86::FLD0, 0, R);
484 else if (CFP->isExactlyValue(+1.0))
485 BuildMI(*MBB, IP, X86::FLD1, 0, R);
487 // Otherwise we need to spill the constant to memory...
488 MachineConstantPool *CP = F->getConstantPool();
489 unsigned CPI = CP->getConstantPoolIndex(CFP);
490 const Type *Ty = CFP->getType();
492 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
493 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m;
494 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI);
497 } else if (isa<ConstantPointerNull>(C)) {
498 // Copy zero (null pointer) to the register.
499 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(0);
500 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
501 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addGlobalAddress(CPR->getValue());
503 std::cerr << "Offending constant: " << C << "\n";
504 assert(0 && "Type not handled yet!");
508 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
509 /// the stack into virtual registers.
511 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
512 // Emit instructions to load the arguments... On entry to a function on the
513 // X86, the stack frame looks like this:
515 // [ESP] -- return address
516 // [ESP + 4] -- first argument (leftmost lexically)
517 // [ESP + 8] -- second argument, if first argument is four bytes in size
520 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
521 MachineFrameInfo *MFI = F->getFrameInfo();
523 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
524 bool ArgLive = !I->use_empty();
525 unsigned Reg = ArgLive ? getReg(*I) : 0;
526 int FI; // Frame object index
528 switch (getClassB(I->getType())) {
531 FI = MFI->CreateFixedObject(1, ArgOffset);
532 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Reg), FI);
537 FI = MFI->CreateFixedObject(2, ArgOffset);
538 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Reg), FI);
543 FI = MFI->CreateFixedObject(4, ArgOffset);
544 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
549 FI = MFI->CreateFixedObject(8, ArgOffset);
550 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
551 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg+1), FI, 4);
553 ArgOffset += 4; // longs require 4 additional bytes
558 if (I->getType() == Type::FloatTy) {
559 Opcode = X86::FLD32m;
560 FI = MFI->CreateFixedObject(4, ArgOffset);
562 Opcode = X86::FLD64m;
563 FI = MFI->CreateFixedObject(8, ArgOffset);
565 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
567 if (I->getType() == Type::DoubleTy)
568 ArgOffset += 4; // doubles require 4 additional bytes
571 assert(0 && "Unhandled argument type!");
573 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
576 // If the function takes variable number of arguments, add a frame offset for
577 // the start of the first vararg value... this is used to expand
579 if (Fn.getFunctionType()->isVarArg())
580 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
584 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
585 /// because we have to generate our sources into the source basic blocks, not
588 void ISel::SelectPHINodes() {
589 const TargetInstrInfo &TII = TM.getInstrInfo();
590 const Function &LF = *F->getFunction(); // The LLVM function...
591 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
592 const BasicBlock *BB = I;
593 MachineBasicBlock &MBB = *MBBMap[I];
595 // Loop over all of the PHI nodes in the LLVM basic block...
596 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
597 for (BasicBlock::const_iterator I = BB->begin();
598 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
600 // Create a new machine instr PHI node, and insert it.
601 unsigned PHIReg = getReg(*PN);
602 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
603 X86::PHI, PN->getNumOperands(), PHIReg);
605 MachineInstr *LongPhiMI = 0;
606 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
607 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
608 X86::PHI, PN->getNumOperands(), PHIReg+1);
610 // PHIValues - Map of blocks to incoming virtual registers. We use this
611 // so that we only initialize one incoming value for a particular block,
612 // even if the block has multiple entries in the PHI node.
614 std::map<MachineBasicBlock*, unsigned> PHIValues;
616 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
617 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
619 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
620 PHIValues.lower_bound(PredMBB);
622 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
623 // We already inserted an initialization of the register for this
624 // predecessor. Recycle it.
625 ValReg = EntryIt->second;
628 // Get the incoming value into a virtual register.
630 Value *Val = PN->getIncomingValue(i);
632 // If this is a constant or GlobalValue, we may have to insert code
633 // into the basic block to compute it into a virtual register.
634 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
635 if (isa<ConstantExpr>(Val)) {
636 // Because we don't want to clobber any values which might be in
637 // physical registers with the computation of this constant (which
638 // might be arbitrarily complex if it is a constant expression),
639 // just insert the computation at the top of the basic block.
640 MachineBasicBlock::iterator PI = PredMBB->begin();
642 // Skip over any PHI nodes though!
643 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
646 ValReg = getReg(Val, PredMBB, PI);
648 // Simple constants get emitted at the end of the basic block,
649 // before any terminator instructions. We "know" that the code to
650 // move a constant into a register will never clobber any flags.
651 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
654 ValReg = getReg(Val);
657 // Remember that we inserted a value for this PHI for this predecessor
658 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
661 PhiMI->addRegOperand(ValReg);
662 PhiMI->addMachineBasicBlockOperand(PredMBB);
664 LongPhiMI->addRegOperand(ValReg+1);
665 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
669 // Now that we emitted all of the incoming values for the PHI node, make
670 // sure to reposition the InsertPoint after the PHI that we just added.
671 // This is needed because we might have inserted a constant into this
672 // block, right after the PHI's which is before the old insert point!
673 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
679 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
680 /// compensation code on critical edges. As such, it requires that we kill all
681 /// FP registers on the exit from any blocks that either ARE critical edges, or
682 /// branch to a block that has incoming critical edges.
684 /// Note that this kill instruction will eventually be eliminated when
685 /// restrictions in the stackifier are relaxed.
687 static bool RequiresFPRegKill(const BasicBlock *BB) {
689 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
690 const BasicBlock *Succ = *SI;
691 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
692 ++PI; // Block have at least one predecessory
693 if (PI != PE) { // If it has exactly one, this isn't crit edge
694 // If this block has more than one predecessor, check all of the
695 // predecessors to see if they have multiple successors. If so, then the
696 // block we are analyzing needs an FPRegKill.
697 for (PI = pred_begin(Succ); PI != PE; ++PI) {
698 const BasicBlock *Pred = *PI;
699 succ_const_iterator SI2 = succ_begin(Pred);
700 ++SI2; // There must be at least one successor of this block.
701 if (SI2 != succ_end(Pred))
702 return true; // Yes, we must insert the kill on this edge.
706 // If we got this far, there is no need to insert the kill instruction.
713 // InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
714 // need them. This only occurs due to the floating point stackifier not being
715 // aggressive enough to handle arbitrary global stackification.
717 // Currently we insert an FP_REG_KILL instruction into each block that uses or
718 // defines a floating point virtual register.
720 // When the global register allocators (like linear scan) finally update live
721 // variable analysis, we can keep floating point values in registers across
722 // portions of the CFG that do not involve critical edges. This will be a big
723 // win, but we are waiting on the global allocators before we can do this.
725 // With a bit of work, the floating point stackifier pass can be enhanced to
726 // break critical edges as needed (to make a place to put compensation code),
727 // but this will require some infrastructure improvements as well.
729 void ISel::InsertFPRegKills() {
730 SSARegMap &RegMap = *F->getSSARegMap();
732 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
733 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
734 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
735 MachineOperand& MO = I->getOperand(i);
736 if (MO.isRegister() && MO.getReg()) {
737 unsigned Reg = MO.getReg();
738 if (MRegisterInfo::isVirtualRegister(Reg))
739 if (RegMap.getRegClass(Reg)->getSize() == 10)
743 // If we haven't found an FP register use or def in this basic block, check
744 // to see if any of our successors has an FP PHI node, which will cause a
745 // copy to be inserted into this block.
746 for (succ_const_iterator SI = succ_begin(BB->getBasicBlock()),
747 E = succ_end(BB->getBasicBlock()); SI != E; ++SI) {
748 MachineBasicBlock *SBB = MBBMap[*SI];
749 for (MachineBasicBlock::iterator I = SBB->begin();
750 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
751 if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
757 // Okay, this block uses an FP register. If the block has successors (ie,
758 // it's not an unwind/return), insert the FP_REG_KILL instruction.
759 if (BB->getBasicBlock()->getTerminator()->getNumSuccessors() &&
760 RequiresFPRegKill(BB->getBasicBlock())) {
761 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
768 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
769 // it into the conditional branch or select instruction which is the only user
770 // of the cc instruction. This is the case if the conditional branch is the
771 // only user of the setcc, and if the setcc is in the same basic block as the
772 // conditional branch. We also don't handle long arguments below, so we reject
773 // them here as well.
775 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
776 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
777 if (SCI->hasOneUse()) {
778 Instruction *User = cast<Instruction>(SCI->use_back());
779 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
780 SCI->getParent() == User->getParent() &&
781 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
782 SCI->getOpcode() == Instruction::SetEQ ||
783 SCI->getOpcode() == Instruction::SetNE))
789 // Return a fixed numbering for setcc instructions which does not depend on the
790 // order of the opcodes.
792 static unsigned getSetCCNumber(unsigned Opcode) {
794 default: assert(0 && "Unknown setcc instruction!");
795 case Instruction::SetEQ: return 0;
796 case Instruction::SetNE: return 1;
797 case Instruction::SetLT: return 2;
798 case Instruction::SetGE: return 3;
799 case Instruction::SetGT: return 4;
800 case Instruction::SetLE: return 5;
804 // LLVM -> X86 signed X86 unsigned
805 // ----- ---------- ------------
806 // seteq -> sete sete
807 // setne -> setne setne
808 // setlt -> setl setb
809 // setge -> setge setae
810 // setgt -> setg seta
811 // setle -> setle setbe
813 // sets // Used by comparison with 0 optimization
815 static const unsigned SetCCOpcodeTab[2][8] = {
816 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
818 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
819 X86::SETSr, X86::SETNSr },
822 // EmitComparison - This function emits a comparison of the two operands,
823 // returning the extended setcc code to use.
824 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
825 MachineBasicBlock *MBB,
826 MachineBasicBlock::iterator IP) {
827 // The arguments are already supposed to be of the same type.
828 const Type *CompTy = Op0->getType();
829 unsigned Class = getClassB(CompTy);
830 unsigned Op0r = getReg(Op0, MBB, IP);
832 // Special case handling of: cmp R, i
833 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
834 if (Class == cByte || Class == cShort || Class == cInt) {
835 unsigned Op1v = CI->getRawValue();
837 // Mask off any upper bits of the constant, if there are any...
838 Op1v &= (1ULL << (8 << Class)) - 1;
840 // If this is a comparison against zero, emit more efficient code. We
841 // can't handle unsigned comparisons against zero unless they are == or
842 // !=. These should have been strength reduced already anyway.
843 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
844 static const unsigned TESTTab[] = {
845 X86::TEST8rr, X86::TEST16rr, X86::TEST32rr
847 BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
849 if (OpNum == 2) return 6; // Map jl -> js
850 if (OpNum == 3) return 7; // Map jg -> jns
854 static const unsigned CMPTab[] = {
855 X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
858 BuildMI(*MBB, IP, CMPTab[Class], 2).addReg(Op0r).addImm(Op1v);
861 assert(Class == cLong && "Unknown integer class!");
862 unsigned LowCst = CI->getRawValue();
863 unsigned HiCst = CI->getRawValue() >> 32;
864 if (OpNum < 2) { // seteq, setne
865 unsigned LoTmp = Op0r;
867 LoTmp = makeAnotherReg(Type::IntTy);
868 BuildMI(*MBB, IP, X86::XOR32ri, 2, LoTmp).addReg(Op0r).addImm(LowCst);
870 unsigned HiTmp = Op0r+1;
872 HiTmp = makeAnotherReg(Type::IntTy);
873 BuildMI(*MBB, IP, X86::XOR32ri, 2,HiTmp).addReg(Op0r+1).addImm(HiCst);
875 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
876 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
879 // Emit a sequence of code which compares the high and low parts once
880 // each, then uses a conditional move to handle the overflow case. For
881 // example, a setlt for long would generate code like this:
883 // AL = lo(op1) < lo(op2) // Signedness depends on operands
884 // BL = hi(op1) < hi(op2) // Always unsigned comparison
885 // dest = hi(op1) == hi(op2) ? AL : BL;
888 // FIXME: This would be much better if we had hierarchical register
889 // classes! Until then, hardcode registers so that we can deal with
890 // their aliases (because we don't have conditional byte moves).
892 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(LowCst);
893 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
894 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r+1).addImm(HiCst);
895 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0,X86::BL);
896 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
897 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
898 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
900 // NOTE: visitSetCondInst knows that the value is dumped into the BL
901 // register at this point for long values...
907 // Special case handling of comparison against +/- 0.0
908 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
909 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
910 BuildMI(*MBB, IP, X86::FTST, 1).addReg(Op0r);
911 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
912 BuildMI(*MBB, IP, X86::SAHF, 1);
916 unsigned Op1r = getReg(Op1, MBB, IP);
918 default: assert(0 && "Unknown type class!");
919 // Emit: cmp <var1>, <var2> (do the comparison). We can
920 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
923 BuildMI(*MBB, IP, X86::CMP8rr, 2).addReg(Op0r).addReg(Op1r);
926 BuildMI(*MBB, IP, X86::CMP16rr, 2).addReg(Op0r).addReg(Op1r);
929 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
932 if (0) { // for processors prior to the P6
933 BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
934 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
935 BuildMI(*MBB, IP, X86::SAHF, 1);
937 BuildMI(*MBB, IP, X86::FpUCOMI, 2).addReg(Op0r).addReg(Op1r);
942 if (OpNum < 2) { // seteq, setne
943 unsigned LoTmp = makeAnotherReg(Type::IntTy);
944 unsigned HiTmp = makeAnotherReg(Type::IntTy);
945 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
946 BuildMI(*MBB, IP, X86::XOR32rr, 2, LoTmp).addReg(Op0r).addReg(Op1r);
947 BuildMI(*MBB, IP, X86::XOR32rr, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
948 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
949 break; // Allow the sete or setne to be generated from flags set by OR
951 // Emit a sequence of code which compares the high and low parts once
952 // each, then uses a conditional move to handle the overflow case. For
953 // example, a setlt for long would generate code like this:
955 // AL = lo(op1) < lo(op2) // Signedness depends on operands
956 // BL = hi(op1) < hi(op2) // Always unsigned comparison
957 // dest = hi(op1) == hi(op2) ? AL : BL;
960 // FIXME: This would be much better if we had hierarchical register
961 // classes! Until then, hardcode registers so that we can deal with their
962 // aliases (because we don't have conditional byte moves).
964 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
965 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
966 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r+1).addReg(Op1r+1);
967 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
968 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
969 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
970 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
972 // NOTE: visitSetCondInst knows that the value is dumped into the BL
973 // register at this point for long values...
980 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
981 /// register, then move it to wherever the result should be.
983 void ISel::visitSetCondInst(SetCondInst &I) {
984 if (canFoldSetCCIntoBranchOrSelect(&I))
985 return; // Fold this into a branch or select.
987 unsigned DestReg = getReg(I);
988 MachineBasicBlock::iterator MII = BB->end();
989 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
993 /// emitSetCCOperation - Common code shared between visitSetCondInst and
994 /// constant expression support.
996 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
997 MachineBasicBlock::iterator IP,
998 Value *Op0, Value *Op1, unsigned Opcode,
999 unsigned TargetReg) {
1000 unsigned OpNum = getSetCCNumber(Opcode);
1001 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
1003 const Type *CompTy = Op0->getType();
1004 unsigned CompClass = getClassB(CompTy);
1005 bool isSigned = CompTy->isSigned() && CompClass != cFP;
1007 if (CompClass != cLong || OpNum < 2) {
1008 // Handle normal comparisons with a setcc instruction...
1009 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
1011 // Handle long comparisons by copying the value which is already in BL into
1012 // the register we want...
1013 BuildMI(*MBB, IP, X86::MOV8rr, 1, TargetReg).addReg(X86::BL);
1017 void ISel::visitSelectInst(SelectInst &SI) {
1018 unsigned DestReg = getReg(SI);
1019 MachineBasicBlock::iterator MII = BB->end();
1020 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1021 SI.getFalseValue(), DestReg);
1024 /// emitSelect - Common code shared between visitSelectInst and the constant
1025 /// expression support.
1026 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
1027 MachineBasicBlock::iterator IP,
1028 Value *Cond, Value *TrueVal, Value *FalseVal,
1030 unsigned SelectClass = getClassB(TrueVal->getType());
1032 // We don't support 8-bit conditional moves. If we have incoming constants,
1033 // transform them into 16-bit constants to avoid having a run-time conversion.
1034 if (SelectClass == cByte) {
1035 if (Constant *T = dyn_cast<Constant>(TrueVal))
1036 TrueVal = ConstantExpr::getCast(T, Type::ShortTy);
1037 if (Constant *F = dyn_cast<Constant>(FalseVal))
1038 FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
1043 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1044 // We successfully folded the setcc into the select instruction.
1046 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1047 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
1050 const Type *CompTy = SCI->getOperand(0)->getType();
1051 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1053 // LLVM -> X86 signed X86 unsigned
1054 // ----- ---------- ------------
1055 // seteq -> cmovNE cmovNE
1056 // setne -> cmovE cmovE
1057 // setlt -> cmovGE cmovAE
1058 // setge -> cmovL cmovB
1059 // setgt -> cmovLE cmovBE
1060 // setle -> cmovG cmovA
1062 // cmovNS // Used by comparison with 0 optimization
1065 switch (SelectClass) {
1066 default: assert(0 && "Unknown value class!");
1068 // Annoyingly, we don't have a full set of floating point conditional
1070 static const unsigned OpcodeTab[2][8] = {
1071 { X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
1072 X86::FCMOVBE, X86::FCMOVA, 0, 0 },
1073 { X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
1075 Opcode = OpcodeTab[isSigned][OpNum];
1077 // If opcode == 0, we hit a case that we don't support. Output a setcc
1078 // and compare the result against zero.
1080 unsigned CompClass = getClassB(CompTy);
1082 if (CompClass != cLong || OpNum < 2) {
1083 CondReg = makeAnotherReg(Type::BoolTy);
1084 // Handle normal comparisons with a setcc instruction...
1085 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
1087 // Long comparisons end up in the BL register.
1091 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1092 Opcode = X86::FCMOVE;
1098 static const unsigned OpcodeTab[2][8] = {
1099 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
1100 X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
1101 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
1102 X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
1104 Opcode = OpcodeTab[isSigned][OpNum];
1109 static const unsigned OpcodeTab[2][8] = {
1110 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
1111 X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
1112 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
1113 X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
1115 Opcode = OpcodeTab[isSigned][OpNum];
1120 // Get the value being branched on, and use it to set the condition codes.
1121 unsigned CondReg = getReg(Cond, MBB, IP);
1122 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1123 switch (SelectClass) {
1124 default: assert(0 && "Unknown value class!");
1125 case cFP: Opcode = X86::FCMOVE; break;
1127 case cShort: Opcode = X86::CMOVE16rr; break;
1129 case cLong: Opcode = X86::CMOVE32rr; break;
1133 unsigned TrueReg = getReg(TrueVal, MBB, IP);
1134 unsigned FalseReg = getReg(FalseVal, MBB, IP);
1135 unsigned RealDestReg = DestReg;
1138 // Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
1139 // this, we have to promote the incoming values to 16 bits, perform a 16-bit
1140 // cmove, then truncate the result.
1141 if (SelectClass == cByte) {
1142 DestReg = makeAnotherReg(Type::ShortTy);
1143 if (getClassB(TrueVal->getType()) == cByte) {
1144 // Promote the true value, by storing it into AL, and reading from AX.
1145 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::AL).addReg(TrueReg);
1146 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::AH).addImm(0);
1147 TrueReg = makeAnotherReg(Type::ShortTy);
1148 BuildMI(*MBB, IP, X86::MOV16rr, 1, TrueReg).addReg(X86::AX);
1150 if (getClassB(FalseVal->getType()) == cByte) {
1151 // Promote the true value, by storing it into CL, and reading from CX.
1152 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(FalseReg);
1153 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::CH).addImm(0);
1154 FalseReg = makeAnotherReg(Type::ShortTy);
1155 BuildMI(*MBB, IP, X86::MOV16rr, 1, FalseReg).addReg(X86::CX);
1159 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(TrueReg).addReg(FalseReg);
1161 switch (SelectClass) {
1163 // We did the computation with 16-bit registers. Truncate back to our
1164 // result by copying into AX then copying out AL.
1165 BuildMI(*MBB, IP, X86::MOV16rr, 1, X86::AX).addReg(DestReg);
1166 BuildMI(*MBB, IP, X86::MOV8rr, 1, RealDestReg).addReg(X86::AL);
1169 // Move the upper half of the value as well.
1170 BuildMI(*MBB, IP, Opcode, 2,DestReg+1).addReg(TrueReg+1).addReg(FalseReg+1);
1177 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1178 /// operand, in the specified target register.
1180 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1181 bool isUnsigned = VR.Ty->isUnsigned();
1183 Value *Val = VR.Val;
1184 const Type *Ty = VR.Ty;
1186 if (Constant *C = dyn_cast<Constant>(Val)) {
1187 Val = ConstantExpr::getCast(C, Type::IntTy);
1191 // If this is a simple constant, just emit a MOVri directly to avoid the
1193 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1194 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1195 BuildMI(BB, X86::MOV32ri, 1, targetReg).addImm(TheVal);
1200 // Make sure we have the register number for this value...
1201 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1203 switch (getClassB(Ty)) {
1205 // Extend value into target register (8->32)
1207 BuildMI(BB, X86::MOVZX32rr8, 1, targetReg).addReg(Reg);
1209 BuildMI(BB, X86::MOVSX32rr8, 1, targetReg).addReg(Reg);
1212 // Extend value into target register (16->32)
1214 BuildMI(BB, X86::MOVZX32rr16, 1, targetReg).addReg(Reg);
1216 BuildMI(BB, X86::MOVSX32rr16, 1, targetReg).addReg(Reg);
1219 // Move value into target register (32->32)
1220 BuildMI(BB, X86::MOV32rr, 1, targetReg).addReg(Reg);
1223 assert(0 && "Unpromotable operand class in promote32");
1227 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
1228 /// we have the following possibilities:
1230 /// ret void: No return value, simply emit a 'ret' instruction
1231 /// ret sbyte, ubyte : Extend value into EAX and return
1232 /// ret short, ushort: Extend value into EAX and return
1233 /// ret int, uint : Move value into EAX and return
1234 /// ret pointer : Move value into EAX and return
1235 /// ret long, ulong : Move value into EAX/EDX and return
1236 /// ret float/double : Top of FP stack
1238 void ISel::visitReturnInst(ReturnInst &I) {
1239 if (I.getNumOperands() == 0) {
1240 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
1244 Value *RetVal = I.getOperand(0);
1245 switch (getClassB(RetVal->getType())) {
1246 case cByte: // integral return values: extend or move into EAX and return
1249 promote32(X86::EAX, ValueRecord(RetVal));
1250 // Declare that EAX is live on exit
1251 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
1253 case cFP: { // Floats & Doubles: Return in ST(0)
1254 unsigned RetReg = getReg(RetVal);
1255 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
1256 // Declare that top-of-stack is live on exit
1257 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
1261 unsigned RetReg = getReg(RetVal);
1262 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
1263 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
1264 // Declare that EAX & EDX are live on exit
1265 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
1270 visitInstruction(I);
1272 // Emit a 'ret' instruction
1273 BuildMI(BB, X86::RET, 0);
1276 // getBlockAfter - Return the basic block which occurs lexically after the
1278 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1279 Function::iterator I = BB; ++I; // Get iterator to next block
1280 return I != BB->getParent()->end() ? &*I : 0;
1283 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1284 /// that since code layout is frozen at this point, that if we are trying to
1285 /// jump to a block that is the immediate successor of the current block, we can
1286 /// just make a fall-through (but we don't currently).
1288 void ISel::visitBranchInst(BranchInst &BI) {
1289 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1291 if (!BI.isConditional()) { // Unconditional branch?
1292 if (BI.getSuccessor(0) != NextBB)
1293 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1297 // See if we can fold the setcc into the branch itself...
1298 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1300 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1301 // computed some other way...
1302 unsigned condReg = getReg(BI.getCondition());
1303 BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
1304 if (BI.getSuccessor(1) == NextBB) {
1305 if (BI.getSuccessor(0) != NextBB)
1306 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
1308 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
1310 if (BI.getSuccessor(0) != NextBB)
1311 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1316 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1317 MachineBasicBlock::iterator MII = BB->end();
1318 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1320 const Type *CompTy = SCI->getOperand(0)->getType();
1321 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1324 // LLVM -> X86 signed X86 unsigned
1325 // ----- ---------- ------------
1333 // js // Used by comparison with 0 optimization
1336 static const unsigned OpcodeTab[2][8] = {
1337 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1338 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1339 X86::JS, X86::JNS },
1342 if (BI.getSuccessor(0) != NextBB) {
1343 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1344 if (BI.getSuccessor(1) != NextBB)
1345 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1347 // Change to the inverse condition...
1348 if (BI.getSuccessor(1) != NextBB) {
1350 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1356 /// doCall - This emits an abstract call instruction, setting up the arguments
1357 /// and the return value as appropriate. For the actual function call itself,
1358 /// it inserts the specified CallMI instruction into the stream.
1360 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1361 const std::vector<ValueRecord> &Args) {
1363 // Count how many bytes are to be pushed on the stack...
1364 unsigned NumBytes = 0;
1366 if (!Args.empty()) {
1367 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1368 switch (getClassB(Args[i].Ty)) {
1369 case cByte: case cShort: case cInt:
1370 NumBytes += 4; break;
1372 NumBytes += 8; break;
1374 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1376 default: assert(0 && "Unknown class!");
1379 // Adjust the stack pointer for the new arguments...
1380 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1382 // Arguments go on the stack in reverse order, as specified by the ABI.
1383 unsigned ArgOffset = 0;
1384 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1386 switch (getClassB(Args[i].Ty)) {
1389 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1390 // Zero/Sign extend constant, then stuff into memory.
1391 ConstantInt *Val = cast<ConstantInt>(Args[i].Val);
1392 Val = cast<ConstantInt>(ConstantExpr::getCast(Val, Type::IntTy));
1393 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1394 .addImm(Val->getRawValue() & 0xFFFFFFFF);
1396 // Promote arg to 32 bits wide into a temporary register...
1397 ArgReg = makeAnotherReg(Type::UIntTy);
1398 promote32(ArgReg, Args[i]);
1399 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1400 X86::ESP, ArgOffset).addReg(ArgReg);
1404 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1405 unsigned Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1406 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1407 X86::ESP, ArgOffset).addImm(Val);
1409 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1410 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1411 X86::ESP, ArgOffset).addReg(ArgReg);
1415 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1416 uint64_t Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1417 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1418 X86::ESP, ArgOffset).addImm(Val & ~0U);
1419 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1420 X86::ESP, ArgOffset+4).addImm(Val >> 32ULL);
1422 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1423 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1424 X86::ESP, ArgOffset).addReg(ArgReg);
1425 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1426 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1428 ArgOffset += 4; // 8 byte entry, not 4.
1432 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1433 if (Args[i].Ty == Type::FloatTy) {
1434 addRegOffset(BuildMI(BB, X86::FST32m, 5),
1435 X86::ESP, ArgOffset).addReg(ArgReg);
1437 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1438 addRegOffset(BuildMI(BB, X86::FST64m, 5),
1439 X86::ESP, ArgOffset).addReg(ArgReg);
1440 ArgOffset += 4; // 8 byte entry, not 4.
1444 default: assert(0 && "Unknown class!");
1449 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(0);
1452 BB->push_back(CallMI);
1454 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addImm(NumBytes);
1456 // If there is a return value, scavenge the result from the location the call
1459 if (Ret.Ty != Type::VoidTy) {
1460 unsigned DestClass = getClassB(Ret.Ty);
1461 switch (DestClass) {
1465 // Integral results are in %eax, or the appropriate portion
1467 static const unsigned regRegMove[] = {
1468 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr
1470 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1471 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1474 case cFP: // Floating-point return values live in %ST(0)
1475 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1477 case cLong: // Long values are left in EDX:EAX
1478 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg).addReg(X86::EAX);
1479 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg+1).addReg(X86::EDX);
1481 default: assert(0 && "Unknown class!");
1487 /// visitCallInst - Push args on stack and do a procedure call instruction.
1488 void ISel::visitCallInst(CallInst &CI) {
1489 MachineInstr *TheCall;
1490 if (Function *F = CI.getCalledFunction()) {
1491 // Is it an intrinsic function call?
1492 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1493 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1497 // Emit a CALL instruction with PC-relative displacement.
1498 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1499 } else { // Emit an indirect call...
1500 unsigned Reg = getReg(CI.getCalledValue());
1501 TheCall = BuildMI(X86::CALL32r, 1).addReg(Reg);
1504 std::vector<ValueRecord> Args;
1505 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1506 Args.push_back(ValueRecord(CI.getOperand(i)));
1508 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1509 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1513 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1514 /// function, lowering any calls to unknown intrinsic functions into the
1515 /// equivalent LLVM code.
1517 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1518 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1519 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1520 if (CallInst *CI = dyn_cast<CallInst>(I++))
1521 if (Function *F = CI->getCalledFunction())
1522 switch (F->getIntrinsicID()) {
1523 case Intrinsic::not_intrinsic:
1524 case Intrinsic::vastart:
1525 case Intrinsic::vacopy:
1526 case Intrinsic::vaend:
1527 case Intrinsic::returnaddress:
1528 case Intrinsic::frameaddress:
1529 case Intrinsic::memcpy:
1530 case Intrinsic::memset:
1531 case Intrinsic::readport:
1532 case Intrinsic::writeport:
1533 // We directly implement these intrinsics
1536 // All other intrinsic calls we must lower.
1537 Instruction *Before = CI->getPrev();
1538 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1539 if (Before) { // Move iterator to instruction after call
1548 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1549 unsigned TmpReg1, TmpReg2;
1551 case Intrinsic::vastart:
1552 // Get the address of the first vararg value...
1553 TmpReg1 = getReg(CI);
1554 addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex);
1557 case Intrinsic::vacopy:
1558 TmpReg1 = getReg(CI);
1559 TmpReg2 = getReg(CI.getOperand(1));
1560 BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2);
1562 case Intrinsic::vaend: return; // Noop on X86
1564 case Intrinsic::returnaddress:
1565 case Intrinsic::frameaddress:
1566 TmpReg1 = getReg(CI);
1567 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1568 if (ID == Intrinsic::returnaddress) {
1569 // Just load the return address
1570 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, TmpReg1),
1571 ReturnAddressIndex);
1573 addFrameReference(BuildMI(BB, X86::LEA32r, 4, TmpReg1),
1574 ReturnAddressIndex, -4);
1577 // Values other than zero are not implemented yet.
1578 BuildMI(BB, X86::MOV32ri, 1, TmpReg1).addImm(0);
1582 case Intrinsic::memcpy: {
1583 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1585 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1586 Align = AlignC->getRawValue();
1587 if (Align == 0) Align = 1;
1590 // Turn the byte code into # iterations
1593 switch (Align & 3) {
1594 case 2: // WORD aligned
1595 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1596 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1598 CountReg = makeAnotherReg(Type::IntTy);
1599 unsigned ByteReg = getReg(CI.getOperand(3));
1600 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1602 Opcode = X86::REP_MOVSW;
1604 case 0: // DWORD aligned
1605 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1606 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1608 CountReg = makeAnotherReg(Type::IntTy);
1609 unsigned ByteReg = getReg(CI.getOperand(3));
1610 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1612 Opcode = X86::REP_MOVSD;
1614 default: // BYTE aligned
1615 CountReg = getReg(CI.getOperand(3));
1616 Opcode = X86::REP_MOVSB;
1620 // No matter what the alignment is, we put the source in ESI, the
1621 // destination in EDI, and the count in ECX.
1622 TmpReg1 = getReg(CI.getOperand(1));
1623 TmpReg2 = getReg(CI.getOperand(2));
1624 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1625 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1626 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
1627 BuildMI(BB, Opcode, 0);
1630 case Intrinsic::memset: {
1631 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1633 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1634 Align = AlignC->getRawValue();
1635 if (Align == 0) Align = 1;
1638 // Turn the byte code into # iterations
1641 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1642 unsigned Val = ValC->getRawValue() & 255;
1644 // If the value is a constant, then we can potentially use larger copies.
1645 switch (Align & 3) {
1646 case 2: // WORD aligned
1647 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1648 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1650 CountReg = makeAnotherReg(Type::IntTy);
1651 unsigned ByteReg = getReg(CI.getOperand(3));
1652 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1654 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
1655 Opcode = X86::REP_STOSW;
1657 case 0: // DWORD aligned
1658 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1659 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1661 CountReg = makeAnotherReg(Type::IntTy);
1662 unsigned ByteReg = getReg(CI.getOperand(3));
1663 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1665 Val = (Val << 8) | Val;
1666 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
1667 Opcode = X86::REP_STOSD;
1669 default: // BYTE aligned
1670 CountReg = getReg(CI.getOperand(3));
1671 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
1672 Opcode = X86::REP_STOSB;
1676 // If it's not a constant value we are storing, just fall back. We could
1677 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1678 unsigned ValReg = getReg(CI.getOperand(2));
1679 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1680 CountReg = getReg(CI.getOperand(3));
1681 Opcode = X86::REP_STOSB;
1684 // No matter what the alignment is, we put the source in ESI, the
1685 // destination in EDI, and the count in ECX.
1686 TmpReg1 = getReg(CI.getOperand(1));
1687 //TmpReg2 = getReg(CI.getOperand(2));
1688 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1689 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1690 BuildMI(BB, Opcode, 0);
1694 case Intrinsic::readport: {
1695 // First, determine that the size of the operand falls within the acceptable
1696 // range for this architecture.
1698 if (getClassB(CI.getOperand(1)->getType()) != cShort) {
1699 std::cerr << "llvm.readport: Address size is not 16 bits\n";
1703 // Now, move the I/O port address into the DX register and use the IN
1704 // instruction to get the input data.
1706 unsigned Class = getClass(CI.getCalledFunction()->getReturnType());
1707 unsigned DestReg = getReg(CI);
1709 // If the port is a single-byte constant, use the immediate form.
1710 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(1)))
1711 if ((C->getRawValue() & 255) == C->getRawValue()) {
1714 BuildMI(BB, X86::IN8ri, 1).addImm((unsigned char)C->getRawValue());
1715 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1718 BuildMI(BB, X86::IN16ri, 1).addImm((unsigned char)C->getRawValue());
1719 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1722 BuildMI(BB, X86::IN32ri, 1).addImm((unsigned char)C->getRawValue());
1723 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1728 unsigned Reg = getReg(CI.getOperand(1));
1729 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1732 BuildMI(BB, X86::IN8rr, 0);
1733 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1736 BuildMI(BB, X86::IN16rr, 0);
1737 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1740 BuildMI(BB, X86::IN32rr, 0);
1741 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1744 std::cerr << "Cannot do input on this data type";
1750 case Intrinsic::writeport: {
1751 // First, determine that the size of the operand falls within the
1752 // acceptable range for this architecture.
1753 if (getClass(CI.getOperand(2)->getType()) != cShort) {
1754 std::cerr << "llvm.writeport: Address size is not 16 bits\n";
1758 unsigned Class = getClassB(CI.getOperand(1)->getType());
1759 unsigned ValReg = getReg(CI.getOperand(1));
1762 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1765 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(ValReg);
1768 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(ValReg);
1771 std::cerr << "llvm.writeport: invalid data type for X86 target";
1776 // If the port is a single-byte constant, use the immediate form.
1777 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(2)))
1778 if ((C->getRawValue() & 255) == C->getRawValue()) {
1779 static const unsigned O[] = { X86::OUT8ir, X86::OUT16ir, X86::OUT32ir };
1780 BuildMI(BB, O[Class], 1).addImm((unsigned char)C->getRawValue());
1784 // Otherwise, move the I/O port address into the DX register and the value
1785 // to write into the AL/AX/EAX register.
1786 static const unsigned Opc[] = { X86::OUT8rr, X86::OUT16rr, X86::OUT32rr };
1787 unsigned Reg = getReg(CI.getOperand(2));
1788 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1789 BuildMI(BB, Opc[Class], 0);
1793 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1797 static bool isSafeToFoldLoadIntoInstruction(LoadInst &LI, Instruction &User) {
1798 if (LI.getParent() != User.getParent())
1800 BasicBlock::iterator It = &LI;
1801 // Check all of the instructions between the load and the user. We should
1802 // really use alias analysis here, but for now we just do something simple.
1803 for (++It; It != BasicBlock::iterator(&User); ++It) {
1804 switch (It->getOpcode()) {
1805 case Instruction::Free:
1806 case Instruction::Store:
1807 case Instruction::Call:
1808 case Instruction::Invoke:
1810 case Instruction::Load:
1811 if (cast<LoadInst>(It)->isVolatile() && LI.isVolatile())
1819 /// visitSimpleBinary - Implement simple binary operators for integral types...
1820 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1823 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1824 unsigned DestReg = getReg(B);
1825 MachineBasicBlock::iterator MI = BB->end();
1826 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1828 // Special case: op Reg, load [mem]
1829 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
1830 if (!B.swapOperands())
1831 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
1833 unsigned Class = getClassB(B.getType());
1834 if (isa<LoadInst>(Op1) && Class != cLong &&
1835 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op1), B)) {
1839 static const unsigned OpcodeTab[][3] = {
1840 // Arithmetic operators
1841 { X86::ADD8rm, X86::ADD16rm, X86::ADD32rm }, // ADD
1842 { X86::SUB8rm, X86::SUB16rm, X86::SUB32rm }, // SUB
1844 // Bitwise operators
1845 { X86::AND8rm, X86::AND16rm, X86::AND32rm }, // AND
1846 { X86:: OR8rm, X86:: OR16rm, X86:: OR32rm }, // OR
1847 { X86::XOR8rm, X86::XOR16rm, X86::XOR32rm }, // XOR
1849 Opcode = OpcodeTab[OperatorClass][Class];
1851 static const unsigned OpcodeTab[][2] = {
1852 { X86::FADD32m, X86::FADD64m }, // ADD
1853 { X86::FSUB32m, X86::FSUB64m }, // SUB
1855 const Type *Ty = Op0->getType();
1856 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1857 Opcode = OpcodeTab[OperatorClass][Ty == Type::DoubleTy];
1860 unsigned BaseReg, Scale, IndexReg, Disp;
1861 getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
1862 Scale, IndexReg, Disp);
1864 unsigned Op0r = getReg(Op0);
1865 addFullAddress(BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r),
1866 BaseReg, Scale, IndexReg, Disp);
1870 // If this is a floating point subtract, check to see if we can fold the first
1872 if (Class == cFP && OperatorClass == 1 &&
1873 isa<LoadInst>(Op0) &&
1874 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B)) {
1875 const Type *Ty = Op0->getType();
1876 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1877 unsigned Opcode = Ty == Type::FloatTy ? X86::FSUBR32m : X86::FSUBR64m;
1879 unsigned BaseReg, Scale, IndexReg, Disp;
1880 getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), BaseReg,
1881 Scale, IndexReg, Disp);
1883 unsigned Op1r = getReg(Op1);
1884 addFullAddress(BuildMI(BB, Opcode, 2, DestReg).addReg(Op1r),
1885 BaseReg, Scale, IndexReg, Disp);
1889 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1893 /// emitBinaryFPOperation - This method handles emission of floating point
1894 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1895 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1896 MachineBasicBlock::iterator IP,
1897 Value *Op0, Value *Op1,
1898 unsigned OperatorClass, unsigned DestReg) {
1900 // Special case: op Reg, <const fp>
1901 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1))
1902 if (!Op1C->isExactlyValue(+0.0) && !Op1C->isExactlyValue(+1.0)) {
1903 // Create a constant pool entry for this constant.
1904 MachineConstantPool *CP = F->getConstantPool();
1905 unsigned CPI = CP->getConstantPoolIndex(Op1C);
1906 const Type *Ty = Op1->getType();
1908 static const unsigned OpcodeTab[][4] = {
1909 { X86::FADD32m, X86::FSUB32m, X86::FMUL32m, X86::FDIV32m }, // Float
1910 { X86::FADD64m, X86::FSUB64m, X86::FMUL64m, X86::FDIV64m }, // Double
1913 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1914 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1915 unsigned Op0r = getReg(Op0, BB, IP);
1916 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
1917 DestReg).addReg(Op0r), CPI);
1921 // Special case: R1 = op <const fp>, R2
1922 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1923 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
1925 unsigned op1Reg = getReg(Op1, BB, IP);
1926 BuildMI(*BB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1928 } else if (!CFP->isExactlyValue(+0.0) && !CFP->isExactlyValue(+1.0)) {
1929 // R1 = op CST, R2 --> R1 = opr R2, CST
1931 // Create a constant pool entry for this constant.
1932 MachineConstantPool *CP = F->getConstantPool();
1933 unsigned CPI = CP->getConstantPoolIndex(CFP);
1934 const Type *Ty = CFP->getType();
1936 static const unsigned OpcodeTab[][4] = {
1937 { X86::FADD32m, X86::FSUBR32m, X86::FMUL32m, X86::FDIVR32m }, // Float
1938 { X86::FADD64m, X86::FSUBR64m, X86::FMUL64m, X86::FDIVR64m }, // Double
1941 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
1942 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1943 unsigned Op1r = getReg(Op1, BB, IP);
1944 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
1945 DestReg).addReg(Op1r), CPI);
1950 static const unsigned OpcodeTab[4] = {
1951 X86::FpADD, X86::FpSUB, X86::FpMUL, X86::FpDIV
1954 unsigned Opcode = OpcodeTab[OperatorClass];
1955 unsigned Op0r = getReg(Op0, BB, IP);
1956 unsigned Op1r = getReg(Op1, BB, IP);
1957 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1960 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1961 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1964 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1965 /// and constant expression support.
1967 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1968 MachineBasicBlock::iterator IP,
1969 Value *Op0, Value *Op1,
1970 unsigned OperatorClass, unsigned DestReg) {
1971 unsigned Class = getClassB(Op0->getType());
1974 assert(OperatorClass < 2 && "No logical ops for FP!");
1975 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1979 // sub 0, X -> neg X
1980 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1981 if (OperatorClass == 1 && CI->isNullValue()) {
1982 unsigned op1Reg = getReg(Op1, MBB, IP);
1983 static unsigned const NEGTab[] = {
1984 X86::NEG8r, X86::NEG16r, X86::NEG32r, 0, X86::NEG32r
1986 BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg);
1988 if (Class == cLong) {
1989 // We just emitted: Dl = neg Sl
1990 // Now emit : T = addc Sh, 0
1992 unsigned T = makeAnotherReg(Type::IntTy);
1993 BuildMI(*MBB, IP, X86::ADC32ri, 2, T).addReg(op1Reg+1).addImm(0);
1994 BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg+1).addReg(T);
1999 // Special case: op Reg, <const int>
2000 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
2001 unsigned Op0r = getReg(Op0, MBB, IP);
2003 // xor X, -1 -> not X
2004 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
2005 static unsigned const NOTTab[] = {
2006 X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
2008 BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
2009 if (Class == cLong) // Invert the top part too
2010 BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
2014 // add X, -1 -> dec X
2015 if (OperatorClass == 0 && Op1C->isAllOnesValue() && Class != cLong) {
2016 // Note that we can't use dec for 64-bit decrements, because it does not
2017 // set the carry flag!
2018 static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
2019 BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
2023 // add X, 1 -> inc X
2024 if (OperatorClass == 0 && Op1C->equalsInt(1) && Class != cLong) {
2025 // Note that we can't use inc for 64-bit increments, because it does not
2026 // set the carry flag!
2027 static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
2028 BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
2032 static const unsigned OpcodeTab[][5] = {
2033 // Arithmetic operators
2034 { X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
2035 { X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
2037 // Bitwise operators
2038 { X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
2039 { X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
2040 { X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
2043 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2044 unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
2046 if (Class != cLong) {
2047 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2051 // If this is a long value and the high or low bits have a special
2052 // property, emit some special cases.
2053 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
2055 // If the constant is zero in the low 32-bits, just copy the low part
2056 // across and apply the normal 32-bit operation to the high parts. There
2057 // will be no carry or borrow into the top.
2059 if (OperatorClass != 2) // All but and...
2060 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0r);
2062 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2063 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg+1)
2064 .addReg(Op0r+1).addImm(Op1h);
2068 // If this is a logical operation and the top 32-bits are zero, just
2069 // operate on the lower 32.
2070 if (Op1h == 0 && OperatorClass > 1) {
2071 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg)
2072 .addReg(Op0r).addImm(Op1l);
2073 if (OperatorClass != 2) // All but and
2074 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(Op0r+1);
2076 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2080 // TODO: We could handle lots of other special cases here, such as AND'ing
2081 // with 0xFFFFFFFF00000000 -> noop, etc.
2083 // Otherwise, code generate the full operation with a constant.
2084 static const unsigned TopTab[] = {
2085 X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
2088 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2089 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
2090 .addReg(Op0r+1).addImm(Op1h);
2094 // Finally, handle the general case now.
2095 static const unsigned OpcodeTab[][5] = {
2096 // Arithmetic operators
2097 { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, 0, X86::ADD32rr }, // ADD
2098 { X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, 0, X86::SUB32rr }, // SUB
2100 // Bitwise operators
2101 { X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
2102 { X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
2103 { X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
2106 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2107 unsigned Op0r = getReg(Op0, MBB, IP);
2108 unsigned Op1r = getReg(Op1, MBB, IP);
2109 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2111 if (Class == cLong) { // Handle the upper 32 bits of long values...
2112 static const unsigned TopTab[] = {
2113 X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
2115 BuildMI(*MBB, IP, TopTab[OperatorClass], 2,
2116 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
2120 /// doMultiply - Emit appropriate instructions to multiply together the
2121 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
2122 /// result should be given as DestTy.
2124 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
2125 unsigned DestReg, const Type *DestTy,
2126 unsigned op0Reg, unsigned op1Reg) {
2127 unsigned Class = getClass(DestTy);
2131 BuildMI(*MBB, MBBI, Class == cInt ? X86::IMUL32rr:X86::IMUL16rr, 2, DestReg)
2132 .addReg(op0Reg).addReg(op1Reg);
2135 // Must use the MUL instruction, which forces use of AL...
2136 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, X86::AL).addReg(op0Reg);
2137 BuildMI(*MBB, MBBI, X86::MUL8r, 1).addReg(op1Reg);
2138 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
2141 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
2145 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
2146 // returns zero when the input is not exactly a power of two.
2147 static unsigned ExactLog2(unsigned Val) {
2148 if (Val == 0) return 0;
2151 if (Val & 1) return 0;
2159 /// doMultiplyConst - This function is specialized to efficiently codegen an 8,
2160 /// 16, or 32-bit integer multiply by a constant.
2161 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
2162 MachineBasicBlock::iterator IP,
2163 unsigned DestReg, const Type *DestTy,
2164 unsigned op0Reg, unsigned ConstRHS) {
2165 static const unsigned MOVrrTab[] = {X86::MOV8rr, X86::MOV16rr, X86::MOV32rr};
2166 static const unsigned MOVriTab[] = {X86::MOV8ri, X86::MOV16ri, X86::MOV32ri};
2168 unsigned Class = getClass(DestTy);
2170 if (ConstRHS == 0) {
2171 BuildMI(*MBB, IP, MOVriTab[Class], 1, DestReg).addImm(0);
2173 } else if (ConstRHS == 1) {
2174 BuildMI(*MBB, IP, MOVrrTab[Class], 1, DestReg).addReg(op0Reg);
2178 // If the element size is exactly a power of 2, use a shift to get it.
2179 if (unsigned Shift = ExactLog2(ConstRHS)) {
2181 default: assert(0 && "Unknown class for this function!");
2183 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2186 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2189 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2194 if (Class == cShort) {
2195 BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2197 } else if (Class == cInt) {
2198 BuildMI(*MBB, IP, X86::IMUL32rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2202 // Most general case, emit a normal multiply...
2203 unsigned TmpReg = makeAnotherReg(DestTy);
2204 BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS);
2206 // Emit a MUL to multiply the register holding the index by
2207 // elementSize, putting the result in OffsetReg.
2208 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
2211 /// visitMul - Multiplies are not simple binary operators because they must deal
2212 /// with the EAX register explicitly.
2214 void ISel::visitMul(BinaryOperator &I) {
2215 unsigned ResultReg = getReg(I);
2217 Value *Op0 = I.getOperand(0);
2218 Value *Op1 = I.getOperand(1);
2220 // Fold loads into floating point multiplies.
2221 if (getClass(Op0->getType()) == cFP) {
2222 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
2223 if (!I.swapOperands())
2224 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
2225 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2226 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2227 const Type *Ty = Op0->getType();
2228 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2229 unsigned Opcode = Ty == Type::FloatTy ? X86::FMUL32m : X86::FMUL64m;
2231 unsigned BaseReg, Scale, IndexReg, Disp;
2232 getAddressingMode(LI->getOperand(0), BaseReg,
2233 Scale, IndexReg, Disp);
2235 unsigned Op0r = getReg(Op0);
2236 addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op0r),
2237 BaseReg, Scale, IndexReg, Disp);
2242 MachineBasicBlock::iterator IP = BB->end();
2243 emitMultiply(BB, IP, Op0, Op1, ResultReg);
2246 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
2247 Value *Op0, Value *Op1, unsigned DestReg) {
2248 MachineBasicBlock &BB = *MBB;
2249 TypeClass Class = getClass(Op0->getType());
2251 // Simple scalar multiply?
2252 unsigned Op0Reg = getReg(Op0, &BB, IP);
2257 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2258 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
2259 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
2261 unsigned Op1Reg = getReg(Op1, &BB, IP);
2262 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
2266 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
2272 // Long value. We have to do things the hard way...
2273 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2274 unsigned CLow = CI->getRawValue();
2275 unsigned CHi = CI->getRawValue() >> 32;
2278 // If the low part of the constant is all zeros, things are simple.
2279 BuildMI(BB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2280 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
2284 // Multiply the two low parts... capturing carry into EDX
2285 unsigned OverflowReg = 0;
2287 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0Reg);
2289 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
2290 OverflowReg = makeAnotherReg(Type::UIntTy);
2291 BuildMI(BB, IP, X86::MOV32ri, 1, Op1RegL).addImm(CLow);
2292 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2293 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1RegL); // AL*BL
2295 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2296 BuildMI(BB, IP, X86::MOV32rr, 1,
2297 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2300 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2301 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
2303 unsigned AHBLplusOverflowReg;
2305 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2306 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2307 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2309 AHBLplusOverflowReg = AHBLReg;
2313 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(AHBLplusOverflowReg);
2315 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2316 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
2318 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2319 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2324 // General 64x64 multiply
2326 unsigned Op1Reg = getReg(Op1, &BB, IP);
2327 // Multiply the two low parts... capturing carry into EDX
2328 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2329 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL
2331 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
2332 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2333 BuildMI(BB, IP, X86::MOV32rr, 1,
2334 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2336 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2337 BuildMI(BB, IP, X86::IMUL32rr, 2,
2338 AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
2340 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2341 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2342 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2344 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2345 BuildMI(BB, IP, X86::IMUL32rr, 2,
2346 ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
2348 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2349 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2353 /// visitDivRem - Handle division and remainder instructions... these
2354 /// instruction both require the same instructions to be generated, they just
2355 /// select the result from a different register. Note that both of these
2356 /// instructions work differently for signed and unsigned operands.
2358 void ISel::visitDivRem(BinaryOperator &I) {
2359 unsigned ResultReg = getReg(I);
2360 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
2362 // Fold loads into floating point divides.
2363 if (getClass(Op0->getType()) == cFP) {
2364 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2365 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2366 const Type *Ty = Op0->getType();
2367 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2368 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIV32m : X86::FDIV64m;
2370 unsigned BaseReg, Scale, IndexReg, Disp;
2371 getAddressingMode(LI->getOperand(0), BaseReg,
2372 Scale, IndexReg, Disp);
2374 unsigned Op0r = getReg(Op0);
2375 addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op0r),
2376 BaseReg, Scale, IndexReg, Disp);
2380 if (LoadInst *LI = dyn_cast<LoadInst>(Op0))
2381 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2382 const Type *Ty = Op0->getType();
2383 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2384 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIVR32m : X86::FDIVR64m;
2386 unsigned BaseReg, Scale, IndexReg, Disp;
2387 getAddressingMode(LI->getOperand(0), BaseReg,
2388 Scale, IndexReg, Disp);
2390 unsigned Op1r = getReg(Op1);
2391 addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op1r),
2392 BaseReg, Scale, IndexReg, Disp);
2398 MachineBasicBlock::iterator IP = BB->end();
2399 emitDivRemOperation(BB, IP, Op0, Op1,
2400 I.getOpcode() == Instruction::Div, ResultReg);
2403 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
2404 MachineBasicBlock::iterator IP,
2405 Value *Op0, Value *Op1, bool isDiv,
2406 unsigned ResultReg) {
2407 const Type *Ty = Op0->getType();
2408 unsigned Class = getClass(Ty);
2410 case cFP: // Floating point divide
2412 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
2414 } else { // Floating point remainder...
2415 unsigned Op0Reg = getReg(Op0, BB, IP);
2416 unsigned Op1Reg = getReg(Op1, BB, IP);
2417 MachineInstr *TheCall =
2418 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
2419 std::vector<ValueRecord> Args;
2420 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
2421 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
2422 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
2426 static const char *FnName[] =
2427 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
2428 unsigned Op0Reg = getReg(Op0, BB, IP);
2429 unsigned Op1Reg = getReg(Op1, BB, IP);
2430 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
2431 MachineInstr *TheCall =
2432 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
2434 std::vector<ValueRecord> Args;
2435 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
2436 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
2437 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
2440 case cByte: case cShort: case cInt:
2441 break; // Small integrals, handled below...
2442 default: assert(0 && "Unknown class!");
2445 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
2446 static const unsigned MovOpcode[]={ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr };
2447 static const unsigned SarOpcode[]={ X86::SAR8ri, X86::SAR16ri, X86::SAR32ri };
2448 static const unsigned ClrOpcode[]={ X86::MOV8ri, X86::MOV16ri, X86::MOV32ri };
2449 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
2451 static const unsigned DivOpcode[][4] = {
2452 { X86::DIV8r , X86::DIV16r , X86::DIV32r , 0 }, // Unsigned division
2453 { X86::IDIV8r, X86::IDIV16r, X86::IDIV32r, 0 }, // Signed division
2456 bool isSigned = Ty->isSigned();
2457 unsigned Reg = Regs[Class];
2458 unsigned ExtReg = ExtRegs[Class];
2460 // Put the first operand into one of the A registers...
2461 unsigned Op0Reg = getReg(Op0, BB, IP);
2462 unsigned Op1Reg = getReg(Op1, BB, IP);
2463 BuildMI(*BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
2466 // Emit a sign extension instruction...
2467 unsigned ShiftResult = makeAnotherReg(Op0->getType());
2468 BuildMI(*BB, IP, SarOpcode[Class], 2,ShiftResult).addReg(Op0Reg).addImm(31);
2469 BuildMI(*BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
2471 // If unsigned, emit a zeroing instruction... (reg = 0)
2472 BuildMI(*BB, IP, ClrOpcode[Class], 2, ExtReg).addImm(0);
2475 // Emit the appropriate divide or remainder instruction...
2476 BuildMI(*BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
2478 // Figure out which register we want to pick the result out of...
2479 unsigned DestReg = isDiv ? Reg : ExtReg;
2481 // Put the result into the destination register...
2482 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
2486 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2487 /// for constant immediate shift values, and for constant immediate
2488 /// shift values equal to 1. Even the general case is sort of special,
2489 /// because the shift amount has to be in CL, not just any old register.
2491 void ISel::visitShiftInst(ShiftInst &I) {
2492 MachineBasicBlock::iterator IP = BB->end ();
2493 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
2494 I.getOpcode () == Instruction::Shl, I.getType (),
2498 /// emitShiftOperation - Common code shared between visitShiftInst and
2499 /// constant expression support.
2500 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2501 MachineBasicBlock::iterator IP,
2502 Value *Op, Value *ShiftAmount, bool isLeftShift,
2503 const Type *ResultTy, unsigned DestReg) {
2504 unsigned SrcReg = getReg (Op, MBB, IP);
2505 bool isSigned = ResultTy->isSigned ();
2506 unsigned Class = getClass (ResultTy);
2508 static const unsigned ConstantOperand[][4] = {
2509 { X86::SHR8ri, X86::SHR16ri, X86::SHR32ri, X86::SHRD32rri8 }, // SHR
2510 { X86::SAR8ri, X86::SAR16ri, X86::SAR32ri, X86::SHRD32rri8 }, // SAR
2511 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SHL
2512 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SAL = SHL
2515 static const unsigned NonConstantOperand[][4] = {
2516 { X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL }, // SHR
2517 { X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL }, // SAR
2518 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SHL
2519 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SAL = SHL
2522 // Longs, as usual, are handled specially...
2523 if (Class == cLong) {
2524 // If we have a constant shift, we can generate much more efficient code
2525 // than otherwise...
2527 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2528 unsigned Amount = CUI->getValue();
2530 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2532 BuildMI(*MBB, IP, Opc[3], 3,
2533 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addImm(Amount);
2534 BuildMI(*MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addImm(Amount);
2536 BuildMI(*MBB, IP, Opc[3], 3,
2537 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount);
2538 BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount);
2540 } else { // Shifting more than 32 bits
2544 BuildMI(*MBB, IP, X86::SHL32ri, 2,
2545 DestReg + 1).addReg(SrcReg).addImm(Amount);
2547 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg);
2549 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2552 BuildMI(*MBB, IP, isSigned ? X86::SAR32ri : X86::SHR32ri, 2,
2553 DestReg).addReg(SrcReg+1).addImm(Amount);
2555 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg+1);
2557 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2561 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2563 if (!isLeftShift && isSigned) {
2564 // If this is a SHR of a Long, then we need to do funny sign extension
2565 // stuff. TmpReg gets the value to use as the high-part if we are
2566 // shifting more than 32 bits.
2567 BuildMI(*MBB, IP, X86::SAR32ri, 2, TmpReg).addReg(SrcReg).addImm(31);
2569 // Other shifts use a fixed zero value if the shift is more than 32
2571 BuildMI(*MBB, IP, X86::MOV32ri, 1, TmpReg).addImm(0);
2574 // Initialize CL with the shift amount...
2575 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
2576 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2578 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2579 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2581 // TmpReg2 = shld inHi, inLo
2582 BuildMI(*MBB, IP, X86::SHLD32rrCL,2,TmpReg2).addReg(SrcReg+1)
2584 // TmpReg3 = shl inLo, CL
2585 BuildMI(*MBB, IP, X86::SHL32rCL, 1, TmpReg3).addReg(SrcReg);
2587 // Set the flags to indicate whether the shift was by more than 32 bits.
2588 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2590 // DestHi = (>32) ? TmpReg3 : TmpReg2;
2591 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2592 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
2593 // DestLo = (>32) ? TmpReg : TmpReg3;
2594 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2595 DestReg).addReg(TmpReg3).addReg(TmpReg);
2597 // TmpReg2 = shrd inLo, inHi
2598 BuildMI(*MBB, IP, X86::SHRD32rrCL,2,TmpReg2).addReg(SrcReg)
2600 // TmpReg3 = s[ah]r inHi, CL
2601 BuildMI(*MBB, IP, isSigned ? X86::SAR32rCL : X86::SHR32rCL, 1, TmpReg3)
2604 // Set the flags to indicate whether the shift was by more than 32 bits.
2605 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2607 // DestLo = (>32) ? TmpReg3 : TmpReg2;
2608 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2609 DestReg).addReg(TmpReg2).addReg(TmpReg3);
2611 // DestHi = (>32) ? TmpReg : TmpReg3;
2612 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2613 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
2619 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2620 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2621 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2623 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2624 BuildMI(*MBB, IP, Opc[Class], 2,
2625 DestReg).addReg(SrcReg).addImm(CUI->getValue());
2626 } else { // The shift amount is non-constant.
2627 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2628 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2630 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
2631 BuildMI(*MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
2636 void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
2637 unsigned &IndexReg, unsigned &Disp) {
2638 BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
2639 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
2640 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
2641 BaseReg, Scale, IndexReg, Disp))
2643 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
2644 if (CE->getOpcode() == Instruction::GetElementPtr)
2645 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
2646 BaseReg, Scale, IndexReg, Disp))
2650 // If it's not foldable, reset addr mode.
2651 BaseReg = getReg(Addr);
2652 Scale = 1; IndexReg = 0; Disp = 0;
2656 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
2657 /// instruction. The load and store instructions are the only place where we
2658 /// need to worry about the memory layout of the target machine.
2660 void ISel::visitLoadInst(LoadInst &I) {
2661 // Check to see if this load instruction is going to be folded into a binary
2662 // instruction, like add. If so, we don't want to emit it. Wouldn't a real
2663 // pattern matching instruction selector be nice?
2664 unsigned Class = getClassB(I.getType());
2665 if (I.hasOneUse()) {
2666 Instruction *User = cast<Instruction>(I.use_back());
2667 switch (User->getOpcode()) {
2668 case Instruction::Cast:
2669 // If this is a cast from a signed-integer type to a floating point type,
2670 // fold the cast here.
2671 if (getClass(User->getType()) == cFP &&
2672 (I.getType() == Type::ShortTy || I.getType() == Type::IntTy ||
2673 I.getType() == Type::LongTy)) {
2674 unsigned DestReg = getReg(User);
2675 static const unsigned Opcode[] = {
2676 0/*BYTE*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m
2678 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
2679 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
2680 addFullAddress(BuildMI(BB, Opcode[Class], 5, DestReg),
2681 BaseReg, Scale, IndexReg, Disp);
2688 case Instruction::Add:
2689 case Instruction::Sub:
2690 case Instruction::And:
2691 case Instruction::Or:
2692 case Instruction::Xor:
2693 if (Class == cLong) User = 0;
2695 case Instruction::Mul:
2696 case Instruction::Div:
2697 if (Class != cFP) User = 0;
2698 break; // Folding only implemented for floating point.
2699 default: User = 0; break;
2703 // Okay, we found a user. If the load is the first operand and there is
2704 // no second operand load, reverse the operand ordering. Note that this
2705 // can fail for a subtract (ie, no change will be made).
2706 if (!isa<LoadInst>(User->getOperand(1)))
2707 cast<BinaryOperator>(User)->swapOperands();
2709 // Okay, now that everything is set up, if this load is used by the second
2710 // operand, and if there are no instructions that invalidate the load
2711 // before the binary operator, eliminate the load.
2712 if (User->getOperand(1) == &I &&
2713 isSafeToFoldLoadIntoInstruction(I, *User))
2714 return; // Eliminate the load!
2716 // If this is a floating point sub or div, we won't be able to swap the
2717 // operands, but we will still be able to eliminate the load.
2718 if (Class == cFP && User->getOperand(0) == &I &&
2719 !isa<LoadInst>(User->getOperand(1)) &&
2720 (User->getOpcode() == Instruction::Sub ||
2721 User->getOpcode() == Instruction::Div) &&
2722 isSafeToFoldLoadIntoInstruction(I, *User))
2723 return; // Eliminate the load!
2727 unsigned DestReg = getReg(I);
2728 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
2729 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
2731 if (Class == cLong) {
2732 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
2733 BaseReg, Scale, IndexReg, Disp);
2734 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
2735 BaseReg, Scale, IndexReg, Disp+4);
2739 static const unsigned Opcodes[] = {
2740 X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m
2742 unsigned Opcode = Opcodes[Class];
2743 if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m;
2744 addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
2745 BaseReg, Scale, IndexReg, Disp);
2748 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
2751 void ISel::visitStoreInst(StoreInst &I) {
2752 unsigned BaseReg, Scale, IndexReg, Disp;
2753 getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
2755 const Type *ValTy = I.getOperand(0)->getType();
2756 unsigned Class = getClassB(ValTy);
2758 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
2759 uint64_t Val = CI->getRawValue();
2760 if (Class == cLong) {
2761 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
2762 BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
2763 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
2764 BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
2766 static const unsigned Opcodes[] = {
2767 X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
2769 unsigned Opcode = Opcodes[Class];
2770 addFullAddress(BuildMI(BB, Opcode, 5),
2771 BaseReg, Scale, IndexReg, Disp).addImm(Val);
2773 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
2774 addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
2775 BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
2777 if (Class == cLong) {
2778 unsigned ValReg = getReg(I.getOperand(0));
2779 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
2780 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2781 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
2782 BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
2784 unsigned ValReg = getReg(I.getOperand(0));
2785 static const unsigned Opcodes[] = {
2786 X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST32m
2788 unsigned Opcode = Opcodes[Class];
2789 if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
2790 addFullAddress(BuildMI(BB, Opcode, 1+4),
2791 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2797 /// visitCastInst - Here we have various kinds of copying with or without sign
2798 /// extension going on.
2800 void ISel::visitCastInst(CastInst &CI) {
2801 Value *Op = CI.getOperand(0);
2803 unsigned SrcClass = getClassB(Op->getType());
2804 unsigned DestClass = getClassB(CI.getType());
2805 // Noop casts are not emitted: getReg will return the source operand as the
2806 // register to use for any uses of the noop cast.
2807 if (DestClass == SrcClass)
2810 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2811 // of the case are GEP instructions, then the cast does not need to be
2812 // generated explicitly, it will be folded into the GEP.
2813 if (DestClass == cLong && SrcClass == cInt) {
2814 bool AllUsesAreGEPs = true;
2815 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2816 if (!isa<GetElementPtrInst>(*I)) {
2817 AllUsesAreGEPs = false;
2821 // No need to codegen this cast if all users are getelementptr instrs...
2822 if (AllUsesAreGEPs) return;
2825 // If this cast converts a load from a short,int, or long integer to a FP
2826 // value, we will have folded this cast away.
2827 if (DestClass == cFP && isa<LoadInst>(Op) && Op->hasOneUse() &&
2828 (Op->getType() == Type::ShortTy || Op->getType() == Type::IntTy ||
2829 Op->getType() == Type::LongTy))
2833 unsigned DestReg = getReg(CI);
2834 MachineBasicBlock::iterator MI = BB->end();
2835 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2838 /// emitCastOperation - Common code shared between visitCastInst and constant
2839 /// expression cast support.
2841 void ISel::emitCastOperation(MachineBasicBlock *BB,
2842 MachineBasicBlock::iterator IP,
2843 Value *Src, const Type *DestTy,
2845 const Type *SrcTy = Src->getType();
2846 unsigned SrcClass = getClassB(SrcTy);
2847 unsigned DestClass = getClassB(DestTy);
2848 unsigned SrcReg = getReg(Src, BB, IP);
2850 // Implement casts to bool by using compare on the operand followed by set if
2851 // not zero on the result.
2852 if (DestTy == Type::BoolTy) {
2855 BuildMI(*BB, IP, X86::TEST8rr, 2).addReg(SrcReg).addReg(SrcReg);
2858 BuildMI(*BB, IP, X86::TEST16rr, 2).addReg(SrcReg).addReg(SrcReg);
2861 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg).addReg(SrcReg);
2864 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2865 BuildMI(*BB, IP, X86::OR32rr, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
2869 BuildMI(*BB, IP, X86::FTST, 1).addReg(SrcReg);
2870 BuildMI(*BB, IP, X86::FNSTSW8r, 0);
2871 BuildMI(*BB, IP, X86::SAHF, 1);
2875 // If the zero flag is not set, then the value is true, set the byte to
2877 BuildMI(*BB, IP, X86::SETNEr, 1, DestReg);
2881 static const unsigned RegRegMove[] = {
2882 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
2885 // Implement casts between values of the same type class (as determined by
2886 // getClass) by using a register-to-register move.
2887 if (SrcClass == DestClass) {
2888 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
2889 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
2890 } else if (SrcClass == cFP) {
2891 if (SrcTy == Type::FloatTy) { // double -> float
2892 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2893 BuildMI(*BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
2894 } else { // float -> double
2895 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2896 "Unknown cFP member!");
2897 // Truncate from double to float by storing to memory as short, then
2899 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
2900 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
2901 addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5), FrameIdx).addReg(SrcReg);
2902 addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx);
2904 } else if (SrcClass == cLong) {
2905 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
2906 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg+1);
2908 assert(0 && "Cannot handle this type of cast instruction!");
2914 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2915 // or zero extension, depending on whether the source type was signed.
2916 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2917 SrcClass < DestClass) {
2918 bool isLong = DestClass == cLong;
2919 if (isLong) DestClass = cInt;
2921 static const unsigned Opc[][4] = {
2922 { X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s
2923 { X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u
2926 bool isUnsigned = SrcTy->isUnsigned();
2927 BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
2928 DestReg).addReg(SrcReg);
2930 if (isLong) { // Handle upper 32 bits as appropriate...
2931 if (isUnsigned) // Zero out top bits...
2932 BuildMI(*BB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2933 else // Sign extend bottom half...
2934 BuildMI(*BB, IP, X86::SAR32ri, 2, DestReg+1).addReg(DestReg).addImm(31);
2939 // Special case long -> int ...
2940 if (SrcClass == cLong && DestClass == cInt) {
2941 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
2945 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
2946 // move out of AX or AL.
2947 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2948 && SrcClass > DestClass) {
2949 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
2950 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
2951 BuildMI(*BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
2955 // Handle casts from integer to floating point now...
2956 if (DestClass == cFP) {
2957 // Promote the integer to a type supported by FLD. We do this because there
2958 // are no unsigned FLD instructions, so we must promote an unsigned value to
2959 // a larger signed value, then use FLD on the larger value.
2961 const Type *PromoteType = 0;
2962 unsigned PromoteOpcode = 0;
2963 unsigned RealDestReg = DestReg;
2964 switch (SrcTy->getPrimitiveID()) {
2965 case Type::BoolTyID:
2966 case Type::SByteTyID:
2967 // We don't have the facilities for directly loading byte sized data from
2968 // memory (even signed). Promote it to 16 bits.
2969 PromoteType = Type::ShortTy;
2970 PromoteOpcode = X86::MOVSX16rr8;
2972 case Type::UByteTyID:
2973 PromoteType = Type::ShortTy;
2974 PromoteOpcode = X86::MOVZX16rr8;
2976 case Type::UShortTyID:
2977 PromoteType = Type::IntTy;
2978 PromoteOpcode = X86::MOVZX32rr16;
2980 case Type::UIntTyID: {
2981 // Make a 64 bit temporary... and zero out the top of it...
2982 unsigned TmpReg = makeAnotherReg(Type::LongTy);
2983 BuildMI(*BB, IP, X86::MOV32rr, 1, TmpReg).addReg(SrcReg);
2984 BuildMI(*BB, IP, X86::MOV32ri, 1, TmpReg+1).addImm(0);
2985 SrcTy = Type::LongTy;
2990 case Type::ULongTyID:
2991 // Don't fild into the read destination.
2992 DestReg = makeAnotherReg(Type::DoubleTy);
2994 default: // No promotion needed...
2999 unsigned TmpReg = makeAnotherReg(PromoteType);
3000 BuildMI(*BB, IP, PromoteOpcode, 1, TmpReg).addReg(SrcReg);
3001 SrcTy = PromoteType;
3002 SrcClass = getClass(PromoteType);
3006 // Spill the integer to memory and reload it from there...
3008 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
3010 if (SrcClass == cLong) {
3011 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3012 FrameIdx).addReg(SrcReg);
3013 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3014 FrameIdx, 4).addReg(SrcReg+1);
3016 static const unsigned Op1[] = { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr };
3017 addFrameReference(BuildMI(*BB, IP, Op1[SrcClass], 5),
3018 FrameIdx).addReg(SrcReg);
3021 static const unsigned Op2[] =
3022 { 0/*byte*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m };
3023 addFrameReference(BuildMI(*BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
3025 // We need special handling for unsigned 64-bit integer sources. If the
3026 // input number has the "sign bit" set, then we loaded it incorrectly as a
3027 // negative 64-bit number. In this case, add an offset value.
3028 if (SrcTy == Type::ULongTy) {
3029 // Emit a test instruction to see if the dynamic input value was signed.
3030 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg+1).addReg(SrcReg+1);
3032 // If the sign bit is set, get a pointer to an offset, otherwise get a
3033 // pointer to a zero.
3034 MachineConstantPool *CP = F->getConstantPool();
3035 unsigned Zero = makeAnotherReg(Type::IntTy);
3036 Constant *Null = Constant::getNullValue(Type::UIntTy);
3037 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
3038 CP->getConstantPoolIndex(Null));
3039 unsigned Offset = makeAnotherReg(Type::IntTy);
3040 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
3042 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset),
3043 CP->getConstantPoolIndex(OffsetCst));
3044 unsigned Addr = makeAnotherReg(Type::IntTy);
3045 BuildMI(*BB, IP, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
3047 // Load the constant for an add. FIXME: this could make an 'fadd' that
3048 // reads directly from memory, but we don't support these yet.
3049 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
3050 addDirectMem(BuildMI(*BB, IP, X86::FLD32m, 4, ConstReg), Addr);
3052 BuildMI(*BB, IP, X86::FpADD, 2, RealDestReg)
3053 .addReg(ConstReg).addReg(DestReg);
3059 // Handle casts from floating point to integer now...
3060 if (SrcClass == cFP) {
3061 // Change the floating point control register to use "round towards zero"
3062 // mode when truncating to an integer value.
3064 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
3065 addFrameReference(BuildMI(*BB, IP, X86::FNSTCW16m, 4), CWFrameIdx);
3067 // Load the old value of the high byte of the control word...
3068 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
3069 addFrameReference(BuildMI(*BB, IP, X86::MOV8rm, 4, HighPartOfCW),
3072 // Set the high part to be round to zero...
3073 addFrameReference(BuildMI(*BB, IP, X86::MOV8mi, 5),
3074 CWFrameIdx, 1).addImm(12);
3076 // Reload the modified control word now...
3077 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3079 // Restore the memory image of control word to original value
3080 addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5),
3081 CWFrameIdx, 1).addReg(HighPartOfCW);
3083 // We don't have the facilities for directly storing byte sized data to
3084 // memory. Promote it to 16 bits. We also must promote unsigned values to
3085 // larger classes because we only have signed FP stores.
3086 unsigned StoreClass = DestClass;
3087 const Type *StoreTy = DestTy;
3088 if (StoreClass == cByte || DestTy->isUnsigned())
3089 switch (StoreClass) {
3090 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
3091 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
3092 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
3093 // The following treatment of cLong may not be perfectly right,
3094 // but it survives chains of casts of the form
3095 // double->ulong->double.
3096 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
3097 default: assert(0 && "Unknown store class!");
3100 // Spill the integer to memory and reload it from there...
3102 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
3104 static const unsigned Op1[] =
3105 { 0, X86::FIST16m, X86::FIST32m, 0, X86::FISTP64m };
3106 addFrameReference(BuildMI(*BB, IP, Op1[StoreClass], 5),
3107 FrameIdx).addReg(SrcReg);
3109 if (DestClass == cLong) {
3110 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg), FrameIdx);
3111 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg+1),
3114 static const unsigned Op2[] = { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm };
3115 addFrameReference(BuildMI(*BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
3118 // Reload the original control word now...
3119 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3123 // Anything we haven't handled already, we can't (yet) handle at all.
3124 assert(0 && "Unhandled cast instruction!");
3128 /// visitVANextInst - Implement the va_next instruction...
3130 void ISel::visitVANextInst(VANextInst &I) {
3131 unsigned VAList = getReg(I.getOperand(0));
3132 unsigned DestReg = getReg(I);
3135 switch (I.getArgType()->getPrimitiveID()) {
3138 assert(0 && "Error: bad type for va_next instruction!");
3140 case Type::PointerTyID:
3141 case Type::UIntTyID:
3145 case Type::ULongTyID:
3146 case Type::LongTyID:
3147 case Type::DoubleTyID:
3152 // Increment the VAList pointer...
3153 BuildMI(BB, X86::ADD32ri, 2, DestReg).addReg(VAList).addImm(Size);
3156 void ISel::visitVAArgInst(VAArgInst &I) {
3157 unsigned VAList = getReg(I.getOperand(0));
3158 unsigned DestReg = getReg(I);
3160 switch (I.getType()->getPrimitiveID()) {
3163 assert(0 && "Error: bad type for va_next instruction!");
3165 case Type::PointerTyID:
3166 case Type::UIntTyID:
3168 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3170 case Type::ULongTyID:
3171 case Type::LongTyID:
3172 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3173 addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4);
3175 case Type::DoubleTyID:
3176 addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList);
3181 /// visitGetElementPtrInst - instruction-select GEP instructions
3183 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
3184 // If this GEP instruction will be folded into all of its users, we don't need
3185 // to explicitly calculate it!
3186 unsigned A, B, C, D;
3187 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
3188 // Check all of the users of the instruction to see if they are loads and
3190 bool AllWillFold = true;
3191 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
3192 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
3193 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
3194 cast<Instruction>(*UI)->getOperand(0) == &I) {
3195 AllWillFold = false;
3199 // If the instruction is foldable, and will be folded into all users, don't
3201 if (AllWillFold) return;
3204 unsigned outputReg = getReg(I);
3205 emitGEPOperation(BB, BB->end(), I.getOperand(0),
3206 I.op_begin()+1, I.op_end(), outputReg);
3209 /// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
3210 /// GEPTypes (the derived types being stepped through at each level). On return
3211 /// from this function, if some indexes of the instruction are representable as
3212 /// an X86 lea instruction, the machine operands are put into the Ops
3213 /// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
3214 /// lists. Otherwise, GEPOps.size() is returned. If this returns a an
3215 /// addressing mode that only partially consumes the input, the BaseReg input of
3216 /// the addressing mode must be left free.
3218 /// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
3220 void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
3221 std::vector<Value*> &GEPOps,
3222 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
3223 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
3224 const TargetData &TD = TM.getTargetData();
3226 // Clear out the state we are working with...
3227 BaseReg = 0; // No base register
3228 Scale = 1; // Unit scale
3229 IndexReg = 0; // No index register
3230 Disp = 0; // No displacement
3232 // While there are GEP indexes that can be folded into the current address,
3233 // keep processing them.
3234 while (!GEPTypes.empty()) {
3235 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
3236 // It's a struct access. CUI is the index into the structure,
3237 // which names the field. This index must have unsigned type.
3238 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
3240 // Use the TargetData structure to pick out what the layout of the
3241 // structure is in memory. Since the structure index must be constant, we
3242 // can get its value and use it to find the right byte offset from the
3243 // StructLayout class's list of structure member offsets.
3244 Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
3245 GEPOps.pop_back(); // Consume a GEP operand
3246 GEPTypes.pop_back();
3248 // It's an array or pointer access: [ArraySize x ElementType].
3249 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3250 Value *idx = GEPOps.back();
3252 // idx is the index into the array. Unlike with structure
3253 // indices, we may not know its actual value at code-generation
3256 // If idx is a constant, fold it into the offset.
3257 unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
3258 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
3259 Disp += TypeSize*CSI->getValue();
3260 } else if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(idx)) {
3261 Disp += TypeSize*CUI->getValue();
3263 // If the index reg is already taken, we can't handle this index.
3264 if (IndexReg) return;
3266 // If this is a size that we can handle, then add the index as
3268 case 1: case 2: case 4: case 8:
3269 // These are all acceptable scales on X86.
3273 // Otherwise, we can't handle this scale
3277 if (CastInst *CI = dyn_cast<CastInst>(idx))
3278 if (CI->getOperand(0)->getType() == Type::IntTy ||
3279 CI->getOperand(0)->getType() == Type::UIntTy)
3280 idx = CI->getOperand(0);
3282 IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
3285 GEPOps.pop_back(); // Consume a GEP operand
3286 GEPTypes.pop_back();
3290 // GEPTypes is empty, which means we have a single operand left. See if we
3291 // can set it as the base register.
3293 // FIXME: When addressing modes are more powerful/correct, we could load
3294 // global addresses directly as 32-bit immediates.
3295 assert(BaseReg == 0);
3296 BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
3297 GEPOps.pop_back(); // Consume the last GEP operand
3301 /// isGEPFoldable - Return true if the specified GEP can be completely
3302 /// folded into the addressing mode of a load/store or lea instruction.
3303 bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
3304 Value *Src, User::op_iterator IdxBegin,
3305 User::op_iterator IdxEnd, unsigned &BaseReg,
3306 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
3307 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
3308 Src = CPR->getValue();
3310 std::vector<Value*> GEPOps;
3311 GEPOps.resize(IdxEnd-IdxBegin+1);
3313 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3315 std::vector<const Type*> GEPTypes;
3316 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3317 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3319 MachineBasicBlock::iterator IP;
3320 if (MBB) IP = MBB->end();
3321 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
3323 // We can fold it away iff the getGEPIndex call eliminated all operands.
3324 return GEPOps.empty();
3327 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
3328 MachineBasicBlock::iterator IP,
3329 Value *Src, User::op_iterator IdxBegin,
3330 User::op_iterator IdxEnd, unsigned TargetReg) {
3331 const TargetData &TD = TM.getTargetData();
3332 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
3333 Src = CPR->getValue();
3335 std::vector<Value*> GEPOps;
3336 GEPOps.resize(IdxEnd-IdxBegin+1);
3338 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3340 std::vector<const Type*> GEPTypes;
3341 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3342 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3344 // Keep emitting instructions until we consume the entire GEP instruction.
3345 while (!GEPOps.empty()) {
3346 unsigned OldSize = GEPOps.size();
3347 unsigned BaseReg, Scale, IndexReg, Disp;
3348 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
3350 if (GEPOps.size() != OldSize) {
3351 // getGEPIndex consumed some of the input. Build an LEA instruction here.
3352 unsigned NextTarget = 0;
3353 if (!GEPOps.empty()) {
3354 assert(BaseReg == 0 &&
3355 "getGEPIndex should have left the base register open for chaining!");
3356 NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
3359 if (IndexReg == 0 && Disp == 0)
3360 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
3362 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg),
3363 BaseReg, Scale, IndexReg, Disp);
3365 TargetReg = NextTarget;
3366 } else if (GEPTypes.empty()) {
3367 // The getGEPIndex operation didn't want to build an LEA. Check to see if
3368 // all operands are consumed but the base pointer. If so, just load it
3369 // into the register.
3370 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
3371 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(GV);
3373 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
3374 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
3376 break; // we are now done
3379 // It's an array or pointer access: [ArraySize x ElementType].
3380 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3381 Value *idx = GEPOps.back();
3382 GEPOps.pop_back(); // Consume a GEP operand
3383 GEPTypes.pop_back();
3385 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
3386 // operand on X86. Handle this case directly now...
3387 if (CastInst *CI = dyn_cast<CastInst>(idx))
3388 if (CI->getOperand(0)->getType() == Type::IntTy ||
3389 CI->getOperand(0)->getType() == Type::UIntTy)
3390 idx = CI->getOperand(0);
3392 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
3393 // must find the size of the pointed-to type (Not coincidentally, the next
3394 // type is the type of the elements in the array).
3395 const Type *ElTy = SqTy->getElementType();
3396 unsigned elementSize = TD.getTypeSize(ElTy);
3398 // If idxReg is a constant, we don't need to perform the multiply!
3399 if (ConstantInt *CSI = dyn_cast<ConstantInt>(idx)) {
3400 if (!CSI->isNullValue()) {
3401 unsigned Offset = elementSize*CSI->getRawValue();
3402 unsigned Reg = makeAnotherReg(Type::UIntTy);
3403 BuildMI(*MBB, IP, X86::ADD32ri, 2, TargetReg)
3404 .addReg(Reg).addImm(Offset);
3405 --IP; // Insert the next instruction before this one.
3406 TargetReg = Reg; // Codegen the rest of the GEP into this
3408 } else if (elementSize == 1) {
3409 // If the element size is 1, we don't have to multiply, just add
3410 unsigned idxReg = getReg(idx, MBB, IP);
3411 unsigned Reg = makeAnotherReg(Type::UIntTy);
3412 BuildMI(*MBB, IP, X86::ADD32rr, 2,TargetReg).addReg(Reg).addReg(idxReg);
3413 --IP; // Insert the next instruction before this one.
3414 TargetReg = Reg; // Codegen the rest of the GEP into this
3416 unsigned idxReg = getReg(idx, MBB, IP);
3417 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
3419 // Make sure we can back the iterator up to point to the first
3420 // instruction emitted.
3421 MachineBasicBlock::iterator BeforeIt = IP;
3422 if (IP == MBB->begin())
3423 BeforeIt = MBB->end();
3426 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
3428 // Emit an ADD to add OffsetReg to the basePtr.
3429 unsigned Reg = makeAnotherReg(Type::UIntTy);
3430 BuildMI(*MBB, IP, X86::ADD32rr, 2, TargetReg)
3431 .addReg(Reg).addReg(OffsetReg);
3433 // Step to the first instruction of the multiply.
3434 if (BeforeIt == MBB->end())
3439 TargetReg = Reg; // Codegen the rest of the GEP into this
3446 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
3447 /// frame manager, otherwise do it the hard way.
3449 void ISel::visitAllocaInst(AllocaInst &I) {
3450 // Find the data size of the alloca inst's getAllocatedType.
3451 const Type *Ty = I.getAllocatedType();
3452 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
3454 // If this is a fixed size alloca in the entry block for the function,
3455 // statically stack allocate the space.
3457 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
3458 if (I.getParent() == I.getParent()->getParent()->begin()) {
3459 TySize *= CUI->getValue(); // Get total allocated size...
3460 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
3462 // Create a new stack object using the frame manager...
3463 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
3464 addFrameReference(BuildMI(BB, X86::LEA32r, 5, getReg(I)), FrameIdx);
3469 // Create a register to hold the temporary result of multiplying the type size
3470 // constant by the variable amount.
3471 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
3472 unsigned SrcReg1 = getReg(I.getArraySize());
3474 // TotalSizeReg = mul <numelements>, <TypeSize>
3475 MachineBasicBlock::iterator MBBI = BB->end();
3476 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
3478 // AddedSize = add <TotalSizeReg>, 15
3479 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
3480 BuildMI(BB, X86::ADD32ri, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
3482 // AlignedSize = and <AddedSize>, ~15
3483 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
3484 BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15);
3486 // Subtract size from stack pointer, thereby allocating some space.
3487 BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
3489 // Put a pointer to the space into the result register, by copying
3490 // the stack pointer.
3491 BuildMI(BB, X86::MOV32rr, 1, getReg(I)).addReg(X86::ESP);
3493 // Inform the Frame Information that we have just allocated a variable-sized
3495 F->getFrameInfo()->CreateVariableSizedObject();
3498 /// visitMallocInst - Malloc instructions are code generated into direct calls
3499 /// to the library malloc.
3501 void ISel::visitMallocInst(MallocInst &I) {
3502 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
3505 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
3506 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
3508 Arg = makeAnotherReg(Type::UIntTy);
3509 unsigned Op0Reg = getReg(I.getOperand(0));
3510 MachineBasicBlock::iterator MBBI = BB->end();
3511 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
3514 std::vector<ValueRecord> Args;
3515 Args.push_back(ValueRecord(Arg, Type::UIntTy));
3516 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3517 1).addExternalSymbol("malloc", true);
3518 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
3522 /// visitFreeInst - Free instructions are code gen'd to call the free libc
3525 void ISel::visitFreeInst(FreeInst &I) {
3526 std::vector<ValueRecord> Args;
3527 Args.push_back(ValueRecord(I.getOperand(0)));
3528 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3529 1).addExternalSymbol("free", true);
3530 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
3533 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
3534 /// into a machine code representation is a very simple peep-hole fashion. The
3535 /// generated code sucks but the implementation is nice and simple.
3537 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
3538 return new ISel(TM);