1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Support/InstVisitor.h"
23 #include "llvm/Target/MRegisterInfo.h"
26 using namespace MOTy; // Get Use, Def, UseAndDef
29 struct ISel : public FunctionPass, InstVisitor<ISel> {
31 MachineFunction *F; // The function we are compiling into
32 MachineBasicBlock *BB; // The current MBB we are compiling
35 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
37 ISel(TargetMachine &tm)
38 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
40 /// runOnFunction - Top level implementation of instruction selection for
41 /// the entire function.
43 bool runOnFunction(Function &Fn) {
44 F = &MachineFunction::construct(&Fn, TM);
47 CurReg = MRegisterInfo::FirstVirtualRegister;
49 return false; // We never modify the LLVM itself.
52 /// visitBasicBlock - This method is called when we are visiting a new basic
53 /// block. This simply creates a new MachineBasicBlock to emit code into
54 /// and adds it to the current MachineFunction. Subsequent visit* for
55 /// instructions will be invoked for all instructions in the basic block.
57 void visitBasicBlock(BasicBlock &LLVM_BB) {
58 BB = new MachineBasicBlock(&LLVM_BB);
59 // FIXME: Use the auto-insert form when it's available
60 F->getBasicBlockList().push_back(BB);
63 // Visitation methods for various instructions. These methods simply emit
64 // fixed X86 code for each instruction.
67 // Control flow operators
68 void visitReturnInst(ReturnInst &RI);
69 void visitBranchInst(BranchInst &BI);
70 void visitCallInst(CallInst &I);
72 // Arithmetic operators
73 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
74 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
75 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
76 void visitMul(BinaryOperator &B);
78 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
79 void visitRem(BinaryOperator &B) { visitDivRem(B); }
80 void visitDivRem(BinaryOperator &B);
83 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
84 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
85 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
87 // Binary comparison operators
88 void visitSetCCInst(SetCondInst &I, unsigned OpNum);
89 void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
90 void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
91 void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
92 void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
93 void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
94 void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
96 // Memory Instructions
97 void visitLoadInst(LoadInst &I);
98 void visitStoreInst(StoreInst &I);
101 void visitShiftInst(ShiftInst &I);
102 void visitPHINode(PHINode &I);
103 void visitCastInst(CastInst &I);
105 void visitInstruction(Instruction &I) {
106 std::cerr << "Cannot instruction select: " << I;
110 void promote32 (const unsigned targetReg, Value *v);
112 /// copyConstantToRegister - Output the instructions required to put the
113 /// specified constant into the specified register.
115 void copyConstantToRegister(Constant *C, unsigned Reg);
117 /// getReg - This method turns an LLVM value into a register number. This
118 /// is guaranteed to produce the same register number for a particular value
119 /// every time it is queried.
121 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
122 unsigned getReg(Value *V) {
123 unsigned &Reg = RegMap[V];
128 // Add the mapping of regnumber => reg class to MachineFunction
130 TM.getRegisterInfo()->getRegClassForType(V->getType()));
133 // If this operand is a constant, emit the code to copy the constant into
134 // the register here...
136 if (Constant *C = dyn_cast<Constant>(V)) {
137 copyConstantToRegister(C, Reg);
138 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
139 // Move the address of the global into the register
140 BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV);
141 } else if (Argument *A = dyn_cast<Argument>(V)) {
142 std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n";
150 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
154 cByte, cShort, cInt, cLong, cFloat, cDouble
157 /// getClass - Turn a primitive type into a "class" number which is based on the
158 /// size of the type, and whether or not it is floating point.
160 static inline TypeClass getClass(const Type *Ty) {
161 switch (Ty->getPrimitiveID()) {
162 case Type::SByteTyID:
163 case Type::UByteTyID: return cByte; // Byte operands are class #0
164 case Type::ShortTyID:
165 case Type::UShortTyID: return cShort; // Short operands are class #1
168 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
171 case Type::ULongTyID: return cLong; // Longs are class #3
172 case Type::FloatTyID: return cFloat; // Float is class #4
173 case Type::DoubleTyID: return cDouble; // Doubles are class #5
175 assert(0 && "Invalid type to getClass!");
176 return cByte; // not reached
181 /// copyConstantToRegister - Output the instructions required to put the
182 /// specified constant into the specified register.
184 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
185 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
187 if (C->getType()->isIntegral()) {
188 unsigned Class = getClass(C->getType());
189 assert(Class != 3 && "Type not handled yet!");
191 static const unsigned IntegralOpcodeTab[] = {
192 X86::MOVir8, X86::MOVir16, X86::MOVir32
195 if (C->getType()->isSigned()) {
196 ConstantSInt *CSI = cast<ConstantSInt>(C);
197 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
199 ConstantUInt *CUI = cast<ConstantUInt>(C);
200 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
203 assert(0 && "Type not handled yet!");
208 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
209 /// register, then move it to wherever the result should be.
210 /// We handle FP setcc instructions by pushing them, doing a
211 /// compare-and-pop-twice, and then copying the concodes to the main
212 /// processor's concodes (I didn't make this up, it's in the Intel manual)
214 void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
215 // The arguments are already supposed to be of the same type.
216 const Type *CompTy = I.getOperand(0)->getType();
217 unsigned reg1 = getReg(I.getOperand(0));
218 unsigned reg2 = getReg(I.getOperand(1));
220 unsigned Class = getClass(CompTy);
222 // Emit: cmp <var1>, <var2> (do the comparison). We can
223 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
226 BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
229 BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
232 BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
235 // Push the variables on the stack with fldl opcodes.
236 // FIXME: assuming var1, var2 are in memory, if not, spill to
238 case cFloat: // Floats
239 BuildMI (BB, X86::FLDr4, 1).addReg (reg1);
240 BuildMI (BB, X86::FLDr4, 1).addReg (reg2);
242 case cDouble: // Doubles
243 BuildMI (BB, X86::FLDr8, 1).addReg (reg1);
244 BuildMI (BB, X86::FLDr8, 1).addReg (reg2);
251 if (CompTy->isFloatingPoint()) {
252 // (Non-trapping) compare and pop twice.
253 BuildMI (BB, X86::FUCOMPP, 0);
254 // Move fp status word (concodes) to ax.
255 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
256 // Load real concodes from ax.
257 BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
260 // Emit setOp instruction (extract concode; clobbers ax),
261 // using the following mapping:
262 // LLVM -> X86 signed X86 unsigned
264 // seteq -> sete sete
265 // setne -> setne setne
266 // setlt -> setl setb
267 // setgt -> setg seta
268 // setle -> setle setbe
269 // setge -> setge setae
271 static const unsigned OpcodeTab[2][6] = {
272 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
273 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
276 BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
278 // Put it in the result using a move.
279 BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
282 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
283 /// operand, in the specified target register.
285 ISel::promote32 (const unsigned targetReg, Value *v)
287 unsigned vReg = getReg (v);
288 unsigned Class = getClass (v->getType ());
289 bool isUnsigned = v->getType ()->isUnsigned ();
290 assert (((Class == cByte) || (Class == cShort) || (Class == cInt))
291 && "Unpromotable operand class in promote32");
295 // Extend value into target register (8->32)
297 BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg);
299 BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg);
302 // Extend value into target register (16->32)
304 BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg);
306 BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg);
309 // Move value into target register (32->32)
310 BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg);
315 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
316 /// we have the following possibilities:
318 /// ret void: No return value, simply emit a 'ret' instruction
319 /// ret sbyte, ubyte : Extend value into EAX and return
320 /// ret short, ushort: Extend value into EAX and return
321 /// ret int, uint : Move value into EAX and return
322 /// ret pointer : Move value into EAX and return
323 /// ret long, ulong : Move value into EAX/EDX and return
324 /// ret float/double : Top of FP stack
327 ISel::visitReturnInst (ReturnInst &I)
329 if (I.getNumOperands () == 0)
331 // Emit a 'ret' instruction
332 BuildMI (BB, X86::RET, 0);
335 Value *rv = I.getOperand (0);
336 unsigned Class = getClass (rv->getType ());
339 // integral return values: extend or move into EAX and return.
343 promote32 (X86::EAX, rv);
345 // ret float/double: top of FP stack
347 case cFloat: // Floats
348 BuildMI (BB, X86::FLDr4, 1).addReg (getReg (rv));
350 case cDouble: // Doubles
351 BuildMI (BB, X86::FLDr8, 1).addReg (getReg (rv));
354 // ret long: use EAX(least significant 32 bits)/EDX (most
355 // significant 32)...uh, I think so Brain, but how do i call
356 // up the two parts of the value from inside this mouse
359 visitInstruction (I);
361 // Emit a 'ret' instruction
362 BuildMI (BB, X86::RET, 0);
365 /// visitBranchInst - Handle conditional and unconditional branches here. Note
366 /// that since code layout is frozen at this point, that if we are trying to
367 /// jump to a block that is the immediate successor of the current block, we can
368 /// just make a fall-through. (but we don't currently).
371 ISel::visitBranchInst (BranchInst & BI)
373 if (BI.isConditional ())
375 BasicBlock *ifTrue = BI.getSuccessor (0);
376 BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
378 // simplest thing I can think of: compare condition with zero,
379 // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
381 unsigned int condReg = getReg (BI.getCondition ());
382 BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
383 BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
384 BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
386 else // unconditional branch
388 BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
392 /// visitCallInst - Push args on stack and do a procedure call instruction.
394 ISel::visitCallInst (CallInst & CI)
396 // Push the arguments on the stack in reverse order, as specified by
398 for (unsigned i = CI.getNumOperands()-1; i >= 1; --i)
400 Value *v = CI.getOperand (i);
401 switch (getClass (v->getType ()))
405 // Promote V to 32 bits wide, and move the result into EAX,
407 promote32 (X86::EAX, v);
408 BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
412 unsigned Reg = getReg(v);
413 BuildMI (BB, X86::PUSHr32, 1).addReg(Reg);
417 // FIXME: long/ulong/double args not handled.
418 visitInstruction (CI);
422 // Emit a CALL instruction with PC-relative displacement.
423 BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ());
426 /// visitSimpleBinary - Implement simple binary operators for integral types...
427 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
430 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
431 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
434 unsigned Class = getClass(B.getType());
435 if (Class > 2) // FIXME: Handle longs
438 static const unsigned OpcodeTab[][4] = {
439 // Arithmetic operators
440 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
441 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
444 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
445 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
446 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
449 unsigned Opcode = OpcodeTab[OperatorClass][Class];
450 unsigned Op0r = getReg(B.getOperand(0));
451 unsigned Op1r = getReg(B.getOperand(1));
452 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
455 /// visitMul - Multiplies are not simple binary operators because they must deal
456 /// with the EAX register explicitly.
458 void ISel::visitMul(BinaryOperator &I) {
459 unsigned Class = getClass(I.getType());
460 if (Class > 2) // FIXME: Handle longs
463 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
464 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
465 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
467 unsigned Reg = Regs[Class];
468 unsigned Op0Reg = getReg(I.getOperand(0));
469 unsigned Op1Reg = getReg(I.getOperand(1));
471 // Put the first operand into one of the A registers...
472 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
474 // Emit the appropriate multiply instruction...
475 BuildMI(BB, MulOpcode[Class], 1).addReg(Op1Reg);
477 // Put the result into the destination register...
478 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
482 /// visitDivRem - Handle division and remainder instructions... these
483 /// instruction both require the same instructions to be generated, they just
484 /// select the result from a different register. Note that both of these
485 /// instructions work differently for signed and unsigned operands.
487 void ISel::visitDivRem(BinaryOperator &I) {
488 unsigned Class = getClass(I.getType());
489 if (Class > 2) // FIXME: Handle longs
492 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
493 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
494 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
495 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
496 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
498 static const unsigned DivOpcode[][4] = {
499 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
500 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
503 bool isSigned = I.getType()->isSigned();
504 unsigned Reg = Regs[Class];
505 unsigned ExtReg = ExtRegs[Class];
506 unsigned Op0Reg = getReg(I.getOperand(0));
507 unsigned Op1Reg = getReg(I.getOperand(1));
509 // Put the first operand into one of the A registers...
510 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
513 // Emit a sign extension instruction...
514 BuildMI(BB, ExtOpcode[Class], 0);
516 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
517 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
520 // Emit the appropriate divide or remainder instruction...
521 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
523 // Figure out which register we want to pick the result out of...
524 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
526 // Put the result into the destination register...
527 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
531 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
532 /// for constant immediate shift values, and for constant immediate
533 /// shift values equal to 1. Even the general case is sort of special,
534 /// because the shift amount has to be in CL, not just any old register.
536 void ISel::visitShiftInst (ShiftInst &I) {
537 unsigned Op0r = getReg (I.getOperand(0));
538 unsigned DestReg = getReg(I);
539 bool isLeftShift = I.getOpcode() == Instruction::Shl;
540 bool isOperandSigned = I.getType()->isUnsigned();
541 unsigned OperandClass = getClass(I.getType());
543 if (OperandClass > 2)
544 visitInstruction(I); // Can't handle longs yet!
546 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
548 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
549 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
550 unsigned char shAmt = CUI->getValue();
552 static const unsigned ConstantOperand[][4] = {
553 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
554 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
555 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
556 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
559 const unsigned *OpTab = // Figure out the operand table to use
560 ConstantOperand[isLeftShift*2+isOperandSigned];
562 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
563 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
567 // The shift amount is non-constant.
569 // In fact, you can only shift with a variable shift amount if
570 // that amount is already in the CL register, so we have to put it
574 // Emit: move cl, shiftAmount (put the shift amount in CL.)
575 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
577 // This is a shift right (SHR).
578 static const unsigned NonConstantOperand[][4] = {
579 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
580 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
581 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
582 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
585 const unsigned *OpTab = // Figure out the operand table to use
586 NonConstantOperand[isLeftShift*2+isOperandSigned];
588 BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
593 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
596 void ISel::visitLoadInst(LoadInst &I) {
597 unsigned Class = getClass(I.getType());
598 if (Class > 2) // FIXME: Handle longs and others...
601 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
603 unsigned AddressReg = getReg(I.getOperand(0));
604 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
608 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
611 void ISel::visitStoreInst(StoreInst &I) {
612 unsigned Class = getClass(I.getOperand(0)->getType());
613 if (Class > 2) // FIXME: Handle longs and others...
616 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
618 unsigned ValReg = getReg(I.getOperand(0));
619 unsigned AddressReg = getReg(I.getOperand(1));
620 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
624 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
626 void ISel::visitPHINode(PHINode &PN) {
627 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
629 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
630 // FIXME: This will put constants after the PHI nodes in the block, which
631 // is invalid. They should be put inline into the PHI node eventually.
633 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
634 MI->addPCDispOperand(PN.getIncomingBlock(i));
638 /// visitCastInst - Here we have various kinds of copying with or without
639 /// sign extension going on.
641 ISel::visitCastInst (CastInst &CI)
643 //> cast larger int to smaller int --> copy least significant byte/word w/ mov?
645 //I'm not really sure what to do with this. We could insert a pseudo-op
646 //that says take the low X bits of a Y bit register, but for now we can just
647 //force the value into, say, EAX, then rip out AL or AX. The advantage of
648 //the former is that the register allocator could use any register it wants,
649 //but for now this obviously doesn't matter. :)
651 const Type *targetType = CI.getType ();
652 Value *operand = CI.getOperand (0);
653 unsigned int operandReg = getReg (operand);
654 const Type *sourceType = operand->getType ();
655 unsigned int destReg = getReg (CI);
658 if (targetType == Type::BoolTy) {
660 BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
661 // Emit Set-if-not-zero
662 BuildMI (BB, X86::SETNEr, 1, destReg);
666 // if size of target type == size of source type
667 // Emit Mov reg(target) <- reg(source)
669 // if size of target type > size of source type
670 // if both types are integer types
671 // if source type is signed
672 // sbyte to short, ushort: Emit movsx 8->16
673 // sbyte to int, uint: Emit movsx 8->32
674 // short to int, uint: Emit movsx 16->32
675 // else if source type is unsigned
676 // ubyte to short, ushort: Emit movzx 8->16
677 // ubyte to int, uint: Emit movzx 8->32
678 // ushort to int, uint: Emit movzx 16->32
679 // if both types are fp types
680 // float to double: Emit fstp, fld (???)
682 visitInstruction (CI);
685 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
686 /// into a machine code representation is a very simple peep-hole fashion. The
687 /// generated code sucks but the implementation is nice and simple.
689 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {