1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 target
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/Instructions.h"
12 #include "llvm/DerivedTypes.h"
13 #include "llvm/Constants.h"
14 #include "llvm/Pass.h"
15 #include "llvm/Intrinsics.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/SSARegMap.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/InstVisitor.h"
25 /// BMI - A special BuildMI variant that takes an iterator to insert the
26 /// instruction at as well as a basic block. This is the version for when you
27 /// have a destination register in mind.
28 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
29 MachineBasicBlock::iterator &I,
30 int Opcode, unsigned NumOperands,
32 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
33 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
34 I = MBB->insert(I, MI)+1;
35 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
38 /// BMI - A special BuildMI variant that takes an iterator to insert the
39 /// instruction at as well as a basic block.
40 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
41 MachineBasicBlock::iterator &I,
42 int Opcode, unsigned NumOperands) {
43 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
44 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
45 I = MBB->insert(I, MI)+1;
46 return MachineInstrBuilder(MI);
51 struct ISel : public FunctionPass, InstVisitor<ISel> {
53 MachineFunction *F; // The function we are compiling into
54 MachineBasicBlock *BB; // The current MBB we are compiling
55 int VarArgsFrameIndex; // FrameIndex for start of varargs area
57 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
59 // MBBMap - Mapping between LLVM BB -> Machine BB
60 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
62 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
64 /// runOnFunction - Top level implementation of instruction selection for
65 /// the entire function.
67 bool runOnFunction(Function &Fn) {
68 F = &MachineFunction::construct(&Fn, TM);
70 // Create all of the machine basic blocks for the function...
71 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
72 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
76 // Copy incoming arguments off of the stack...
77 LoadArgumentsToVirtualRegs(Fn);
79 // Instruction select everything except PHI nodes
82 // Select the PHI nodes
88 // We always build a machine code representation for the function
92 virtual const char *getPassName() const {
93 return "X86 Simple Instruction Selection";
96 /// visitBasicBlock - This method is called when we are visiting a new basic
97 /// block. This simply creates a new MachineBasicBlock to emit code into
98 /// and adds it to the current MachineFunction. Subsequent visit* for
99 /// instructions will be invoked for all instructions in the basic block.
101 void visitBasicBlock(BasicBlock &LLVM_BB) {
102 BB = MBBMap[&LLVM_BB];
105 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
106 /// from the stack into virtual registers.
108 void LoadArgumentsToVirtualRegs(Function &F);
110 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
111 /// because we have to generate our sources into the source basic blocks,
112 /// not the current one.
114 void SelectPHINodes();
116 // Visitation methods for various instructions. These methods simply emit
117 // fixed X86 code for each instruction.
120 // Control flow operators
121 void visitReturnInst(ReturnInst &RI);
122 void visitBranchInst(BranchInst &BI);
128 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
129 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
131 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
132 const std::vector<ValueRecord> &Args);
133 void visitCallInst(CallInst &I);
134 void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
136 // Arithmetic operators
137 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
138 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
139 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
140 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
141 unsigned DestReg, const Type *DestTy,
142 unsigned Op0Reg, unsigned Op1Reg);
143 void visitMul(BinaryOperator &B);
145 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
146 void visitRem(BinaryOperator &B) { visitDivRem(B); }
147 void visitDivRem(BinaryOperator &B);
150 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
151 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
152 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
154 // Comparison operators...
155 void visitSetCondInst(SetCondInst &I);
156 bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
157 MachineBasicBlock *MBB,
158 MachineBasicBlock::iterator &MBBI);
160 // Memory Instructions
161 MachineInstr *doFPLoad(MachineBasicBlock *MBB,
162 MachineBasicBlock::iterator &MBBI,
163 const Type *Ty, unsigned DestReg);
164 void visitLoadInst(LoadInst &I);
165 void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg);
166 void visitStoreInst(StoreInst &I);
167 void visitGetElementPtrInst(GetElementPtrInst &I);
168 void visitAllocaInst(AllocaInst &I);
169 void visitMallocInst(MallocInst &I);
170 void visitFreeInst(FreeInst &I);
173 void visitShiftInst(ShiftInst &I);
174 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
175 void visitCastInst(CastInst &I);
176 void visitVANextInst(VANextInst &I);
177 void visitVAArgInst(VAArgInst &I);
179 void visitInstruction(Instruction &I) {
180 std::cerr << "Cannot instruction select: " << I;
184 /// promote32 - Make a value 32-bits wide, and put it somewhere.
186 void promote32(unsigned targetReg, const ValueRecord &VR);
188 /// EmitByteSwap - Byteswap SrcReg into DestReg.
190 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
192 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
193 /// constant expression GEP support.
195 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
196 Value *Src, User::op_iterator IdxBegin,
197 User::op_iterator IdxEnd, unsigned TargetReg);
199 /// emitCastOperation - Common code shared between visitCastInst and
200 /// constant expression cast support.
201 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
202 Value *Src, const Type *DestTy, unsigned TargetReg);
204 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
205 /// and constant expression support.
206 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
207 MachineBasicBlock::iterator &IP,
208 Value *Op0, Value *Op1,
209 unsigned OperatorClass, unsigned TargetReg);
211 /// emitSetCCOperation - Common code shared between visitSetCondInst and
212 /// constant expression support.
213 void emitSetCCOperation(MachineBasicBlock *BB,
214 MachineBasicBlock::iterator &IP,
215 Value *Op0, Value *Op1, unsigned Opcode,
219 /// copyConstantToRegister - Output the instructions required to put the
220 /// specified constant into the specified register.
222 void copyConstantToRegister(MachineBasicBlock *MBB,
223 MachineBasicBlock::iterator &MBBI,
224 Constant *C, unsigned Reg);
226 /// makeAnotherReg - This method returns the next register number we haven't
229 /// Long values are handled somewhat specially. They are always allocated
230 /// as pairs of 32 bit integer values. The register number returned is the
231 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
232 /// of the long value.
234 unsigned makeAnotherReg(const Type *Ty) {
235 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
236 "Current target doesn't have X86 reg info??");
237 const X86RegisterInfo *MRI =
238 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
239 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
240 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
241 // Create the lower part
242 F->getSSARegMap()->createVirtualRegister(RC);
243 // Create the upper part.
244 return F->getSSARegMap()->createVirtualRegister(RC)-1;
247 // Add the mapping of regnumber => reg class to MachineFunction
248 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
249 return F->getSSARegMap()->createVirtualRegister(RC);
252 /// getReg - This method turns an LLVM value into a register number. This
253 /// is guaranteed to produce the same register number for a particular value
254 /// every time it is queried.
256 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
257 unsigned getReg(Value *V) {
258 // Just append to the end of the current bb.
259 MachineBasicBlock::iterator It = BB->end();
260 return getReg(V, BB, It);
262 unsigned getReg(Value *V, MachineBasicBlock *MBB,
263 MachineBasicBlock::iterator &IPt) {
264 unsigned &Reg = RegMap[V];
266 Reg = makeAnotherReg(V->getType());
270 // If this operand is a constant, emit the code to copy the constant into
271 // the register here...
273 if (Constant *C = dyn_cast<Constant>(V)) {
274 copyConstantToRegister(MBB, IPt, C, Reg);
275 RegMap.erase(V); // Assign a new name to this constant if ref'd again
276 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
277 // Move the address of the global into the register
278 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
279 RegMap.erase(V); // Assign a new name to this address if ref'd again
287 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
291 cByte, cShort, cInt, cFP, cLong
294 /// getClass - Turn a primitive type into a "class" number which is based on the
295 /// size of the type, and whether or not it is floating point.
297 static inline TypeClass getClass(const Type *Ty) {
298 switch (Ty->getPrimitiveID()) {
299 case Type::SByteTyID:
300 case Type::UByteTyID: return cByte; // Byte operands are class #0
301 case Type::ShortTyID:
302 case Type::UShortTyID: return cShort; // Short operands are class #1
305 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
307 case Type::FloatTyID:
308 case Type::DoubleTyID: return cFP; // Floating Point is #3
311 case Type::ULongTyID: return cLong; // Longs are class #4
313 assert(0 && "Invalid type to getClass!");
314 return cByte; // not reached
318 // getClassB - Just like getClass, but treat boolean values as bytes.
319 static inline TypeClass getClassB(const Type *Ty) {
320 if (Ty == Type::BoolTy) return cByte;
325 /// copyConstantToRegister - Output the instructions required to put the
326 /// specified constant into the specified register.
328 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
329 MachineBasicBlock::iterator &IP,
330 Constant *C, unsigned R) {
331 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
333 switch (CE->getOpcode()) {
334 case Instruction::GetElementPtr:
335 emitGEPOperation(MBB, IP, CE->getOperand(0),
336 CE->op_begin()+1, CE->op_end(), R);
338 case Instruction::Cast:
339 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
342 case Instruction::Xor: ++Class; // FALL THROUGH
343 case Instruction::Or: ++Class; // FALL THROUGH
344 case Instruction::And: ++Class; // FALL THROUGH
345 case Instruction::Sub: ++Class; // FALL THROUGH
346 case Instruction::Add:
347 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
351 case Instruction::SetNE:
352 case Instruction::SetEQ:
353 case Instruction::SetLT:
354 case Instruction::SetGT:
355 case Instruction::SetLE:
356 case Instruction::SetGE:
357 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
362 std::cerr << "Offending expr: " << C << "\n";
363 assert(0 && "Constant expressions not yet handled!\n");
367 if (C->getType()->isIntegral()) {
368 unsigned Class = getClassB(C->getType());
370 if (Class == cLong) {
371 // Copy the value into the register pair.
372 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
373 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
374 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
378 assert(Class <= cInt && "Type not handled yet!");
380 static const unsigned IntegralOpcodeTab[] = {
381 X86::MOVir8, X86::MOVir16, X86::MOVir32
384 if (C->getType() == Type::BoolTy) {
385 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
387 ConstantInt *CI = cast<ConstantInt>(C);
388 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
390 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
391 double Value = CFP->getValue();
393 BMI(MBB, IP, X86::FLD0, 0, R);
394 else if (Value == +1.0)
395 BMI(MBB, IP, X86::FLD1, 0, R);
397 // Otherwise we need to spill the constant to memory...
398 MachineConstantPool *CP = F->getConstantPool();
399 unsigned CPI = CP->getConstantPoolIndex(CFP);
400 addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI);
403 } else if (isa<ConstantPointerNull>(C)) {
404 // Copy zero (null pointer) to the register.
405 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
406 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
407 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
408 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
410 std::cerr << "Offending constant: " << C << "\n";
411 assert(0 && "Type not handled yet!");
415 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
416 /// the stack into virtual registers.
418 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
419 // Emit instructions to load the arguments... On entry to a function on the
420 // X86, the stack frame looks like this:
422 // [ESP] -- return address
423 // [ESP + 4] -- first argument (leftmost lexically)
424 // [ESP + 8] -- second argument, if first argument is four bytes in size
427 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
428 MachineFrameInfo *MFI = F->getFrameInfo();
430 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
431 unsigned Reg = getReg(*I);
433 int FI; // Frame object index
434 switch (getClassB(I->getType())) {
436 FI = MFI->CreateFixedObject(1, ArgOffset);
437 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
440 FI = MFI->CreateFixedObject(2, ArgOffset);
441 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
444 FI = MFI->CreateFixedObject(4, ArgOffset);
445 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
448 FI = MFI->CreateFixedObject(8, ArgOffset);
449 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
450 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
451 ArgOffset += 4; // longs require 4 additional bytes
455 if (I->getType() == Type::FloatTy) {
456 Opcode = X86::FLDr32;
457 FI = MFI->CreateFixedObject(4, ArgOffset);
459 Opcode = X86::FLDr64;
460 FI = MFI->CreateFixedObject(8, ArgOffset);
461 ArgOffset += 4; // doubles require 4 additional bytes
463 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
466 assert(0 && "Unhandled argument type!");
468 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
471 // If the function takes variable number of arguments, add a frame offset for
472 // the start of the first vararg value... this is used to expand
474 if (Fn.getFunctionType()->isVarArg())
475 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
479 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
480 /// because we have to generate our sources into the source basic blocks, not
483 void ISel::SelectPHINodes() {
484 const TargetInstrInfo &TII = TM.getInstrInfo();
485 const Function &LF = *F->getFunction(); // The LLVM function...
486 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
487 const BasicBlock *BB = I;
488 MachineBasicBlock *MBB = MBBMap[I];
490 // Loop over all of the PHI nodes in the LLVM basic block...
491 unsigned NumPHIs = 0;
492 for (BasicBlock::const_iterator I = BB->begin();
493 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
495 // Create a new machine instr PHI node, and insert it.
496 unsigned PHIReg = getReg(*PN);
497 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
498 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
500 MachineInstr *LongPhiMI = 0;
501 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
502 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
503 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
506 // PHIValues - Map of blocks to incoming virtual registers. We use this
507 // so that we only initialize one incoming value for a particular block,
508 // even if the block has multiple entries in the PHI node.
510 std::map<MachineBasicBlock*, unsigned> PHIValues;
512 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
513 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
515 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
516 PHIValues.lower_bound(PredMBB);
518 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
519 // We already inserted an initialization of the register for this
520 // predecessor. Recycle it.
521 ValReg = EntryIt->second;
524 // Get the incoming value into a virtual register.
526 Value *Val = PN->getIncomingValue(i);
528 // If this is a constant or GlobalValue, we may have to insert code
529 // into the basic block to compute it into a virtual register.
530 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
531 // Because we don't want to clobber any values which might be in
532 // physical registers with the computation of this constant (which
533 // might be arbitrarily complex if it is a constant expression),
534 // just insert the computation at the top of the basic block.
535 MachineBasicBlock::iterator PI = PredMBB->begin();
537 // Skip over any PHI nodes though!
538 while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
541 ValReg = getReg(Val, PredMBB, PI);
543 ValReg = getReg(Val);
546 // Remember that we inserted a value for this PHI for this predecessor
547 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
550 PhiMI->addRegOperand(ValReg);
551 PhiMI->addMachineBasicBlockOperand(PredMBB);
553 LongPhiMI->addRegOperand(ValReg+1);
554 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
561 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
562 // the conditional branch instruction which is the only user of the cc
563 // instruction. This is the case if the conditional branch is the only user of
564 // the setcc, and if the setcc is in the same basic block as the conditional
565 // branch. We also don't handle long arguments below, so we reject them here as
568 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
569 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
570 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
571 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
572 const Type *Ty = SCI->getOperand(0)->getType();
573 if (Ty != Type::LongTy && Ty != Type::ULongTy)
579 // Return a fixed numbering for setcc instructions which does not depend on the
580 // order of the opcodes.
582 static unsigned getSetCCNumber(unsigned Opcode) {
584 default: assert(0 && "Unknown setcc instruction!");
585 case Instruction::SetEQ: return 0;
586 case Instruction::SetNE: return 1;
587 case Instruction::SetLT: return 2;
588 case Instruction::SetGE: return 3;
589 case Instruction::SetGT: return 4;
590 case Instruction::SetLE: return 5;
594 // LLVM -> X86 signed X86 unsigned
595 // ----- ---------- ------------
596 // seteq -> sete sete
597 // setne -> setne setne
598 // setlt -> setl setb
599 // setge -> setge setae
600 // setgt -> setg seta
601 // setle -> setle setbe
602 static const unsigned SetCCOpcodeTab[2][6] = {
603 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
604 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
607 bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
608 MachineBasicBlock *MBB,
609 MachineBasicBlock::iterator &IP) {
610 // The arguments are already supposed to be of the same type.
611 const Type *CompTy = Op0->getType();
612 bool isSigned = CompTy->isSigned();
613 unsigned Class = getClassB(CompTy);
614 unsigned Op0r = getReg(Op0, MBB, IP);
616 // Special case handling of: cmp R, i
617 if (Class == cByte || Class == cShort || Class == cInt)
618 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
619 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
621 // Mask off any upper bits of the constant, if there are any...
622 Op1v &= (1ULL << (8 << Class)) - 1;
625 case cByte: BMI(MBB,IP, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
626 case cShort: BMI(MBB,IP, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
627 case cInt: BMI(MBB,IP, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
629 assert(0 && "Invalid class!");
634 unsigned Op1r = getReg(Op1, MBB, IP);
636 default: assert(0 && "Unknown type class!");
637 // Emit: cmp <var1>, <var2> (do the comparison). We can
638 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
641 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
644 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
647 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
650 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
651 BMI(MBB, IP, X86::FNSTSWr8, 0);
652 BMI(MBB, IP, X86::SAHF, 1);
653 isSigned = false; // Compare with unsigned operators
657 if (OpNum < 2) { // seteq, setne
658 unsigned LoTmp = makeAnotherReg(Type::IntTy);
659 unsigned HiTmp = makeAnotherReg(Type::IntTy);
660 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
661 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
662 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
663 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
664 break; // Allow the sete or setne to be generated from flags set by OR
666 // Emit a sequence of code which compares the high and low parts once
667 // each, then uses a conditional move to handle the overflow case. For
668 // example, a setlt for long would generate code like this:
670 // AL = lo(op1) < lo(op2) // Signedness depends on operands
671 // BL = hi(op1) < hi(op2) // Always unsigned comparison
672 // dest = hi(op1) == hi(op2) ? AL : BL;
675 // FIXME: This would be much better if we had hierarchical register
676 // classes! Until then, hardcode registers so that we can deal with their
677 // aliases (because we don't have conditional byte moves).
679 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
680 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
681 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
682 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
683 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
684 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
685 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
686 // NOTE: visitSetCondInst knows that the value is dumped into the BL
687 // register at this point for long values...
695 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
696 /// register, then move it to wherever the result should be.
698 void ISel::visitSetCondInst(SetCondInst &I) {
699 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
701 unsigned DestReg = getReg(I);
702 MachineBasicBlock::iterator MII = BB->end();
703 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
707 /// emitSetCCOperation - Common code shared between visitSetCondInst and
708 /// constant expression support.
709 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
710 MachineBasicBlock::iterator &IP,
711 Value *Op0, Value *Op1, unsigned Opcode,
712 unsigned TargetReg) {
713 unsigned OpNum = getSetCCNumber(Opcode);
714 bool isSigned = EmitComparisonGetSignedness(OpNum, Op0, Op1, MBB, IP);
716 if (getClassB(Op0->getType()) != cLong || OpNum < 2) {
717 // Handle normal comparisons with a setcc instruction...
718 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
720 // Handle long comparisons by copying the value which is already in BL into
721 // the register we want...
722 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
729 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
730 /// operand, in the specified target register.
731 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
732 bool isUnsigned = VR.Ty->isUnsigned();
734 // Make sure we have the register number for this value...
735 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
737 switch (getClassB(VR.Ty)) {
739 // Extend value into target register (8->32)
741 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
743 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
746 // Extend value into target register (16->32)
748 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
750 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
753 // Move value into target register (32->32)
754 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
757 assert(0 && "Unpromotable operand class in promote32");
761 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
762 /// we have the following possibilities:
764 /// ret void: No return value, simply emit a 'ret' instruction
765 /// ret sbyte, ubyte : Extend value into EAX and return
766 /// ret short, ushort: Extend value into EAX and return
767 /// ret int, uint : Move value into EAX and return
768 /// ret pointer : Move value into EAX and return
769 /// ret long, ulong : Move value into EAX/EDX and return
770 /// ret float/double : Top of FP stack
772 void ISel::visitReturnInst(ReturnInst &I) {
773 if (I.getNumOperands() == 0) {
774 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
778 Value *RetVal = I.getOperand(0);
779 unsigned RetReg = getReg(RetVal);
780 switch (getClassB(RetVal->getType())) {
781 case cByte: // integral return values: extend or move into EAX and return
784 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
785 // Declare that EAX is live on exit
786 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
788 case cFP: // Floats & Doubles: Return in ST(0)
789 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
790 // Declare that top-of-stack is live on exit
791 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
794 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
795 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
796 // Declare that EAX & EDX are live on exit
797 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP);
802 // Emit a 'ret' instruction
803 BuildMI(BB, X86::RET, 0);
806 // getBlockAfter - Return the basic block which occurs lexically after the
808 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
809 Function::iterator I = BB; ++I; // Get iterator to next block
810 return I != BB->getParent()->end() ? &*I : 0;
813 /// visitBranchInst - Handle conditional and unconditional branches here. Note
814 /// that since code layout is frozen at this point, that if we are trying to
815 /// jump to a block that is the immediate successor of the current block, we can
816 /// just make a fall-through (but we don't currently).
818 void ISel::visitBranchInst(BranchInst &BI) {
819 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
821 if (!BI.isConditional()) { // Unconditional branch?
822 if (BI.getSuccessor(0) != NextBB)
823 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
827 // See if we can fold the setcc into the branch itself...
828 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
830 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
831 // computed some other way...
832 unsigned condReg = getReg(BI.getCondition());
833 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
834 if (BI.getSuccessor(1) == NextBB) {
835 if (BI.getSuccessor(0) != NextBB)
836 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
838 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
840 if (BI.getSuccessor(0) != NextBB)
841 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
846 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
847 MachineBasicBlock::iterator MII = BB->end();
848 bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
849 SCI->getOperand(1), BB, MII);
851 // LLVM -> X86 signed X86 unsigned
852 // ----- ---------- ------------
859 static const unsigned OpcodeTab[2][6] = {
860 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
861 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
864 if (BI.getSuccessor(0) != NextBB) {
865 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
866 if (BI.getSuccessor(1) != NextBB)
867 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
869 // Change to the inverse condition...
870 if (BI.getSuccessor(1) != NextBB) {
872 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
878 /// doCall - This emits an abstract call instruction, setting up the arguments
879 /// and the return value as appropriate. For the actual function call itself,
880 /// it inserts the specified CallMI instruction into the stream.
882 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
883 const std::vector<ValueRecord> &Args) {
885 // Count how many bytes are to be pushed on the stack...
886 unsigned NumBytes = 0;
889 for (unsigned i = 0, e = Args.size(); i != e; ++i)
890 switch (getClassB(Args[i].Ty)) {
891 case cByte: case cShort: case cInt:
892 NumBytes += 4; break;
894 NumBytes += 8; break;
896 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
898 default: assert(0 && "Unknown class!");
901 // Adjust the stack pointer for the new arguments...
902 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
904 // Arguments go on the stack in reverse order, as specified by the ABI.
905 unsigned ArgOffset = 0;
906 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
907 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
908 switch (getClassB(Args[i].Ty)) {
911 // Promote arg to 32 bits wide into a temporary register...
912 unsigned R = makeAnotherReg(Type::UIntTy);
913 promote32(R, Args[i]);
914 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
915 X86::ESP, ArgOffset).addReg(R);
919 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
920 X86::ESP, ArgOffset).addReg(ArgReg);
923 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
924 X86::ESP, ArgOffset).addReg(ArgReg);
925 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
926 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
927 ArgOffset += 4; // 8 byte entry, not 4.
931 if (Args[i].Ty == Type::FloatTy) {
932 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
933 X86::ESP, ArgOffset).addReg(ArgReg);
935 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
936 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
937 X86::ESP, ArgOffset).addReg(ArgReg);
938 ArgOffset += 4; // 8 byte entry, not 4.
942 default: assert(0 && "Unknown class!");
947 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
950 BB->push_back(CallMI);
952 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
954 // If there is a return value, scavenge the result from the location the call
957 if (Ret.Ty != Type::VoidTy) {
958 unsigned DestClass = getClassB(Ret.Ty);
963 // Integral results are in %eax, or the appropriate portion
965 static const unsigned regRegMove[] = {
966 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
968 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
969 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
972 case cFP: // Floating-point return values live in %ST(0)
973 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
975 case cLong: // Long values are left in EDX:EAX
976 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
977 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
979 default: assert(0 && "Unknown class!");
985 /// visitCallInst - Push args on stack and do a procedure call instruction.
986 void ISel::visitCallInst(CallInst &CI) {
987 MachineInstr *TheCall;
988 if (Function *F = CI.getCalledFunction()) {
989 // Is it an intrinsic function call?
990 if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
991 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
995 // Emit a CALL instruction with PC-relative displacement.
996 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
997 } else { // Emit an indirect call...
998 unsigned Reg = getReg(CI.getCalledValue());
999 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1002 std::vector<ValueRecord> Args;
1003 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1004 Args.push_back(ValueRecord(CI.getOperand(i)));
1006 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1007 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1011 void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
1012 unsigned TmpReg1, TmpReg2;
1014 case LLVMIntrinsic::va_start:
1015 // Get the address of the first vararg value...
1016 TmpReg1 = getReg(CI);
1017 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1020 case LLVMIntrinsic::va_copy:
1021 TmpReg1 = getReg(CI);
1022 TmpReg2 = getReg(CI.getOperand(1));
1023 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1025 case LLVMIntrinsic::va_end: return; // Noop on X86
1027 case LLVMIntrinsic::longjmp:
1028 case LLVMIntrinsic::siglongjmp:
1029 BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true);
1032 case LLVMIntrinsic::setjmp:
1033 case LLVMIntrinsic::sigsetjmp:
1034 // Setjmp always returns zero...
1035 BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0);
1037 default: assert(0 && "Unknown intrinsic for X86!");
1042 /// visitSimpleBinary - Implement simple binary operators for integral types...
1043 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1045 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1046 unsigned DestReg = getReg(B);
1047 MachineBasicBlock::iterator MI = BB->end();
1048 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1049 OperatorClass, DestReg);
1052 /// visitSimpleBinary - Implement simple binary operators for integral types...
1053 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
1056 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1057 /// and constant expression support.
1058 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
1059 MachineBasicBlock::iterator &IP,
1060 Value *Op0, Value *Op1,
1061 unsigned OperatorClass,unsigned TargetReg){
1062 unsigned Class = getClassB(Op0->getType());
1063 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1064 static const unsigned OpcodeTab[][4] = {
1065 // Arithmetic operators
1066 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1067 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1069 // Bitwise operators
1070 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1071 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1072 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1075 bool isLong = false;
1076 if (Class == cLong) {
1078 Class = cInt; // Bottom 32 bits are handled just like ints
1081 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1082 assert(Opcode && "Floating point arguments to logical inst?");
1083 unsigned Op0r = getReg(Op0, BB, IP);
1084 unsigned Op1r = getReg(Op1, BB, IP);
1085 BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
1087 if (isLong) { // Handle the upper 32 bits of long values...
1088 static const unsigned TopTab[] = {
1089 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1091 BMI(BB, IP, TopTab[OperatorClass], 2,
1092 TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
1095 // Special case: op Reg, <const>
1096 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1098 static const unsigned OpcodeTab[][3] = {
1099 // Arithmetic operators
1100 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1101 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1103 // Bitwise operators
1104 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1105 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1106 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1109 assert(Class < 3 && "General code handles 64-bit integer types!");
1110 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1111 unsigned Op0r = getReg(Op0, BB, IP);
1112 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1114 // Mask off any upper bits of the constant, if there are any...
1115 Op1v &= (1ULL << (8 << Class)) - 1;
1116 BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
1120 /// doMultiply - Emit appropriate instructions to multiply together the
1121 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1122 /// result should be given as DestTy.
1124 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1125 unsigned DestReg, const Type *DestTy,
1126 unsigned op0Reg, unsigned op1Reg) {
1127 unsigned Class = getClass(DestTy);
1129 case cFP: // Floating point multiply
1130 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1134 BMI(BB, MBBI, Class == cInt ? X86::IMULr32 : X86::IMULr16, 2, DestReg)
1135 .addReg(op0Reg).addReg(op1Reg);
1138 // Must use the MUL instruction, which forces use of AL...
1139 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1140 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1141 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1144 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1148 /// visitMul - Multiplies are not simple binary operators because they must deal
1149 /// with the EAX register explicitly.
1151 void ISel::visitMul(BinaryOperator &I) {
1152 unsigned Op0Reg = getReg(I.getOperand(0));
1153 unsigned Op1Reg = getReg(I.getOperand(1));
1154 unsigned DestReg = getReg(I);
1156 // Simple scalar multiply?
1157 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1158 MachineBasicBlock::iterator MBBI = BB->end();
1159 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1161 // Long value. We have to do things the hard way...
1162 // Multiply the two low parts... capturing carry into EDX
1163 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1164 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1166 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1167 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1168 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1170 MachineBasicBlock::iterator MBBI = BB->end();
1171 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1172 BMI(BB, MBBI, X86::IMULr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1174 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1175 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1176 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1179 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1180 BMI(BB, MBBI, X86::IMULr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1182 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1183 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1188 /// visitDivRem - Handle division and remainder instructions... these
1189 /// instruction both require the same instructions to be generated, they just
1190 /// select the result from a different register. Note that both of these
1191 /// instructions work differently for signed and unsigned operands.
1193 void ISel::visitDivRem(BinaryOperator &I) {
1194 unsigned Class = getClass(I.getType());
1195 unsigned Op0Reg, Op1Reg, ResultReg = getReg(I);
1198 case cFP: // Floating point divide
1199 if (I.getOpcode() == Instruction::Div) {
1200 Op0Reg = getReg(I.getOperand(0));
1201 Op1Reg = getReg(I.getOperand(1));
1202 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1203 } else { // Floating point remainder...
1204 MachineInstr *TheCall =
1205 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1206 std::vector<ValueRecord> Args;
1207 Args.push_back(ValueRecord(I.getOperand(0)));
1208 Args.push_back(ValueRecord(I.getOperand(1)));
1209 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1213 static const char *FnName[] =
1214 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1216 unsigned NameIdx = I.getType()->isUnsigned()*2;
1217 NameIdx += I.getOpcode() == Instruction::Div;
1218 MachineInstr *TheCall =
1219 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1221 std::vector<ValueRecord> Args;
1222 Args.push_back(ValueRecord(I.getOperand(0)));
1223 Args.push_back(ValueRecord(I.getOperand(1)));
1224 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1227 case cByte: case cShort: case cInt:
1228 break; // Small integrals, handled below...
1229 default: assert(0 && "Unknown class!");
1232 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1233 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1234 static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
1235 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1236 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1238 static const unsigned DivOpcode[][4] = {
1239 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1240 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1243 bool isSigned = I.getType()->isSigned();
1244 unsigned Reg = Regs[Class];
1245 unsigned ExtReg = ExtRegs[Class];
1247 // Put the first operand into one of the A registers...
1248 Op0Reg = getReg(I.getOperand(0));
1249 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1252 // Emit a sign extension instruction...
1253 unsigned ShiftResult = makeAnotherReg(I.getType());
1254 BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1255 BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1257 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1258 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1261 // Emit the appropriate divide or remainder instruction...
1262 Op1Reg = getReg(I.getOperand(1));
1263 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1265 // Figure out which register we want to pick the result out of...
1266 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1268 // Put the result into the destination register...
1269 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1273 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1274 /// for constant immediate shift values, and for constant immediate
1275 /// shift values equal to 1. Even the general case is sort of special,
1276 /// because the shift amount has to be in CL, not just any old register.
1278 void ISel::visitShiftInst(ShiftInst &I) {
1279 unsigned SrcReg = getReg(I.getOperand(0));
1280 unsigned DestReg = getReg(I);
1281 bool isLeftShift = I.getOpcode() == Instruction::Shl;
1282 bool isSigned = I.getType()->isSigned();
1283 unsigned Class = getClass(I.getType());
1285 static const unsigned ConstantOperand[][4] = {
1286 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1287 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1288 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1289 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1292 static const unsigned NonConstantOperand[][4] = {
1293 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1294 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1295 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1296 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1299 // Longs, as usual, are handled specially...
1300 if (Class == cLong) {
1301 // If we have a constant shift, we can generate much more efficient code
1302 // than otherwise...
1304 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1305 unsigned Amount = CUI->getValue();
1307 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1309 BuildMI(BB, Opc[3], 3,
1310 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1311 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1313 BuildMI(BB, Opc[3], 3,
1314 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1315 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1317 } else { // Shifting more than 32 bits
1320 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1321 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1323 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1324 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1325 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1329 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1331 if (!isLeftShift && isSigned) {
1332 // If this is a SHR of a Long, then we need to do funny sign extension
1333 // stuff. TmpReg gets the value to use as the high-part if we are
1334 // shifting more than 32 bits.
1335 BuildMI(BB, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1337 // Other shifts use a fixed zero value if the shift is more than 32
1339 BuildMI(BB, X86::MOVir32, 1, TmpReg).addZImm(0);
1342 // Initialize CL with the shift amount...
1343 unsigned ShiftAmount = getReg(I.getOperand(1));
1344 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmount);
1346 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1347 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1349 // TmpReg2 = shld inHi, inLo
1350 BuildMI(BB, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1351 // TmpReg3 = shl inLo, CL
1352 BuildMI(BB, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1354 // Set the flags to indicate whether the shift was by more than 32 bits.
1355 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1357 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1358 BuildMI(BB, X86::CMOVNErr32, 2,
1359 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1360 // DestLo = (>32) ? TmpReg : TmpReg3;
1361 BuildMI(BB, X86::CMOVNErr32, 2, DestReg).addReg(TmpReg3).addReg(TmpReg);
1363 // TmpReg2 = shrd inLo, inHi
1364 BuildMI(BB, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1365 // TmpReg3 = s[ah]r inHi, CL
1366 BuildMI(BB, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1369 // Set the flags to indicate whether the shift was by more than 32 bits.
1370 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1372 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1373 BuildMI(BB, X86::CMOVNErr32, 2,
1374 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1376 // DestHi = (>32) ? TmpReg : TmpReg3;
1377 BuildMI(BB, X86::CMOVNErr32, 2,
1378 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1384 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1385 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1386 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1388 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1389 BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1390 } else { // The shift amount is non-constant.
1391 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
1393 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1394 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1399 /// doFPLoad - This method is used to load an FP value from memory using the
1400 /// current endianness. NOTE: This method returns a partially constructed load
1401 /// instruction which needs to have the memory source filled in still.
1403 MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB,
1404 MachineBasicBlock::iterator &MBBI,
1405 const Type *Ty, unsigned DestReg) {
1406 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1407 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
1409 if (TM.getTargetData().isLittleEndian()) // fast path...
1410 return BMI(MBB, MBBI, LoadOpcode, 4, DestReg);
1412 // If we are big-endian, start by creating an LEA instruction to represent the
1413 // address of the memory location to load from...
1415 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1416 MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg);
1418 // Allocate a temporary stack slot to transform the value into...
1419 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1421 // Perform the bswaps 32 bits at a time...
1422 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1423 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1424 addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1425 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1426 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1427 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5),
1428 FrameIdx, Offset).addReg(TmpReg2);
1430 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1431 TmpReg1 = makeAnotherReg(Type::UIntTy);
1432 TmpReg2 = makeAnotherReg(Type::UIntTy);
1434 addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1435 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1436 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1437 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2);
1440 // Now we can reload the final byteswapped result into the final destination.
1441 addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx);
1445 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1447 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1448 // Emit the byte swap instruction...
1451 // No byteswap necessary for 8 bit value...
1452 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1455 // Use the 32 bit bswap instruction to do a 32 bit swap...
1456 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1460 // For 16 bit we have to use an xchg instruction, because there is no
1461 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1462 // into AX to do the xchg.
1464 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1465 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1466 .addReg(X86::AH, MOTy::UseAndDef);
1467 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1469 default: assert(0 && "Cannot byteswap this class!");
1474 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1475 /// instruction. The load and store instructions are the only place where we
1476 /// need to worry about the memory layout of the target machine.
1478 void ISel::visitLoadInst(LoadInst &I) {
1479 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1480 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1481 unsigned SrcAddrReg = getReg(I.getOperand(0));
1482 unsigned DestReg = getReg(I);
1484 unsigned Class = getClassB(I.getType());
1487 MachineBasicBlock::iterator MBBI = BB->end();
1488 addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg);
1491 case cLong: case cInt: case cShort: case cByte:
1492 break; // Integers of various sizes handled below
1493 default: assert(0 && "Unknown memory class!");
1496 // We need to adjust the input pointer if we are emulating a big-endian
1497 // long-pointer target. On these systems, the pointer that we are interested
1498 // in is in the upper part of the eight byte memory image of the pointer. It
1499 // also happens to be byte-swapped, but this will be handled later.
1501 if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
1502 unsigned R = makeAnotherReg(Type::UIntTy);
1503 BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
1507 unsigned IReg = DestReg;
1508 if (!isLittleEndian) // If big endian we need an intermediate stage
1509 DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy);
1511 static const unsigned Opcode[] = {
1512 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
1514 addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
1516 // Handle long values now...
1517 if (Class == cLong) {
1518 if (isLittleEndian) {
1519 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1521 EmitByteSwap(IReg+1, DestReg, cInt);
1522 unsigned TempReg = makeAnotherReg(Type::IntTy);
1523 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4);
1524 EmitByteSwap(IReg, TempReg, cInt);
1529 if (!isLittleEndian)
1530 EmitByteSwap(IReg, DestReg, Class);
1534 /// doFPStore - This method is used to store an FP value to memory using the
1535 /// current endianness.
1537 void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) {
1538 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1539 unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
1541 if (TM.getTargetData().isLittleEndian()) { // fast path...
1542 addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg);
1546 // Allocate a temporary stack slot to transform the value into...
1547 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1548 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1549 addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx);
1551 // Store the value into a temporary stack slot...
1552 addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg);
1554 // Perform the bswaps 32 bits at a time...
1555 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1556 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1557 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1558 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1559 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1560 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1561 DestAddrReg, Offset).addReg(TmpReg2);
1563 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1564 TmpReg1 = makeAnotherReg(Type::UIntTy);
1565 TmpReg2 = makeAnotherReg(Type::UIntTy);
1567 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1568 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1569 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1570 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2);
1575 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1578 void ISel::visitStoreInst(StoreInst &I) {
1579 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1580 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1581 unsigned ValReg = getReg(I.getOperand(0));
1582 unsigned AddressReg = getReg(I.getOperand(1));
1584 unsigned Class = getClassB(I.getOperand(0)->getType());
1587 if (isLittleEndian) {
1588 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1589 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4),
1590 AddressReg, 4).addReg(ValReg+1);
1592 unsigned T1 = makeAnotherReg(Type::IntTy);
1593 unsigned T2 = makeAnotherReg(Type::IntTy);
1594 EmitByteSwap(T1, ValReg , cInt);
1595 EmitByteSwap(T2, ValReg+1, cInt);
1596 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2);
1597 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1);
1601 doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg);
1603 case cInt: case cShort: case cByte:
1604 break; // Integers of various sizes handled below
1605 default: assert(0 && "Unknown memory class!");
1608 if (!isLittleEndian && hasLongPointers &&
1609 isa<PointerType>(I.getOperand(0)->getType())) {
1610 unsigned R = makeAnotherReg(Type::UIntTy);
1611 BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
1615 if (!isLittleEndian && Class != cByte) {
1616 unsigned R = makeAnotherReg(I.getOperand(0)->getType());
1617 EmitByteSwap(R, ValReg, Class);
1621 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1622 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
1626 /// visitCastInst - Here we have various kinds of copying with or without
1627 /// sign extension going on.
1628 void ISel::visitCastInst(CastInst &CI) {
1629 Value *Op = CI.getOperand(0);
1630 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1631 // of the case are GEP instructions, then the cast does not need to be
1632 // generated explicitly, it will be folded into the GEP.
1633 if (CI.getType() == Type::LongTy &&
1634 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1635 bool AllUsesAreGEPs = true;
1636 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1637 if (!isa<GetElementPtrInst>(*I)) {
1638 AllUsesAreGEPs = false;
1642 // No need to codegen this cast if all users are getelementptr instrs...
1643 if (AllUsesAreGEPs) return;
1646 unsigned DestReg = getReg(CI);
1647 MachineBasicBlock::iterator MI = BB->end();
1648 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1651 /// emitCastOperation - Common code shared between visitCastInst and
1652 /// constant expression cast support.
1653 void ISel::emitCastOperation(MachineBasicBlock *BB,
1654 MachineBasicBlock::iterator &IP,
1655 Value *Src, const Type *DestTy,
1657 unsigned SrcReg = getReg(Src, BB, IP);
1658 const Type *SrcTy = Src->getType();
1659 unsigned SrcClass = getClassB(SrcTy);
1660 unsigned DestClass = getClassB(DestTy);
1662 // Implement casts to bool by using compare on the operand followed by set if
1663 // not zero on the result.
1664 if (DestTy == Type::BoolTy) {
1667 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1670 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1673 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1676 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1677 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1681 assert(0 && "FIXME: implement cast FP to bool");
1685 // If the zero flag is not set, then the value is true, set the byte to
1687 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1691 static const unsigned RegRegMove[] = {
1692 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1695 // Implement casts between values of the same type class (as determined by
1696 // getClass) by using a register-to-register move.
1697 if (SrcClass == DestClass) {
1698 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1699 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1700 } else if (SrcClass == cFP) {
1701 if (SrcTy == Type::FloatTy) { // double -> float
1702 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1703 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1704 } else { // float -> double
1705 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1706 "Unknown cFP member!");
1707 // Truncate from double to float by storing to memory as short, then
1709 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1710 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1711 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1712 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1714 } else if (SrcClass == cLong) {
1715 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1716 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1718 assert(0 && "Cannot handle this type of cast instruction!");
1724 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1725 // or zero extension, depending on whether the source type was signed.
1726 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1727 SrcClass < DestClass) {
1728 bool isLong = DestClass == cLong;
1729 if (isLong) DestClass = cInt;
1731 static const unsigned Opc[][4] = {
1732 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1733 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1736 bool isUnsigned = SrcTy->isUnsigned();
1737 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1738 DestReg).addReg(SrcReg);
1740 if (isLong) { // Handle upper 32 bits as appropriate...
1741 if (isUnsigned) // Zero out top bits...
1742 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1743 else // Sign extend bottom half...
1744 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1749 // Special case long -> int ...
1750 if (SrcClass == cLong && DestClass == cInt) {
1751 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1755 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1756 // move out of AX or AL.
1757 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1758 && SrcClass > DestClass) {
1759 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1760 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1761 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1765 // Handle casts from integer to floating point now...
1766 if (DestClass == cFP) {
1767 // Promote the integer to a type supported by FLD. We do this because there
1768 // are no unsigned FLD instructions, so we must promote an unsigned value to
1769 // a larger signed value, then use FLD on the larger value.
1771 const Type *PromoteType = 0;
1772 unsigned PromoteOpcode;
1773 switch (SrcTy->getPrimitiveID()) {
1774 case Type::BoolTyID:
1775 case Type::SByteTyID:
1776 // We don't have the facilities for directly loading byte sized data from
1777 // memory (even signed). Promote it to 16 bits.
1778 PromoteType = Type::ShortTy;
1779 PromoteOpcode = X86::MOVSXr16r8;
1781 case Type::UByteTyID:
1782 PromoteType = Type::ShortTy;
1783 PromoteOpcode = X86::MOVZXr16r8;
1785 case Type::UShortTyID:
1786 PromoteType = Type::IntTy;
1787 PromoteOpcode = X86::MOVZXr32r16;
1789 case Type::UIntTyID: {
1790 // Make a 64 bit temporary... and zero out the top of it...
1791 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1792 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1793 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1794 SrcTy = Type::LongTy;
1799 case Type::ULongTyID:
1800 assert("FIXME: not implemented: cast ulong X to fp type!");
1801 default: // No promotion needed...
1806 unsigned TmpReg = makeAnotherReg(PromoteType);
1807 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1808 1, TmpReg).addReg(SrcReg);
1809 SrcTy = PromoteType;
1810 SrcClass = getClass(PromoteType);
1814 // Spill the integer to memory and reload it from there...
1816 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1818 if (SrcClass == cLong) {
1819 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1820 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1821 FrameIdx, 4).addReg(SrcReg+1);
1823 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1824 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1827 static const unsigned Op2[] =
1828 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1829 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1833 // Handle casts from floating point to integer now...
1834 if (SrcClass == cFP) {
1835 // Change the floating point control register to use "round towards zero"
1836 // mode when truncating to an integer value.
1838 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1839 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1841 // Load the old value of the high byte of the control word...
1842 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1843 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1845 // Set the high part to be round to zero...
1846 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1848 // Reload the modified control word now...
1849 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1851 // Restore the memory image of control word to original value
1852 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1853 CWFrameIdx, 1).addReg(HighPartOfCW);
1855 // We don't have the facilities for directly storing byte sized data to
1856 // memory. Promote it to 16 bits. We also must promote unsigned values to
1857 // larger classes because we only have signed FP stores.
1858 unsigned StoreClass = DestClass;
1859 const Type *StoreTy = DestTy;
1860 if (StoreClass == cByte || DestTy->isUnsigned())
1861 switch (StoreClass) {
1862 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1863 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1864 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1865 // The following treatment of cLong may not be perfectly right,
1866 // but it survives chains of casts of the form
1867 // double->ulong->double.
1868 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
1869 default: assert(0 && "Unknown store class!");
1872 // Spill the integer to memory and reload it from there...
1874 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1876 static const unsigned Op1[] =
1877 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1878 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1880 if (DestClass == cLong) {
1881 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1882 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1884 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1885 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1888 // Reload the original control word now...
1889 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1893 // Anything we haven't handled already, we can't (yet) handle at all.
1894 assert(0 && "Unhandled cast instruction!");
1898 /// visitVANextInst - Implement the va_next instruction...
1900 void ISel::visitVANextInst(VANextInst &I) {
1901 unsigned VAList = getReg(I.getOperand(0));
1902 unsigned DestReg = getReg(I);
1905 switch (I.getArgType()->getPrimitiveID()) {
1908 assert(0 && "Error: bad type for va_next instruction!");
1910 case Type::PointerTyID:
1911 case Type::UIntTyID:
1915 case Type::ULongTyID:
1916 case Type::LongTyID:
1917 case Type::DoubleTyID:
1922 // Increment the VAList pointer...
1923 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
1926 void ISel::visitVAArgInst(VAArgInst &I) {
1927 unsigned VAList = getReg(I.getOperand(0));
1928 unsigned DestReg = getReg(I);
1930 switch (I.getType()->getPrimitiveID()) {
1933 assert(0 && "Error: bad type for va_next instruction!");
1935 case Type::PointerTyID:
1936 case Type::UIntTyID:
1938 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1940 case Type::ULongTyID:
1941 case Type::LongTyID:
1942 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1943 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
1945 case Type::DoubleTyID:
1946 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
1952 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1953 // returns zero when the input is not exactly a power of two.
1954 static unsigned ExactLog2(unsigned Val) {
1955 if (Val == 0) return 0;
1958 if (Val & 1) return 0;
1965 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
1966 unsigned outputReg = getReg(I);
1967 MachineBasicBlock::iterator MI = BB->end();
1968 emitGEPOperation(BB, MI, I.getOperand(0),
1969 I.op_begin()+1, I.op_end(), outputReg);
1972 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
1973 MachineBasicBlock::iterator &IP,
1974 Value *Src, User::op_iterator IdxBegin,
1975 User::op_iterator IdxEnd, unsigned TargetReg) {
1976 const TargetData &TD = TM.getTargetData();
1977 const Type *Ty = Src->getType();
1978 unsigned BaseReg = getReg(Src, MBB, IP);
1980 // GEPs have zero or more indices; we must perform a struct access
1981 // or array access for each one.
1982 for (GetElementPtrInst::op_iterator oi = IdxBegin,
1983 oe = IdxEnd; oi != oe; ++oi) {
1985 unsigned NextReg = BaseReg;
1986 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1987 // It's a struct access. idx is the index into the structure,
1988 // which names the field. This index must have ubyte type.
1989 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
1990 assert(CUI->getType() == Type::UByteTy
1991 && "Funny-looking structure index in GEP");
1992 // Use the TargetData structure to pick out what the layout of
1993 // the structure is in memory. Since the structure index must
1994 // be constant, we can get its value and use it to find the
1995 // right byte offset from the StructLayout class's list of
1996 // structure member offsets.
1997 unsigned idxValue = CUI->getValue();
1998 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
2000 NextReg = makeAnotherReg(Type::UIntTy);
2001 // Emit an ADD to add FieldOff to the basePtr.
2002 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
2004 // The next type is the member of the structure selected by the
2006 Ty = StTy->getElementTypes()[idxValue];
2007 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
2008 // It's an array or pointer access: [ArraySize x ElementType].
2010 // idx is the index into the array. Unlike with structure
2011 // indices, we may not know its actual value at code-generation
2013 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2015 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2016 // operand on X86. Handle this case directly now...
2017 if (CastInst *CI = dyn_cast<CastInst>(idx))
2018 if (CI->getOperand(0)->getType() == Type::IntTy ||
2019 CI->getOperand(0)->getType() == Type::UIntTy)
2020 idx = CI->getOperand(0);
2022 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2023 // must find the size of the pointed-to type (Not coincidentally, the next
2024 // type is the type of the elements in the array).
2025 Ty = SqTy->getElementType();
2026 unsigned elementSize = TD.getTypeSize(Ty);
2028 // If idxReg is a constant, we don't need to perform the multiply!
2029 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2030 if (!CSI->isNullValue()) {
2031 unsigned Offset = elementSize*CSI->getValue();
2032 NextReg = makeAnotherReg(Type::UIntTy);
2033 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
2035 } else if (elementSize == 1) {
2036 // If the element size is 1, we don't have to multiply, just add
2037 unsigned idxReg = getReg(idx, MBB, IP);
2038 NextReg = makeAnotherReg(Type::UIntTy);
2039 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
2041 unsigned idxReg = getReg(idx, MBB, IP);
2042 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2043 if (unsigned Shift = ExactLog2(elementSize)) {
2044 // If the element size is exactly a power of 2, use a shift to get it.
2045 BMI(MBB, IP, X86::SHLir32, 2,
2046 OffsetReg).addReg(idxReg).addZImm(Shift-1);
2048 // Most general case, emit a multiply...
2049 unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
2050 BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
2052 // Emit a MUL to multiply the register holding the index by
2053 // elementSize, putting the result in OffsetReg.
2054 doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
2056 // Emit an ADD to add OffsetReg to the basePtr.
2057 NextReg = makeAnotherReg(Type::UIntTy);
2058 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
2061 // Now that we are here, further indices refer to subtypes of this
2062 // one, so we don't need to worry about BaseReg itself, anymore.
2065 // After we have processed all the indices, the result is left in
2066 // BaseReg. Move it to the register where we were expected to
2067 // put the answer. A 32-bit move should do it, because we are in
2069 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2073 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2074 /// frame manager, otherwise do it the hard way.
2076 void ISel::visitAllocaInst(AllocaInst &I) {
2077 // Find the data size of the alloca inst's getAllocatedType.
2078 const Type *Ty = I.getAllocatedType();
2079 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2081 // If this is a fixed size alloca in the entry block for the function,
2082 // statically stack allocate the space.
2084 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2085 if (I.getParent() == I.getParent()->getParent()->begin()) {
2086 TySize *= CUI->getValue(); // Get total allocated size...
2087 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2089 // Create a new stack object using the frame manager...
2090 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2091 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2096 // Create a register to hold the temporary result of multiplying the type size
2097 // constant by the variable amount.
2098 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2099 unsigned SrcReg1 = getReg(I.getArraySize());
2100 unsigned SizeReg = makeAnotherReg(Type::UIntTy);
2101 BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
2103 // TotalSizeReg = mul <numelements>, <TypeSize>
2104 MachineBasicBlock::iterator MBBI = BB->end();
2105 doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
2107 // AddedSize = add <TotalSizeReg>, 15
2108 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2109 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2111 // AlignedSize = and <AddedSize>, ~15
2112 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2113 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2115 // Subtract size from stack pointer, thereby allocating some space.
2116 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2118 // Put a pointer to the space into the result register, by copying
2119 // the stack pointer.
2120 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2122 // Inform the Frame Information that we have just allocated a variable-sized
2124 F->getFrameInfo()->CreateVariableSizedObject();
2127 /// visitMallocInst - Malloc instructions are code generated into direct calls
2128 /// to the library malloc.
2130 void ISel::visitMallocInst(MallocInst &I) {
2131 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2134 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2135 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2137 Arg = makeAnotherReg(Type::UIntTy);
2138 unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
2139 unsigned Op1Reg = getReg(I.getOperand(0));
2140 MachineBasicBlock::iterator MBBI = BB->end();
2141 doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
2144 std::vector<ValueRecord> Args;
2145 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2146 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2147 1).addExternalSymbol("malloc", true);
2148 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2152 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2155 void ISel::visitFreeInst(FreeInst &I) {
2156 std::vector<ValueRecord> Args;
2157 Args.push_back(ValueRecord(I.getOperand(0)));
2158 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2159 1).addExternalSymbol("free", true);
2160 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2164 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2165 /// into a machine code representation is a very simple peep-hole fashion. The
2166 /// generated code sucks but the implementation is nice and simple.
2168 FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) {
2169 return new ISel(TM);