1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/InstVisitor.h"
31 #include "llvm/Support/CFG.h"
36 /// BMI - A special BuildMI variant that takes an iterator to insert the
37 /// instruction at as well as a basic block. This is the version for when you
38 /// have a destination register in mind.
39 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
40 MachineBasicBlock::iterator I,
41 int Opcode, unsigned NumOperands,
43 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
45 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
48 /// BMI - A special BuildMI variant that takes an iterator to insert the
49 /// instruction at as well as a basic block.
50 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
51 MachineBasicBlock::iterator I,
52 int Opcode, unsigned NumOperands) {
53 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
55 return MachineInstrBuilder(MI);
60 struct ISel : public FunctionPass, InstVisitor<ISel> {
62 MachineFunction *F; // The function we are compiling into
63 MachineBasicBlock *BB; // The current MBB we are compiling
64 int VarArgsFrameIndex; // FrameIndex for start of varargs area
66 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
68 // MBBMap - Mapping between LLVM BB -> Machine BB
69 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
71 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
73 /// runOnFunction - Top level implementation of instruction selection for
74 /// the entire function.
76 bool runOnFunction(Function &Fn) {
77 // First pass over the function, lower any unknown intrinsic functions
78 // with the IntrinsicLowering class.
79 LowerUnknownIntrinsicFunctionCalls(Fn);
81 F = &MachineFunction::construct(&Fn, TM);
83 // Create all of the machine basic blocks for the function...
84 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
85 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
89 // Copy incoming arguments off of the stack...
90 LoadArgumentsToVirtualRegs(Fn);
92 // Instruction select everything except PHI nodes
95 // Select the PHI nodes
101 // We always build a machine code representation for the function
105 virtual const char *getPassName() const {
106 return "X86 Simple Instruction Selection";
109 /// visitBasicBlock - This method is called when we are visiting a new basic
110 /// block. This simply creates a new MachineBasicBlock to emit code into
111 /// and adds it to the current MachineFunction. Subsequent visit* for
112 /// instructions will be invoked for all instructions in the basic block.
114 void visitBasicBlock(BasicBlock &LLVM_BB) {
115 BB = MBBMap[&LLVM_BB];
118 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
119 /// function, lowering any calls to unknown intrinsic functions into the
120 /// equivalent LLVM code.
121 void LowerUnknownIntrinsicFunctionCalls(Function &F);
123 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
124 /// from the stack into virtual registers.
126 void LoadArgumentsToVirtualRegs(Function &F);
128 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
129 /// because we have to generate our sources into the source basic blocks,
130 /// not the current one.
132 void SelectPHINodes();
134 // Visitation methods for various instructions. These methods simply emit
135 // fixed X86 code for each instruction.
138 // Control flow operators
139 void visitReturnInst(ReturnInst &RI);
140 void visitBranchInst(BranchInst &BI);
146 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
147 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
149 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
150 const std::vector<ValueRecord> &Args);
151 void visitCallInst(CallInst &I);
152 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
154 // Arithmetic operators
155 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
156 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
157 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
158 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
159 unsigned DestReg, const Type *DestTy,
160 unsigned Op0Reg, unsigned Op1Reg);
161 void doMultiplyConst(MachineBasicBlock *MBB,
162 MachineBasicBlock::iterator &MBBI,
163 unsigned DestReg, const Type *DestTy,
164 unsigned Op0Reg, unsigned Op1Val);
165 void visitMul(BinaryOperator &B);
167 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
168 void visitRem(BinaryOperator &B) { visitDivRem(B); }
169 void visitDivRem(BinaryOperator &B);
172 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
173 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
174 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
176 // Comparison operators...
177 void visitSetCondInst(SetCondInst &I);
178 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
179 MachineBasicBlock *MBB,
180 MachineBasicBlock::iterator &MBBI);
182 // Memory Instructions
183 void visitLoadInst(LoadInst &I);
184 void visitStoreInst(StoreInst &I);
185 void visitGetElementPtrInst(GetElementPtrInst &I);
186 void visitAllocaInst(AllocaInst &I);
187 void visitMallocInst(MallocInst &I);
188 void visitFreeInst(FreeInst &I);
191 void visitShiftInst(ShiftInst &I);
192 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
193 void visitCastInst(CastInst &I);
194 void visitVANextInst(VANextInst &I);
195 void visitVAArgInst(VAArgInst &I);
197 void visitInstruction(Instruction &I) {
198 std::cerr << "Cannot instruction select: " << I;
202 /// promote32 - Make a value 32-bits wide, and put it somewhere.
204 void promote32(unsigned targetReg, const ValueRecord &VR);
206 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
207 /// constant expression GEP support.
209 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
210 Value *Src, User::op_iterator IdxBegin,
211 User::op_iterator IdxEnd, unsigned TargetReg);
213 /// emitCastOperation - Common code shared between visitCastInst and
214 /// constant expression cast support.
215 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
216 Value *Src, const Type *DestTy, unsigned TargetReg);
218 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
219 /// and constant expression support.
220 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
221 MachineBasicBlock::iterator &IP,
222 Value *Op0, Value *Op1,
223 unsigned OperatorClass, unsigned TargetReg);
225 void emitDivRemOperation(MachineBasicBlock *BB,
226 MachineBasicBlock::iterator &IP,
227 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
228 const Type *Ty, unsigned TargetReg);
230 /// emitSetCCOperation - Common code shared between visitSetCondInst and
231 /// constant expression support.
232 void emitSetCCOperation(MachineBasicBlock *BB,
233 MachineBasicBlock::iterator &IP,
234 Value *Op0, Value *Op1, unsigned Opcode,
237 /// emitShiftOperation - Common code shared between visitShiftInst and
238 /// constant expression support.
239 void emitShiftOperation(MachineBasicBlock *MBB,
240 MachineBasicBlock::iterator &IP,
241 Value *Op, Value *ShiftAmount, bool isLeftShift,
242 const Type *ResultTy, unsigned DestReg);
245 /// copyConstantToRegister - Output the instructions required to put the
246 /// specified constant into the specified register.
248 void copyConstantToRegister(MachineBasicBlock *MBB,
249 MachineBasicBlock::iterator &MBBI,
250 Constant *C, unsigned Reg);
252 /// makeAnotherReg - This method returns the next register number we haven't
255 /// Long values are handled somewhat specially. They are always allocated
256 /// as pairs of 32 bit integer values. The register number returned is the
257 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
258 /// of the long value.
260 unsigned makeAnotherReg(const Type *Ty) {
261 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
262 "Current target doesn't have X86 reg info??");
263 const X86RegisterInfo *MRI =
264 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
265 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
266 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
267 // Create the lower part
268 F->getSSARegMap()->createVirtualRegister(RC);
269 // Create the upper part.
270 return F->getSSARegMap()->createVirtualRegister(RC)-1;
273 // Add the mapping of regnumber => reg class to MachineFunction
274 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
275 return F->getSSARegMap()->createVirtualRegister(RC);
278 /// getReg - This method turns an LLVM value into a register number. This
279 /// is guaranteed to produce the same register number for a particular value
280 /// every time it is queried.
282 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
283 unsigned getReg(Value *V) {
284 // Just append to the end of the current bb.
285 MachineBasicBlock::iterator It = BB->end();
286 return getReg(V, BB, It);
288 unsigned getReg(Value *V, MachineBasicBlock *MBB,
289 MachineBasicBlock::iterator &IPt) {
290 unsigned &Reg = RegMap[V];
292 Reg = makeAnotherReg(V->getType());
296 // If this operand is a constant, emit the code to copy the constant into
297 // the register here...
299 if (Constant *C = dyn_cast<Constant>(V)) {
300 copyConstantToRegister(MBB, IPt, C, Reg);
301 RegMap.erase(V); // Assign a new name to this constant if ref'd again
302 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
303 // Move the address of the global into the register
304 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
305 RegMap.erase(V); // Assign a new name to this address if ref'd again
313 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
317 cByte, cShort, cInt, cFP, cLong
320 /// getClass - Turn a primitive type into a "class" number which is based on the
321 /// size of the type, and whether or not it is floating point.
323 static inline TypeClass getClass(const Type *Ty) {
324 switch (Ty->getPrimitiveID()) {
325 case Type::SByteTyID:
326 case Type::UByteTyID: return cByte; // Byte operands are class #0
327 case Type::ShortTyID:
328 case Type::UShortTyID: return cShort; // Short operands are class #1
331 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
333 case Type::FloatTyID:
334 case Type::DoubleTyID: return cFP; // Floating Point is #3
337 case Type::ULongTyID: return cLong; // Longs are class #4
339 assert(0 && "Invalid type to getClass!");
340 return cByte; // not reached
344 // getClassB - Just like getClass, but treat boolean values as bytes.
345 static inline TypeClass getClassB(const Type *Ty) {
346 if (Ty == Type::BoolTy) return cByte;
351 /// copyConstantToRegister - Output the instructions required to put the
352 /// specified constant into the specified register.
354 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
355 MachineBasicBlock::iterator &IP,
356 Constant *C, unsigned R) {
357 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
359 switch (CE->getOpcode()) {
360 case Instruction::GetElementPtr:
361 emitGEPOperation(MBB, IP, CE->getOperand(0),
362 CE->op_begin()+1, CE->op_end(), R);
364 case Instruction::Cast:
365 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
368 case Instruction::Xor: ++Class; // FALL THROUGH
369 case Instruction::Or: ++Class; // FALL THROUGH
370 case Instruction::And: ++Class; // FALL THROUGH
371 case Instruction::Sub: ++Class; // FALL THROUGH
372 case Instruction::Add:
373 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
377 case Instruction::Mul: {
378 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
379 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
380 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
383 case Instruction::Div:
384 case Instruction::Rem: {
385 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
386 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
387 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
388 CE->getOpcode() == Instruction::Div,
393 case Instruction::SetNE:
394 case Instruction::SetEQ:
395 case Instruction::SetLT:
396 case Instruction::SetGT:
397 case Instruction::SetLE:
398 case Instruction::SetGE:
399 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
403 case Instruction::Shl:
404 case Instruction::Shr:
405 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
406 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
410 std::cerr << "Offending expr: " << C << "\n";
411 assert(0 && "Constant expression not yet handled!\n");
415 if (C->getType()->isIntegral()) {
416 unsigned Class = getClassB(C->getType());
418 if (Class == cLong) {
419 // Copy the value into the register pair.
420 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
421 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
422 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
426 assert(Class <= cInt && "Type not handled yet!");
428 static const unsigned IntegralOpcodeTab[] = {
429 X86::MOVir8, X86::MOVir16, X86::MOVir32
432 if (C->getType() == Type::BoolTy) {
433 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
435 ConstantInt *CI = cast<ConstantInt>(C);
436 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
438 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
439 if (CFP->isExactlyValue(+0.0))
440 BMI(MBB, IP, X86::FLD0, 0, R);
441 else if (CFP->isExactlyValue(+1.0))
442 BMI(MBB, IP, X86::FLD1, 0, R);
444 // Otherwise we need to spill the constant to memory...
445 MachineConstantPool *CP = F->getConstantPool();
446 unsigned CPI = CP->getConstantPoolIndex(CFP);
447 const Type *Ty = CFP->getType();
449 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
450 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
451 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
454 } else if (isa<ConstantPointerNull>(C)) {
455 // Copy zero (null pointer) to the register.
456 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
457 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
458 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
459 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
461 std::cerr << "Offending constant: " << C << "\n";
462 assert(0 && "Type not handled yet!");
466 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
467 /// the stack into virtual registers.
469 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
470 // Emit instructions to load the arguments... On entry to a function on the
471 // X86, the stack frame looks like this:
473 // [ESP] -- return address
474 // [ESP + 4] -- first argument (leftmost lexically)
475 // [ESP + 8] -- second argument, if first argument is four bytes in size
478 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
479 MachineFrameInfo *MFI = F->getFrameInfo();
481 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
482 unsigned Reg = getReg(*I);
484 int FI; // Frame object index
485 switch (getClassB(I->getType())) {
487 FI = MFI->CreateFixedObject(1, ArgOffset);
488 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
491 FI = MFI->CreateFixedObject(2, ArgOffset);
492 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
495 FI = MFI->CreateFixedObject(4, ArgOffset);
496 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
499 FI = MFI->CreateFixedObject(8, ArgOffset);
500 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
501 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
502 ArgOffset += 4; // longs require 4 additional bytes
506 if (I->getType() == Type::FloatTy) {
507 Opcode = X86::FLDr32;
508 FI = MFI->CreateFixedObject(4, ArgOffset);
510 Opcode = X86::FLDr64;
511 FI = MFI->CreateFixedObject(8, ArgOffset);
512 ArgOffset += 4; // doubles require 4 additional bytes
514 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
517 assert(0 && "Unhandled argument type!");
519 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
522 // If the function takes variable number of arguments, add a frame offset for
523 // the start of the first vararg value... this is used to expand
525 if (Fn.getFunctionType()->isVarArg())
526 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
530 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
531 /// because we have to generate our sources into the source basic blocks, not
534 void ISel::SelectPHINodes() {
535 const TargetInstrInfo &TII = TM.getInstrInfo();
536 const Function &LF = *F->getFunction(); // The LLVM function...
537 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
538 const BasicBlock *BB = I;
539 MachineBasicBlock *MBB = MBBMap[I];
541 // Loop over all of the PHI nodes in the LLVM basic block...
542 MachineInstr* instr = MBB->begin();
543 for (BasicBlock::const_iterator I = BB->begin();
544 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
546 // Create a new machine instr PHI node, and insert it.
547 unsigned PHIReg = getReg(*PN);
548 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
549 MBB->insert(instr, PhiMI);
551 MachineInstr *LongPhiMI = 0;
552 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
553 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
554 MBB->insert(instr, LongPhiMI);
557 // PHIValues - Map of blocks to incoming virtual registers. We use this
558 // so that we only initialize one incoming value for a particular block,
559 // even if the block has multiple entries in the PHI node.
561 std::map<MachineBasicBlock*, unsigned> PHIValues;
563 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
564 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
566 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
567 PHIValues.lower_bound(PredMBB);
569 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
570 // We already inserted an initialization of the register for this
571 // predecessor. Recycle it.
572 ValReg = EntryIt->second;
575 // Get the incoming value into a virtual register.
577 Value *Val = PN->getIncomingValue(i);
579 // If this is a constant or GlobalValue, we may have to insert code
580 // into the basic block to compute it into a virtual register.
581 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
582 // Because we don't want to clobber any values which might be in
583 // physical registers with the computation of this constant (which
584 // might be arbitrarily complex if it is a constant expression),
585 // just insert the computation at the top of the basic block.
586 MachineBasicBlock::iterator PI = PredMBB->begin();
588 // Skip over any PHI nodes though!
589 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
592 ValReg = getReg(Val, PredMBB, PI);
594 ValReg = getReg(Val);
597 // Remember that we inserted a value for this PHI for this predecessor
598 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
601 PhiMI->addRegOperand(ValReg);
602 PhiMI->addMachineBasicBlockOperand(PredMBB);
604 LongPhiMI->addRegOperand(ValReg+1);
605 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
612 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
613 // the conditional branch instruction which is the only user of the cc
614 // instruction. This is the case if the conditional branch is the only user of
615 // the setcc, and if the setcc is in the same basic block as the conditional
616 // branch. We also don't handle long arguments below, so we reject them here as
619 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
620 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
621 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
622 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
623 const Type *Ty = SCI->getOperand(0)->getType();
624 if (Ty != Type::LongTy && Ty != Type::ULongTy)
630 // Return a fixed numbering for setcc instructions which does not depend on the
631 // order of the opcodes.
633 static unsigned getSetCCNumber(unsigned Opcode) {
635 default: assert(0 && "Unknown setcc instruction!");
636 case Instruction::SetEQ: return 0;
637 case Instruction::SetNE: return 1;
638 case Instruction::SetLT: return 2;
639 case Instruction::SetGE: return 3;
640 case Instruction::SetGT: return 4;
641 case Instruction::SetLE: return 5;
645 // LLVM -> X86 signed X86 unsigned
646 // ----- ---------- ------------
647 // seteq -> sete sete
648 // setne -> setne setne
649 // setlt -> setl setb
650 // setge -> setge setae
651 // setgt -> setg seta
652 // setle -> setle setbe
654 // sets // Used by comparison with 0 optimization
656 static const unsigned SetCCOpcodeTab[2][8] = {
657 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
659 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
660 X86::SETSr, X86::SETNSr },
663 // EmitComparison - This function emits a comparison of the two operands,
664 // returning the extended setcc code to use.
665 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
666 MachineBasicBlock *MBB,
667 MachineBasicBlock::iterator &IP) {
668 // The arguments are already supposed to be of the same type.
669 const Type *CompTy = Op0->getType();
670 unsigned Class = getClassB(CompTy);
671 unsigned Op0r = getReg(Op0, MBB, IP);
673 // Special case handling of: cmp R, i
674 if (Class == cByte || Class == cShort || Class == cInt)
675 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
676 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
678 // Mask off any upper bits of the constant, if there are any...
679 Op1v &= (1ULL << (8 << Class)) - 1;
681 // If this is a comparison against zero, emit more efficient code. We
682 // can't handle unsigned comparisons against zero unless they are == or
683 // !=. These should have been strength reduced already anyway.
684 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
685 static const unsigned TESTTab[] = {
686 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
688 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
690 if (OpNum == 2) return 6; // Map jl -> js
691 if (OpNum == 3) return 7; // Map jg -> jns
695 static const unsigned CMPTab[] = {
696 X86::CMPri8, X86::CMPri16, X86::CMPri32
699 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
703 // Special case handling of comparison against +/- 0.0
704 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
705 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
706 BMI(MBB, IP, X86::FTST, 1).addReg(Op0r);
707 BMI(MBB, IP, X86::FNSTSWr8, 0);
708 BMI(MBB, IP, X86::SAHF, 1);
712 unsigned Op1r = getReg(Op1, MBB, IP);
714 default: assert(0 && "Unknown type class!");
715 // Emit: cmp <var1>, <var2> (do the comparison). We can
716 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
719 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
722 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
725 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
728 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
729 BMI(MBB, IP, X86::FNSTSWr8, 0);
730 BMI(MBB, IP, X86::SAHF, 1);
734 if (OpNum < 2) { // seteq, setne
735 unsigned LoTmp = makeAnotherReg(Type::IntTy);
736 unsigned HiTmp = makeAnotherReg(Type::IntTy);
737 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
738 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
739 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
740 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
741 break; // Allow the sete or setne to be generated from flags set by OR
743 // Emit a sequence of code which compares the high and low parts once
744 // each, then uses a conditional move to handle the overflow case. For
745 // example, a setlt for long would generate code like this:
747 // AL = lo(op1) < lo(op2) // Signedness depends on operands
748 // BL = hi(op1) < hi(op2) // Always unsigned comparison
749 // dest = hi(op1) == hi(op2) ? AL : BL;
752 // FIXME: This would be much better if we had hierarchical register
753 // classes! Until then, hardcode registers so that we can deal with their
754 // aliases (because we don't have conditional byte moves).
756 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
757 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
758 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
759 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
760 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
761 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
762 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
763 // NOTE: visitSetCondInst knows that the value is dumped into the BL
764 // register at this point for long values...
772 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
773 /// register, then move it to wherever the result should be.
775 void ISel::visitSetCondInst(SetCondInst &I) {
776 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
778 unsigned DestReg = getReg(I);
779 MachineBasicBlock::iterator MII = BB->end();
780 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
784 /// emitSetCCOperation - Common code shared between visitSetCondInst and
785 /// constant expression support.
786 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
787 MachineBasicBlock::iterator &IP,
788 Value *Op0, Value *Op1, unsigned Opcode,
789 unsigned TargetReg) {
790 unsigned OpNum = getSetCCNumber(Opcode);
791 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
793 const Type *CompTy = Op0->getType();
794 unsigned CompClass = getClassB(CompTy);
795 bool isSigned = CompTy->isSigned() && CompClass != cFP;
797 if (CompClass != cLong || OpNum < 2) {
798 // Handle normal comparisons with a setcc instruction...
799 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
801 // Handle long comparisons by copying the value which is already in BL into
802 // the register we want...
803 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
810 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
811 /// operand, in the specified target register.
812 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
813 bool isUnsigned = VR.Ty->isUnsigned();
815 // Make sure we have the register number for this value...
816 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
818 switch (getClassB(VR.Ty)) {
820 // Extend value into target register (8->32)
822 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
824 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
827 // Extend value into target register (16->32)
829 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
831 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
834 // Move value into target register (32->32)
835 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
838 assert(0 && "Unpromotable operand class in promote32");
842 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
843 /// we have the following possibilities:
845 /// ret void: No return value, simply emit a 'ret' instruction
846 /// ret sbyte, ubyte : Extend value into EAX and return
847 /// ret short, ushort: Extend value into EAX and return
848 /// ret int, uint : Move value into EAX and return
849 /// ret pointer : Move value into EAX and return
850 /// ret long, ulong : Move value into EAX/EDX and return
851 /// ret float/double : Top of FP stack
853 void ISel::visitReturnInst(ReturnInst &I) {
854 if (I.getNumOperands() == 0) {
856 BuildMI(BB, X86::FP_REG_KILL, 0);
858 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
862 Value *RetVal = I.getOperand(0);
863 unsigned RetReg = getReg(RetVal);
864 switch (getClassB(RetVal->getType())) {
865 case cByte: // integral return values: extend or move into EAX and return
868 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
869 // Declare that EAX is live on exit
870 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
872 case cFP: // Floats & Doubles: Return in ST(0)
873 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
874 // Declare that top-of-stack is live on exit
875 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
878 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
879 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
880 // Declare that EAX & EDX are live on exit
881 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
887 // Emit a 'ret' instruction
889 BuildMI(BB, X86::FP_REG_KILL, 0);
891 BuildMI(BB, X86::RET, 0);
894 // getBlockAfter - Return the basic block which occurs lexically after the
896 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
897 Function::iterator I = BB; ++I; // Get iterator to next block
898 return I != BB->getParent()->end() ? &*I : 0;
901 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
902 /// compensation code on critical edges. As such, it requires that we kill all
903 /// FP registers on the exit from any blocks that either ARE critical edges, or
904 /// branch to a block that has incoming critical edges.
906 /// Note that this kill instruction will eventually be eliminated when
907 /// restrictions in the stackifier are relaxed.
909 static bool RequiresFPRegKill(const BasicBlock *BB) {
911 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
912 const BasicBlock *Succ = *SI;
913 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
914 ++PI; // Block have at least one predecessory
915 if (PI != PE) { // If it has exactly one, this isn't crit edge
916 // If this block has more than one predecessor, check all of the
917 // predecessors to see if they have multiple successors. If so, then the
918 // block we are analyzing needs an FPRegKill.
919 for (PI = pred_begin(Succ); PI != PE; ++PI) {
920 const BasicBlock *Pred = *PI;
921 succ_const_iterator SI2 = succ_begin(Pred);
922 ++SI2; // There must be at least one successor of this block.
923 if (SI2 != succ_end(Pred))
924 return true; // Yes, we must insert the kill on this edge.
928 // If we got this far, there is no need to insert the kill instruction.
935 /// visitBranchInst - Handle conditional and unconditional branches here. Note
936 /// that since code layout is frozen at this point, that if we are trying to
937 /// jump to a block that is the immediate successor of the current block, we can
938 /// just make a fall-through (but we don't currently).
940 void ISel::visitBranchInst(BranchInst &BI) {
941 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
943 if (!BI.isConditional()) { // Unconditional branch?
944 if (RequiresFPRegKill(BI.getParent()))
945 BuildMI(BB, X86::FP_REG_KILL, 0);
946 if (BI.getSuccessor(0) != NextBB)
947 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
951 // See if we can fold the setcc into the branch itself...
952 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
954 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
955 // computed some other way...
956 unsigned condReg = getReg(BI.getCondition());
957 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
958 if (RequiresFPRegKill(BI.getParent()))
959 BuildMI(BB, X86::FP_REG_KILL, 0);
960 if (BI.getSuccessor(1) == NextBB) {
961 if (BI.getSuccessor(0) != NextBB)
962 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
964 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
966 if (BI.getSuccessor(0) != NextBB)
967 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
972 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
973 MachineBasicBlock::iterator MII = BB->end();
974 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
976 const Type *CompTy = SCI->getOperand(0)->getType();
977 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
980 // LLVM -> X86 signed X86 unsigned
981 // ----- ---------- ------------
989 // js // Used by comparison with 0 optimization
992 static const unsigned OpcodeTab[2][8] = {
993 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
994 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
998 if (RequiresFPRegKill(BI.getParent()))
999 BuildMI(BB, X86::FP_REG_KILL, 0);
1000 if (BI.getSuccessor(0) != NextBB) {
1001 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1002 if (BI.getSuccessor(1) != NextBB)
1003 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1005 // Change to the inverse condition...
1006 if (BI.getSuccessor(1) != NextBB) {
1008 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1014 /// doCall - This emits an abstract call instruction, setting up the arguments
1015 /// and the return value as appropriate. For the actual function call itself,
1016 /// it inserts the specified CallMI instruction into the stream.
1018 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1019 const std::vector<ValueRecord> &Args) {
1021 // Count how many bytes are to be pushed on the stack...
1022 unsigned NumBytes = 0;
1024 if (!Args.empty()) {
1025 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1026 switch (getClassB(Args[i].Ty)) {
1027 case cByte: case cShort: case cInt:
1028 NumBytes += 4; break;
1030 NumBytes += 8; break;
1032 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1034 default: assert(0 && "Unknown class!");
1037 // Adjust the stack pointer for the new arguments...
1038 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
1040 // Arguments go on the stack in reverse order, as specified by the ABI.
1041 unsigned ArgOffset = 0;
1042 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1043 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1044 switch (getClassB(Args[i].Ty)) {
1047 // Promote arg to 32 bits wide into a temporary register...
1048 unsigned R = makeAnotherReg(Type::UIntTy);
1049 promote32(R, Args[i]);
1050 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1051 X86::ESP, ArgOffset).addReg(R);
1055 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1056 X86::ESP, ArgOffset).addReg(ArgReg);
1059 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1060 X86::ESP, ArgOffset).addReg(ArgReg);
1061 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1062 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1063 ArgOffset += 4; // 8 byte entry, not 4.
1067 if (Args[i].Ty == Type::FloatTy) {
1068 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
1069 X86::ESP, ArgOffset).addReg(ArgReg);
1071 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1072 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
1073 X86::ESP, ArgOffset).addReg(ArgReg);
1074 ArgOffset += 4; // 8 byte entry, not 4.
1078 default: assert(0 && "Unknown class!");
1083 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
1086 BB->push_back(CallMI);
1088 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
1090 // If there is a return value, scavenge the result from the location the call
1093 if (Ret.Ty != Type::VoidTy) {
1094 unsigned DestClass = getClassB(Ret.Ty);
1095 switch (DestClass) {
1099 // Integral results are in %eax, or the appropriate portion
1101 static const unsigned regRegMove[] = {
1102 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1104 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1105 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1108 case cFP: // Floating-point return values live in %ST(0)
1109 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1111 case cLong: // Long values are left in EDX:EAX
1112 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1113 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1115 default: assert(0 && "Unknown class!");
1121 /// visitCallInst - Push args on stack and do a procedure call instruction.
1122 void ISel::visitCallInst(CallInst &CI) {
1123 MachineInstr *TheCall;
1124 if (Function *F = CI.getCalledFunction()) {
1125 // Is it an intrinsic function call?
1126 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1127 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1131 // Emit a CALL instruction with PC-relative displacement.
1132 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1133 } else { // Emit an indirect call...
1134 unsigned Reg = getReg(CI.getCalledValue());
1135 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1138 std::vector<ValueRecord> Args;
1139 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1140 Args.push_back(ValueRecord(CI.getOperand(i)));
1142 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1143 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1147 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1148 /// function, lowering any calls to unknown intrinsic functions into the
1149 /// equivalent LLVM code.
1150 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1151 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1152 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1153 if (CallInst *CI = dyn_cast<CallInst>(I++))
1154 if (Function *F = CI->getCalledFunction())
1155 switch (F->getIntrinsicID()) {
1156 case Intrinsic::not_intrinsic:
1157 case Intrinsic::va_start:
1158 case Intrinsic::va_copy:
1159 case Intrinsic::va_end:
1160 // We directly implement these intrinsics
1163 // All other intrinsic calls we must lower.
1164 Instruction *Before = CI->getPrev();
1165 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1166 if (Before) { // Move iterator to instruction after call
1175 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1176 unsigned TmpReg1, TmpReg2;
1178 case Intrinsic::va_start:
1179 // Get the address of the first vararg value...
1180 TmpReg1 = getReg(CI);
1181 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1184 case Intrinsic::va_copy:
1185 TmpReg1 = getReg(CI);
1186 TmpReg2 = getReg(CI.getOperand(1));
1187 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1189 case Intrinsic::va_end: return; // Noop on X86
1191 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1196 /// visitSimpleBinary - Implement simple binary operators for integral types...
1197 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1199 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1200 unsigned DestReg = getReg(B);
1201 MachineBasicBlock::iterator MI = BB->end();
1202 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1203 OperatorClass, DestReg);
1206 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1207 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1210 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1211 /// and constant expression support.
1213 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1214 MachineBasicBlock::iterator &IP,
1215 Value *Op0, Value *Op1,
1216 unsigned OperatorClass, unsigned DestReg) {
1217 unsigned Class = getClassB(Op0->getType());
1219 // sub 0, X -> neg X
1220 if (OperatorClass == 1 && Class != cLong)
1221 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1222 if (CI->isNullValue()) {
1223 unsigned op1Reg = getReg(Op1, MBB, IP);
1225 default: assert(0 && "Unknown class for this function!");
1227 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1230 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1233 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1237 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1238 if (CFP->isExactlyValue(-0.0)) {
1240 unsigned op1Reg = getReg(Op1, MBB, IP);
1241 BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1245 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1246 static const unsigned OpcodeTab[][4] = {
1247 // Arithmetic operators
1248 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1249 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1251 // Bitwise operators
1252 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1253 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1254 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1257 bool isLong = false;
1258 if (Class == cLong) {
1260 Class = cInt; // Bottom 32 bits are handled just like ints
1263 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1264 assert(Opcode && "Floating point arguments to logical inst?");
1265 unsigned Op0r = getReg(Op0, MBB, IP);
1266 unsigned Op1r = getReg(Op1, MBB, IP);
1267 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1269 if (isLong) { // Handle the upper 32 bits of long values...
1270 static const unsigned TopTab[] = {
1271 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1273 BMI(MBB, IP, TopTab[OperatorClass], 2,
1274 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1279 // Special case: op Reg, <const>
1280 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1281 unsigned Op0r = getReg(Op0, MBB, IP);
1283 // xor X, -1 -> not X
1284 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1285 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1286 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1290 // add X, -1 -> dec X
1291 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1292 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1293 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1297 // add X, 1 -> inc X
1298 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1299 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1300 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1304 static const unsigned OpcodeTab[][3] = {
1305 // Arithmetic operators
1306 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1307 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1309 // Bitwise operators
1310 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1311 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1312 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1315 assert(Class < 3 && "General code handles 64-bit integer types!");
1316 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1317 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1319 // Mask off any upper bits of the constant, if there are any...
1320 Op1v &= (1ULL << (8 << Class)) - 1;
1321 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1324 /// doMultiply - Emit appropriate instructions to multiply together the
1325 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1326 /// result should be given as DestTy.
1328 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1329 unsigned DestReg, const Type *DestTy,
1330 unsigned op0Reg, unsigned op1Reg) {
1331 unsigned Class = getClass(DestTy);
1333 case cFP: // Floating point multiply
1334 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1338 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1339 .addReg(op0Reg).addReg(op1Reg);
1342 // Must use the MUL instruction, which forces use of AL...
1343 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1344 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1345 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1348 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1352 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1353 // returns zero when the input is not exactly a power of two.
1354 static unsigned ExactLog2(unsigned Val) {
1355 if (Val == 0) return 0;
1358 if (Val & 1) return 0;
1365 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1366 MachineBasicBlock::iterator &IP,
1367 unsigned DestReg, const Type *DestTy,
1368 unsigned op0Reg, unsigned ConstRHS) {
1369 unsigned Class = getClass(DestTy);
1371 // If the element size is exactly a power of 2, use a shift to get it.
1372 if (unsigned Shift = ExactLog2(ConstRHS)) {
1374 default: assert(0 && "Unknown class for this function!");
1376 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1379 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1382 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1387 if (Class == cShort) {
1388 BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1390 } else if (Class == cInt) {
1391 BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1395 // Most general case, emit a normal multiply...
1396 static const unsigned MOVirTab[] = {
1397 X86::MOVir8, X86::MOVir16, X86::MOVir32
1400 unsigned TmpReg = makeAnotherReg(DestTy);
1401 BMI(MBB, IP, MOVirTab[Class], 1, TmpReg).addZImm(ConstRHS);
1403 // Emit a MUL to multiply the register holding the index by
1404 // elementSize, putting the result in OffsetReg.
1405 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1408 /// visitMul - Multiplies are not simple binary operators because they must deal
1409 /// with the EAX register explicitly.
1411 void ISel::visitMul(BinaryOperator &I) {
1412 unsigned Op0Reg = getReg(I.getOperand(0));
1413 unsigned DestReg = getReg(I);
1415 // Simple scalar multiply?
1416 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1417 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1418 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1419 MachineBasicBlock::iterator MBBI = BB->end();
1420 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1422 unsigned Op1Reg = getReg(I.getOperand(1));
1423 MachineBasicBlock::iterator MBBI = BB->end();
1424 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1427 unsigned Op1Reg = getReg(I.getOperand(1));
1429 // Long value. We have to do things the hard way...
1430 // Multiply the two low parts... capturing carry into EDX
1431 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1432 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1434 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1435 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1436 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1438 MachineBasicBlock::iterator MBBI = BB->end();
1439 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1440 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1442 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1443 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1444 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1447 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1448 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1450 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1451 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1456 /// visitDivRem - Handle division and remainder instructions... these
1457 /// instruction both require the same instructions to be generated, they just
1458 /// select the result from a different register. Note that both of these
1459 /// instructions work differently for signed and unsigned operands.
1461 void ISel::visitDivRem(BinaryOperator &I) {
1462 unsigned Op0Reg = getReg(I.getOperand(0));
1463 unsigned Op1Reg = getReg(I.getOperand(1));
1464 unsigned ResultReg = getReg(I);
1466 MachineBasicBlock::iterator IP = BB->end();
1467 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1468 I.getType(), ResultReg);
1471 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1472 MachineBasicBlock::iterator &IP,
1473 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1474 const Type *Ty, unsigned ResultReg) {
1475 unsigned Class = getClass(Ty);
1477 case cFP: // Floating point divide
1479 BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1480 } else { // Floating point remainder...
1481 MachineInstr *TheCall =
1482 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1483 std::vector<ValueRecord> Args;
1484 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1485 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1486 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1490 static const char *FnName[] =
1491 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1493 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1494 MachineInstr *TheCall =
1495 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1497 std::vector<ValueRecord> Args;
1498 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1499 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1500 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1503 case cByte: case cShort: case cInt:
1504 break; // Small integrals, handled below...
1505 default: assert(0 && "Unknown class!");
1508 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1509 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1510 static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
1511 static const unsigned ClrOpcode[]={ X86::MOVir8, X86::MOVir16, X86::MOVir32 };
1512 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1514 static const unsigned DivOpcode[][4] = {
1515 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1516 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1519 bool isSigned = Ty->isSigned();
1520 unsigned Reg = Regs[Class];
1521 unsigned ExtReg = ExtRegs[Class];
1523 // Put the first operand into one of the A registers...
1524 BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1527 // Emit a sign extension instruction...
1528 unsigned ShiftResult = makeAnotherReg(Ty);
1529 BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1530 BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1532 // If unsigned, emit a zeroing instruction... (reg = 0)
1533 BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0);
1536 // Emit the appropriate divide or remainder instruction...
1537 BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1539 // Figure out which register we want to pick the result out of...
1540 unsigned DestReg = isDiv ? Reg : ExtReg;
1542 // Put the result into the destination register...
1543 BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1547 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1548 /// for constant immediate shift values, and for constant immediate
1549 /// shift values equal to 1. Even the general case is sort of special,
1550 /// because the shift amount has to be in CL, not just any old register.
1552 void ISel::visitShiftInst(ShiftInst &I) {
1553 MachineBasicBlock::iterator IP = BB->end ();
1554 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1555 I.getOpcode () == Instruction::Shl, I.getType (),
1559 /// emitShiftOperation - Common code shared between visitShiftInst and
1560 /// constant expression support.
1561 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1562 MachineBasicBlock::iterator &IP,
1563 Value *Op, Value *ShiftAmount, bool isLeftShift,
1564 const Type *ResultTy, unsigned DestReg) {
1565 unsigned SrcReg = getReg (Op, MBB, IP);
1566 bool isSigned = ResultTy->isSigned ();
1567 unsigned Class = getClass (ResultTy);
1569 static const unsigned ConstantOperand[][4] = {
1570 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1571 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1572 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1573 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1576 static const unsigned NonConstantOperand[][4] = {
1577 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1578 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1579 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1580 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1583 // Longs, as usual, are handled specially...
1584 if (Class == cLong) {
1585 // If we have a constant shift, we can generate much more efficient code
1586 // than otherwise...
1588 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1589 unsigned Amount = CUI->getValue();
1591 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1593 BMI(MBB, IP, Opc[3], 3,
1594 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1595 BMI(MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1597 BMI(MBB, IP, Opc[3], 3,
1598 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1599 BMI(MBB, IP, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1601 } else { // Shifting more than 32 bits
1604 BMI(MBB, IP, X86::SHLir32, 2,
1605 DestReg + 1).addReg(SrcReg).addZImm(Amount);
1606 BMI(MBB, IP, X86::MOVir32, 1,
1607 DestReg).addZImm(0);
1609 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1610 BMI(MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1611 BMI(MBB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1615 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1617 if (!isLeftShift && isSigned) {
1618 // If this is a SHR of a Long, then we need to do funny sign extension
1619 // stuff. TmpReg gets the value to use as the high-part if we are
1620 // shifting more than 32 bits.
1621 BMI(MBB, IP, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1623 // Other shifts use a fixed zero value if the shift is more than 32
1625 BMI(MBB, IP, X86::MOVir32, 1, TmpReg).addZImm(0);
1628 // Initialize CL with the shift amount...
1629 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
1630 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1632 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1633 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1635 // TmpReg2 = shld inHi, inLo
1636 BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1637 // TmpReg3 = shl inLo, CL
1638 BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1640 // Set the flags to indicate whether the shift was by more than 32 bits.
1641 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1643 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1644 BMI(MBB, IP, X86::CMOVNErr32, 2,
1645 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1646 // DestLo = (>32) ? TmpReg : TmpReg3;
1647 BMI(MBB, IP, X86::CMOVNErr32, 2,
1648 DestReg).addReg(TmpReg3).addReg(TmpReg);
1650 // TmpReg2 = shrd inLo, inHi
1651 BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1652 // TmpReg3 = s[ah]r inHi, CL
1653 BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1656 // Set the flags to indicate whether the shift was by more than 32 bits.
1657 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1659 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1660 BMI(MBB, IP, X86::CMOVNErr32, 2,
1661 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1663 // DestHi = (>32) ? TmpReg : TmpReg3;
1664 BMI(MBB, IP, X86::CMOVNErr32, 2,
1665 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1671 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1672 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1673 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1675 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1676 BMI(MBB, IP, Opc[Class], 2,
1677 DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1678 } else { // The shift amount is non-constant.
1679 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
1680 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1682 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1683 BMI(MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
1688 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1689 /// instruction. The load and store instructions are the only place where we
1690 /// need to worry about the memory layout of the target machine.
1692 void ISel::visitLoadInst(LoadInst &I) {
1693 unsigned SrcAddrReg = getReg(I.getOperand(0));
1694 unsigned DestReg = getReg(I);
1696 unsigned Class = getClassB(I.getType());
1698 if (Class == cLong) {
1699 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), SrcAddrReg);
1700 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1704 static const unsigned Opcodes[] = {
1705 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr32
1707 unsigned Opcode = Opcodes[Class];
1708 if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
1709 addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
1712 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1715 void ISel::visitStoreInst(StoreInst &I) {
1716 unsigned ValReg = getReg(I.getOperand(0));
1717 unsigned AddressReg = getReg(I.getOperand(1));
1719 const Type *ValTy = I.getOperand(0)->getType();
1720 unsigned Class = getClassB(ValTy);
1722 if (Class == cLong) {
1723 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1724 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
1728 static const unsigned Opcodes[] = {
1729 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTr32
1731 unsigned Opcode = Opcodes[Class];
1732 if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
1733 addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
1737 /// visitCastInst - Here we have various kinds of copying with or without
1738 /// sign extension going on.
1739 void ISel::visitCastInst(CastInst &CI) {
1740 Value *Op = CI.getOperand(0);
1741 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1742 // of the case are GEP instructions, then the cast does not need to be
1743 // generated explicitly, it will be folded into the GEP.
1744 if (CI.getType() == Type::LongTy &&
1745 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1746 bool AllUsesAreGEPs = true;
1747 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1748 if (!isa<GetElementPtrInst>(*I)) {
1749 AllUsesAreGEPs = false;
1753 // No need to codegen this cast if all users are getelementptr instrs...
1754 if (AllUsesAreGEPs) return;
1757 unsigned DestReg = getReg(CI);
1758 MachineBasicBlock::iterator MI = BB->end();
1759 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1762 /// emitCastOperation - Common code shared between visitCastInst and
1763 /// constant expression cast support.
1764 void ISel::emitCastOperation(MachineBasicBlock *BB,
1765 MachineBasicBlock::iterator &IP,
1766 Value *Src, const Type *DestTy,
1768 unsigned SrcReg = getReg(Src, BB, IP);
1769 const Type *SrcTy = Src->getType();
1770 unsigned SrcClass = getClassB(SrcTy);
1771 unsigned DestClass = getClassB(DestTy);
1773 // Implement casts to bool by using compare on the operand followed by set if
1774 // not zero on the result.
1775 if (DestTy == Type::BoolTy) {
1778 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1781 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1784 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1787 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1788 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1792 assert(0 && "FIXME: implement cast FP to bool");
1796 // If the zero flag is not set, then the value is true, set the byte to
1798 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1802 static const unsigned RegRegMove[] = {
1803 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1806 // Implement casts between values of the same type class (as determined by
1807 // getClass) by using a register-to-register move.
1808 if (SrcClass == DestClass) {
1809 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1810 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1811 } else if (SrcClass == cFP) {
1812 if (SrcTy == Type::FloatTy) { // double -> float
1813 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1814 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1815 } else { // float -> double
1816 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1817 "Unknown cFP member!");
1818 // Truncate from double to float by storing to memory as short, then
1820 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1821 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1822 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1823 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1825 } else if (SrcClass == cLong) {
1826 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1827 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1829 assert(0 && "Cannot handle this type of cast instruction!");
1835 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1836 // or zero extension, depending on whether the source type was signed.
1837 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1838 SrcClass < DestClass) {
1839 bool isLong = DestClass == cLong;
1840 if (isLong) DestClass = cInt;
1842 static const unsigned Opc[][4] = {
1843 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1844 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1847 bool isUnsigned = SrcTy->isUnsigned();
1848 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1849 DestReg).addReg(SrcReg);
1851 if (isLong) { // Handle upper 32 bits as appropriate...
1852 if (isUnsigned) // Zero out top bits...
1853 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1854 else // Sign extend bottom half...
1855 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1860 // Special case long -> int ...
1861 if (SrcClass == cLong && DestClass == cInt) {
1862 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1866 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1867 // move out of AX or AL.
1868 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1869 && SrcClass > DestClass) {
1870 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1871 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1872 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1876 // Handle casts from integer to floating point now...
1877 if (DestClass == cFP) {
1878 // Promote the integer to a type supported by FLD. We do this because there
1879 // are no unsigned FLD instructions, so we must promote an unsigned value to
1880 // a larger signed value, then use FLD on the larger value.
1882 const Type *PromoteType = 0;
1883 unsigned PromoteOpcode;
1884 switch (SrcTy->getPrimitiveID()) {
1885 case Type::BoolTyID:
1886 case Type::SByteTyID:
1887 // We don't have the facilities for directly loading byte sized data from
1888 // memory (even signed). Promote it to 16 bits.
1889 PromoteType = Type::ShortTy;
1890 PromoteOpcode = X86::MOVSXr16r8;
1892 case Type::UByteTyID:
1893 PromoteType = Type::ShortTy;
1894 PromoteOpcode = X86::MOVZXr16r8;
1896 case Type::UShortTyID:
1897 PromoteType = Type::IntTy;
1898 PromoteOpcode = X86::MOVZXr32r16;
1900 case Type::UIntTyID: {
1901 // Make a 64 bit temporary... and zero out the top of it...
1902 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1903 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1904 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1905 SrcTy = Type::LongTy;
1910 case Type::ULongTyID:
1911 assert("FIXME: not implemented: cast ulong X to fp type!");
1912 default: // No promotion needed...
1917 unsigned TmpReg = makeAnotherReg(PromoteType);
1918 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1919 1, TmpReg).addReg(SrcReg);
1920 SrcTy = PromoteType;
1921 SrcClass = getClass(PromoteType);
1925 // Spill the integer to memory and reload it from there...
1927 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1929 if (SrcClass == cLong) {
1930 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1931 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1932 FrameIdx, 4).addReg(SrcReg+1);
1934 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1935 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1938 static const unsigned Op2[] =
1939 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1940 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1944 // Handle casts from floating point to integer now...
1945 if (SrcClass == cFP) {
1946 // Change the floating point control register to use "round towards zero"
1947 // mode when truncating to an integer value.
1949 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1950 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1952 // Load the old value of the high byte of the control word...
1953 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1954 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1956 // Set the high part to be round to zero...
1957 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1959 // Reload the modified control word now...
1960 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1962 // Restore the memory image of control word to original value
1963 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1964 CWFrameIdx, 1).addReg(HighPartOfCW);
1966 // We don't have the facilities for directly storing byte sized data to
1967 // memory. Promote it to 16 bits. We also must promote unsigned values to
1968 // larger classes because we only have signed FP stores.
1969 unsigned StoreClass = DestClass;
1970 const Type *StoreTy = DestTy;
1971 if (StoreClass == cByte || DestTy->isUnsigned())
1972 switch (StoreClass) {
1973 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1974 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1975 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1976 // The following treatment of cLong may not be perfectly right,
1977 // but it survives chains of casts of the form
1978 // double->ulong->double.
1979 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
1980 default: assert(0 && "Unknown store class!");
1983 // Spill the integer to memory and reload it from there...
1985 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1987 static const unsigned Op1[] =
1988 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1989 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1991 if (DestClass == cLong) {
1992 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1993 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1995 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1996 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1999 // Reload the original control word now...
2000 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2004 // Anything we haven't handled already, we can't (yet) handle at all.
2005 assert(0 && "Unhandled cast instruction!");
2009 /// visitVANextInst - Implement the va_next instruction...
2011 void ISel::visitVANextInst(VANextInst &I) {
2012 unsigned VAList = getReg(I.getOperand(0));
2013 unsigned DestReg = getReg(I);
2016 switch (I.getArgType()->getPrimitiveID()) {
2019 assert(0 && "Error: bad type for va_next instruction!");
2021 case Type::PointerTyID:
2022 case Type::UIntTyID:
2026 case Type::ULongTyID:
2027 case Type::LongTyID:
2028 case Type::DoubleTyID:
2033 // Increment the VAList pointer...
2034 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
2037 void ISel::visitVAArgInst(VAArgInst &I) {
2038 unsigned VAList = getReg(I.getOperand(0));
2039 unsigned DestReg = getReg(I);
2041 switch (I.getType()->getPrimitiveID()) {
2044 assert(0 && "Error: bad type for va_next instruction!");
2046 case Type::PointerTyID:
2047 case Type::UIntTyID:
2049 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
2051 case Type::ULongTyID:
2052 case Type::LongTyID:
2053 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
2054 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
2056 case Type::DoubleTyID:
2057 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
2063 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2064 unsigned outputReg = getReg(I);
2065 MachineBasicBlock::iterator MI = BB->end();
2066 emitGEPOperation(BB, MI, I.getOperand(0),
2067 I.op_begin()+1, I.op_end(), outputReg);
2070 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2071 MachineBasicBlock::iterator &IP,
2072 Value *Src, User::op_iterator IdxBegin,
2073 User::op_iterator IdxEnd, unsigned TargetReg) {
2074 const TargetData &TD = TM.getTargetData();
2075 const Type *Ty = Src->getType();
2076 unsigned BaseReg = getReg(Src, MBB, IP);
2078 // GEPs have zero or more indices; we must perform a struct access
2079 // or array access for each one.
2080 for (GetElementPtrInst::op_iterator oi = IdxBegin,
2081 oe = IdxEnd; oi != oe; ++oi) {
2083 unsigned NextReg = BaseReg;
2084 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2085 // It's a struct access. idx is the index into the structure,
2086 // which names the field. This index must have ubyte type.
2087 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
2088 assert(CUI->getType() == Type::UByteTy
2089 && "Funny-looking structure index in GEP");
2090 // Use the TargetData structure to pick out what the layout of
2091 // the structure is in memory. Since the structure index must
2092 // be constant, we can get its value and use it to find the
2093 // right byte offset from the StructLayout class's list of
2094 // structure member offsets.
2095 unsigned idxValue = CUI->getValue();
2096 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
2098 NextReg = makeAnotherReg(Type::UIntTy);
2099 // Emit an ADD to add FieldOff to the basePtr.
2100 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
2102 // The next type is the member of the structure selected by the
2104 Ty = StTy->getElementType(idxValue);
2105 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
2106 // It's an array or pointer access: [ArraySize x ElementType].
2108 // idx is the index into the array. Unlike with structure
2109 // indices, we may not know its actual value at code-generation
2111 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2113 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2114 // operand on X86. Handle this case directly now...
2115 if (CastInst *CI = dyn_cast<CastInst>(idx))
2116 if (CI->getOperand(0)->getType() == Type::IntTy ||
2117 CI->getOperand(0)->getType() == Type::UIntTy)
2118 idx = CI->getOperand(0);
2120 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2121 // must find the size of the pointed-to type (Not coincidentally, the next
2122 // type is the type of the elements in the array).
2123 Ty = SqTy->getElementType();
2124 unsigned elementSize = TD.getTypeSize(Ty);
2126 // If idxReg is a constant, we don't need to perform the multiply!
2127 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2128 if (!CSI->isNullValue()) {
2129 unsigned Offset = elementSize*CSI->getValue();
2130 NextReg = makeAnotherReg(Type::UIntTy);
2131 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
2133 } else if (elementSize == 1) {
2134 // If the element size is 1, we don't have to multiply, just add
2135 unsigned idxReg = getReg(idx, MBB, IP);
2136 NextReg = makeAnotherReg(Type::UIntTy);
2137 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
2139 unsigned idxReg = getReg(idx, MBB, IP);
2140 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2142 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2144 // Emit an ADD to add OffsetReg to the basePtr.
2145 NextReg = makeAnotherReg(Type::UIntTy);
2146 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
2149 // Now that we are here, further indices refer to subtypes of this
2150 // one, so we don't need to worry about BaseReg itself, anymore.
2153 // After we have processed all the indices, the result is left in
2154 // BaseReg. Move it to the register where we were expected to
2155 // put the answer. A 32-bit move should do it, because we are in
2157 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2161 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2162 /// frame manager, otherwise do it the hard way.
2164 void ISel::visitAllocaInst(AllocaInst &I) {
2165 // Find the data size of the alloca inst's getAllocatedType.
2166 const Type *Ty = I.getAllocatedType();
2167 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2169 // If this is a fixed size alloca in the entry block for the function,
2170 // statically stack allocate the space.
2172 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2173 if (I.getParent() == I.getParent()->getParent()->begin()) {
2174 TySize *= CUI->getValue(); // Get total allocated size...
2175 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2177 // Create a new stack object using the frame manager...
2178 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2179 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2184 // Create a register to hold the temporary result of multiplying the type size
2185 // constant by the variable amount.
2186 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2187 unsigned SrcReg1 = getReg(I.getArraySize());
2189 // TotalSizeReg = mul <numelements>, <TypeSize>
2190 MachineBasicBlock::iterator MBBI = BB->end();
2191 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2193 // AddedSize = add <TotalSizeReg>, 15
2194 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2195 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2197 // AlignedSize = and <AddedSize>, ~15
2198 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2199 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2201 // Subtract size from stack pointer, thereby allocating some space.
2202 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2204 // Put a pointer to the space into the result register, by copying
2205 // the stack pointer.
2206 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2208 // Inform the Frame Information that we have just allocated a variable-sized
2210 F->getFrameInfo()->CreateVariableSizedObject();
2213 /// visitMallocInst - Malloc instructions are code generated into direct calls
2214 /// to the library malloc.
2216 void ISel::visitMallocInst(MallocInst &I) {
2217 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2220 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2221 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2223 Arg = makeAnotherReg(Type::UIntTy);
2224 unsigned Op0Reg = getReg(I.getOperand(0));
2225 MachineBasicBlock::iterator MBBI = BB->end();
2226 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2229 std::vector<ValueRecord> Args;
2230 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2231 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2232 1).addExternalSymbol("malloc", true);
2233 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2237 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2240 void ISel::visitFreeInst(FreeInst &I) {
2241 std::vector<ValueRecord> Args;
2242 Args.push_back(ValueRecord(I.getOperand(0)));
2243 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2244 1).addExternalSymbol("free", true);
2245 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2248 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2249 /// into a machine code representation is a very simple peep-hole fashion. The
2250 /// generated code sucks but the implementation is nice and simple.
2252 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
2253 return new ISel(TM);