1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 target
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/InstVisitor.h"
27 #include "llvm/Target/MRegisterInfo.h"
30 /// BMI - A special BuildMI variant that takes an iterator to insert the
31 /// instruction at as well as a basic block. This is the version for when you
32 /// have a destination register in mind.
33 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
34 MachineBasicBlock::iterator &I,
38 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
39 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
40 I = MBB->insert(I, MI)+1;
41 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
44 /// BMI - A special BuildMI variant that takes an iterator to insert the
45 /// instruction at as well as a basic block.
46 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
47 MachineBasicBlock::iterator &I,
49 unsigned NumOperands) {
50 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
51 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
52 I = MBB->insert(I, MI)+1;
53 return MachineInstrBuilder(MI);
58 struct ISel : public FunctionPass, InstVisitor<ISel> {
60 MachineFunction *F; // The function we are compiling into
61 MachineBasicBlock *BB; // The current MBB we are compiling
63 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
65 // MBBMap - Mapping between LLVM BB -> Machine BB
66 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
68 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
70 /// runOnFunction - Top level implementation of instruction selection for
71 /// the entire function.
73 bool runOnFunction(Function &Fn) {
74 F = &MachineFunction::construct(&Fn, TM);
76 // Create all of the machine basic blocks for the function...
77 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
78 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
82 // Declare that the stack pointer is live on entrance to the function
83 BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::ESP);
85 // Copy incoming arguments off of the stack...
86 LoadArgumentsToVirtualRegs(Fn);
88 // Instruction select everything except PHI nodes
91 // Select the PHI nodes
97 return false; // We never modify the LLVM itself.
100 virtual const char *getPassName() const {
101 return "X86 Simple Instruction Selection";
104 /// visitBasicBlock - This method is called when we are visiting a new basic
105 /// block. This simply creates a new MachineBasicBlock to emit code into
106 /// and adds it to the current MachineFunction. Subsequent visit* for
107 /// instructions will be invoked for all instructions in the basic block.
109 void visitBasicBlock(BasicBlock &LLVM_BB) {
110 BB = MBBMap[&LLVM_BB];
113 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
114 /// from the stack into virtual registers.
116 void LoadArgumentsToVirtualRegs(Function &F);
118 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
119 /// because we have to generate our sources into the source basic blocks,
120 /// not the current one.
122 void SelectPHINodes();
124 // Visitation methods for various instructions. These methods simply emit
125 // fixed X86 code for each instruction.
128 // Control flow operators
129 void visitReturnInst(ReturnInst &RI);
130 void visitBranchInst(BranchInst &BI);
135 ValueRecord(unsigned R, const Type *T) : Reg(R), Ty(T) {}
137 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
138 const std::vector<ValueRecord> &Args);
139 void visitCallInst(CallInst &I);
141 // Arithmetic operators
142 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
143 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
144 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
145 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
146 unsigned DestReg, const Type *DestTy,
147 unsigned Op0Reg, unsigned Op1Reg);
148 void visitMul(BinaryOperator &B);
150 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
151 void visitRem(BinaryOperator &B) { visitDivRem(B); }
152 void visitDivRem(BinaryOperator &B);
155 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
156 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
157 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
159 // Comparison operators...
160 void visitSetCondInst(SetCondInst &I);
161 bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
163 // Memory Instructions
164 MachineInstr *doFPLoad(MachineBasicBlock *MBB,
165 MachineBasicBlock::iterator &MBBI,
166 const Type *Ty, unsigned DestReg);
167 void visitLoadInst(LoadInst &I);
168 void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg);
169 void visitStoreInst(StoreInst &I);
170 void visitGetElementPtrInst(GetElementPtrInst &I);
171 void visitAllocaInst(AllocaInst &I);
172 void visitMallocInst(MallocInst &I);
173 void visitFreeInst(FreeInst &I);
176 void visitShiftInst(ShiftInst &I);
177 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
178 void visitCastInst(CastInst &I);
180 void visitInstruction(Instruction &I) {
181 std::cerr << "Cannot instruction select: " << I;
185 /// promote32 - Make a value 32-bits wide, and put it somewhere.
187 void promote32(unsigned targetReg, const ValueRecord &VR);
189 /// EmitByteSwap - Byteswap SrcReg into DestReg.
191 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
193 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
194 /// constant expression GEP support.
196 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
197 Value *Src, User::op_iterator IdxBegin,
198 User::op_iterator IdxEnd, unsigned TargetReg);
200 /// emitCastOperation - Common code shared between visitCastInst and
201 /// constant expression cast support.
202 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
203 Value *Src, const Type *DestTy, unsigned TargetReg);
205 /// copyConstantToRegister - Output the instructions required to put the
206 /// specified constant into the specified register.
208 void copyConstantToRegister(MachineBasicBlock *MBB,
209 MachineBasicBlock::iterator &MBBI,
210 Constant *C, unsigned Reg);
212 /// makeAnotherReg - This method returns the next register number we haven't
215 /// Long values are handled somewhat specially. They are always allocated
216 /// as pairs of 32 bit integer values. The register number returned is the
217 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
218 /// of the long value.
220 unsigned makeAnotherReg(const Type *Ty) {
221 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
222 const TargetRegisterClass *RC =
223 TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
224 // Create the lower part
225 F->getSSARegMap()->createVirtualRegister(RC);
226 // Create the upper part.
227 return F->getSSARegMap()->createVirtualRegister(RC)-1;
230 // Add the mapping of regnumber => reg class to MachineFunction
231 const TargetRegisterClass *RC =
232 TM.getRegisterInfo()->getRegClassForType(Ty);
233 return F->getSSARegMap()->createVirtualRegister(RC);
236 /// getReg - This method turns an LLVM value into a register number. This
237 /// is guaranteed to produce the same register number for a particular value
238 /// every time it is queried.
240 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
241 unsigned getReg(Value *V) {
242 // Just append to the end of the current bb.
243 MachineBasicBlock::iterator It = BB->end();
244 return getReg(V, BB, It);
246 unsigned getReg(Value *V, MachineBasicBlock *MBB,
247 MachineBasicBlock::iterator &IPt) {
248 unsigned &Reg = RegMap[V];
250 Reg = makeAnotherReg(V->getType());
254 // If this operand is a constant, emit the code to copy the constant into
255 // the register here...
257 if (Constant *C = dyn_cast<Constant>(V)) {
258 copyConstantToRegister(MBB, IPt, C, Reg);
259 RegMap.erase(V); // Assign a new name to this constant if ref'd again
260 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
261 // Move the address of the global into the register
262 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
263 RegMap.erase(V); // Assign a new name to this address if ref'd again
271 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
275 cByte, cShort, cInt, cFP, cLong
278 /// getClass - Turn a primitive type into a "class" number which is based on the
279 /// size of the type, and whether or not it is floating point.
281 static inline TypeClass getClass(const Type *Ty) {
282 switch (Ty->getPrimitiveID()) {
283 case Type::SByteTyID:
284 case Type::UByteTyID: return cByte; // Byte operands are class #0
285 case Type::ShortTyID:
286 case Type::UShortTyID: return cShort; // Short operands are class #1
289 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
291 case Type::FloatTyID:
292 case Type::DoubleTyID: return cFP; // Floating Point is #3
295 case Type::ULongTyID: return cLong; // Longs are class #4
297 assert(0 && "Invalid type to getClass!");
298 return cByte; // not reached
302 // getClassB - Just like getClass, but treat boolean values as bytes.
303 static inline TypeClass getClassB(const Type *Ty) {
304 if (Ty == Type::BoolTy) return cByte;
309 /// copyConstantToRegister - Output the instructions required to put the
310 /// specified constant into the specified register.
312 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
313 MachineBasicBlock::iterator &IP,
314 Constant *C, unsigned R) {
315 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
316 if (CE->getOpcode() == Instruction::GetElementPtr) {
317 emitGEPOperation(MBB, IP, CE->getOperand(0),
318 CE->op_begin()+1, CE->op_end(), R);
320 } else if (CE->getOpcode() == Instruction::Cast) {
321 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
325 std::cerr << "Offending expr: " << C << "\n";
326 assert(0 && "Constant expressions not yet handled!\n");
329 if (C->getType()->isIntegral()) {
330 unsigned Class = getClassB(C->getType());
332 if (Class == cLong) {
333 // Copy the value into the register pair.
335 if (C->getType()->isSigned())
336 Val = cast<ConstantSInt>(C)->getValue();
338 Val = cast<ConstantUInt>(C)->getValue();
340 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
341 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
345 assert(Class <= cInt && "Type not handled yet!");
347 static const unsigned IntegralOpcodeTab[] = {
348 X86::MOVir8, X86::MOVir16, X86::MOVir32
351 if (C->getType() == Type::BoolTy) {
352 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
353 } else if (C->getType()->isSigned()) {
354 ConstantSInt *CSI = cast<ConstantSInt>(C);
355 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CSI->getValue());
357 ConstantUInt *CUI = cast<ConstantUInt>(C);
358 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
360 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
361 double Value = CFP->getValue();
363 BMI(MBB, IP, X86::FLD0, 0, R);
364 else if (Value == +1.0)
365 BMI(MBB, IP, X86::FLD1, 0, R);
367 // Otherwise we need to spill the constant to memory...
368 MachineConstantPool *CP = F->getConstantPool();
369 unsigned CPI = CP->getConstantPoolIndex(CFP);
370 addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI);
373 } else if (isa<ConstantPointerNull>(C)) {
374 // Copy zero (null pointer) to the register.
375 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
376 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
377 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
378 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
380 std::cerr << "Offending constant: " << C << "\n";
381 assert(0 && "Type not handled yet!");
385 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
386 /// the stack into virtual registers.
388 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
389 // Emit instructions to load the arguments... On entry to a function on the
390 // X86, the stack frame looks like this:
392 // [ESP] -- return address
393 // [ESP + 4] -- first argument (leftmost lexically)
394 // [ESP + 8] -- second argument, if first argument is four bytes in size
397 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
398 MachineFrameInfo *MFI = F->getFrameInfo();
400 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
401 unsigned Reg = getReg(*I);
403 int FI; // Frame object index
404 switch (getClassB(I->getType())) {
406 FI = MFI->CreateFixedObject(1, ArgOffset);
407 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
410 FI = MFI->CreateFixedObject(2, ArgOffset);
411 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
414 FI = MFI->CreateFixedObject(4, ArgOffset);
415 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
418 FI = MFI->CreateFixedObject(8, ArgOffset);
419 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
420 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
421 ArgOffset += 4; // longs require 4 additional bytes
425 if (I->getType() == Type::FloatTy) {
426 Opcode = X86::FLDr32;
427 FI = MFI->CreateFixedObject(4, ArgOffset);
429 Opcode = X86::FLDr64;
430 FI = MFI->CreateFixedObject(8, ArgOffset);
431 ArgOffset += 4; // doubles require 4 additional bytes
433 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
436 assert(0 && "Unhandled argument type!");
438 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
443 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
444 /// because we have to generate our sources into the source basic blocks, not
447 void ISel::SelectPHINodes() {
448 const TargetInstrInfo &TII = TM.getInstrInfo();
449 const Function &LF = *F->getFunction(); // The LLVM function...
450 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
451 const BasicBlock *BB = I;
452 MachineBasicBlock *MBB = MBBMap[I];
454 // Loop over all of the PHI nodes in the LLVM basic block...
455 unsigned NumPHIs = 0;
456 for (BasicBlock::const_iterator I = BB->begin();
457 PHINode *PN = (PHINode*)dyn_cast<PHINode>(I); ++I) {
459 // Create a new machine instr PHI node, and insert it.
460 unsigned PHIReg = getReg(*PN);
461 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
462 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
464 MachineInstr *LongPhiMI = 0;
465 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
466 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
467 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
470 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
471 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
473 // Get the incoming value into a virtual register. If it is not already
474 // available in a virtual register, insert the computation code into
477 MachineBasicBlock::iterator PI = PredMBB->end();
478 while (PI != PredMBB->begin() &&
479 TII.isTerminatorInstr((*(PI-1))->getOpcode()))
481 unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
482 PhiMI->addRegOperand(ValReg);
483 PhiMI->addMachineBasicBlockOperand(PredMBB);
485 LongPhiMI->addRegOperand(ValReg+1);
486 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
493 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
494 // the conditional branch instruction which is the only user of the cc
495 // instruction. This is the case if the conditional branch is the only user of
496 // the setcc, and if the setcc is in the same basic block as the conditional
497 // branch. We also don't handle long arguments below, so we reject them here as
500 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
501 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
502 if (SCI->use_size() == 1 && isa<BranchInst>(SCI->use_back()) &&
503 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
504 const Type *Ty = SCI->getOperand(0)->getType();
505 if (Ty != Type::LongTy && Ty != Type::ULongTy)
511 // Return a fixed numbering for setcc instructions which does not depend on the
512 // order of the opcodes.
514 static unsigned getSetCCNumber(unsigned Opcode) {
516 default: assert(0 && "Unknown setcc instruction!");
517 case Instruction::SetEQ: return 0;
518 case Instruction::SetNE: return 1;
519 case Instruction::SetLT: return 2;
520 case Instruction::SetGE: return 3;
521 case Instruction::SetGT: return 4;
522 case Instruction::SetLE: return 5;
526 // LLVM -> X86 signed X86 unsigned
527 // ----- ---------- ------------
528 // seteq -> sete sete
529 // setne -> setne setne
530 // setlt -> setl setb
531 // setge -> setge setae
532 // setgt -> setg seta
533 // setle -> setle setbe
534 static const unsigned SetCCOpcodeTab[2][6] = {
535 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
536 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
539 bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
541 // The arguments are already supposed to be of the same type.
542 const Type *CompTy = Op0->getType();
543 bool isSigned = CompTy->isSigned();
544 unsigned reg1 = getReg(Op0);
545 unsigned reg2 = getReg(Op1);
547 unsigned Class = getClassB(CompTy);
549 default: assert(0 && "Unknown type class!");
550 // Emit: cmp <var1>, <var2> (do the comparison). We can
551 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
554 BuildMI(BB, X86::CMPrr8, 2).addReg(reg1).addReg(reg2);
557 BuildMI(BB, X86::CMPrr16, 2).addReg(reg1).addReg(reg2);
560 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
563 BuildMI(BB, X86::FpUCOM, 2).addReg(reg1).addReg(reg2);
564 BuildMI(BB, X86::FNSTSWr8, 0);
565 BuildMI(BB, X86::SAHF, 1);
566 isSigned = false; // Compare with unsigned operators
570 if (OpNum < 2) { // seteq, setne
571 unsigned LoTmp = makeAnotherReg(Type::IntTy);
572 unsigned HiTmp = makeAnotherReg(Type::IntTy);
573 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
574 BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(reg1).addReg(reg2);
575 BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(reg1+1).addReg(reg2+1);
576 BuildMI(BB, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
577 break; // Allow the sete or setne to be generated from flags set by OR
579 // Emit a sequence of code which compares the high and low parts once
580 // each, then uses a conditional move to handle the overflow case. For
581 // example, a setlt for long would generate code like this:
583 // AL = lo(op1) < lo(op2) // Signedness depends on operands
584 // BL = hi(op1) < hi(op2) // Always unsigned comparison
585 // dest = hi(op1) == hi(op2) ? AL : BL;
588 // FIXME: This would be much better if we had hierarchical register
589 // classes! Until then, hardcode registers so that we can deal with their
590 // aliases (because we don't have conditional byte moves).
592 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
593 BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
594 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1+1).addReg(reg2+1);
595 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
596 BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
597 // NOTE: visitSetCondInst knows that the value is dumped into the BL
598 // register at this point for long values...
606 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
607 /// register, then move it to wherever the result should be.
609 void ISel::visitSetCondInst(SetCondInst &I) {
610 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
612 unsigned OpNum = getSetCCNumber(I.getOpcode());
613 unsigned DestReg = getReg(I);
614 bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
617 if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
618 // Handle normal comparisons with a setcc instruction...
619 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
621 // Handle long comparisons by copying the value which is already in BL into
622 // the register we want...
623 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
627 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
628 /// operand, in the specified target register.
629 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
630 bool isUnsigned = VR.Ty->isUnsigned();
631 switch (getClassB(VR.Ty)) {
633 // Extend value into target register (8->32)
635 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(VR.Reg);
637 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(VR.Reg);
640 // Extend value into target register (16->32)
642 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(VR.Reg);
644 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(VR.Reg);
647 // Move value into target register (32->32)
648 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(VR.Reg);
651 assert(0 && "Unpromotable operand class in promote32");
655 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
656 /// we have the following possibilities:
658 /// ret void: No return value, simply emit a 'ret' instruction
659 /// ret sbyte, ubyte : Extend value into EAX and return
660 /// ret short, ushort: Extend value into EAX and return
661 /// ret int, uint : Move value into EAX and return
662 /// ret pointer : Move value into EAX and return
663 /// ret long, ulong : Move value into EAX/EDX and return
664 /// ret float/double : Top of FP stack
666 void ISel::visitReturnInst(ReturnInst &I) {
667 if (I.getNumOperands() == 0) {
668 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
672 Value *RetVal = I.getOperand(0);
673 unsigned RetReg = getReg(RetVal);
674 switch (getClassB(RetVal->getType())) {
675 case cByte: // integral return values: extend or move into EAX and return
678 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
679 // Declare that EAX is live on exit
680 BuildMI(BB, X86::IMPLICIT_USE, 1).addReg(X86::EAX);
682 case cFP: // Floats & Doubles: Return in ST(0)
683 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
684 // Declare that top-of-stack is live on exit
685 BuildMI(BB, X86::IMPLICIT_USE, 1).addReg(X86::ST0);
688 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
689 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
690 // Declare that EAX & EDX are live on exit
691 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::EDX);
696 // Emit a 'ret' instruction
697 BuildMI(BB, X86::RET, 0);
700 // getBlockAfter - Return the basic block which occurs lexically after the
702 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
703 Function::iterator I = BB; ++I; // Get iterator to next block
704 return I != BB->getParent()->end() ? &*I : 0;
707 /// visitBranchInst - Handle conditional and unconditional branches here. Note
708 /// that since code layout is frozen at this point, that if we are trying to
709 /// jump to a block that is the immediate successor of the current block, we can
710 /// just make a fall-through (but we don't currently).
712 void ISel::visitBranchInst(BranchInst &BI) {
713 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
715 if (!BI.isConditional()) { // Unconditional branch?
716 if (BI.getSuccessor(0) != NextBB)
717 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
721 // See if we can fold the setcc into the branch itself...
722 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
724 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
725 // computed some other way...
726 unsigned condReg = getReg(BI.getCondition());
727 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
728 if (BI.getSuccessor(1) == NextBB) {
729 if (BI.getSuccessor(0) != NextBB)
730 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
732 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
734 if (BI.getSuccessor(0) != NextBB)
735 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
740 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
741 bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
744 // LLVM -> X86 signed X86 unsigned
745 // ----- ---------- ------------
752 static const unsigned OpcodeTab[2][6] = {
753 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
754 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
757 if (BI.getSuccessor(0) != NextBB) {
758 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
759 if (BI.getSuccessor(1) != NextBB)
760 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
762 // Change to the inverse condition...
763 if (BI.getSuccessor(1) != NextBB) {
765 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
771 /// doCall - This emits an abstract call instruction, setting up the arguments
772 /// and the return value as appropriate. For the actual function call itself,
773 /// it inserts the specified CallMI instruction into the stream.
775 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
776 const std::vector<ValueRecord> &Args) {
778 // Count how many bytes are to be pushed on the stack...
779 unsigned NumBytes = 0;
782 for (unsigned i = 0, e = Args.size(); i != e; ++i)
783 switch (getClassB(Args[i].Ty)) {
784 case cByte: case cShort: case cInt:
785 NumBytes += 4; break;
787 NumBytes += 8; break;
789 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
791 default: assert(0 && "Unknown class!");
794 // Adjust the stack pointer for the new arguments...
795 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
797 // Arguments go on the stack in reverse order, as specified by the ABI.
798 unsigned ArgOffset = 0;
799 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
800 unsigned ArgReg = Args[i].Reg;
801 switch (getClassB(Args[i].Ty)) {
804 // Promote arg to 32 bits wide into a temporary register...
805 unsigned R = makeAnotherReg(Type::UIntTy);
806 promote32(R, Args[i]);
807 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
808 X86::ESP, ArgOffset).addReg(R);
812 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
813 X86::ESP, ArgOffset).addReg(ArgReg);
816 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
817 X86::ESP, ArgOffset).addReg(ArgReg);
818 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
819 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
820 ArgOffset += 4; // 8 byte entry, not 4.
824 if (Args[i].Ty == Type::FloatTy) {
825 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
826 X86::ESP, ArgOffset).addReg(ArgReg);
828 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
829 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
830 X86::ESP, ArgOffset).addReg(ArgReg);
831 ArgOffset += 4; // 8 byte entry, not 4.
835 default: assert(0 && "Unknown class!");
840 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
843 BB->push_back(CallMI);
845 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
847 // If there is a return value, scavenge the result from the location the call
850 if (Ret.Ty != Type::VoidTy) {
851 unsigned DestClass = getClassB(Ret.Ty);
856 // Integral results are in %eax, or the appropriate portion
858 static const unsigned regRegMove[] = {
859 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
861 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
862 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
865 case cFP: // Floating-point return values live in %ST(0)
866 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
868 case cLong: // Long values are left in EDX:EAX
869 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
870 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
872 default: assert(0 && "Unknown class!");
878 /// visitCallInst - Push args on stack and do a procedure call instruction.
879 void ISel::visitCallInst(CallInst &CI) {
880 MachineInstr *TheCall;
881 if (Function *F = CI.getCalledFunction()) {
882 // Emit a CALL instruction with PC-relative displacement.
883 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
884 } else { // Emit an indirect call...
885 unsigned Reg = getReg(CI.getCalledValue());
886 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
889 std::vector<ValueRecord> Args;
890 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
891 Args.push_back(ValueRecord(getReg(CI.getOperand(i)),
892 CI.getOperand(i)->getType()));
894 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
895 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
899 /// visitSimpleBinary - Implement simple binary operators for integral types...
900 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
903 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
904 unsigned Class = getClassB(B.getType());
906 static const unsigned OpcodeTab[][4] = {
907 // Arithmetic operators
908 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
909 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
912 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
913 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
914 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
918 if (Class == cLong) {
920 Class = cInt; // Bottom 32 bits are handled just like ints
923 unsigned Opcode = OpcodeTab[OperatorClass][Class];
924 assert(Opcode && "Floating point arguments to logical inst?");
925 unsigned Op0r = getReg(B.getOperand(0));
926 unsigned Op1r = getReg(B.getOperand(1));
927 unsigned DestReg = getReg(B);
928 BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
930 if (isLong) { // Handle the upper 32 bits of long values...
931 static const unsigned TopTab[] = {
932 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
934 BuildMI(BB, TopTab[OperatorClass], 2,
935 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
939 /// doMultiply - Emit appropriate instructions to multiply together the
940 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
941 /// result should be given as DestTy.
943 /// FIXME: doMultiply should use one of the two address IMUL instructions!
945 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
946 unsigned DestReg, const Type *DestTy,
947 unsigned op0Reg, unsigned op1Reg) {
948 unsigned Class = getClass(DestTy);
950 case cFP: // Floating point multiply
951 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
954 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
957 case cInt: // Small integerals, handled below...
961 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
962 static const unsigned MulOpcode[]={ X86::MULr8 , X86::MULr16 , X86::MULr32 };
963 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
964 unsigned Reg = Regs[Class];
966 // Emit a MOV to put the first operand into the appropriately-sized
968 BMI(MBB, MBBI, MovOpcode[Class], 1, Reg).addReg(op0Reg);
970 // Emit the appropriate multiply instruction.
971 BMI(MBB, MBBI, MulOpcode[Class], 1).addReg(op1Reg);
973 // Emit another MOV to put the result into the destination register.
974 BMI(MBB, MBBI, MovOpcode[Class], 1, DestReg).addReg(Reg);
977 /// visitMul - Multiplies are not simple binary operators because they must deal
978 /// with the EAX register explicitly.
980 void ISel::visitMul(BinaryOperator &I) {
981 unsigned Op0Reg = getReg(I.getOperand(0));
982 unsigned Op1Reg = getReg(I.getOperand(1));
983 unsigned DestReg = getReg(I);
985 // Simple scalar multiply?
986 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
987 MachineBasicBlock::iterator MBBI = BB->end();
988 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
990 // Long value. We have to do things the hard way...
991 // Multiply the two low parts... capturing carry into EDX
992 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
993 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
995 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
996 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
997 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
999 MachineBasicBlock::iterator MBBI = BB->end();
1000 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1001 doMultiply(BB, MBBI, AHBLReg, Type::UIntTy, Op0Reg+1, Op1Reg); // AH*BL
1003 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1004 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1005 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1008 unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
1009 doMultiply(BB, MBBI, ALBHReg, Type::UIntTy, Op0Reg, Op1Reg+1); // AL*BH
1011 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1012 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1017 /// visitDivRem - Handle division and remainder instructions... these
1018 /// instruction both require the same instructions to be generated, they just
1019 /// select the result from a different register. Note that both of these
1020 /// instructions work differently for signed and unsigned operands.
1022 void ISel::visitDivRem(BinaryOperator &I) {
1023 unsigned Class = getClass(I.getType());
1024 unsigned Op0Reg = getReg(I.getOperand(0));
1025 unsigned Op1Reg = getReg(I.getOperand(1));
1026 unsigned ResultReg = getReg(I);
1029 case cFP: // Floating point divide
1030 if (I.getOpcode() == Instruction::Div)
1031 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1032 else { // Floating point remainder...
1033 MachineInstr *TheCall =
1034 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1035 std::vector<ValueRecord> Args;
1036 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1037 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1038 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1042 static const char *FnName[] =
1043 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1045 unsigned NameIdx = I.getType()->isUnsigned()*2;
1046 NameIdx += I.getOpcode() == Instruction::Div;
1047 MachineInstr *TheCall =
1048 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1050 std::vector<ValueRecord> Args;
1051 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1052 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1053 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1056 case cByte: case cShort: case cInt:
1057 break; // Small integerals, handled below...
1058 default: assert(0 && "Unknown class!");
1061 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1062 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1063 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
1064 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1065 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1067 static const unsigned DivOpcode[][4] = {
1068 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1069 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1072 bool isSigned = I.getType()->isSigned();
1073 unsigned Reg = Regs[Class];
1074 unsigned ExtReg = ExtRegs[Class];
1076 // Put the first operand into one of the A registers...
1077 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1080 // Emit a sign extension instruction...
1081 BuildMI(BB, ExtOpcode[Class], 0);
1083 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1084 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1087 // Emit the appropriate divide or remainder instruction...
1088 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1090 // Figure out which register we want to pick the result out of...
1091 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1093 // Put the result into the destination register...
1094 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1098 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1099 /// for constant immediate shift values, and for constant immediate
1100 /// shift values equal to 1. Even the general case is sort of special,
1101 /// because the shift amount has to be in CL, not just any old register.
1103 void ISel::visitShiftInst(ShiftInst &I) {
1104 unsigned SrcReg = getReg(I.getOperand(0));
1105 unsigned DestReg = getReg(I);
1106 bool isLeftShift = I.getOpcode() == Instruction::Shl;
1107 bool isSigned = I.getType()->isSigned();
1108 unsigned Class = getClass(I.getType());
1110 static const unsigned ConstantOperand[][4] = {
1111 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1112 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1113 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1114 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1117 static const unsigned NonConstantOperand[][4] = {
1118 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1119 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1120 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1121 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1124 // Longs, as usual, are handled specially...
1125 if (Class == cLong) {
1126 // If we have a constant shift, we can generate much more efficient code
1127 // than otherwise...
1129 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1130 unsigned Amount = CUI->getValue();
1132 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1134 BuildMI(BB, Opc[3], 3,
1135 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1136 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1138 BuildMI(BB, Opc[3], 3,
1139 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1140 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1142 } else { // Shifting more than 32 bits
1145 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1146 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1148 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1149 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1150 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1154 visitInstruction(I); // FIXME: Implement long shift by non-constant
1159 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1160 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1161 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1163 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1164 BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1165 } else { // The shift amount is non-constant.
1166 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
1168 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1169 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1174 /// doFPLoad - This method is used to load an FP value from memory using the
1175 /// current endianness. NOTE: This method returns a partially constructed load
1176 /// instruction which needs to have the memory source filled in still.
1178 MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB,
1179 MachineBasicBlock::iterator &MBBI,
1180 const Type *Ty, unsigned DestReg) {
1181 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1182 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
1184 if (TM.getTargetData().isLittleEndian()) // fast path...
1185 return BMI(MBB, MBBI, LoadOpcode, 4, DestReg);
1187 // If we are big-endian, start by creating an LEA instruction to represent the
1188 // address of the memory location to load from...
1190 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1191 MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg);
1193 // Allocate a temporary stack slot to transform the value into...
1194 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1196 // Perform the bswaps 32 bits at a time...
1197 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1198 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1199 addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1200 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1201 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1202 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5),
1203 FrameIdx, Offset).addReg(TmpReg2);
1205 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1206 TmpReg1 = makeAnotherReg(Type::UIntTy);
1207 TmpReg2 = makeAnotherReg(Type::UIntTy);
1209 addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1210 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1211 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1212 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2);
1215 // Now we can reload the final byteswapped result into the final destination.
1216 addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx);
1220 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1222 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1223 // Emit the byte swap instruction...
1226 // No byteswap necessary for 8 bit value...
1227 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1230 // Use the 32 bit bswap instruction to do a 32 bit swap...
1231 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1235 // For 16 bit we have to use an xchg instruction, because there is no
1236 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1237 // into AX to do the xchg.
1239 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1240 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1241 .addReg(X86::AH, MOTy::UseAndDef);
1242 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1244 default: assert(0 && "Cannot byteswap this class!");
1249 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1250 /// instruction. The load and store instructions are the only place where we
1251 /// need to worry about the memory layout of the target machine.
1253 void ISel::visitLoadInst(LoadInst &I) {
1254 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1255 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1256 unsigned SrcAddrReg = getReg(I.getOperand(0));
1257 unsigned DestReg = getReg(I);
1259 unsigned Class = getClass(I.getType());
1262 MachineBasicBlock::iterator MBBI = BB->end();
1263 addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg);
1266 case cLong: case cInt: case cShort: case cByte:
1267 break; // Integers of various sizes handled below
1268 default: assert(0 && "Unknown memory class!");
1271 // We need to adjust the input pointer if we are emulating a big-endian
1272 // long-pointer target. On these systems, the pointer that we are interested
1273 // in is in the upper part of the eight byte memory image of the pointer. It
1274 // also happens to be byte-swapped, but this will be handled later.
1276 if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
1277 unsigned R = makeAnotherReg(Type::UIntTy);
1278 BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
1282 unsigned IReg = DestReg;
1283 if (!isLittleEndian) // If big endian we need an intermediate stage
1284 DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy);
1286 static const unsigned Opcode[] = {
1287 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
1289 addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
1291 // Handle long values now...
1292 if (Class == cLong) {
1293 if (isLittleEndian) {
1294 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1296 EmitByteSwap(IReg+1, DestReg, cInt);
1297 unsigned TempReg = makeAnotherReg(Type::IntTy);
1298 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4);
1299 EmitByteSwap(IReg, TempReg, cInt);
1304 if (!isLittleEndian)
1305 EmitByteSwap(IReg, DestReg, Class);
1309 /// doFPStore - This method is used to store an FP value to memory using the
1310 /// current endianness.
1312 void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) {
1313 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1314 unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
1316 if (TM.getTargetData().isLittleEndian()) { // fast path...
1317 addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg);
1321 // Allocate a temporary stack slot to transform the value into...
1322 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1323 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1324 addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx);
1326 // Store the value into a temporary stack slot...
1327 addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg);
1329 // Perform the bswaps 32 bits at a time...
1330 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1331 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1332 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1333 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1334 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1335 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1336 DestAddrReg, Offset).addReg(TmpReg2);
1338 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1339 TmpReg1 = makeAnotherReg(Type::UIntTy);
1340 TmpReg2 = makeAnotherReg(Type::UIntTy);
1342 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1343 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1344 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1345 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2);
1350 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1353 void ISel::visitStoreInst(StoreInst &I) {
1354 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1355 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1356 unsigned ValReg = getReg(I.getOperand(0));
1357 unsigned AddressReg = getReg(I.getOperand(1));
1359 unsigned Class = getClass(I.getOperand(0)->getType());
1362 if (isLittleEndian) {
1363 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1364 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4),
1365 AddressReg, 4).addReg(ValReg+1);
1367 unsigned T1 = makeAnotherReg(Type::IntTy);
1368 unsigned T2 = makeAnotherReg(Type::IntTy);
1369 EmitByteSwap(T1, ValReg , cInt);
1370 EmitByteSwap(T2, ValReg+1, cInt);
1371 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2);
1372 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1);
1376 doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg);
1378 case cInt: case cShort: case cByte:
1379 break; // Integers of various sizes handled below
1380 default: assert(0 && "Unknown memory class!");
1383 if (!isLittleEndian && hasLongPointers &&
1384 isa<PointerType>(I.getOperand(0)->getType())) {
1385 unsigned R = makeAnotherReg(Type::UIntTy);
1386 BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
1390 if (!isLittleEndian && Class != cByte) {
1391 unsigned R = makeAnotherReg(I.getOperand(0)->getType());
1392 EmitByteSwap(R, ValReg, Class);
1396 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1397 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
1401 /// visitCastInst - Here we have various kinds of copying with or without
1402 /// sign extension going on.
1403 void ISel::visitCastInst(CastInst &CI) {
1404 unsigned DestReg = getReg(CI);
1405 MachineBasicBlock::iterator MI = BB->end();
1406 emitCastOperation(BB, MI, CI.getOperand(0), CI.getType(), DestReg);
1409 /// emitCastOperation - Common code shared between visitCastInst and
1410 /// constant expression cast support.
1411 void ISel::emitCastOperation(MachineBasicBlock *BB,
1412 MachineBasicBlock::iterator &IP,
1413 Value *Src, const Type *DestTy,
1415 unsigned SrcReg = getReg(Src, BB, IP);
1416 const Type *SrcTy = Src->getType();
1417 unsigned SrcClass = getClassB(SrcTy);
1418 unsigned DestClass = getClassB(DestTy);
1420 // Implement casts to bool by using compare on the operand followed by set if
1421 // not zero on the result.
1422 if (DestTy == Type::BoolTy) {
1423 if (SrcClass == cFP || SrcClass == cLong)
1424 abort(); // FIXME: implement cast (long & FP) to bool
1426 BMI(BB, IP, X86::CMPri8, 2).addReg(SrcReg).addZImm(0);
1427 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1431 static const unsigned RegRegMove[] = {
1432 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1435 // Implement casts between values of the same type class (as determined by
1436 // getClass) by using a register-to-register move.
1437 if (SrcClass == DestClass) {
1438 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1439 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1440 } else if (SrcClass == cFP) {
1441 if (SrcTy == Type::FloatTy) { // double -> float
1442 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1443 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1444 } else { // float -> double
1445 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1446 "Unknown cFP member!");
1447 // Truncate from double to float by storing to memory as short, then
1449 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1450 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1451 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1452 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1454 } else if (SrcClass == cLong) {
1455 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1456 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1463 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1464 // or zero extension, depending on whether the source type was signed.
1465 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1466 SrcClass < DestClass) {
1467 bool isLong = DestClass == cLong;
1468 if (isLong) DestClass = cInt;
1470 static const unsigned Opc[][4] = {
1471 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1472 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1475 bool isUnsigned = SrcTy->isUnsigned();
1476 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1477 DestReg).addReg(SrcReg);
1479 if (isLong) { // Handle upper 32 bits as appropriate...
1480 if (isUnsigned) // Zero out top bits...
1481 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1482 else // Sign extend bottom half...
1483 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1488 // Special case long -> int ...
1489 if (SrcClass == cLong && DestClass == cInt) {
1490 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1494 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1495 // move out of AX or AL.
1496 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1497 && SrcClass > DestClass) {
1498 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1499 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1500 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1504 // Handle casts from integer to floating point now...
1505 if (DestClass == cFP) {
1506 // unsigned int -> load as 64 bit int.
1507 // unsigned long long -> more complex
1508 if (SrcTy->isUnsigned() && SrcTy != Type::UByteTy)
1509 abort(); // don't handle unsigned src yet!
1511 // We don't have the facilities for directly loading byte sized data from
1512 // memory. Promote it to 16 bits.
1513 if (SrcClass == cByte) {
1514 unsigned TmpReg = makeAnotherReg(Type::ShortTy);
1515 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1516 1, TmpReg).addReg(SrcReg);
1517 SrcTy = Type::ShortTy; // Pretend the short is our input now!
1522 // Spill the integer to memory and reload it from there...
1524 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1526 if (SrcClass == cLong) {
1527 if (SrcTy == Type::ULongTy) abort(); // FIXME: Handle ulong -> FP
1528 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1529 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1530 FrameIdx, 4).addReg(SrcReg+1);
1532 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1533 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1536 static const unsigned Op2[] =
1537 { 0, X86::FILDr16, X86::FILDr32, 0, X86::FILDr64 };
1538 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1542 // Handle casts from floating point to integer now...
1543 if (SrcClass == cFP) {
1544 // Change the floating point control register to use "round towards zero"
1545 // mode when truncating to an integer value.
1547 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1548 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1550 // Load the old value of the high byte of the control word...
1551 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1552 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1554 // Set the high part to be round to zero...
1555 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1557 // Reload the modified control word now...
1558 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1560 // Restore the memory image of control word to original value
1561 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1562 CWFrameIdx, 1).addReg(HighPartOfCW);
1564 // We don't have the facilities for directly storing byte sized data to
1565 // memory. Promote it to 16 bits. We also must promote unsigned values to
1566 // larger classes because we only have signed FP stores.
1567 unsigned StoreClass = DestClass;
1568 const Type *StoreTy = DestTy;
1569 if (StoreClass == cByte || DestTy->isUnsigned())
1570 switch (StoreClass) {
1571 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1572 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1573 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1574 case cLong: abort(); // FIXME: unsigned long long -> more complex
1575 default: assert(0 && "Unknown store class!");
1578 // Spill the integer to memory and reload it from there...
1580 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1582 static const unsigned Op1[] =
1583 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1584 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1586 if (DestClass == cLong) {
1587 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1588 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1590 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1591 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1594 // Reload the original control word now...
1595 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1599 // Anything we haven't handled already, we can't (yet) handle at all.
1603 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1604 // returns zero when the input is not exactly a power of two.
1605 static unsigned ExactLog2(unsigned Val) {
1606 if (Val == 0) return 0;
1609 if (Val & 1) return 0;
1616 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
1617 unsigned outputReg = getReg(I);
1618 MachineBasicBlock::iterator MI = BB->end();
1619 emitGEPOperation(BB, MI, I.getOperand(0),
1620 I.op_begin()+1, I.op_end(), outputReg);
1623 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
1624 MachineBasicBlock::iterator &IP,
1625 Value *Src, User::op_iterator IdxBegin,
1626 User::op_iterator IdxEnd, unsigned TargetReg) {
1627 const TargetData &TD = TM.getTargetData();
1628 const Type *Ty = Src->getType();
1629 unsigned BaseReg = getReg(Src, MBB, IP);
1631 // GEPs have zero or more indices; we must perform a struct access
1632 // or array access for each one.
1633 for (GetElementPtrInst::op_iterator oi = IdxBegin,
1634 oe = IdxEnd; oi != oe; ++oi) {
1636 unsigned NextReg = BaseReg;
1637 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1638 // It's a struct access. idx is the index into the structure,
1639 // which names the field. This index must have ubyte type.
1640 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
1641 assert(CUI->getType() == Type::UByteTy
1642 && "Funny-looking structure index in GEP");
1643 // Use the TargetData structure to pick out what the layout of
1644 // the structure is in memory. Since the structure index must
1645 // be constant, we can get its value and use it to find the
1646 // right byte offset from the StructLayout class's list of
1647 // structure member offsets.
1648 unsigned idxValue = CUI->getValue();
1649 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
1651 NextReg = makeAnotherReg(Type::UIntTy);
1652 // Emit an ADD to add FieldOff to the basePtr.
1653 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1655 // The next type is the member of the structure selected by the
1657 Ty = StTy->getElementTypes()[idxValue];
1658 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
1659 // It's an array or pointer access: [ArraySize x ElementType].
1661 // idx is the index into the array. Unlike with structure
1662 // indices, we may not know its actual value at code-generation
1664 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
1666 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
1667 // must find the size of the pointed-to type (Not coincidentally, the next
1668 // type is the type of the elements in the array).
1669 Ty = SqTy->getElementType();
1670 unsigned elementSize = TD.getTypeSize(Ty);
1672 // If idxReg is a constant, we don't need to perform the multiply!
1673 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
1674 if (!CSI->isNullValue()) {
1675 unsigned Offset = elementSize*CSI->getValue();
1676 NextReg = makeAnotherReg(Type::UIntTy);
1677 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
1679 } else if (elementSize == 1) {
1680 // If the element size is 1, we don't have to multiply, just add
1681 unsigned idxReg = getReg(idx, MBB, IP);
1682 NextReg = makeAnotherReg(Type::UIntTy);
1683 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
1685 unsigned idxReg = getReg(idx, MBB, IP);
1686 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
1687 if (unsigned Shift = ExactLog2(elementSize)) {
1688 // If the element size is exactly a power of 2, use a shift to get it.
1689 BMI(MBB, IP, X86::SHLir32, 2,
1690 OffsetReg).addReg(idxReg).addZImm(Shift-1);
1692 // Most general case, emit a multiply...
1693 unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
1694 BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
1696 // Emit a MUL to multiply the register holding the index by
1697 // elementSize, putting the result in OffsetReg.
1698 doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
1700 // Emit an ADD to add OffsetReg to the basePtr.
1701 NextReg = makeAnotherReg(Type::UIntTy);
1702 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
1705 // Now that we are here, further indices refer to subtypes of this
1706 // one, so we don't need to worry about BaseReg itself, anymore.
1709 // After we have processed all the indices, the result is left in
1710 // BaseReg. Move it to the register where we were expected to
1711 // put the answer. A 32-bit move should do it, because we are in
1713 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
1717 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
1718 /// frame manager, otherwise do it the hard way.
1720 void ISel::visitAllocaInst(AllocaInst &I) {
1721 // Find the data size of the alloca inst's getAllocatedType.
1722 const Type *Ty = I.getAllocatedType();
1723 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1725 // If this is a fixed size alloca in the entry block for the function,
1726 // statically stack allocate the space.
1728 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
1729 if (I.getParent() == I.getParent()->getParent()->begin()) {
1730 TySize *= CUI->getValue(); // Get total allocated size...
1731 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
1733 // Create a new stack object using the frame manager...
1734 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
1735 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
1740 // Create a register to hold the temporary result of multiplying the type size
1741 // constant by the variable amount.
1742 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
1743 unsigned SrcReg1 = getReg(I.getArraySize());
1744 unsigned SizeReg = makeAnotherReg(Type::UIntTy);
1745 BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
1747 // TotalSizeReg = mul <numelements>, <TypeSize>
1748 MachineBasicBlock::iterator MBBI = BB->end();
1749 doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
1751 // AddedSize = add <TotalSizeReg>, 15
1752 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
1753 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
1755 // AlignedSize = and <AddedSize>, ~15
1756 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
1757 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
1759 // Subtract size from stack pointer, thereby allocating some space.
1760 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
1762 // Put a pointer to the space into the result register, by copying
1763 // the stack pointer.
1764 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
1766 // Inform the Frame Information that we have just allocated a variable-sized
1768 F->getFrameInfo()->CreateVariableSizedObject();
1771 /// visitMallocInst - Malloc instructions are code generated into direct calls
1772 /// to the library malloc.
1774 void ISel::visitMallocInst(MallocInst &I) {
1775 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
1778 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
1779 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
1781 Arg = makeAnotherReg(Type::UIntTy);
1782 unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
1783 unsigned Op1Reg = getReg(I.getOperand(0));
1784 MachineBasicBlock::iterator MBBI = BB->end();
1785 doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
1790 std::vector<ValueRecord> Args;
1791 Args.push_back(ValueRecord(Arg, Type::UIntTy));
1792 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
1793 1).addExternalSymbol("malloc", true);
1794 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
1798 /// visitFreeInst - Free instructions are code gen'd to call the free libc
1801 void ISel::visitFreeInst(FreeInst &I) {
1802 std::vector<ValueRecord> Args;
1803 Args.push_back(ValueRecord(getReg(I.getOperand(0)),
1804 I.getOperand(0)->getType()));
1805 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
1806 1).addExternalSymbol("free", true);
1807 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
1811 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
1812 /// into a machine code representation is a very simple peep-hole fashion. The
1813 /// generated code sucks but the implementation is nice and simple.
1815 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
1816 return new ISel(TM);