1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
144 // FIXME: We need to teach codegen about single list of call-clobbered registers.
146 // All calls clobber the non-callee saved registers. RSP is marked as
147 // a use to prevent stack-pointer assignments that appear immediately
148 // before calls from potentially appearing dead. Uses for argument
149 // registers are added manually.
150 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
151 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
152 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
153 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
155 def WINCALL64pcrel32 : I<0xE8, RawFrm,
156 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
159 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
161 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
162 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
164 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
168 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
169 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
171 "#TC_RETURN $dst $offset",
174 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
175 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
177 "#TC_RETURN $dst $offset",
181 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
182 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
183 "jmp{q}\t{*}$dst # TAILCALL",
187 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
188 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
189 [(brind GR64:$dst)]>;
190 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
191 [(brind (loadi64 addr:$dst))]>;
194 //===----------------------------------------------------------------------===//
195 // EH Pseudo Instructions
197 let isTerminator = 1, isReturn = 1, isBarrier = 1,
199 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
200 "ret\t#eh_return, addr: $addr",
201 [(X86ehret GR64:$addr)]>;
205 //===----------------------------------------------------------------------===//
206 // Miscellaneous Instructions...
208 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
209 def LEAVE64 : I<0xC9, RawFrm,
210 (outs), (ins), "leave", []>;
211 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
213 def POP64r : I<0x58, AddRegFrm,
214 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
216 def PUSH64r : I<0x50, AddRegFrm,
217 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
220 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
221 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
222 "push{q}\t$imm", []>;
223 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
224 "push{q}\t$imm", []>;
225 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
226 "push{q}\t$imm", []>;
229 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
230 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
231 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
232 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
234 def LEA64_32r : I<0x8D, MRMSrcMem,
235 (outs GR32:$dst), (ins lea64_32mem:$src),
236 "lea{l}\t{$src|$dst}, {$dst|$src}",
237 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
239 let isReMaterializable = 1 in
240 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
241 "lea{q}\t{$src|$dst}, {$dst|$src}",
242 [(set GR64:$dst, lea64addr:$src)]>;
244 let isTwoAddress = 1 in
245 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
247 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
249 // Bit scan instructions.
250 let Defs = [EFLAGS] in {
251 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
252 "bsf{q}\t{$src, $dst|$dst, $src}",
253 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
254 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
255 "bsf{q}\t{$src, $dst|$dst, $src}",
256 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
257 (implicit EFLAGS)]>, TB;
259 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
260 "bsr{q}\t{$src, $dst|$dst, $src}",
261 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
262 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
263 "bsr{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
265 (implicit EFLAGS)]>, TB;
269 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
270 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
271 [(X86rep_movs i64)]>, REP;
272 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
273 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
274 [(X86rep_stos i64)]>, REP;
276 // Fast system-call instructions
277 def SYSEXIT64 : RI<0x35, RawFrm,
278 (outs), (ins), "sysexit", []>, TB;
280 //===----------------------------------------------------------------------===//
281 // Move Instructions...
284 let neverHasSideEffects = 1 in
285 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
286 "mov{q}\t{$src, $dst|$dst, $src}", []>;
288 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
289 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
290 "movabs{q}\t{$src, $dst|$dst, $src}",
291 [(set GR64:$dst, imm:$src)]>;
292 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
293 "mov{q}\t{$src, $dst|$dst, $src}",
294 [(set GR64:$dst, i64immSExt32:$src)]>;
297 let canFoldAsLoad = 1 in
298 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
299 "mov{q}\t{$src, $dst|$dst, $src}",
300 [(set GR64:$dst, (load addr:$src))]>;
302 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
303 "mov{q}\t{$src, $dst|$dst, $src}",
304 [(store GR64:$src, addr:$dst)]>;
305 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
306 "mov{q}\t{$src, $dst|$dst, $src}",
307 [(store i64immSExt32:$src, addr:$dst)]>;
309 // Sign/Zero extenders
311 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
312 // operand, which makes it a rare instruction with an 8-bit register
313 // operand that can never access an h register. If support for h registers
314 // were generalized, this would require a special register class.
315 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
316 "movs{bq|x}\t{$src, $dst|$dst, $src}",
317 [(set GR64:$dst, (sext GR8:$src))]>, TB;
318 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
319 "movs{bq|x}\t{$src, $dst|$dst, $src}",
320 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
321 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
322 "movs{wq|x}\t{$src, $dst|$dst, $src}",
323 [(set GR64:$dst, (sext GR16:$src))]>, TB;
324 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
325 "movs{wq|x}\t{$src, $dst|$dst, $src}",
326 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
327 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
328 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
329 [(set GR64:$dst, (sext GR32:$src))]>;
330 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
331 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
332 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
334 // Use movzbl instead of movzbq when the destination is a register; it's
335 // equivalent due to implicit zero-extending, and it has a smaller encoding.
336 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
337 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
338 [(set GR64:$dst, (zext GR8:$src))]>, TB;
339 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
340 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
341 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
342 // Use movzwl instead of movzwq when the destination is a register; it's
343 // equivalent due to implicit zero-extending, and it has a smaller encoding.
344 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
345 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
346 [(set GR64:$dst, (zext GR16:$src))]>, TB;
347 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
348 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
349 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
351 // There's no movzlq instruction, but movl can be used for this purpose, using
352 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
353 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
354 // zero-extension, however this isn't possible when the 32-bit value is
355 // defined by a truncate or is copied from something where the high bits aren't
356 // necessarily all zero. In such cases, we fall back to these explicit zext
358 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
359 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
360 [(set GR64:$dst, (zext GR32:$src))]>;
361 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
362 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
363 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
365 // Any instruction that defines a 32-bit result leaves the high half of the
366 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
367 // be copying from a truncate, but any other 32-bit operation will zero-extend
369 def def32 : PatLeaf<(i32 GR32:$src), [{
370 return N->getOpcode() != ISD::TRUNCATE &&
371 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
372 N->getOpcode() != ISD::CopyFromReg;
375 // In the case of a 32-bit def that is known to implicitly zero-extend,
376 // we can use a SUBREG_TO_REG.
377 def : Pat<(i64 (zext def32:$src)),
378 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
380 let neverHasSideEffects = 1 in {
381 let Defs = [RAX], Uses = [EAX] in
382 def CDQE : RI<0x98, RawFrm, (outs), (ins),
383 "{cltq|cdqe}", []>; // RAX = signext(EAX)
385 let Defs = [RAX,RDX], Uses = [RAX] in
386 def CQO : RI<0x99, RawFrm, (outs), (ins),
387 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
390 //===----------------------------------------------------------------------===//
391 // Arithmetic Instructions...
394 let Defs = [EFLAGS] in {
395 let isTwoAddress = 1 in {
396 let isConvertibleToThreeAddress = 1 in {
397 let isCommutable = 1 in
398 // Register-Register Addition
399 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
400 "add{q}\t{$src2, $dst|$dst, $src2}",
401 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
404 // Register-Integer Addition
405 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
406 "add{q}\t{$src2, $dst|$dst, $src2}",
407 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
409 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
410 "add{q}\t{$src2, $dst|$dst, $src2}",
411 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
413 } // isConvertibleToThreeAddress
415 // Register-Memory Addition
416 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
417 "add{q}\t{$src2, $dst|$dst, $src2}",
418 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
422 // Memory-Register Addition
423 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
424 "add{q}\t{$src2, $dst|$dst, $src2}",
425 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
427 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
428 "add{q}\t{$src2, $dst|$dst, $src2}",
429 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
431 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
432 "add{q}\t{$src2, $dst|$dst, $src2}",
433 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
436 let Uses = [EFLAGS] in {
437 let isTwoAddress = 1 in {
438 let isCommutable = 1 in
439 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
440 "adc{q}\t{$src2, $dst|$dst, $src2}",
441 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
443 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
444 "adc{q}\t{$src2, $dst|$dst, $src2}",
445 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
447 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
448 "adc{q}\t{$src2, $dst|$dst, $src2}",
449 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
450 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
451 "adc{q}\t{$src2, $dst|$dst, $src2}",
452 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
455 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
456 "adc{q}\t{$src2, $dst|$dst, $src2}",
457 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
458 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
459 "adc{q}\t{$src2, $dst|$dst, $src2}",
460 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
461 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
462 "adc{q}\t{$src2, $dst|$dst, $src2}",
463 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
466 let isTwoAddress = 1 in {
467 // Register-Register Subtraction
468 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
469 "sub{q}\t{$src2, $dst|$dst, $src2}",
470 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
473 // Register-Memory Subtraction
474 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
475 "sub{q}\t{$src2, $dst|$dst, $src2}",
476 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
479 // Register-Integer Subtraction
480 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
481 (ins GR64:$src1, i64i8imm:$src2),
482 "sub{q}\t{$src2, $dst|$dst, $src2}",
483 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
485 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
486 (ins GR64:$src1, i64i32imm:$src2),
487 "sub{q}\t{$src2, $dst|$dst, $src2}",
488 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
492 // Memory-Register Subtraction
493 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
494 "sub{q}\t{$src2, $dst|$dst, $src2}",
495 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
498 // Memory-Integer Subtraction
499 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
500 "sub{q}\t{$src2, $dst|$dst, $src2}",
501 [(store (sub (load addr:$dst), i64immSExt8:$src2),
504 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
505 "sub{q}\t{$src2, $dst|$dst, $src2}",
506 [(store (sub (load addr:$dst), i64immSExt32:$src2),
510 let Uses = [EFLAGS] in {
511 let isTwoAddress = 1 in {
512 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
513 "sbb{q}\t{$src2, $dst|$dst, $src2}",
514 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
516 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
517 "sbb{q}\t{$src2, $dst|$dst, $src2}",
518 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
520 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
521 "sbb{q}\t{$src2, $dst|$dst, $src2}",
522 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
523 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
524 "sbb{q}\t{$src2, $dst|$dst, $src2}",
525 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
528 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
529 "sbb{q}\t{$src2, $dst|$dst, $src2}",
530 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
531 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
532 "sbb{q}\t{$src2, $dst|$dst, $src2}",
533 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
534 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
535 "sbb{q}\t{$src2, $dst|$dst, $src2}",
536 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
540 // Unsigned multiplication
541 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
542 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
543 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
545 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
546 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
548 // Signed multiplication
549 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
550 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
552 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
553 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
556 let Defs = [EFLAGS] in {
557 let isTwoAddress = 1 in {
558 let isCommutable = 1 in
559 // Register-Register Signed Integer Multiplication
560 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
561 (ins GR64:$src1, GR64:$src2),
562 "imul{q}\t{$src2, $dst|$dst, $src2}",
563 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
564 (implicit EFLAGS)]>, TB;
566 // Register-Memory Signed Integer Multiplication
567 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
568 (ins GR64:$src1, i64mem:$src2),
569 "imul{q}\t{$src2, $dst|$dst, $src2}",
570 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
571 (implicit EFLAGS)]>, TB;
574 // Suprisingly enough, these are not two address instructions!
576 // Register-Integer Signed Integer Multiplication
577 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
578 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
579 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
580 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
582 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
583 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
584 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
585 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
588 // Memory-Integer Signed Integer Multiplication
589 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
590 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
591 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
592 [(set GR64:$dst, (mul (load addr:$src1),
595 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
596 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
597 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
598 [(set GR64:$dst, (mul (load addr:$src1),
599 i64immSExt32:$src2)),
603 // Unsigned division / remainder
604 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
605 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
607 // Signed division / remainder
608 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
609 "idiv{q}\t$src", []>;
611 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
613 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
614 "idiv{q}\t$src", []>;
618 // Unary instructions
619 let Defs = [EFLAGS], CodeSize = 2 in {
620 let isTwoAddress = 1 in
621 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
622 [(set GR64:$dst, (ineg GR64:$src)),
624 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
625 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
628 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
629 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
630 [(set GR64:$dst, (add GR64:$src, 1)),
632 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
633 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
636 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
637 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
638 [(set GR64:$dst, (add GR64:$src, -1)),
640 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
641 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
644 // In 64-bit mode, single byte INC and DEC cannot be encoded.
645 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
646 // Can transform into LEA.
647 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
648 [(set GR16:$dst, (add GR16:$src, 1)),
650 OpSize, Requires<[In64BitMode]>;
651 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
652 [(set GR32:$dst, (add GR32:$src, 1)),
654 Requires<[In64BitMode]>;
655 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
656 [(set GR16:$dst, (add GR16:$src, -1)),
658 OpSize, Requires<[In64BitMode]>;
659 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
660 [(set GR32:$dst, (add GR32:$src, -1)),
662 Requires<[In64BitMode]>;
663 } // isConvertibleToThreeAddress
665 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
666 // how to unfold them.
667 let isTwoAddress = 0, CodeSize = 2 in {
668 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
669 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
671 OpSize, Requires<[In64BitMode]>;
672 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
673 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
675 Requires<[In64BitMode]>;
676 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
677 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
679 OpSize, Requires<[In64BitMode]>;
680 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
681 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
683 Requires<[In64BitMode]>;
685 } // Defs = [EFLAGS], CodeSize
688 let Defs = [EFLAGS] in {
689 // Shift instructions
690 let isTwoAddress = 1 in {
692 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
693 "shl{q}\t{%cl, $dst|$dst, %CL}",
694 [(set GR64:$dst, (shl GR64:$src, CL))]>;
695 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
696 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
697 "shl{q}\t{$src2, $dst|$dst, $src2}",
698 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
699 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
704 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
705 "shl{q}\t{%cl, $dst|$dst, %CL}",
706 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
707 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
708 "shl{q}\t{$src, $dst|$dst, $src}",
709 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
710 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
712 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
714 let isTwoAddress = 1 in {
716 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
717 "shr{q}\t{%cl, $dst|$dst, %CL}",
718 [(set GR64:$dst, (srl GR64:$src, CL))]>;
719 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
720 "shr{q}\t{$src2, $dst|$dst, $src2}",
721 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
722 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
724 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
728 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
729 "shr{q}\t{%cl, $dst|$dst, %CL}",
730 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
731 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
732 "shr{q}\t{$src, $dst|$dst, $src}",
733 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
734 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
736 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
738 let isTwoAddress = 1 in {
740 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
741 "sar{q}\t{%cl, $dst|$dst, %CL}",
742 [(set GR64:$dst, (sra GR64:$src, CL))]>;
743 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
744 "sar{q}\t{$src2, $dst|$dst, $src2}",
745 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
746 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
748 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
752 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
753 "sar{q}\t{%cl, $dst|$dst, %CL}",
754 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
755 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
756 "sar{q}\t{$src, $dst|$dst, $src}",
757 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
758 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
760 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
762 // Rotate instructions
763 let isTwoAddress = 1 in {
765 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
766 "rol{q}\t{%cl, $dst|$dst, %CL}",
767 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
768 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
769 "rol{q}\t{$src2, $dst|$dst, $src2}",
770 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
771 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
773 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
777 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
778 "rol{q}\t{%cl, $dst|$dst, %CL}",
779 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
780 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
781 "rol{q}\t{$src, $dst|$dst, $src}",
782 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
783 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
785 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
787 let isTwoAddress = 1 in {
789 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
790 "ror{q}\t{%cl, $dst|$dst, %CL}",
791 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
792 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
793 "ror{q}\t{$src2, $dst|$dst, $src2}",
794 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
795 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
797 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
801 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
802 "ror{q}\t{%cl, $dst|$dst, %CL}",
803 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
804 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
805 "ror{q}\t{$src, $dst|$dst, $src}",
806 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
807 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
809 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
811 // Double shift instructions (generalizations of rotate)
812 let isTwoAddress = 1 in {
814 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
815 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
816 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
817 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
818 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
819 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
822 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
823 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
824 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
825 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
826 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
829 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
830 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
831 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
832 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
839 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
840 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
841 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
843 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
844 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
845 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
848 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
849 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
850 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
851 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
852 (i8 imm:$src3)), addr:$dst)]>,
854 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
855 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
856 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
857 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
858 (i8 imm:$src3)), addr:$dst)]>,
862 //===----------------------------------------------------------------------===//
863 // Logical Instructions...
866 let isTwoAddress = 1 , AddedComplexity = 15 in
867 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
868 [(set GR64:$dst, (not GR64:$src))]>;
869 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
870 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
872 let Defs = [EFLAGS] in {
873 let isTwoAddress = 1 in {
874 let isCommutable = 1 in
875 def AND64rr : RI<0x21, MRMDestReg,
876 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
877 "and{q}\t{$src2, $dst|$dst, $src2}",
878 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
880 def AND64rm : RI<0x23, MRMSrcMem,
881 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
882 "and{q}\t{$src2, $dst|$dst, $src2}",
883 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
885 def AND64ri8 : RIi8<0x83, MRM4r,
886 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
887 "and{q}\t{$src2, $dst|$dst, $src2}",
888 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
890 def AND64ri32 : RIi32<0x81, MRM4r,
891 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
892 "and{q}\t{$src2, $dst|$dst, $src2}",
893 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
897 def AND64mr : RI<0x21, MRMDestMem,
898 (outs), (ins i64mem:$dst, GR64:$src),
899 "and{q}\t{$src, $dst|$dst, $src}",
900 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
902 def AND64mi8 : RIi8<0x83, MRM4m,
903 (outs), (ins i64mem:$dst, i64i8imm :$src),
904 "and{q}\t{$src, $dst|$dst, $src}",
905 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
907 def AND64mi32 : RIi32<0x81, MRM4m,
908 (outs), (ins i64mem:$dst, i64i32imm:$src),
909 "and{q}\t{$src, $dst|$dst, $src}",
910 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
913 let isTwoAddress = 1 in {
914 let isCommutable = 1 in
915 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
916 "or{q}\t{$src2, $dst|$dst, $src2}",
917 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
919 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
920 "or{q}\t{$src2, $dst|$dst, $src2}",
921 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
923 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
924 "or{q}\t{$src2, $dst|$dst, $src2}",
925 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
927 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
928 "or{q}\t{$src2, $dst|$dst, $src2}",
929 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
933 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
934 "or{q}\t{$src, $dst|$dst, $src}",
935 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
937 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
938 "or{q}\t{$src, $dst|$dst, $src}",
939 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
941 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
942 "or{q}\t{$src, $dst|$dst, $src}",
943 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
946 let isTwoAddress = 1 in {
947 let isCommutable = 1 in
948 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
949 "xor{q}\t{$src2, $dst|$dst, $src2}",
950 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
952 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
953 "xor{q}\t{$src2, $dst|$dst, $src2}",
954 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
956 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
957 "xor{q}\t{$src2, $dst|$dst, $src2}",
958 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
960 def XOR64ri32 : RIi32<0x81, MRM6r,
961 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
962 "xor{q}\t{$src2, $dst|$dst, $src2}",
963 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
967 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
968 "xor{q}\t{$src, $dst|$dst, $src}",
969 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
971 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
972 "xor{q}\t{$src, $dst|$dst, $src}",
973 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
975 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
976 "xor{q}\t{$src, $dst|$dst, $src}",
977 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
981 //===----------------------------------------------------------------------===//
982 // Comparison Instructions...
985 // Integer comparison
986 let Defs = [EFLAGS] in {
987 let isCommutable = 1 in
988 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
989 "test{q}\t{$src2, $src1|$src1, $src2}",
990 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
992 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
993 "test{q}\t{$src2, $src1|$src1, $src2}",
994 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
996 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
997 (ins GR64:$src1, i64i32imm:$src2),
998 "test{q}\t{$src2, $src1|$src1, $src2}",
999 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1000 (implicit EFLAGS)]>;
1001 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1002 (ins i64mem:$src1, i64i32imm:$src2),
1003 "test{q}\t{$src2, $src1|$src1, $src2}",
1004 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1005 (implicit EFLAGS)]>;
1007 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1008 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1009 [(X86cmp GR64:$src1, GR64:$src2),
1010 (implicit EFLAGS)]>;
1011 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1012 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1013 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1014 (implicit EFLAGS)]>;
1015 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1016 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1017 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1018 (implicit EFLAGS)]>;
1019 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1020 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1021 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1022 (implicit EFLAGS)]>;
1023 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1024 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1025 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1026 (implicit EFLAGS)]>;
1027 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1028 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1029 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1030 (implicit EFLAGS)]>;
1031 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1032 (ins i64mem:$src1, i64i32imm:$src2),
1033 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1034 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1035 (implicit EFLAGS)]>;
1036 } // Defs = [EFLAGS]
1039 // TODO: BTC, BTR, and BTS
1040 let Defs = [EFLAGS] in {
1041 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1042 "bt{q}\t{$src2, $src1|$src1, $src2}",
1043 [(X86bt GR64:$src1, GR64:$src2),
1044 (implicit EFLAGS)]>, TB;
1046 // Unlike with the register+register form, the memory+register form of the
1047 // bt instruction does not ignore the high bits of the index. From ISel's
1048 // perspective, this is pretty bizarre. Disable these instructions for now.
1049 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1050 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1051 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1052 // (implicit EFLAGS)]>, TB;
1054 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1055 "bt{q}\t{$src2, $src1|$src1, $src2}",
1056 [(X86bt GR64:$src1, i64immSExt8:$src2),
1057 (implicit EFLAGS)]>, TB;
1058 // Note that these instructions don't need FastBTMem because that
1059 // only applies when the other operand is in a register. When it's
1060 // an immediate, bt is still fast.
1061 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1062 "bt{q}\t{$src2, $src1|$src1, $src2}",
1063 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1064 (implicit EFLAGS)]>, TB;
1065 } // Defs = [EFLAGS]
1067 // Conditional moves
1068 let Uses = [EFLAGS], isTwoAddress = 1 in {
1069 let isCommutable = 1 in {
1070 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1071 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1072 "cmovb\t{$src2, $dst|$dst, $src2}",
1073 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1074 X86_COND_B, EFLAGS))]>, TB;
1075 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1076 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1077 "cmovae\t{$src2, $dst|$dst, $src2}",
1078 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1079 X86_COND_AE, EFLAGS))]>, TB;
1080 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1081 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1082 "cmove\t{$src2, $dst|$dst, $src2}",
1083 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1084 X86_COND_E, EFLAGS))]>, TB;
1085 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1086 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1087 "cmovne\t{$src2, $dst|$dst, $src2}",
1088 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1089 X86_COND_NE, EFLAGS))]>, TB;
1090 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1091 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1092 "cmovbe\t{$src2, $dst|$dst, $src2}",
1093 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1094 X86_COND_BE, EFLAGS))]>, TB;
1095 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1096 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1097 "cmova\t{$src2, $dst|$dst, $src2}",
1098 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1099 X86_COND_A, EFLAGS))]>, TB;
1100 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1101 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1102 "cmovl\t{$src2, $dst|$dst, $src2}",
1103 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1104 X86_COND_L, EFLAGS))]>, TB;
1105 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1106 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1107 "cmovge\t{$src2, $dst|$dst, $src2}",
1108 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1109 X86_COND_GE, EFLAGS))]>, TB;
1110 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1111 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1112 "cmovle\t{$src2, $dst|$dst, $src2}",
1113 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1114 X86_COND_LE, EFLAGS))]>, TB;
1115 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1116 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1117 "cmovg\t{$src2, $dst|$dst, $src2}",
1118 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1119 X86_COND_G, EFLAGS))]>, TB;
1120 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1121 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1122 "cmovs\t{$src2, $dst|$dst, $src2}",
1123 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1124 X86_COND_S, EFLAGS))]>, TB;
1125 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1126 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1127 "cmovns\t{$src2, $dst|$dst, $src2}",
1128 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1129 X86_COND_NS, EFLAGS))]>, TB;
1130 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1131 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1132 "cmovp\t{$src2, $dst|$dst, $src2}",
1133 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1134 X86_COND_P, EFLAGS))]>, TB;
1135 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1136 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1137 "cmovnp\t{$src2, $dst|$dst, $src2}",
1138 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1139 X86_COND_NP, EFLAGS))]>, TB;
1140 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1141 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1142 "cmovo\t{$src2, $dst|$dst, $src2}",
1143 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1144 X86_COND_O, EFLAGS))]>, TB;
1145 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1146 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1147 "cmovno\t{$src2, $dst|$dst, $src2}",
1148 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1149 X86_COND_NO, EFLAGS))]>, TB;
1150 } // isCommutable = 1
1152 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1153 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1154 "cmovb\t{$src2, $dst|$dst, $src2}",
1155 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1156 X86_COND_B, EFLAGS))]>, TB;
1157 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1158 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1159 "cmovae\t{$src2, $dst|$dst, $src2}",
1160 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1161 X86_COND_AE, EFLAGS))]>, TB;
1162 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1163 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1164 "cmove\t{$src2, $dst|$dst, $src2}",
1165 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1166 X86_COND_E, EFLAGS))]>, TB;
1167 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1168 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1169 "cmovne\t{$src2, $dst|$dst, $src2}",
1170 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1171 X86_COND_NE, EFLAGS))]>, TB;
1172 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1173 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1174 "cmovbe\t{$src2, $dst|$dst, $src2}",
1175 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1176 X86_COND_BE, EFLAGS))]>, TB;
1177 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1178 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1179 "cmova\t{$src2, $dst|$dst, $src2}",
1180 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1181 X86_COND_A, EFLAGS))]>, TB;
1182 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1183 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1184 "cmovl\t{$src2, $dst|$dst, $src2}",
1185 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1186 X86_COND_L, EFLAGS))]>, TB;
1187 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1188 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1189 "cmovge\t{$src2, $dst|$dst, $src2}",
1190 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1191 X86_COND_GE, EFLAGS))]>, TB;
1192 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1193 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1194 "cmovle\t{$src2, $dst|$dst, $src2}",
1195 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1196 X86_COND_LE, EFLAGS))]>, TB;
1197 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1198 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1199 "cmovg\t{$src2, $dst|$dst, $src2}",
1200 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1201 X86_COND_G, EFLAGS))]>, TB;
1202 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1203 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1204 "cmovs\t{$src2, $dst|$dst, $src2}",
1205 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1206 X86_COND_S, EFLAGS))]>, TB;
1207 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1208 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1209 "cmovns\t{$src2, $dst|$dst, $src2}",
1210 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1211 X86_COND_NS, EFLAGS))]>, TB;
1212 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1213 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1214 "cmovp\t{$src2, $dst|$dst, $src2}",
1215 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1216 X86_COND_P, EFLAGS))]>, TB;
1217 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1218 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1219 "cmovnp\t{$src2, $dst|$dst, $src2}",
1220 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1221 X86_COND_NP, EFLAGS))]>, TB;
1222 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1223 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1224 "cmovo\t{$src2, $dst|$dst, $src2}",
1225 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1226 X86_COND_O, EFLAGS))]>, TB;
1227 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1228 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1229 "cmovno\t{$src2, $dst|$dst, $src2}",
1230 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1231 X86_COND_NO, EFLAGS))]>, TB;
1234 //===----------------------------------------------------------------------===//
1235 // Conversion Instructions...
1238 // f64 -> signed i64
1239 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1240 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1242 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1243 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1244 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1245 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1246 (load addr:$src)))]>;
1247 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1248 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1249 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1250 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1251 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1252 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1253 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1254 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1256 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1257 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1258 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1260 (int_x86_sse2_cvttsd2si64
1261 (load addr:$src)))]>;
1263 // Signed i64 -> f64
1264 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1265 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1266 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1267 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1268 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1269 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1271 let isTwoAddress = 1 in {
1272 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1273 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1274 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1276 (int_x86_sse2_cvtsi642sd VR128:$src1,
1278 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1279 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1280 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1282 (int_x86_sse2_cvtsi642sd VR128:$src1,
1283 (loadi64 addr:$src2)))]>;
1286 // Signed i64 -> f32
1287 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1288 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1289 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1290 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1291 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1292 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1294 let isTwoAddress = 1 in {
1295 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1296 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1297 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1299 (int_x86_sse_cvtsi642ss VR128:$src1,
1301 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1302 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1303 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1305 (int_x86_sse_cvtsi642ss VR128:$src1,
1306 (loadi64 addr:$src2)))]>;
1309 // f32 -> signed i64
1310 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1311 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1313 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1314 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1315 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1316 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1317 (load addr:$src)))]>;
1318 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1319 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1320 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1321 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1322 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1323 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1324 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1325 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1327 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1328 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1329 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1331 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1333 //===----------------------------------------------------------------------===//
1334 // Alias Instructions
1335 //===----------------------------------------------------------------------===//
1337 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1338 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1340 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1341 // when we have a better way to specify isel priority.
1342 let AddedComplexity = 1 in
1344 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1347 // Materialize i64 constant where top 32-bits are zero.
1348 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1349 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1350 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1351 [(set GR64:$dst, i64immZExt32:$src)]>;
1353 //===----------------------------------------------------------------------===//
1354 // Thread Local Storage Instructions
1355 //===----------------------------------------------------------------------===//
1357 // All calls clobber the non-callee saved registers. RSP is marked as
1358 // a use to prevent stack-pointer assignments that appear immediately
1359 // before calls from potentially appearing dead.
1360 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1361 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1362 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1363 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1364 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1366 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1368 "leaq\t$sym(%rip), %rdi; "
1371 "call\t__tls_get_addr@PLT",
1372 [(X86tlsaddr tls64addr:$sym)]>,
1373 Requires<[In64BitMode]>;
1375 let AddedComplexity = 5, isCodeGenOnly = 1 in
1376 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1377 "movq\t%gs:$src, $dst",
1378 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1380 let AddedComplexity = 5, isCodeGenOnly = 1 in
1381 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1382 "movq\t%fs:$src, $dst",
1383 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1385 //===----------------------------------------------------------------------===//
1386 // Atomic Instructions
1387 //===----------------------------------------------------------------------===//
1389 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1390 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1392 "cmpxchgq\t$swap,$ptr",
1393 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1396 let Constraints = "$val = $dst" in {
1397 let Defs = [EFLAGS] in
1398 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1401 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1404 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1406 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1409 // Optimized codegen when the non-memory output is not used.
1410 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1411 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1413 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1414 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1415 (ins i64mem:$dst, i64i8imm :$src2),
1417 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1418 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1419 (ins i64mem:$dst, i64i32imm :$src2),
1421 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1422 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1424 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1425 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1426 (ins i64mem:$dst, i64i8imm :$src2),
1428 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1429 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1430 (ins i64mem:$dst, i64i32imm:$src2),
1432 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1433 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1435 "inc{q}\t$dst", []>, LOCK;
1436 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1438 "dec{q}\t$dst", []>, LOCK;
1440 // Atomic exchange, and, or, xor
1441 let Constraints = "$val = $dst", Defs = [EFLAGS],
1442 usesCustomDAGSchedInserter = 1 in {
1443 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1444 "#ATOMAND64 PSEUDO!",
1445 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1446 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1447 "#ATOMOR64 PSEUDO!",
1448 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1449 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1450 "#ATOMXOR64 PSEUDO!",
1451 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1452 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1453 "#ATOMNAND64 PSEUDO!",
1454 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1455 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1456 "#ATOMMIN64 PSEUDO!",
1457 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1458 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1459 "#ATOMMAX64 PSEUDO!",
1460 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1461 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1462 "#ATOMUMIN64 PSEUDO!",
1463 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1464 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1465 "#ATOMUMAX64 PSEUDO!",
1466 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1469 //===----------------------------------------------------------------------===//
1470 // Non-Instruction Patterns
1471 //===----------------------------------------------------------------------===//
1473 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1474 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1475 // 'movabs' predicate should handle this sort of thing.
1476 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1477 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1478 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1479 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1480 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1481 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1482 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1483 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1485 // In static codegen with small code model, we can get the address of a label
1486 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1487 // the MOV64ri64i32 should accept these.
1488 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1489 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1490 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1491 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1492 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1493 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1494 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1495 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1497 // In kernel code model, we can get the address of a label
1498 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1499 // the MOV64ri32 should accept these.
1500 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1501 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1502 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1503 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1504 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1505 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1506 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1507 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1509 // If we have small model and -static mode, it is safe to store global addresses
1510 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1511 // for MOV64mi32 should handle this sort of thing.
1512 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1513 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1514 Requires<[NearData, IsStatic]>;
1515 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1516 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1517 Requires<[NearData, IsStatic]>;
1518 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1519 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1520 Requires<[NearData, IsStatic]>;
1521 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1522 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1523 Requires<[NearData, IsStatic]>;
1526 // Direct PC relative function call for small code model. 32-bit displacement
1527 // sign extended to 64-bit.
1528 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1529 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1530 def : Pat<(X86call (i64 texternalsym:$dst)),
1531 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1533 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1534 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1535 def : Pat<(X86call (i64 texternalsym:$dst)),
1536 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1539 def : Pat<(X86tcret GR64:$dst, imm:$off),
1540 (TCRETURNri64 GR64:$dst, imm:$off)>;
1542 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1543 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1545 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1546 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1550 // TEST R,R is smaller than CMP R,0
1551 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1552 (TEST64rr GR64:$src1, GR64:$src1)>;
1554 // Conditional moves with folded loads with operands swapped and conditions
1556 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1557 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1558 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1559 (CMOVB64rm GR64:$src2, addr:$src1)>;
1560 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1561 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1562 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1563 (CMOVE64rm GR64:$src2, addr:$src1)>;
1564 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1565 (CMOVA64rm GR64:$src2, addr:$src1)>;
1566 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1567 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1568 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1569 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1570 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1571 (CMOVL64rm GR64:$src2, addr:$src1)>;
1572 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1573 (CMOVG64rm GR64:$src2, addr:$src1)>;
1574 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1575 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1576 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1577 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1578 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1579 (CMOVP64rm GR64:$src2, addr:$src1)>;
1580 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1581 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1582 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1583 (CMOVS64rm GR64:$src2, addr:$src1)>;
1584 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1585 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1586 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1587 (CMOVO64rm GR64:$src2, addr:$src1)>;
1589 // zextload bool -> zextload byte
1590 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1593 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1594 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1595 // partial-register updates.
1596 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1597 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1598 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1599 // For other extloads, use subregs, since the high contents of the register are
1600 // defined after an extload.
1601 def : Pat<(extloadi64i32 addr:$src),
1602 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1605 // anyext. Define these to do an explicit zero-extend to
1606 // avoid partial-register updates.
1607 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1608 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1609 def : Pat<(i64 (anyext GR32:$src)),
1610 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1612 //===----------------------------------------------------------------------===//
1614 //===----------------------------------------------------------------------===//
1616 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1617 // +128 doesn't, so in this special case use a sub instead of an add.
1618 def : Pat<(add GR64:$src1, 128),
1619 (SUB64ri8 GR64:$src1, -128)>;
1620 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1621 (SUB64mi8 addr:$dst, -128)>;
1623 // The same trick applies for 32-bit immediate fields in 64-bit
1625 def : Pat<(add GR64:$src1, 0x0000000080000000),
1626 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1627 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1628 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1630 // r & (2^32-1) ==> movz
1631 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1632 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1633 // r & (2^16-1) ==> movz
1634 def : Pat<(and GR64:$src, 0xffff),
1635 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1636 // r & (2^8-1) ==> movz
1637 def : Pat<(and GR64:$src, 0xff),
1638 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1639 // r & (2^8-1) ==> movz
1640 def : Pat<(and GR32:$src1, 0xff),
1641 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1642 Requires<[In64BitMode]>;
1643 // r & (2^8-1) ==> movz
1644 def : Pat<(and GR16:$src1, 0xff),
1645 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1646 Requires<[In64BitMode]>;
1648 // sext_inreg patterns
1649 def : Pat<(sext_inreg GR64:$src, i32),
1650 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1651 def : Pat<(sext_inreg GR64:$src, i16),
1652 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1653 def : Pat<(sext_inreg GR64:$src, i8),
1654 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1655 def : Pat<(sext_inreg GR32:$src, i8),
1656 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1657 Requires<[In64BitMode]>;
1658 def : Pat<(sext_inreg GR16:$src, i8),
1659 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1660 Requires<[In64BitMode]>;
1663 def : Pat<(i32 (trunc GR64:$src)),
1664 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1665 def : Pat<(i16 (trunc GR64:$src)),
1666 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1667 def : Pat<(i8 (trunc GR64:$src)),
1668 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1669 def : Pat<(i8 (trunc GR32:$src)),
1670 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1671 Requires<[In64BitMode]>;
1672 def : Pat<(i8 (trunc GR16:$src)),
1673 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1674 Requires<[In64BitMode]>;
1676 // h-register tricks.
1677 // For now, be conservative on x86-64 and use an h-register extract only if the
1678 // value is immediately zero-extended or stored, which are somewhat common
1679 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1680 // from being allocated in the same instruction as the h register, as there's
1681 // currently no way to describe this requirement to the register allocator.
1683 // h-register extract and zero-extend.
1684 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1688 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1689 x86_subreg_8bit_hi)),
1691 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1693 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1694 x86_subreg_8bit_hi))>,
1695 Requires<[In64BitMode]>;
1696 def : Pat<(srl_su GR16:$src, (i8 8)),
1699 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1700 x86_subreg_8bit_hi)),
1702 Requires<[In64BitMode]>;
1703 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1705 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1706 x86_subreg_8bit_hi))>,
1707 Requires<[In64BitMode]>;
1708 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1710 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1711 x86_subreg_8bit_hi))>,
1712 Requires<[In64BitMode]>;
1713 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1717 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1718 x86_subreg_8bit_hi)),
1720 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1724 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1725 x86_subreg_8bit_hi)),
1728 // h-register extract and store.
1729 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1732 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1733 x86_subreg_8bit_hi))>;
1734 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1737 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1738 x86_subreg_8bit_hi))>,
1739 Requires<[In64BitMode]>;
1740 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1743 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1744 x86_subreg_8bit_hi))>,
1745 Requires<[In64BitMode]>;
1747 // (shl x, 1) ==> (add x, x)
1748 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1750 // (shl x (and y, 63)) ==> (shl x, y)
1751 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1752 (SHL64rCL GR64:$src1)>;
1753 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1754 (SHL64mCL addr:$dst)>;
1756 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1757 (SHR64rCL GR64:$src1)>;
1758 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1759 (SHR64mCL addr:$dst)>;
1761 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1762 (SAR64rCL GR64:$src1)>;
1763 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1764 (SAR64mCL addr:$dst)>;
1766 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1767 def : Pat<(or (srl GR64:$src1, CL:$amt),
1768 (shl GR64:$src2, (sub 64, CL:$amt))),
1769 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1771 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1772 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1773 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1775 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1776 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1777 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1779 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1780 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1782 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1784 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1785 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1787 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1788 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1789 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1791 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1792 def : Pat<(or (shl GR64:$src1, CL:$amt),
1793 (srl GR64:$src2, (sub 64, CL:$amt))),
1794 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1796 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1797 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1798 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1800 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1801 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1802 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1804 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1805 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1807 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1809 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1810 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1812 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1813 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1814 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1816 // X86 specific add which produces a flag.
1817 def : Pat<(addc GR64:$src1, GR64:$src2),
1818 (ADD64rr GR64:$src1, GR64:$src2)>;
1819 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1820 (ADD64rm GR64:$src1, addr:$src2)>;
1821 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1822 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1823 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1824 (ADD64ri32 GR64:$src1, imm:$src2)>;
1826 def : Pat<(subc GR64:$src1, GR64:$src2),
1827 (SUB64rr GR64:$src1, GR64:$src2)>;
1828 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1829 (SUB64rm GR64:$src1, addr:$src2)>;
1830 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1831 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1832 def : Pat<(subc GR64:$src1, imm:$src2),
1833 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1835 //===----------------------------------------------------------------------===//
1836 // EFLAGS-defining Patterns
1837 //===----------------------------------------------------------------------===//
1839 // Register-Register Addition with EFLAGS result
1840 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1842 (ADD64rr GR64:$src1, GR64:$src2)>;
1844 // Register-Integer Addition with EFLAGS result
1845 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1847 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1848 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1850 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1852 // Register-Memory Addition with EFLAGS result
1853 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1855 (ADD64rm GR64:$src1, addr:$src2)>;
1857 // Memory-Register Addition with EFLAGS result
1858 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1861 (ADD64mr addr:$dst, GR64:$src2)>;
1862 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1865 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1866 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1869 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1871 // Register-Register Subtraction with EFLAGS result
1872 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1874 (SUB64rr GR64:$src1, GR64:$src2)>;
1876 // Register-Memory Subtraction with EFLAGS result
1877 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1879 (SUB64rm GR64:$src1, addr:$src2)>;
1881 // Register-Integer Subtraction with EFLAGS result
1882 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1884 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1885 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1887 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1889 // Memory-Register Subtraction with EFLAGS result
1890 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1893 (SUB64mr addr:$dst, GR64:$src2)>;
1895 // Memory-Integer Subtraction with EFLAGS result
1896 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1899 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1900 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1903 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1905 // Register-Register Signed Integer Multiplication with EFLAGS result
1906 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1908 (IMUL64rr GR64:$src1, GR64:$src2)>;
1910 // Register-Memory Signed Integer Multiplication with EFLAGS result
1911 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1913 (IMUL64rm GR64:$src1, addr:$src2)>;
1915 // Register-Integer Signed Integer Multiplication with EFLAGS result
1916 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1918 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1919 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1921 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1923 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1924 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1926 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1927 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1929 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1931 // INC and DEC with EFLAGS result. Note that these do not set CF.
1932 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1933 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1934 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1936 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1937 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1938 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1939 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1941 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1943 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1944 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1945 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1947 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1948 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1949 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1950 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1952 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1954 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1955 (INC64r GR64:$src)>;
1956 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1958 (INC64m addr:$dst)>;
1959 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1960 (DEC64r GR64:$src)>;
1961 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1963 (DEC64m addr:$dst)>;
1965 //===----------------------------------------------------------------------===//
1966 // X86-64 SSE Instructions
1967 //===----------------------------------------------------------------------===//
1969 // Move instructions...
1971 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1972 "mov{d|q}\t{$src, $dst|$dst, $src}",
1974 (v2i64 (scalar_to_vector GR64:$src)))]>;
1975 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1976 "mov{d|q}\t{$src, $dst|$dst, $src}",
1977 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1980 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1981 "mov{d|q}\t{$src, $dst|$dst, $src}",
1982 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1983 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1984 "movq\t{$src, $dst|$dst, $src}",
1985 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1987 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1988 "mov{d|q}\t{$src, $dst|$dst, $src}",
1989 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1990 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1991 "movq\t{$src, $dst|$dst, $src}",
1992 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1994 //===----------------------------------------------------------------------===//
1995 // X86-64 SSE4.1 Instructions
1996 //===----------------------------------------------------------------------===//
1998 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1999 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2000 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2001 (ins VR128:$src1, i32i8imm:$src2),
2002 !strconcat(OpcodeStr,
2003 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2005 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2006 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2007 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2008 !strconcat(OpcodeStr,
2009 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2010 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2011 addr:$dst)]>, OpSize, REX_W;
2014 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2016 let isTwoAddress = 1 in {
2017 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2018 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2019 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2020 !strconcat(OpcodeStr,
2021 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2023 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2025 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2026 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2027 !strconcat(OpcodeStr,
2028 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2030 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2031 imm:$src3)))]>, OpSize, REX_W;
2035 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;