1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 // Interrupt Instructions
115 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
117 //===----------------------------------------------------------------------===//
118 // Call Instructions...
121 // All calls clobber the non-callee saved registers. RSP is marked as
122 // a use to prevent stack-pointer assignments that appear immediately
123 // before calls from potentially appearing dead. Uses for argument
124 // registers are added manually.
125 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
126 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
127 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
128 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
129 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
132 // NOTE: this pattern doesn't match "X86call imm", because we do not know
133 // that the offset between an arbitrary immediate and the call will fit in
134 // the 32-bit pcrel field that we have.
135 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
136 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
137 "call{q}\t$dst", []>,
138 Requires<[In64BitMode, NotWin64]>;
139 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
140 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
141 Requires<[NotWin64]>;
142 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
143 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
144 Requires<[NotWin64]>;
146 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
147 "lcall{q}\t{*}$dst", []>;
150 // FIXME: We need to teach codegen about single list of call-clobbered
153 // All calls clobber the non-callee saved registers. RSP is marked as
154 // a use to prevent stack-pointer assignments that appear immediately
155 // before calls from potentially appearing dead. Uses for argument
156 // registers are added manually.
157 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
158 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
159 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
160 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
162 def WINCALL64pcrel32 : I<0xE8, RawFrm,
163 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
166 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
168 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
169 def WINCALL64m : I<0xFF, MRM2m, (outs),
170 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
171 [(X86call (loadi64 addr:$dst))]>,
176 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
177 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
179 "#TC_RETURN $dst $offset",
182 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
183 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
185 "#TC_RETURN $dst $offset",
189 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
190 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst, variable_ops),
191 "jmp{q}\t{*}$dst # TAILCALL",
195 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
196 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
198 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
199 [(brind GR64:$dst)]>;
200 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
201 [(brind (loadi64 addr:$dst))]>;
202 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
203 "ljmp{q}\t{*}$dst", []>;
206 //===----------------------------------------------------------------------===//
207 // EH Pseudo Instructions
209 let isTerminator = 1, isReturn = 1, isBarrier = 1,
210 hasCtrlDep = 1, isCodeGenOnly = 1 in {
211 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
212 "ret\t#eh_return, addr: $addr",
213 [(X86ehret GR64:$addr)]>;
217 //===----------------------------------------------------------------------===//
218 // Miscellaneous Instructions...
221 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
222 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
223 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
224 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
226 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
227 def LEAVE64 : I<0xC9, RawFrm,
228 (outs), (ins), "leave", []>;
229 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
231 def POP64r : I<0x58, AddRegFrm,
232 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
233 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
234 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
236 let mayStore = 1 in {
237 def PUSH64r : I<0x50, AddRegFrm,
238 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
239 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
240 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
244 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
245 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
246 "push{q}\t$imm", []>;
247 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
248 "push{q}\t$imm", []>;
249 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
250 "push{q}\t$imm", []>;
253 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
254 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
255 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
256 def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
258 def LEA64_32r : I<0x8D, MRMSrcMem,
259 (outs GR32:$dst), (ins lea64_32mem:$src),
260 "lea{l}\t{$src|$dst}, {$dst|$src}",
261 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
263 let isReMaterializable = 1 in
264 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
265 "lea{q}\t{$src|$dst}, {$dst|$src}",
266 [(set GR64:$dst, lea64addr:$src)]>;
268 let isTwoAddress = 1 in
269 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
271 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
273 // Bit scan instructions.
274 let Defs = [EFLAGS] in {
275 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
276 "bsf{q}\t{$src, $dst|$dst, $src}",
277 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
278 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
279 "bsf{q}\t{$src, $dst|$dst, $src}",
280 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
281 (implicit EFLAGS)]>, TB;
283 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
284 "bsr{q}\t{$src, $dst|$dst, $src}",
285 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
286 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
287 "bsr{q}\t{$src, $dst|$dst, $src}",
288 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
289 (implicit EFLAGS)]>, TB;
293 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
294 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
295 [(X86rep_movs i64)]>, REP;
296 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
297 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
298 [(X86rep_stos i64)]>, REP;
300 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
302 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
304 // Fast system-call instructions
305 def SYSEXIT64 : RI<0x35, RawFrm,
306 (outs), (ins), "sysexit", []>, TB;
308 //===----------------------------------------------------------------------===//
309 // Move Instructions...
312 let neverHasSideEffects = 1 in
313 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
314 "mov{q}\t{$src, $dst|$dst, $src}", []>;
316 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
317 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
318 "movabs{q}\t{$src, $dst|$dst, $src}",
319 [(set GR64:$dst, imm:$src)]>;
320 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
321 "mov{q}\t{$src, $dst|$dst, $src}",
322 [(set GR64:$dst, i64immSExt32:$src)]>;
325 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
326 "mov{q}\t{$src, $dst|$dst, $src}", []>;
328 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
329 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
330 "mov{q}\t{$src, $dst|$dst, $src}",
331 [(set GR64:$dst, (load addr:$src))]>;
333 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
334 "mov{q}\t{$src, $dst|$dst, $src}",
335 [(store GR64:$src, addr:$dst)]>;
336 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
337 "mov{q}\t{$src, $dst|$dst, $src}",
338 [(store i64immSExt32:$src, addr:$dst)]>;
340 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
341 "mov{q}\t{$src, %rax|%rax, $src}", []>;
342 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
343 "mov{q}\t{$src, %rax|%rax, $src}", []>;
344 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
345 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
346 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
347 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
349 // Moves to and from segment registers
350 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
351 "mov{q}\t{$src, $dst|$dst, $src}", []>;
352 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
353 "mov{q}\t{$src, $dst|$dst, $src}", []>;
354 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
355 "mov{q}\t{$src, $dst|$dst, $src}", []>;
356 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
357 "mov{q}\t{$src, $dst|$dst, $src}", []>;
359 // Moves to and from debug registers
360 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
361 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
362 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
363 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
365 // Moves to and from control registers
366 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
367 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
368 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
369 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
371 // Sign/Zero extenders
373 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
374 // operand, which makes it a rare instruction with an 8-bit register
375 // operand that can never access an h register. If support for h registers
376 // were generalized, this would require a special register class.
377 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
378 "movs{bq|x}\t{$src, $dst|$dst, $src}",
379 [(set GR64:$dst, (sext GR8:$src))]>, TB;
380 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
381 "movs{bq|x}\t{$src, $dst|$dst, $src}",
382 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
383 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
384 "movs{wq|x}\t{$src, $dst|$dst, $src}",
385 [(set GR64:$dst, (sext GR16:$src))]>, TB;
386 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
387 "movs{wq|x}\t{$src, $dst|$dst, $src}",
388 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
389 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
390 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
391 [(set GR64:$dst, (sext GR32:$src))]>;
392 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
393 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
394 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
396 // movzbq and movzwq encodings for the disassembler
397 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
398 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
399 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
400 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
401 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
402 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
403 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
404 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
406 // Use movzbl instead of movzbq when the destination is a register; it's
407 // equivalent due to implicit zero-extending, and it has a smaller encoding.
408 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
409 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
410 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
411 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
412 // Use movzwl instead of movzwq when the destination is a register; it's
413 // equivalent due to implicit zero-extending, and it has a smaller encoding.
414 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
415 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
416 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
417 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
419 // There's no movzlq instruction, but movl can be used for this purpose, using
420 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
421 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
422 // zero-extension, however this isn't possible when the 32-bit value is
423 // defined by a truncate or is copied from something where the high bits aren't
424 // necessarily all zero. In such cases, we fall back to these explicit zext
426 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
427 "", [(set GR64:$dst, (zext GR32:$src))]>;
428 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
429 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
431 // Any instruction that defines a 32-bit result leaves the high half of the
432 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
433 // be copying from a truncate. And x86's cmov doesn't do anything if the
434 // condition is false. But any other 32-bit operation will zero-extend
436 def def32 : PatLeaf<(i32 GR32:$src), [{
437 return N->getOpcode() != ISD::TRUNCATE &&
438 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
439 N->getOpcode() != ISD::CopyFromReg &&
440 N->getOpcode() != X86ISD::CMOV;
443 // In the case of a 32-bit def that is known to implicitly zero-extend,
444 // we can use a SUBREG_TO_REG.
445 def : Pat<(i64 (zext def32:$src)),
446 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
448 let neverHasSideEffects = 1 in {
449 let Defs = [RAX], Uses = [EAX] in
450 def CDQE : RI<0x98, RawFrm, (outs), (ins),
451 "{cltq|cdqe}", []>; // RAX = signext(EAX)
453 let Defs = [RAX,RDX], Uses = [RAX] in
454 def CQO : RI<0x99, RawFrm, (outs), (ins),
455 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
458 //===----------------------------------------------------------------------===//
459 // Arithmetic Instructions...
462 let Defs = [EFLAGS] in {
464 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
465 "add{q}\t{$src, %rax|%rax, $src}", []>;
467 let isTwoAddress = 1 in {
468 let isConvertibleToThreeAddress = 1 in {
469 let isCommutable = 1 in
470 // Register-Register Addition
471 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
472 (ins GR64:$src1, GR64:$src2),
473 "add{q}\t{$src2, $dst|$dst, $src2}",
474 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
477 // Register-Integer Addition
478 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
479 (ins GR64:$src1, i64i8imm:$src2),
480 "add{q}\t{$src2, $dst|$dst, $src2}",
481 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
483 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
484 (ins GR64:$src1, i64i32imm:$src2),
485 "add{q}\t{$src2, $dst|$dst, $src2}",
486 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
488 } // isConvertibleToThreeAddress
490 // Register-Memory Addition
491 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
492 (ins GR64:$src1, i64mem:$src2),
493 "add{q}\t{$src2, $dst|$dst, $src2}",
494 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
497 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
498 // differently encoded.
499 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
500 (ins GR64:$src1, GR64:$src2),
501 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
505 // Memory-Register Addition
506 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
507 "add{q}\t{$src2, $dst|$dst, $src2}",
508 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
510 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
511 "add{q}\t{$src2, $dst|$dst, $src2}",
512 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
514 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
515 "add{q}\t{$src2, $dst|$dst, $src2}",
516 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
519 let Uses = [EFLAGS] in {
521 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
522 "adc{q}\t{$src, %rax|%rax, $src}", []>;
524 let isTwoAddress = 1 in {
525 let isCommutable = 1 in
526 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
527 (ins GR64:$src1, GR64:$src2),
528 "adc{q}\t{$src2, $dst|$dst, $src2}",
529 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
531 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
532 (ins GR64:$src1, GR64:$src2),
533 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
535 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
536 (ins GR64:$src1, i64mem:$src2),
537 "adc{q}\t{$src2, $dst|$dst, $src2}",
538 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
540 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
541 (ins GR64:$src1, i64i8imm:$src2),
542 "adc{q}\t{$src2, $dst|$dst, $src2}",
543 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
544 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
545 (ins GR64:$src1, i64i32imm:$src2),
546 "adc{q}\t{$src2, $dst|$dst, $src2}",
547 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
550 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
551 "adc{q}\t{$src2, $dst|$dst, $src2}",
552 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
553 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
554 "adc{q}\t{$src2, $dst|$dst, $src2}",
555 [(store (adde (load addr:$dst), i64immSExt8:$src2),
557 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
558 "adc{q}\t{$src2, $dst|$dst, $src2}",
559 [(store (adde (load addr:$dst), i64immSExt8:$src2),
563 let isTwoAddress = 1 in {
564 // Register-Register Subtraction
565 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
566 (ins GR64:$src1, GR64:$src2),
567 "sub{q}\t{$src2, $dst|$dst, $src2}",
568 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
571 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
572 (ins GR64:$src1, GR64:$src2),
573 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
575 // Register-Memory Subtraction
576 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
577 (ins GR64:$src1, i64mem:$src2),
578 "sub{q}\t{$src2, $dst|$dst, $src2}",
579 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
582 // Register-Integer Subtraction
583 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
584 (ins GR64:$src1, i64i8imm:$src2),
585 "sub{q}\t{$src2, $dst|$dst, $src2}",
586 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
588 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
589 (ins GR64:$src1, i64i32imm:$src2),
590 "sub{q}\t{$src2, $dst|$dst, $src2}",
591 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
595 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
596 "sub{q}\t{$src, %rax|%rax, $src}", []>;
598 // Memory-Register Subtraction
599 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
600 "sub{q}\t{$src2, $dst|$dst, $src2}",
601 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
604 // Memory-Integer Subtraction
605 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
606 "sub{q}\t{$src2, $dst|$dst, $src2}",
607 [(store (sub (load addr:$dst), i64immSExt8:$src2),
610 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
611 "sub{q}\t{$src2, $dst|$dst, $src2}",
612 [(store (sub (load addr:$dst), i64immSExt32:$src2),
616 let Uses = [EFLAGS] in {
617 let isTwoAddress = 1 in {
618 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
619 (ins GR64:$src1, GR64:$src2),
620 "sbb{q}\t{$src2, $dst|$dst, $src2}",
621 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
623 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
624 (ins GR64:$src1, GR64:$src2),
625 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
627 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
628 (ins GR64:$src1, i64mem:$src2),
629 "sbb{q}\t{$src2, $dst|$dst, $src2}",
630 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
632 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
633 (ins GR64:$src1, i64i8imm:$src2),
634 "sbb{q}\t{$src2, $dst|$dst, $src2}",
635 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
636 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
637 (ins GR64:$src1, i64i32imm:$src2),
638 "sbb{q}\t{$src2, $dst|$dst, $src2}",
639 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
642 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
643 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
645 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
646 "sbb{q}\t{$src2, $dst|$dst, $src2}",
647 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
648 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
649 "sbb{q}\t{$src2, $dst|$dst, $src2}",
650 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
651 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
652 "sbb{q}\t{$src2, $dst|$dst, $src2}",
653 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
657 // Unsigned multiplication
658 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
659 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
660 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
662 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
663 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
665 // Signed multiplication
666 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
667 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
669 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
670 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
673 let Defs = [EFLAGS] in {
674 let isTwoAddress = 1 in {
675 let isCommutable = 1 in
676 // Register-Register Signed Integer Multiplication
677 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
678 (ins GR64:$src1, GR64:$src2),
679 "imul{q}\t{$src2, $dst|$dst, $src2}",
680 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
681 (implicit EFLAGS)]>, TB;
683 // Register-Memory Signed Integer Multiplication
684 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
685 (ins GR64:$src1, i64mem:$src2),
686 "imul{q}\t{$src2, $dst|$dst, $src2}",
687 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
688 (implicit EFLAGS)]>, TB;
691 // Suprisingly enough, these are not two address instructions!
693 // Register-Integer Signed Integer Multiplication
694 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
695 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
696 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
697 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
699 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
700 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
701 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
702 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
705 // Memory-Integer Signed Integer Multiplication
706 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
707 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
708 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
709 [(set GR64:$dst, (mul (load addr:$src1),
712 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
713 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
714 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 [(set GR64:$dst, (mul (load addr:$src1),
716 i64immSExt32:$src2)),
720 // Unsigned division / remainder
721 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
722 // RDX:RAX/r64 = RAX,RDX
723 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
725 // Signed division / remainder
726 // RDX:RAX/r64 = RAX,RDX
727 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
728 "idiv{q}\t$src", []>;
730 // RDX:RAX/[mem64] = RAX,RDX
731 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
733 // RDX:RAX/[mem64] = RAX,RDX
734 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
735 "idiv{q}\t$src", []>;
739 // Unary instructions
740 let Defs = [EFLAGS], CodeSize = 2 in {
741 let isTwoAddress = 1 in
742 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
743 [(set GR64:$dst, (ineg GR64:$src)),
745 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
746 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
749 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
750 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
751 [(set GR64:$dst, (add GR64:$src, 1)),
753 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
754 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
757 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
758 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
759 [(set GR64:$dst, (add GR64:$src, -1)),
761 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
762 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
765 // In 64-bit mode, single byte INC and DEC cannot be encoded.
766 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
767 // Can transform into LEA.
768 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
770 [(set GR16:$dst, (add GR16:$src, 1)),
772 OpSize, Requires<[In64BitMode]>;
773 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
775 [(set GR32:$dst, (add GR32:$src, 1)),
777 Requires<[In64BitMode]>;
778 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
780 [(set GR16:$dst, (add GR16:$src, -1)),
782 OpSize, Requires<[In64BitMode]>;
783 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
785 [(set GR32:$dst, (add GR32:$src, -1)),
787 Requires<[In64BitMode]>;
788 } // isConvertibleToThreeAddress
790 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
791 // how to unfold them.
792 let isTwoAddress = 0, CodeSize = 2 in {
793 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
794 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
796 OpSize, Requires<[In64BitMode]>;
797 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
798 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
800 Requires<[In64BitMode]>;
801 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
802 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
804 OpSize, Requires<[In64BitMode]>;
805 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
806 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
808 Requires<[In64BitMode]>;
810 } // Defs = [EFLAGS], CodeSize
813 let Defs = [EFLAGS] in {
814 // Shift instructions
815 let isTwoAddress = 1 in {
817 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
818 "shl{q}\t{%cl, $dst|$dst, %CL}",
819 [(set GR64:$dst, (shl GR64:$src, CL))]>;
820 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
821 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
822 (ins GR64:$src1, i8imm:$src2),
823 "shl{q}\t{$src2, $dst|$dst, $src2}",
824 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
825 // NOTE: We don't include patterns for shifts of a register by one, because
826 // 'add reg,reg' is cheaper.
827 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
832 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
833 "shl{q}\t{%cl, $dst|$dst, %CL}",
834 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
835 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
836 "shl{q}\t{$src, $dst|$dst, $src}",
837 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
838 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
840 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
842 let isTwoAddress = 1 in {
844 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
845 "shr{q}\t{%cl, $dst|$dst, %CL}",
846 [(set GR64:$dst, (srl GR64:$src, CL))]>;
847 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
848 "shr{q}\t{$src2, $dst|$dst, $src2}",
849 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
850 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
852 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
856 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
857 "shr{q}\t{%cl, $dst|$dst, %CL}",
858 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
859 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
860 "shr{q}\t{$src, $dst|$dst, $src}",
861 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
862 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
864 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
866 let isTwoAddress = 1 in {
868 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
869 "sar{q}\t{%cl, $dst|$dst, %CL}",
870 [(set GR64:$dst, (sra GR64:$src, CL))]>;
871 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
872 (ins GR64:$src1, i8imm:$src2),
873 "sar{q}\t{$src2, $dst|$dst, $src2}",
874 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
875 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
877 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
881 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
882 "sar{q}\t{%cl, $dst|$dst, %CL}",
883 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
884 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
885 "sar{q}\t{$src, $dst|$dst, $src}",
886 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
887 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
889 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
891 // Rotate instructions
893 let isTwoAddress = 1 in {
894 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
895 "rcl{q}\t{1, $dst|$dst, 1}", []>;
896 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
897 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
899 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
900 "rcr{q}\t{1, $dst|$dst, 1}", []>;
901 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
902 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
905 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
906 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
907 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
908 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
912 let isTwoAddress = 0 in {
913 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
914 "rcl{q}\t{1, $dst|$dst, 1}", []>;
915 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
916 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
917 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
918 "rcr{q}\t{1, $dst|$dst, 1}", []>;
919 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
920 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
923 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
924 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
925 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
926 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
930 let isTwoAddress = 1 in {
932 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
933 "rol{q}\t{%cl, $dst|$dst, %CL}",
934 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
935 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
936 (ins GR64:$src1, i8imm:$src2),
937 "rol{q}\t{$src2, $dst|$dst, $src2}",
938 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
939 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
941 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
945 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
946 "rol{q}\t{%cl, $dst|$dst, %CL}",
947 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
948 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
949 "rol{q}\t{$src, $dst|$dst, $src}",
950 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
951 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
953 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
955 let isTwoAddress = 1 in {
957 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
958 "ror{q}\t{%cl, $dst|$dst, %CL}",
959 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
960 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
961 (ins GR64:$src1, i8imm:$src2),
962 "ror{q}\t{$src2, $dst|$dst, $src2}",
963 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
964 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
966 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
970 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
971 "ror{q}\t{%cl, $dst|$dst, %CL}",
972 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
973 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
974 "ror{q}\t{$src, $dst|$dst, $src}",
975 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
976 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
978 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
980 // Double shift instructions (generalizations of rotate)
981 let isTwoAddress = 1 in {
983 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
984 (ins GR64:$src1, GR64:$src2),
985 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
986 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
988 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
989 (ins GR64:$src1, GR64:$src2),
990 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
991 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
995 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
996 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
998 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
999 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1000 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1003 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1005 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1006 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1007 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1013 let Uses = [CL] in {
1014 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1015 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1016 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1018 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1019 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1020 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1023 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1024 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1025 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1026 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1027 (i8 imm:$src3)), addr:$dst)]>,
1029 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1030 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1031 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1032 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1033 (i8 imm:$src3)), addr:$dst)]>,
1035 } // Defs = [EFLAGS]
1037 //===----------------------------------------------------------------------===//
1038 // Logical Instructions...
1041 let isTwoAddress = 1 , AddedComplexity = 15 in
1042 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1043 [(set GR64:$dst, (not GR64:$src))]>;
1044 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1045 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1047 let Defs = [EFLAGS] in {
1048 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
1049 "and{q}\t{$src, %rax|%rax, $src}", []>;
1051 let isTwoAddress = 1 in {
1052 let isCommutable = 1 in
1053 def AND64rr : RI<0x21, MRMDestReg,
1054 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1055 "and{q}\t{$src2, $dst|$dst, $src2}",
1056 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
1057 (implicit EFLAGS)]>;
1058 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1059 (ins GR64:$src1, GR64:$src2),
1060 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
1061 def AND64rm : RI<0x23, MRMSrcMem,
1062 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1063 "and{q}\t{$src2, $dst|$dst, $src2}",
1064 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
1065 (implicit EFLAGS)]>;
1066 def AND64ri8 : RIi8<0x83, MRM4r,
1067 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1068 "and{q}\t{$src2, $dst|$dst, $src2}",
1069 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
1070 (implicit EFLAGS)]>;
1071 def AND64ri32 : RIi32<0x81, MRM4r,
1072 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1073 "and{q}\t{$src2, $dst|$dst, $src2}",
1074 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
1075 (implicit EFLAGS)]>;
1078 def AND64mr : RI<0x21, MRMDestMem,
1079 (outs), (ins i64mem:$dst, GR64:$src),
1080 "and{q}\t{$src, $dst|$dst, $src}",
1081 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
1082 (implicit EFLAGS)]>;
1083 def AND64mi8 : RIi8<0x83, MRM4m,
1084 (outs), (ins i64mem:$dst, i64i8imm :$src),
1085 "and{q}\t{$src, $dst|$dst, $src}",
1086 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1087 (implicit EFLAGS)]>;
1088 def AND64mi32 : RIi32<0x81, MRM4m,
1089 (outs), (ins i64mem:$dst, i64i32imm:$src),
1090 "and{q}\t{$src, $dst|$dst, $src}",
1091 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1092 (implicit EFLAGS)]>;
1094 let isTwoAddress = 1 in {
1095 let isCommutable = 1 in
1096 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1097 (ins GR64:$src1, GR64:$src2),
1098 "or{q}\t{$src2, $dst|$dst, $src2}",
1099 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
1100 (implicit EFLAGS)]>;
1101 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1102 (ins GR64:$src1, GR64:$src2),
1103 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1104 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1105 (ins GR64:$src1, i64mem:$src2),
1106 "or{q}\t{$src2, $dst|$dst, $src2}",
1107 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
1108 (implicit EFLAGS)]>;
1109 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1110 (ins GR64:$src1, i64i8imm:$src2),
1111 "or{q}\t{$src2, $dst|$dst, $src2}",
1112 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
1113 (implicit EFLAGS)]>;
1114 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1115 (ins GR64:$src1, i64i32imm:$src2),
1116 "or{q}\t{$src2, $dst|$dst, $src2}",
1117 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
1118 (implicit EFLAGS)]>;
1121 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1122 "or{q}\t{$src, $dst|$dst, $src}",
1123 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1124 (implicit EFLAGS)]>;
1125 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1126 "or{q}\t{$src, $dst|$dst, $src}",
1127 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1128 (implicit EFLAGS)]>;
1129 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1130 "or{q}\t{$src, $dst|$dst, $src}",
1131 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1132 (implicit EFLAGS)]>;
1134 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1135 "or{q}\t{$src, %rax|%rax, $src}", []>;
1137 let isTwoAddress = 1 in {
1138 let isCommutable = 1 in
1139 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1140 (ins GR64:$src1, GR64:$src2),
1141 "xor{q}\t{$src2, $dst|$dst, $src2}",
1142 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1143 (implicit EFLAGS)]>;
1144 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1145 (ins GR64:$src1, GR64:$src2),
1146 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1147 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1148 (ins GR64:$src1, i64mem:$src2),
1149 "xor{q}\t{$src2, $dst|$dst, $src2}",
1150 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1151 (implicit EFLAGS)]>;
1152 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1153 (ins GR64:$src1, i64i8imm:$src2),
1154 "xor{q}\t{$src2, $dst|$dst, $src2}",
1155 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1156 (implicit EFLAGS)]>;
1157 def XOR64ri32 : RIi32<0x81, MRM6r,
1158 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1159 "xor{q}\t{$src2, $dst|$dst, $src2}",
1160 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1161 (implicit EFLAGS)]>;
1164 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1165 "xor{q}\t{$src, $dst|$dst, $src}",
1166 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1167 (implicit EFLAGS)]>;
1168 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1169 "xor{q}\t{$src, $dst|$dst, $src}",
1170 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1171 (implicit EFLAGS)]>;
1172 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1173 "xor{q}\t{$src, $dst|$dst, $src}",
1174 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1175 (implicit EFLAGS)]>;
1177 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1178 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1180 } // Defs = [EFLAGS]
1182 //===----------------------------------------------------------------------===//
1183 // Comparison Instructions...
1186 // Integer comparison
1187 let Defs = [EFLAGS] in {
1188 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1189 "test{q}\t{$src, %rax|%rax, $src}", []>;
1190 let isCommutable = 1 in
1191 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1192 "test{q}\t{$src2, $src1|$src1, $src2}",
1193 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1194 (implicit EFLAGS)]>;
1195 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1196 "test{q}\t{$src2, $src1|$src1, $src2}",
1197 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1198 (implicit EFLAGS)]>;
1199 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1200 (ins GR64:$src1, i64i32imm:$src2),
1201 "test{q}\t{$src2, $src1|$src1, $src2}",
1202 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1203 (implicit EFLAGS)]>;
1204 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1205 (ins i64mem:$src1, i64i32imm:$src2),
1206 "test{q}\t{$src2, $src1|$src1, $src2}",
1207 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1208 (implicit EFLAGS)]>;
1211 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1212 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1213 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1214 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1215 [(X86cmp GR64:$src1, GR64:$src2),
1216 (implicit EFLAGS)]>;
1217 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1218 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1219 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1220 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1221 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1222 (implicit EFLAGS)]>;
1223 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1224 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1225 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1226 (implicit EFLAGS)]>;
1227 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1228 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1229 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1230 (implicit EFLAGS)]>;
1231 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1232 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1233 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1234 (implicit EFLAGS)]>;
1235 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1236 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1237 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1238 (implicit EFLAGS)]>;
1239 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1240 (ins i64mem:$src1, i64i32imm:$src2),
1241 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1242 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1243 (implicit EFLAGS)]>;
1244 } // Defs = [EFLAGS]
1247 // TODO: BTC, BTR, and BTS
1248 let Defs = [EFLAGS] in {
1249 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1250 "bt{q}\t{$src2, $src1|$src1, $src2}",
1251 [(X86bt GR64:$src1, GR64:$src2),
1252 (implicit EFLAGS)]>, TB;
1254 // Unlike with the register+register form, the memory+register form of the
1255 // bt instruction does not ignore the high bits of the index. From ISel's
1256 // perspective, this is pretty bizarre. Disable these instructions for now.
1257 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1258 "bt{q}\t{$src2, $src1|$src1, $src2}",
1259 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1260 // (implicit EFLAGS)]
1264 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1265 "bt{q}\t{$src2, $src1|$src1, $src2}",
1266 [(X86bt GR64:$src1, i64immSExt8:$src2),
1267 (implicit EFLAGS)]>, TB;
1268 // Note that these instructions don't need FastBTMem because that
1269 // only applies when the other operand is in a register. When it's
1270 // an immediate, bt is still fast.
1271 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1272 "bt{q}\t{$src2, $src1|$src1, $src2}",
1273 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1274 (implicit EFLAGS)]>, TB;
1276 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1277 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1278 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1279 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1280 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1281 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1282 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1283 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1285 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1286 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1287 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1288 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1289 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1290 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1291 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1292 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1294 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1295 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1296 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1297 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1298 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1299 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1300 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1301 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1302 } // Defs = [EFLAGS]
1304 // Conditional moves
1305 let Uses = [EFLAGS], isTwoAddress = 1 in {
1306 let isCommutable = 1 in {
1307 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1308 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1309 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1311 X86_COND_B, EFLAGS))]>, TB;
1312 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1313 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1314 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1315 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1316 X86_COND_AE, EFLAGS))]>, TB;
1317 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1318 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1319 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1321 X86_COND_E, EFLAGS))]>, TB;
1322 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1323 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1324 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1326 X86_COND_NE, EFLAGS))]>, TB;
1327 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1328 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1329 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1330 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1331 X86_COND_BE, EFLAGS))]>, TB;
1332 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1333 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1334 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1335 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1336 X86_COND_A, EFLAGS))]>, TB;
1337 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1338 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1339 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1340 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1341 X86_COND_L, EFLAGS))]>, TB;
1342 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1343 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1344 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1345 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1346 X86_COND_GE, EFLAGS))]>, TB;
1347 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1348 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1349 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1350 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1351 X86_COND_LE, EFLAGS))]>, TB;
1352 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1353 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1354 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1356 X86_COND_G, EFLAGS))]>, TB;
1357 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1358 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1359 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1360 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1361 X86_COND_S, EFLAGS))]>, TB;
1362 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1363 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1364 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1366 X86_COND_NS, EFLAGS))]>, TB;
1367 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1368 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1369 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1371 X86_COND_P, EFLAGS))]>, TB;
1372 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1373 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1374 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1375 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1376 X86_COND_NP, EFLAGS))]>, TB;
1377 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1378 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1379 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1380 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1381 X86_COND_O, EFLAGS))]>, TB;
1382 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1383 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1384 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1386 X86_COND_NO, EFLAGS))]>, TB;
1387 } // isCommutable = 1
1389 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1390 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1391 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1393 X86_COND_B, EFLAGS))]>, TB;
1394 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1395 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1396 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1398 X86_COND_AE, EFLAGS))]>, TB;
1399 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1400 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1401 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1403 X86_COND_E, EFLAGS))]>, TB;
1404 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1405 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1406 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1408 X86_COND_NE, EFLAGS))]>, TB;
1409 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1410 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1411 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1412 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1413 X86_COND_BE, EFLAGS))]>, TB;
1414 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1415 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1416 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1418 X86_COND_A, EFLAGS))]>, TB;
1419 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1420 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1421 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1422 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1423 X86_COND_L, EFLAGS))]>, TB;
1424 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1425 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1426 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1428 X86_COND_GE, EFLAGS))]>, TB;
1429 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1430 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1431 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1432 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1433 X86_COND_LE, EFLAGS))]>, TB;
1434 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1435 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1436 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1438 X86_COND_G, EFLAGS))]>, TB;
1439 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1440 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1441 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1443 X86_COND_S, EFLAGS))]>, TB;
1444 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1445 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1446 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1448 X86_COND_NS, EFLAGS))]>, TB;
1449 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1450 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1451 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1452 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1453 X86_COND_P, EFLAGS))]>, TB;
1454 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1455 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1456 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1458 X86_COND_NP, EFLAGS))]>, TB;
1459 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1460 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1461 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1463 X86_COND_O, EFLAGS))]>, TB;
1464 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1465 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1466 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1467 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1468 X86_COND_NO, EFLAGS))]>, TB;
1471 // Use sbb to materialize carry flag into a GPR.
1472 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1473 // However, Pat<> can't replicate the destination reg into the inputs of the
1475 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1477 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1478 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1479 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1481 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1484 //===----------------------------------------------------------------------===//
1485 // Conversion Instructions...
1488 // f64 -> signed i64
1489 def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1490 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1491 def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1492 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1493 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1494 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1496 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1497 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1499 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1500 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1501 (load addr:$src)))]>;
1502 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1505 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1506 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1507 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1508 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1509 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1511 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1512 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1514 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1516 (int_x86_sse2_cvttsd2si64
1517 (load addr:$src)))]>;
1519 // Signed i64 -> f64
1520 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1521 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1522 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1523 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1524 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1525 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1527 let isTwoAddress = 1 in {
1528 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1529 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1530 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1532 (int_x86_sse2_cvtsi642sd VR128:$src1,
1534 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1535 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1536 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1538 (int_x86_sse2_cvtsi642sd VR128:$src1,
1539 (loadi64 addr:$src2)))]>;
1542 // Signed i64 -> f32
1543 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1544 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1545 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1546 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1547 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1548 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1550 let isTwoAddress = 1 in {
1551 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1552 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1553 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1555 (int_x86_sse_cvtsi642ss VR128:$src1,
1557 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1559 (ins VR128:$src1, i64mem:$src2),
1560 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1562 (int_x86_sse_cvtsi642ss VR128:$src1,
1563 (loadi64 addr:$src2)))]>;
1566 // f32 -> signed i64
1567 def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1568 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1569 def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1570 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1571 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1572 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1574 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1575 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1576 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1577 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1578 (load addr:$src)))]>;
1579 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1580 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1581 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1582 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1583 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1584 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1585 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1586 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1588 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1589 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1591 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1593 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1595 // Descriptor-table support instructions
1597 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1599 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1600 "sldt{q}\t$dst", []>, TB;
1601 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1602 "sldt{q}\t$dst", []>, TB;
1604 //===----------------------------------------------------------------------===//
1605 // Alias Instructions
1606 //===----------------------------------------------------------------------===//
1608 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1609 // smaller encoding, but doing so at isel time interferes with rematerialization
1610 // in the current register allocator. For now, this is rewritten when the
1611 // instruction is lowered to an MCInst.
1612 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1613 // when we have a better way to specify isel priority.
1614 let Defs = [EFLAGS],
1615 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1616 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1617 [(set GR64:$dst, 0)]>;
1619 // Materialize i64 constant where top 32-bits are zero. This could theoretically
1620 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1621 // that would make it more difficult to rematerialize.
1622 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1623 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1624 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1626 //===----------------------------------------------------------------------===//
1627 // Thread Local Storage Instructions
1628 //===----------------------------------------------------------------------===//
1630 // All calls clobber the non-callee saved registers. RSP is marked as
1631 // a use to prevent stack-pointer assignments that appear immediately
1632 // before calls from potentially appearing dead.
1633 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1634 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1635 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1636 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1637 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1639 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1641 "leaq\t$sym(%rip), %rdi; "
1644 "call\t__tls_get_addr@PLT",
1645 [(X86tlsaddr tls64addr:$sym)]>,
1646 Requires<[In64BitMode]>;
1648 let AddedComplexity = 5, isCodeGenOnly = 1 in
1649 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1650 "movq\t%gs:$src, $dst",
1651 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1653 let AddedComplexity = 5, isCodeGenOnly = 1 in
1654 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1655 "movq\t%fs:$src, $dst",
1656 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1658 //===----------------------------------------------------------------------===//
1659 // Atomic Instructions
1660 //===----------------------------------------------------------------------===//
1662 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1663 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1665 "cmpxchgq\t$swap,$ptr",
1666 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1669 let Constraints = "$val = $dst" in {
1670 let Defs = [EFLAGS] in
1671 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1674 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1677 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1678 (ins GR64:$val,i64mem:$ptr),
1679 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1680 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1682 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1683 "xchg{q}\t{$val, $src|$src, $val}", []>;
1686 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1687 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1688 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1689 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1691 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1692 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1693 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1694 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1696 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1697 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1698 "cmpxchg16b\t$dst", []>, TB;
1700 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1701 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1703 // Optimized codegen when the non-memory output is not used.
1704 let Defs = [EFLAGS] in {
1705 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1706 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1708 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1709 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1710 (ins i64mem:$dst, i64i8imm :$src2),
1712 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1713 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1714 (ins i64mem:$dst, i64i32imm :$src2),
1716 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1717 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1719 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1720 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1721 (ins i64mem:$dst, i64i8imm :$src2),
1723 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1724 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1725 (ins i64mem:$dst, i64i32imm:$src2),
1727 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1728 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1730 "inc{q}\t$dst", []>, LOCK;
1731 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1733 "dec{q}\t$dst", []>, LOCK;
1735 // Atomic exchange, and, or, xor
1736 let Constraints = "$val = $dst", Defs = [EFLAGS],
1737 usesCustomInserter = 1 in {
1738 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1739 "#ATOMAND64 PSEUDO!",
1740 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1741 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1742 "#ATOMOR64 PSEUDO!",
1743 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1744 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1745 "#ATOMXOR64 PSEUDO!",
1746 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1747 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1748 "#ATOMNAND64 PSEUDO!",
1749 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1750 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1751 "#ATOMMIN64 PSEUDO!",
1752 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1753 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1754 "#ATOMMAX64 PSEUDO!",
1755 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1756 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1757 "#ATOMUMIN64 PSEUDO!",
1758 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1759 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1760 "#ATOMUMAX64 PSEUDO!",
1761 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1764 // Segmentation support instructions
1766 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1767 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1768 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1769 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1770 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1772 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1773 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1774 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1775 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1777 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1779 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1780 "push{q}\t%fs", []>, TB;
1781 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1782 "push{q}\t%gs", []>, TB;
1784 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1785 "pop{q}\t%fs", []>, TB;
1786 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1787 "pop{q}\t%gs", []>, TB;
1789 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1790 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1791 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1792 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1793 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1794 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1796 // Specialized register support
1798 // no m form encodable; use SMSW16m
1799 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1800 "smsw{q}\t$dst", []>, TB;
1802 // String manipulation instructions
1804 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1806 //===----------------------------------------------------------------------===//
1807 // Non-Instruction Patterns
1808 //===----------------------------------------------------------------------===//
1810 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1811 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1812 // 'movabs' predicate should handle this sort of thing.
1813 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1814 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1815 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1816 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1817 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1818 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1819 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1820 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1821 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1822 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1824 // In static codegen with small code model, we can get the address of a label
1825 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1826 // the MOV64ri64i32 should accept these.
1827 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1828 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1829 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1830 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1831 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1832 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1833 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1834 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1835 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1836 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1838 // In kernel code model, we can get the address of a label
1839 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1840 // the MOV64ri32 should accept these.
1841 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1842 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1843 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1844 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1845 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1846 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1847 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1848 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1849 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1850 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1852 // If we have small model and -static mode, it is safe to store global addresses
1853 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1854 // for MOV64mi32 should handle this sort of thing.
1855 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1856 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1857 Requires<[NearData, IsStatic]>;
1858 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1859 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1860 Requires<[NearData, IsStatic]>;
1861 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1862 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1863 Requires<[NearData, IsStatic]>;
1864 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1865 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1866 Requires<[NearData, IsStatic]>;
1867 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1868 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1869 Requires<[NearData, IsStatic]>;
1872 // Direct PC relative function call for small code model. 32-bit displacement
1873 // sign extended to 64-bit.
1874 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1875 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1876 def : Pat<(X86call (i64 texternalsym:$dst)),
1877 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1879 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1880 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1881 def : Pat<(X86call (i64 texternalsym:$dst)),
1882 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1885 def : Pat<(X86tcret GR64:$dst, imm:$off),
1886 (TCRETURNri64 GR64:$dst, imm:$off)>;
1888 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1889 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>;
1891 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1892 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1896 // TEST R,R is smaller than CMP R,0
1897 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1898 (TEST64rr GR64:$src1, GR64:$src1)>;
1900 // Conditional moves with folded loads with operands swapped and conditions
1902 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1903 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1904 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1905 (CMOVB64rm GR64:$src2, addr:$src1)>;
1906 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1907 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1908 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1909 (CMOVE64rm GR64:$src2, addr:$src1)>;
1910 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1911 (CMOVA64rm GR64:$src2, addr:$src1)>;
1912 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1913 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1914 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1915 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1916 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1917 (CMOVL64rm GR64:$src2, addr:$src1)>;
1918 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1919 (CMOVG64rm GR64:$src2, addr:$src1)>;
1920 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1921 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1922 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1923 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1924 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1925 (CMOVP64rm GR64:$src2, addr:$src1)>;
1926 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1927 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1928 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1929 (CMOVS64rm GR64:$src2, addr:$src1)>;
1930 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1931 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1932 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1933 (CMOVO64rm GR64:$src2, addr:$src1)>;
1935 // zextload bool -> zextload byte
1936 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1939 // When extloading from 16-bit and smaller memory locations into 64-bit
1940 // registers, use zero-extending loads so that the entire 64-bit register is
1941 // defined, avoiding partial-register updates.
1942 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1943 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1944 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1945 // For other extloads, use subregs, since the high contents of the register are
1946 // defined after an extload.
1947 def : Pat<(extloadi64i32 addr:$src),
1948 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1951 // anyext. Define these to do an explicit zero-extend to
1952 // avoid partial-register updates.
1953 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1954 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1955 def : Pat<(i64 (anyext GR32:$src)),
1956 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1958 //===----------------------------------------------------------------------===//
1960 //===----------------------------------------------------------------------===//
1962 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1963 // +128 doesn't, so in this special case use a sub instead of an add.
1964 def : Pat<(add GR64:$src1, 128),
1965 (SUB64ri8 GR64:$src1, -128)>;
1966 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1967 (SUB64mi8 addr:$dst, -128)>;
1969 // The same trick applies for 32-bit immediate fields in 64-bit
1971 def : Pat<(add GR64:$src1, 0x0000000080000000),
1972 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1973 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1974 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1976 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
1977 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
1978 // materialize that immediate in a register first.
1979 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1983 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit),
1987 // r & (2^32-1) ==> movz
1988 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1989 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1990 // r & (2^16-1) ==> movz
1991 def : Pat<(and GR64:$src, 0xffff),
1992 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1993 // r & (2^8-1) ==> movz
1994 def : Pat<(and GR64:$src, 0xff),
1995 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1996 // r & (2^8-1) ==> movz
1997 def : Pat<(and GR32:$src1, 0xff),
1998 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1999 Requires<[In64BitMode]>;
2000 // r & (2^8-1) ==> movz
2001 def : Pat<(and GR16:$src1, 0xff),
2002 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
2003 Requires<[In64BitMode]>;
2005 // sext_inreg patterns
2006 def : Pat<(sext_inreg GR64:$src, i32),
2007 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2008 def : Pat<(sext_inreg GR64:$src, i16),
2009 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2010 def : Pat<(sext_inreg GR64:$src, i8),
2011 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
2012 def : Pat<(sext_inreg GR32:$src, i8),
2013 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
2014 Requires<[In64BitMode]>;
2015 def : Pat<(sext_inreg GR16:$src, i8),
2016 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
2017 Requires<[In64BitMode]>;
2020 def : Pat<(i32 (trunc GR64:$src)),
2021 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
2022 def : Pat<(i16 (trunc GR64:$src)),
2023 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
2024 def : Pat<(i8 (trunc GR64:$src)),
2025 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
2026 def : Pat<(i8 (trunc GR32:$src)),
2027 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
2028 Requires<[In64BitMode]>;
2029 def : Pat<(i8 (trunc GR16:$src)),
2030 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
2031 Requires<[In64BitMode]>;
2033 // h-register tricks.
2034 // For now, be conservative on x86-64 and use an h-register extract only if the
2035 // value is immediately zero-extended or stored, which are somewhat common
2036 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
2037 // from being allocated in the same instruction as the h register, as there's
2038 // currently no way to describe this requirement to the register allocator.
2040 // h-register extract and zero-extend.
2041 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2045 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2046 x86_subreg_8bit_hi)),
2048 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2050 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2051 x86_subreg_8bit_hi))>,
2052 Requires<[In64BitMode]>;
2053 def : Pat<(srl GR16:$src, (i8 8)),
2056 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2057 x86_subreg_8bit_hi)),
2059 Requires<[In64BitMode]>;
2060 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2062 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2063 x86_subreg_8bit_hi))>,
2064 Requires<[In64BitMode]>;
2065 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2067 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2068 x86_subreg_8bit_hi))>,
2069 Requires<[In64BitMode]>;
2070 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2074 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2075 x86_subreg_8bit_hi)),
2077 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2081 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2082 x86_subreg_8bit_hi)),
2085 // h-register extract and store.
2086 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2089 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2090 x86_subreg_8bit_hi))>;
2091 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2094 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2095 x86_subreg_8bit_hi))>,
2096 Requires<[In64BitMode]>;
2097 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2100 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2101 x86_subreg_8bit_hi))>,
2102 Requires<[In64BitMode]>;
2104 // (shl x, 1) ==> (add x, x)
2105 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2107 // (shl x (and y, 63)) ==> (shl x, y)
2108 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
2109 (SHL64rCL GR64:$src1)>;
2110 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
2111 (SHL64mCL addr:$dst)>;
2113 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
2114 (SHR64rCL GR64:$src1)>;
2115 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
2116 (SHR64mCL addr:$dst)>;
2118 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
2119 (SAR64rCL GR64:$src1)>;
2120 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
2121 (SAR64mCL addr:$dst)>;
2123 // Double shift patterns
2124 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
2125 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2127 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
2128 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
2129 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2131 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
2132 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2134 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
2135 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
2136 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2138 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2139 let AddedComplexity = 5 in { // Try this before the selecting to OR
2140 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt8:$src2),
2142 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2143 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt32:$src2),
2145 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2146 def : Pat<(parallel (or_is_add GR64:$src1, GR64:$src2),
2148 (ADD64rr GR64:$src1, GR64:$src2)>;
2149 } // AddedComplexity
2151 // X86 specific add which produces a flag.
2152 def : Pat<(addc GR64:$src1, GR64:$src2),
2153 (ADD64rr GR64:$src1, GR64:$src2)>;
2154 def : Pat<(addc GR64:$src1, (load addr:$src2)),
2155 (ADD64rm GR64:$src1, addr:$src2)>;
2156 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2157 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2158 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2159 (ADD64ri32 GR64:$src1, imm:$src2)>;
2161 def : Pat<(subc GR64:$src1, GR64:$src2),
2162 (SUB64rr GR64:$src1, GR64:$src2)>;
2163 def : Pat<(subc GR64:$src1, (load addr:$src2)),
2164 (SUB64rm GR64:$src1, addr:$src2)>;
2165 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2166 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2167 def : Pat<(subc GR64:$src1, imm:$src2),
2168 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2170 //===----------------------------------------------------------------------===//
2171 // EFLAGS-defining Patterns
2172 //===----------------------------------------------------------------------===//
2174 // Register-Register Addition with EFLAGS result
2175 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
2177 (ADD64rr GR64:$src1, GR64:$src2)>;
2179 // Register-Integer Addition with EFLAGS result
2180 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
2182 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2183 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
2185 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2187 // Register-Memory Addition with EFLAGS result
2188 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
2190 (ADD64rm GR64:$src1, addr:$src2)>;
2192 // Memory-Register Addition with EFLAGS result
2193 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
2196 (ADD64mr addr:$dst, GR64:$src2)>;
2197 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2200 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
2201 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
2202 i64immSExt32:$src2),
2205 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
2207 // Register-Register Subtraction with EFLAGS result
2208 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
2210 (SUB64rr GR64:$src1, GR64:$src2)>;
2212 // Register-Memory Subtraction with EFLAGS result
2213 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
2215 (SUB64rm GR64:$src1, addr:$src2)>;
2217 // Register-Integer Subtraction with EFLAGS result
2218 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
2220 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2221 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
2223 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2225 // Memory-Register Subtraction with EFLAGS result
2226 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
2229 (SUB64mr addr:$dst, GR64:$src2)>;
2231 // Memory-Integer Subtraction with EFLAGS result
2232 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2236 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2237 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2238 i64immSExt32:$src2),
2241 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
2243 // Register-Register Signed Integer Multiplication with EFLAGS result
2244 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
2246 (IMUL64rr GR64:$src1, GR64:$src2)>;
2248 // Register-Memory Signed Integer Multiplication with EFLAGS result
2249 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
2251 (IMUL64rm GR64:$src1, addr:$src2)>;
2253 // Register-Integer Signed Integer Multiplication with EFLAGS result
2254 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2256 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2257 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2259 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2261 // Memory-Integer Signed Integer Multiplication with EFLAGS result
2262 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2264 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2265 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2267 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2269 // INC and DEC with EFLAGS result. Note that these do not set CF.
2270 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2271 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2272 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2274 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2275 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2276 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2277 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2279 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2281 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2282 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2283 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2285 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2286 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2287 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2288 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2290 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2292 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2293 (INC64r GR64:$src)>;
2294 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2296 (INC64m addr:$dst)>;
2297 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2298 (DEC64r GR64:$src)>;
2299 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2301 (DEC64m addr:$dst)>;
2303 // Register-Register Logical Or with EFLAGS result
2304 def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2306 (OR64rr GR64:$src1, GR64:$src2)>;
2308 // Register-Integer Logical Or with EFLAGS result
2309 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2311 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2312 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2314 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2316 // Register-Memory Logical Or with EFLAGS result
2317 def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2319 (OR64rm GR64:$src1, addr:$src2)>;
2321 // Memory-Register Logical Or with EFLAGS result
2322 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2325 (OR64mr addr:$dst, GR64:$src2)>;
2326 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2329 (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2330 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2333 (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2335 // Register-Register Logical XOr with EFLAGS result
2336 def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2338 (XOR64rr GR64:$src1, GR64:$src2)>;
2340 // Register-Integer Logical XOr with EFLAGS result
2341 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2343 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2344 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2346 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2348 // Register-Memory Logical XOr with EFLAGS result
2349 def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2351 (XOR64rm GR64:$src1, addr:$src2)>;
2353 // Memory-Register Logical XOr with EFLAGS result
2354 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2357 (XOR64mr addr:$dst, GR64:$src2)>;
2358 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2361 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2362 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
2363 i64immSExt32:$src2),
2366 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2368 // Register-Register Logical And with EFLAGS result
2369 def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2371 (AND64rr GR64:$src1, GR64:$src2)>;
2373 // Register-Integer Logical And with EFLAGS result
2374 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2376 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2377 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2379 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2381 // Register-Memory Logical And with EFLAGS result
2382 def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2384 (AND64rm GR64:$src1, addr:$src2)>;
2386 // Memory-Register Logical And with EFLAGS result
2387 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2390 (AND64mr addr:$dst, GR64:$src2)>;
2391 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2394 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2395 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
2396 i64immSExt32:$src2),
2399 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2401 //===----------------------------------------------------------------------===//
2402 // X86-64 SSE Instructions
2403 //===----------------------------------------------------------------------===//
2405 // Move instructions...
2407 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2408 "mov{d|q}\t{$src, $dst|$dst, $src}",
2410 (v2i64 (scalar_to_vector GR64:$src)))]>;
2411 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2412 "mov{d|q}\t{$src, $dst|$dst, $src}",
2413 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2416 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2417 "mov{d|q}\t{$src, $dst|$dst, $src}",
2418 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2419 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2420 "movq\t{$src, $dst|$dst, $src}",
2421 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2423 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2424 "mov{d|q}\t{$src, $dst|$dst, $src}",
2425 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2426 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2427 "movq\t{$src, $dst|$dst, $src}",
2428 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2430 //===----------------------------------------------------------------------===//
2431 // X86-64 SSE4.1 Instructions
2432 //===----------------------------------------------------------------------===//
2434 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2435 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2436 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2437 (ins VR128:$src1, i32i8imm:$src2),
2438 !strconcat(OpcodeStr,
2439 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2441 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2442 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2443 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2444 !strconcat(OpcodeStr,
2445 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2446 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2447 addr:$dst)]>, OpSize, REX_W;
2450 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2452 let isTwoAddress = 1 in {
2453 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2454 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2455 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2456 !strconcat(OpcodeStr,
2457 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2459 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2461 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2462 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2463 !strconcat(OpcodeStr,
2464 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2466 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2467 imm:$src3)))]>, OpSize, REX_W;
2471 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2473 // -disable-16bit support.
2474 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2475 (MOV16mi addr:$dst, imm:$src)>;
2476 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2477 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2478 def : Pat<(i64 (sextloadi16 addr:$dst)),
2479 (MOVSX64rm16 addr:$dst)>;
2480 def : Pat<(i64 (zextloadi16 addr:$dst)),
2481 (MOVZX64rm16 addr:$dst)>;
2482 def : Pat<(i64 (extloadi16 addr:$dst)),
2483 (MOVZX64rm16 addr:$dst)>;