1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions.
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
46 def i64immSExt32 : PatLeaf<(i64 imm), [{
47 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
48 // sign extended field.
49 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
52 def i64immZExt32 : PatLeaf<(i64 imm), [{
53 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // unsignedsign extended field.
55 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
58 def i64immSExt8 : PatLeaf<(i64 imm), [{
59 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
60 // sign extended field.
61 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
64 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
65 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
66 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
68 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
69 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
70 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
71 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
73 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
74 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
75 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
76 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
78 //===----------------------------------------------------------------------===//
79 // Instruction list...
82 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
83 // a stack adjustment and the codegen must know that they may modify the stack
84 // pointer before prolog-epilog rewriting occurs.
85 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
86 // sub / add which can clobber EFLAGS.
87 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
90 [(X86callseq_start timm:$amt)]>,
91 Requires<[In64BitMode]>;
92 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
94 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
95 Requires<[In64BitMode]>;
98 //===----------------------------------------------------------------------===//
99 // Call Instructions...
102 // All calls clobber the non-callee saved registers. RSP is marked as
103 // a use to prevent stack-pointer assignments that appear immediately
104 // before calls from potentially appearing dead. Uses for argument
105 // registers are added manually.
106 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
107 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
108 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
109 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
110 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
112 def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops),
113 "call\t${dst:call}", []>;
114 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
115 "call\t{*}$dst", [(X86call GR64:$dst)]>;
116 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
117 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>;
122 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
123 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset, variable_ops),
124 "#TC_RETURN $dst $offset",
127 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
128 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset, variable_ops),
129 "#TC_RETURN $dst $offset",
133 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
134 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst # TAILCALL",
138 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
139 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
140 [(brind GR64:$dst)]>;
141 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
142 [(brind (loadi64 addr:$dst))]>;
145 //===----------------------------------------------------------------------===//
146 // EH Pseudo Instructions
148 let isTerminator = 1, isReturn = 1, isBarrier = 1,
150 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
151 "ret\t#eh_return, addr: $addr",
152 [(X86ehret GR64:$addr)]>;
156 //===----------------------------------------------------------------------===//
157 // Miscellaneous Instructions...
159 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
160 def LEAVE64 : I<0xC9, RawFrm,
161 (outs), (ins), "leave", []>;
162 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
164 def POP64r : I<0x58, AddRegFrm,
165 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
167 def PUSH64r : I<0x50, AddRegFrm,
168 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
171 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
172 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
173 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
174 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
176 def LEA64_32r : I<0x8D, MRMSrcMem,
177 (outs GR32:$dst), (ins lea64_32mem:$src),
178 "lea{l}\t{$src|$dst}, {$dst|$src}",
179 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
181 let isReMaterializable = 1 in
182 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
183 "lea{q}\t{$src|$dst}, {$dst|$src}",
184 [(set GR64:$dst, lea64addr:$src)]>;
186 let isTwoAddress = 1 in
187 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
189 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
191 // Bit scan instructions.
192 let Defs = [EFLAGS] in {
193 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
194 "bsf{q}\t{$src, $dst|$dst, $src}",
195 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
196 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
197 "bsf{q}\t{$src, $dst|$dst, $src}",
198 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
199 (implicit EFLAGS)]>, TB;
201 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
202 "bsr{q}\t{$src, $dst|$dst, $src}",
203 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
204 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
205 "bsr{q}\t{$src, $dst|$dst, $src}",
206 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
207 (implicit EFLAGS)]>, TB;
211 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
212 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
213 [(X86rep_movs i64)]>, REP;
214 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
215 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
216 [(X86rep_stos i64)]>, REP;
218 //===----------------------------------------------------------------------===//
219 // Move Instructions...
222 let neverHasSideEffects = 1 in
223 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
224 "mov{q}\t{$src, $dst|$dst, $src}", []>;
226 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
227 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
228 "movabs{q}\t{$src, $dst|$dst, $src}",
229 [(set GR64:$dst, imm:$src)]>;
230 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
231 "mov{q}\t{$src, $dst|$dst, $src}",
232 [(set GR64:$dst, i64immSExt32:$src)]>;
235 let canFoldAsLoad = 1 in
236 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
237 "mov{q}\t{$src, $dst|$dst, $src}",
238 [(set GR64:$dst, (load addr:$src))]>;
240 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
241 "mov{q}\t{$src, $dst|$dst, $src}",
242 [(store GR64:$src, addr:$dst)]>;
243 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
244 "mov{q}\t{$src, $dst|$dst, $src}",
245 [(store i64immSExt32:$src, addr:$dst)]>;
247 // Sign/Zero extenders
249 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
250 "movs{bq|x}\t{$src, $dst|$dst, $src}",
251 [(set GR64:$dst, (sext GR8:$src))]>, TB;
252 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
253 "movs{bq|x}\t{$src, $dst|$dst, $src}",
254 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
255 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
256 "movs{wq|x}\t{$src, $dst|$dst, $src}",
257 [(set GR64:$dst, (sext GR16:$src))]>, TB;
258 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
259 "movs{wq|x}\t{$src, $dst|$dst, $src}",
260 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
261 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
262 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
263 [(set GR64:$dst, (sext GR32:$src))]>;
264 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
265 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
266 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
268 // Use movzbl instead of movzbq when the destination is a register; it's
269 // equivalent due to implicit zero-extending, and it has a smaller encoding.
270 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
271 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
272 [(set GR64:$dst, (zext GR8:$src))]>, TB;
273 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
274 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
275 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
276 // Use movzwl instead of movzwq when the destination is a register; it's
277 // equivalent due to implicit zero-extending, and it has a smaller encoding.
278 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
279 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
280 [(set GR64:$dst, (zext GR16:$src))]>, TB;
281 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
282 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
283 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
285 // There's no movzlq instruction, but movl can be used for this purpose, using
286 // implicit zero-extension. We need this because the seeming alternative for
287 // implementing zext from 32 to 64, an EXTRACT_SUBREG/SUBREG_TO_REG pair, isn't
288 // safe because both instructions could be optimized away in the
289 // register-to-register case, leaving nothing behind to do the zero extension.
290 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
291 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
292 [(set GR64:$dst, (zext GR32:$src))]>;
293 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
294 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
295 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
297 let neverHasSideEffects = 1 in {
298 let Defs = [RAX], Uses = [EAX] in
299 def CDQE : RI<0x98, RawFrm, (outs), (ins),
300 "{cltq|cdqe}", []>; // RAX = signext(EAX)
302 let Defs = [RAX,RDX], Uses = [RAX] in
303 def CQO : RI<0x99, RawFrm, (outs), (ins),
304 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
307 //===----------------------------------------------------------------------===//
308 // Arithmetic Instructions...
311 let Defs = [EFLAGS] in {
312 let isTwoAddress = 1 in {
313 let isConvertibleToThreeAddress = 1 in {
314 let isCommutable = 1 in
315 // Register-Register Addition
316 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
317 "add{q}\t{$src2, $dst|$dst, $src2}",
318 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
321 // Register-Integer Addition
322 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
323 "add{q}\t{$src2, $dst|$dst, $src2}",
324 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
326 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
327 "add{q}\t{$src2, $dst|$dst, $src2}",
328 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
330 } // isConvertibleToThreeAddress
332 // Register-Memory Addition
333 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
334 "add{q}\t{$src2, $dst|$dst, $src2}",
335 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
339 // Memory-Register Addition
340 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
341 "add{q}\t{$src2, $dst|$dst, $src2}",
342 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
344 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
345 "add{q}\t{$src2, $dst|$dst, $src2}",
346 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
348 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
349 "add{q}\t{$src2, $dst|$dst, $src2}",
350 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
353 let Uses = [EFLAGS] in {
354 let isTwoAddress = 1 in {
355 let isCommutable = 1 in
356 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
357 "adc{q}\t{$src2, $dst|$dst, $src2}",
358 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
360 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
361 "adc{q}\t{$src2, $dst|$dst, $src2}",
362 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
364 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
365 "adc{q}\t{$src2, $dst|$dst, $src2}",
366 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
367 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
368 "adc{q}\t{$src2, $dst|$dst, $src2}",
369 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
372 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
373 "adc{q}\t{$src2, $dst|$dst, $src2}",
374 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
375 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
376 "adc{q}\t{$src2, $dst|$dst, $src2}",
377 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
378 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
379 "adc{q}\t{$src2, $dst|$dst, $src2}",
380 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
383 let isTwoAddress = 1 in {
384 // Register-Register Subtraction
385 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
386 "sub{q}\t{$src2, $dst|$dst, $src2}",
387 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
390 // Register-Memory Subtraction
391 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
392 "sub{q}\t{$src2, $dst|$dst, $src2}",
393 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
396 // Register-Integer Subtraction
397 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
398 (ins GR64:$src1, i64i32imm:$src2),
399 "sub{q}\t{$src2, $dst|$dst, $src2}",
400 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
402 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
403 (ins GR64:$src1, i64i8imm:$src2),
404 "sub{q}\t{$src2, $dst|$dst, $src2}",
405 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
409 // Memory-Register Subtraction
410 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
411 "sub{q}\t{$src2, $dst|$dst, $src2}",
412 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
415 // Memory-Integer Subtraction
416 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
417 "sub{q}\t{$src2, $dst|$dst, $src2}",
418 [(store (sub (load addr:$dst), i64immSExt32:$src2),
421 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
422 "sub{q}\t{$src2, $dst|$dst, $src2}",
423 [(store (sub (load addr:$dst), i64immSExt8:$src2),
427 let Uses = [EFLAGS] in {
428 let isTwoAddress = 1 in {
429 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
430 "sbb{q}\t{$src2, $dst|$dst, $src2}",
431 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
433 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
434 "sbb{q}\t{$src2, $dst|$dst, $src2}",
435 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
437 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
438 "sbb{q}\t{$src2, $dst|$dst, $src2}",
439 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
440 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
441 "sbb{q}\t{$src2, $dst|$dst, $src2}",
442 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
445 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
446 "sbb{q}\t{$src2, $dst|$dst, $src2}",
447 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
448 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
449 "sbb{q}\t{$src2, $dst|$dst, $src2}",
450 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
451 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
452 "sbb{q}\t{$src2, $dst|$dst, $src2}",
453 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
457 // Unsigned multiplication
458 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
459 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
460 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
462 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
463 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
465 // Signed multiplication
466 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
467 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
469 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
470 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
473 let Defs = [EFLAGS] in {
474 let isTwoAddress = 1 in {
475 let isCommutable = 1 in
476 // Register-Register Signed Integer Multiplication
477 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
478 (ins GR64:$src1, GR64:$src2),
479 "imul{q}\t{$src2, $dst|$dst, $src2}",
480 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
481 (implicit EFLAGS)]>, TB;
483 // Register-Memory Signed Integer Multiplication
484 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
485 (ins GR64:$src1, i64mem:$src2),
486 "imul{q}\t{$src2, $dst|$dst, $src2}",
487 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
488 (implicit EFLAGS)]>, TB;
491 // Suprisingly enough, these are not two address instructions!
493 // Register-Integer Signed Integer Multiplication
494 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
495 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
496 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
497 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
499 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
500 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
501 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
502 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
505 // Memory-Integer Signed Integer Multiplication
506 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
507 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
508 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
509 [(set GR64:$dst, (mul (load addr:$src1),
510 i64immSExt32:$src2)),
512 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
513 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
514 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
515 [(set GR64:$dst, (mul (load addr:$src1),
520 // Unsigned division / remainder
521 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
522 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
524 // Signed division / remainder
525 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
526 "idiv{q}\t$src", []>;
528 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
530 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
531 "idiv{q}\t$src", []>;
535 // Unary instructions
536 let Defs = [EFLAGS], CodeSize = 2 in {
537 let isTwoAddress = 1 in
538 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
539 [(set GR64:$dst, (ineg GR64:$src))]>;
540 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
541 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
543 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
544 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
545 [(set GR64:$dst, (add GR64:$src, 1))]>;
546 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
547 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
549 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
550 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
551 [(set GR64:$dst, (add GR64:$src, -1))]>;
552 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
553 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
555 // In 64-bit mode, single byte INC and DEC cannot be encoded.
556 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
557 // Can transform into LEA.
558 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
559 [(set GR16:$dst, (add GR16:$src, 1))]>,
560 OpSize, Requires<[In64BitMode]>;
561 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
562 [(set GR32:$dst, (add GR32:$src, 1))]>,
563 Requires<[In64BitMode]>;
564 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
565 [(set GR16:$dst, (add GR16:$src, -1))]>,
566 OpSize, Requires<[In64BitMode]>;
567 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
568 [(set GR32:$dst, (add GR32:$src, -1))]>,
569 Requires<[In64BitMode]>;
570 } // isConvertibleToThreeAddress
572 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
573 // how to unfold them.
574 let isTwoAddress = 0, CodeSize = 2 in {
575 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
576 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
577 OpSize, Requires<[In64BitMode]>;
578 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
579 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
580 Requires<[In64BitMode]>;
581 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
582 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
583 OpSize, Requires<[In64BitMode]>;
584 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
585 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
586 Requires<[In64BitMode]>;
588 } // Defs = [EFLAGS], CodeSize
591 let Defs = [EFLAGS] in {
592 // Shift instructions
593 let isTwoAddress = 1 in {
595 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
596 "shl{q}\t{%cl, $dst|$dst, %CL}",
597 [(set GR64:$dst, (shl GR64:$src, CL))]>;
598 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
599 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
600 "shl{q}\t{$src2, $dst|$dst, $src2}",
601 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
602 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
607 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
608 "shl{q}\t{%cl, $dst|$dst, %CL}",
609 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
610 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
611 "shl{q}\t{$src, $dst|$dst, $src}",
612 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
613 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
615 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
617 let isTwoAddress = 1 in {
619 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
620 "shr{q}\t{%cl, $dst|$dst, %CL}",
621 [(set GR64:$dst, (srl GR64:$src, CL))]>;
622 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
623 "shr{q}\t{$src2, $dst|$dst, $src2}",
624 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
625 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
627 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
631 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
632 "shr{q}\t{%cl, $dst|$dst, %CL}",
633 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
634 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
635 "shr{q}\t{$src, $dst|$dst, $src}",
636 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
637 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
639 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
641 let isTwoAddress = 1 in {
643 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
644 "sar{q}\t{%cl, $dst|$dst, %CL}",
645 [(set GR64:$dst, (sra GR64:$src, CL))]>;
646 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
647 "sar{q}\t{$src2, $dst|$dst, $src2}",
648 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
649 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
651 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
655 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
656 "sar{q}\t{%cl, $dst|$dst, %CL}",
657 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
658 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
659 "sar{q}\t{$src, $dst|$dst, $src}",
660 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
661 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
663 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
665 // Rotate instructions
666 let isTwoAddress = 1 in {
668 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
669 "rol{q}\t{%cl, $dst|$dst, %CL}",
670 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
671 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
672 "rol{q}\t{$src2, $dst|$dst, $src2}",
673 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
674 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
676 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
680 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
681 "rol{q}\t{%cl, $dst|$dst, %CL}",
682 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
683 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
684 "rol{q}\t{$src, $dst|$dst, $src}",
685 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
686 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
688 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
690 let isTwoAddress = 1 in {
692 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
693 "ror{q}\t{%cl, $dst|$dst, %CL}",
694 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
695 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
696 "ror{q}\t{$src2, $dst|$dst, $src2}",
697 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
698 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
700 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
704 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
705 "ror{q}\t{%cl, $dst|$dst, %CL}",
706 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
707 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
708 "ror{q}\t{$src, $dst|$dst, $src}",
709 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
710 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
712 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
714 // Double shift instructions (generalizations of rotate)
715 let isTwoAddress = 1 in {
717 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
718 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
719 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
720 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
721 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
722 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
725 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
726 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
727 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
728 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
729 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
732 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
733 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
734 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
735 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
742 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
743 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
744 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
746 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
747 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
748 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
751 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
752 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
753 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
754 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
755 (i8 imm:$src3)), addr:$dst)]>,
757 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
758 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
759 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
760 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
761 (i8 imm:$src3)), addr:$dst)]>,
765 //===----------------------------------------------------------------------===//
766 // Logical Instructions...
769 let isTwoAddress = 1 in
770 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
771 [(set GR64:$dst, (not GR64:$src))]>;
772 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
773 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
775 let Defs = [EFLAGS] in {
776 let isTwoAddress = 1 in {
777 let isCommutable = 1 in
778 def AND64rr : RI<0x21, MRMDestReg,
779 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
780 "and{q}\t{$src2, $dst|$dst, $src2}",
781 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
782 def AND64rm : RI<0x23, MRMSrcMem,
783 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
784 "and{q}\t{$src2, $dst|$dst, $src2}",
785 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
786 def AND64ri32 : RIi32<0x81, MRM4r,
787 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
788 "and{q}\t{$src2, $dst|$dst, $src2}",
789 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
790 def AND64ri8 : RIi8<0x83, MRM4r,
791 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
792 "and{q}\t{$src2, $dst|$dst, $src2}",
793 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
796 def AND64mr : RI<0x21, MRMDestMem,
797 (outs), (ins i64mem:$dst, GR64:$src),
798 "and{q}\t{$src, $dst|$dst, $src}",
799 [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
800 def AND64mi32 : RIi32<0x81, MRM4m,
801 (outs), (ins i64mem:$dst, i64i32imm:$src),
802 "and{q}\t{$src, $dst|$dst, $src}",
803 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
804 def AND64mi8 : RIi8<0x83, MRM4m,
805 (outs), (ins i64mem:$dst, i64i8imm :$src),
806 "and{q}\t{$src, $dst|$dst, $src}",
807 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
809 let isTwoAddress = 1 in {
810 let isCommutable = 1 in
811 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
812 "or{q}\t{$src2, $dst|$dst, $src2}",
813 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
814 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
815 "or{q}\t{$src2, $dst|$dst, $src2}",
816 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
817 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
818 "or{q}\t{$src2, $dst|$dst, $src2}",
819 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
820 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
821 "or{q}\t{$src2, $dst|$dst, $src2}",
822 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
825 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
826 "or{q}\t{$src, $dst|$dst, $src}",
827 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
828 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
829 "or{q}\t{$src, $dst|$dst, $src}",
830 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
831 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
832 "or{q}\t{$src, $dst|$dst, $src}",
833 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
835 let isTwoAddress = 1 in {
836 let isCommutable = 1 in
837 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
838 "xor{q}\t{$src2, $dst|$dst, $src2}",
839 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
840 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
841 "xor{q}\t{$src2, $dst|$dst, $src2}",
842 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
843 def XOR64ri32 : RIi32<0x81, MRM6r,
844 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
845 "xor{q}\t{$src2, $dst|$dst, $src2}",
846 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
847 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
848 "xor{q}\t{$src2, $dst|$dst, $src2}",
849 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
852 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
853 "xor{q}\t{$src, $dst|$dst, $src}",
854 [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
855 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
856 "xor{q}\t{$src, $dst|$dst, $src}",
857 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
858 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
859 "xor{q}\t{$src, $dst|$dst, $src}",
860 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
863 //===----------------------------------------------------------------------===//
864 // Comparison Instructions...
867 // Integer comparison
868 let Defs = [EFLAGS] in {
869 let isCommutable = 1 in
870 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
871 "test{q}\t{$src2, $src1|$src1, $src2}",
872 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
874 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
875 "test{q}\t{$src2, $src1|$src1, $src2}",
876 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
878 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
879 (ins GR64:$src1, i64i32imm:$src2),
880 "test{q}\t{$src2, $src1|$src1, $src2}",
881 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
883 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
884 (ins i64mem:$src1, i64i32imm:$src2),
885 "test{q}\t{$src2, $src1|$src1, $src2}",
886 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
889 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
890 "cmp{q}\t{$src2, $src1|$src1, $src2}",
891 [(X86cmp GR64:$src1, GR64:$src2),
893 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
894 "cmp{q}\t{$src2, $src1|$src1, $src2}",
895 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
897 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
898 "cmp{q}\t{$src2, $src1|$src1, $src2}",
899 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
901 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
902 "cmp{q}\t{$src2, $src1|$src1, $src2}",
903 [(X86cmp GR64:$src1, i64immSExt32:$src2),
905 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
906 (ins i64mem:$src1, i64i32imm:$src2),
907 "cmp{q}\t{$src2, $src1|$src1, $src2}",
908 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
910 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
911 "cmp{q}\t{$src2, $src1|$src1, $src2}",
912 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
914 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
915 "cmp{q}\t{$src2, $src1|$src1, $src2}",
916 [(X86cmp GR64:$src1, i64immSExt8:$src2),
921 let Uses = [EFLAGS], isTwoAddress = 1 in {
922 let isCommutable = 1 in {
923 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
924 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
925 "cmovb\t{$src2, $dst|$dst, $src2}",
926 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
927 X86_COND_B, EFLAGS))]>, TB;
928 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
929 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
930 "cmovae\t{$src2, $dst|$dst, $src2}",
931 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
932 X86_COND_AE, EFLAGS))]>, TB;
933 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
934 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
935 "cmove\t{$src2, $dst|$dst, $src2}",
936 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
937 X86_COND_E, EFLAGS))]>, TB;
938 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
939 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
940 "cmovne\t{$src2, $dst|$dst, $src2}",
941 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
942 X86_COND_NE, EFLAGS))]>, TB;
943 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
944 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
945 "cmovbe\t{$src2, $dst|$dst, $src2}",
946 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
947 X86_COND_BE, EFLAGS))]>, TB;
948 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
949 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
950 "cmova\t{$src2, $dst|$dst, $src2}",
951 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
952 X86_COND_A, EFLAGS))]>, TB;
953 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
954 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
955 "cmovl\t{$src2, $dst|$dst, $src2}",
956 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
957 X86_COND_L, EFLAGS))]>, TB;
958 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
959 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
960 "cmovge\t{$src2, $dst|$dst, $src2}",
961 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
962 X86_COND_GE, EFLAGS))]>, TB;
963 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
964 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
965 "cmovle\t{$src2, $dst|$dst, $src2}",
966 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
967 X86_COND_LE, EFLAGS))]>, TB;
968 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
969 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
970 "cmovg\t{$src2, $dst|$dst, $src2}",
971 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
972 X86_COND_G, EFLAGS))]>, TB;
973 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
974 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
975 "cmovs\t{$src2, $dst|$dst, $src2}",
976 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
977 X86_COND_S, EFLAGS))]>, TB;
978 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
979 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
980 "cmovns\t{$src2, $dst|$dst, $src2}",
981 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
982 X86_COND_NS, EFLAGS))]>, TB;
983 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
984 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
985 "cmovp\t{$src2, $dst|$dst, $src2}",
986 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
987 X86_COND_P, EFLAGS))]>, TB;
988 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
989 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
990 "cmovnp\t{$src2, $dst|$dst, $src2}",
991 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
992 X86_COND_NP, EFLAGS))]>, TB;
993 } // isCommutable = 1
995 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
996 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
997 "cmovb\t{$src2, $dst|$dst, $src2}",
998 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
999 X86_COND_B, EFLAGS))]>, TB;
1000 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1001 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1002 "cmovae\t{$src2, $dst|$dst, $src2}",
1003 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1004 X86_COND_AE, EFLAGS))]>, TB;
1005 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1006 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1007 "cmove\t{$src2, $dst|$dst, $src2}",
1008 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1009 X86_COND_E, EFLAGS))]>, TB;
1010 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1011 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1012 "cmovne\t{$src2, $dst|$dst, $src2}",
1013 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1014 X86_COND_NE, EFLAGS))]>, TB;
1015 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1016 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1017 "cmovbe\t{$src2, $dst|$dst, $src2}",
1018 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1019 X86_COND_BE, EFLAGS))]>, TB;
1020 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1021 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1022 "cmova\t{$src2, $dst|$dst, $src2}",
1023 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1024 X86_COND_A, EFLAGS))]>, TB;
1025 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1026 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1027 "cmovl\t{$src2, $dst|$dst, $src2}",
1028 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1029 X86_COND_L, EFLAGS))]>, TB;
1030 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1031 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1032 "cmovge\t{$src2, $dst|$dst, $src2}",
1033 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1034 X86_COND_GE, EFLAGS))]>, TB;
1035 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1036 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1037 "cmovle\t{$src2, $dst|$dst, $src2}",
1038 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1039 X86_COND_LE, EFLAGS))]>, TB;
1040 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1041 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1042 "cmovg\t{$src2, $dst|$dst, $src2}",
1043 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1044 X86_COND_G, EFLAGS))]>, TB;
1045 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1046 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1047 "cmovs\t{$src2, $dst|$dst, $src2}",
1048 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1049 X86_COND_S, EFLAGS))]>, TB;
1050 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1051 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1052 "cmovns\t{$src2, $dst|$dst, $src2}",
1053 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1054 X86_COND_NS, EFLAGS))]>, TB;
1055 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1056 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1057 "cmovp\t{$src2, $dst|$dst, $src2}",
1058 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1059 X86_COND_P, EFLAGS))]>, TB;
1060 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1061 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1062 "cmovnp\t{$src2, $dst|$dst, $src2}",
1063 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1064 X86_COND_NP, EFLAGS))]>, TB;
1067 //===----------------------------------------------------------------------===//
1068 // Conversion Instructions...
1071 // f64 -> signed i64
1072 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1073 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1075 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1076 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1077 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1078 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1079 (load addr:$src)))]>;
1080 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1081 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1082 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1083 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1084 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1085 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1086 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1087 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1089 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1090 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1091 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1093 (int_x86_sse2_cvttsd2si64
1094 (load addr:$src)))]>;
1096 // Signed i64 -> f64
1097 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1098 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1099 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1100 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1101 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1102 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1104 let isTwoAddress = 1 in {
1105 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1106 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1107 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1109 (int_x86_sse2_cvtsi642sd VR128:$src1,
1111 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1112 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1113 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1115 (int_x86_sse2_cvtsi642sd VR128:$src1,
1116 (loadi64 addr:$src2)))]>;
1119 // Signed i64 -> f32
1120 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1121 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1122 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1123 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1124 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1125 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1127 let isTwoAddress = 1 in {
1128 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1129 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1130 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1132 (int_x86_sse_cvtsi642ss VR128:$src1,
1134 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1135 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1136 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1138 (int_x86_sse_cvtsi642ss VR128:$src1,
1139 (loadi64 addr:$src2)))]>;
1142 // f32 -> signed i64
1143 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1144 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1146 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1147 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1148 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1149 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1150 (load addr:$src)))]>;
1151 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1152 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1153 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1154 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1155 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1156 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1157 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1158 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1160 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1161 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1162 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1164 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1166 //===----------------------------------------------------------------------===//
1167 // Alias Instructions
1168 //===----------------------------------------------------------------------===//
1170 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1171 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1173 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1174 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1175 // when we have a better way to specify isel priority.
1176 let Defs = [EFLAGS], AddedComplexity = 1,
1177 isReMaterializable = 1, isAsCheapAsAMove = 1 in
1178 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1179 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1180 [(set GR64:$dst, 0)]>;
1182 // Materialize i64 constant where top 32-bits are zero.
1183 let AddedComplexity = 1, isReMaterializable = 1 in
1184 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1185 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1186 [(set GR64:$dst, i64immZExt32:$src)]>;
1188 //===----------------------------------------------------------------------===//
1189 // Thread Local Storage Instructions
1190 //===----------------------------------------------------------------------===//
1192 def TLS_addr64 : I<0, Pseudo, (outs GR64:$dst), (ins i64imm:$sym),
1193 ".byte\t0x66; leaq\t${sym:mem}(%rip), $dst; .word\t0x6666; rex64",
1194 [(set GR64:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
1196 //===----------------------------------------------------------------------===//
1197 // Atomic Instructions
1198 //===----------------------------------------------------------------------===//
1200 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1201 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1202 "lock\n\tcmpxchgq\t$swap,$ptr",
1203 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1206 let Constraints = "$val = $dst" in {
1207 let Defs = [EFLAGS] in
1208 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1209 "lock\n\txadd\t$val, $ptr",
1210 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1212 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1214 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1217 // Atomic exchange, and, or, xor
1218 let Constraints = "$val = $dst", Defs = [EFLAGS],
1219 usesCustomDAGSchedInserter = 1 in {
1220 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1221 "#ATOMAND64 PSEUDO!",
1222 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1223 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1224 "#ATOMOR64 PSEUDO!",
1225 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1226 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1227 "#ATOMXOR64 PSEUDO!",
1228 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1229 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1230 "#ATOMNAND64 PSEUDO!",
1231 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1232 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1233 "#ATOMMIN64 PSEUDO!",
1234 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1235 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1236 "#ATOMMAX64 PSEUDO!",
1237 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1238 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1239 "#ATOMUMIN64 PSEUDO!",
1240 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1241 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1242 "#ATOMUMAX64 PSEUDO!",
1243 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1246 //===----------------------------------------------------------------------===//
1247 // Non-Instruction Patterns
1248 //===----------------------------------------------------------------------===//
1250 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1251 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1252 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1253 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1254 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1255 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1256 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1257 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1258 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1260 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1261 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1262 Requires<[SmallCode, IsStatic]>;
1263 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1264 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1265 Requires<[SmallCode, IsStatic]>;
1266 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1267 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1268 Requires<[SmallCode, IsStatic]>;
1269 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1270 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1271 Requires<[SmallCode, IsStatic]>;
1274 // Direct PC relative function call for small code model. 32-bit displacement
1275 // sign extended to 64-bit.
1276 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1277 (CALL64pcrel32 tglobaladdr:$dst)>;
1278 def : Pat<(X86call (i64 texternalsym:$dst)),
1279 (CALL64pcrel32 texternalsym:$dst)>;
1281 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1282 (CALL64pcrel32 tglobaladdr:$dst)>;
1283 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1284 (CALL64pcrel32 texternalsym:$dst)>;
1286 def : Pat<(X86tailcall GR64:$dst),
1287 (CALL64r GR64:$dst)>;
1291 def : Pat<(X86tailcall GR32:$dst),
1293 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1295 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1298 def : Pat<(X86tcret GR64:$dst, imm:$off),
1299 (TCRETURNri64 GR64:$dst, imm:$off)>;
1301 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1302 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1304 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1305 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1309 // TEST R,R is smaller than CMP R,0
1310 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1311 (TEST64rr GR64:$src1, GR64:$src1)>;
1316 def : Pat<(i64 (zext GR32:$src)),
1317 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1319 // zextload bool -> zextload byte
1320 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1323 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1324 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1325 // partial-register updates.
1326 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1327 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1328 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1329 // For other extloads, use subregs, since the high contents of the register are
1330 // defined after an extload.
1331 def : Pat<(extloadi64i32 addr:$src),
1332 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1334 def : Pat<(extloadi16i1 addr:$src),
1335 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1337 Requires<[In64BitMode]>;
1338 def : Pat<(extloadi16i8 addr:$src),
1339 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1341 Requires<[In64BitMode]>;
1344 def : Pat<(i64 (anyext GR8:$src)),
1345 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1346 def : Pat<(i64 (anyext GR16:$src)),
1347 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1348 def : Pat<(i64 (anyext GR32:$src)),
1349 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1350 def : Pat<(i16 (anyext GR8:$src)),
1351 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1352 Requires<[In64BitMode]>;
1353 def : Pat<(i32 (anyext GR8:$src)),
1354 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1355 Requires<[In64BitMode]>;
1357 //===----------------------------------------------------------------------===//
1359 //===----------------------------------------------------------------------===//
1361 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1362 // +128 doesn't, so in this special case use a sub instead of an add.
1363 def : Pat<(add GR64:$src1, 128),
1364 (SUB64ri8 GR64:$src1, -128)>;
1365 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1366 (SUB64mi8 addr:$dst, -128)>;
1368 // The same trick applies for 32-bit immediate fields in 64-bit
1370 def : Pat<(add GR64:$src1, 0x0000000080000000),
1371 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1372 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1373 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1375 // r & (2^32-1) ==> movz
1376 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1377 (MOVZX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1378 // r & (2^16-1) ==> movz
1379 def : Pat<(and GR64:$src, 0xffff),
1380 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1381 // r & (2^8-1) ==> movz
1382 def : Pat<(and GR64:$src, 0xff),
1383 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1384 // r & (2^8-1) ==> movz
1385 def : Pat<(and GR32:$src1, 0xff),
1386 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>,
1387 Requires<[In64BitMode]>;
1388 // r & (2^8-1) ==> movz
1389 def : Pat<(and GR16:$src1, 0xff),
1390 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1391 Requires<[In64BitMode]>;
1393 // sext_inreg patterns
1394 def : Pat<(sext_inreg GR64:$src, i32),
1395 (MOVSX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1396 def : Pat<(sext_inreg GR64:$src, i16),
1397 (MOVSX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1398 def : Pat<(sext_inreg GR64:$src, i8),
1399 (MOVSX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1400 def : Pat<(sext_inreg GR32:$src, i8),
1401 (MOVSX32rr8 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)))>,
1402 Requires<[In64BitMode]>;
1403 def : Pat<(sext_inreg GR16:$src, i8),
1404 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1405 Requires<[In64BitMode]>;
1408 def : Pat<(i32 (trunc GR64:$src)),
1409 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1410 def : Pat<(i16 (trunc GR64:$src)),
1411 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1412 def : Pat<(i8 (trunc GR64:$src)),
1413 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1414 def : Pat<(i8 (trunc GR32:$src)),
1415 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1416 Requires<[In64BitMode]>;
1417 def : Pat<(i8 (trunc GR16:$src)),
1418 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit))>,
1419 Requires<[In64BitMode]>;
1421 // (shl x, 1) ==> (add x, x)
1422 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1424 // (shl x (and y, 63)) ==> (shl x, y)
1425 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1426 (SHL64rCL GR64:$src1)>;
1427 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1428 (SHL64mCL addr:$dst)>;
1430 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1431 (SHR64rCL GR64:$src1)>;
1432 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1433 (SHR64mCL addr:$dst)>;
1435 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1436 (SAR64rCL GR64:$src1)>;
1437 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1438 (SAR64mCL addr:$dst)>;
1440 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1441 def : Pat<(or (srl GR64:$src1, CL:$amt),
1442 (shl GR64:$src2, (sub 64, CL:$amt))),
1443 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1445 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1446 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1447 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1449 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1450 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1451 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1453 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1454 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1456 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1458 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1459 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1461 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1462 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1463 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1465 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1466 def : Pat<(or (shl GR64:$src1, CL:$amt),
1467 (srl GR64:$src2, (sub 64, CL:$amt))),
1468 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1470 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1471 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1472 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1474 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1475 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1476 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1478 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1479 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1481 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1483 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1484 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1486 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1487 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1488 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1490 // X86 specific add which produces a flag.
1491 def : Pat<(addc GR64:$src1, GR64:$src2),
1492 (ADD64rr GR64:$src1, GR64:$src2)>;
1493 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1494 (ADD64rm GR64:$src1, addr:$src2)>;
1495 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1496 (ADD64ri32 GR64:$src1, imm:$src2)>;
1497 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1498 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1500 def : Pat<(subc GR64:$src1, GR64:$src2),
1501 (SUB64rr GR64:$src1, GR64:$src2)>;
1502 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1503 (SUB64rm GR64:$src1, addr:$src2)>;
1504 def : Pat<(subc GR64:$src1, imm:$src2),
1505 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1506 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1507 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1509 //===----------------------------------------------------------------------===//
1510 // Overflow Patterns
1511 //===----------------------------------------------------------------------===//
1513 // Register-Register Addition with Overflow
1514 def : Pat<(parallel (X86add_ovf GR64:$src1, GR64:$src2),
1516 (ADD64rr GR64:$src1, GR64:$src2)>;
1518 // Register-Integer Addition with Overflow
1519 def : Pat<(parallel (X86add_ovf GR64:$src1, i64immSExt32:$src2),
1521 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1522 def : Pat<(parallel (X86add_ovf GR64:$src1, i64immSExt8:$src2),
1524 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1526 // Register-Memory Addition with Overflow
1527 def : Pat<(parallel (X86add_ovf GR64:$src1, (load addr:$src2)),
1529 (ADD64rm GR64:$src1, addr:$src2)>;
1531 // Memory-Register Addition with Overflow
1532 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR64:$src2),
1535 (ADD64mr addr:$dst, GR64:$src2)>;
1536 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i64immSExt32:$src2),
1539 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1540 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i64immSExt8:$src2),
1543 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1545 // Register-Register Subtraction with Overflow
1546 def : Pat<(parallel (X86sub_ovf GR64:$src1, GR64:$src2),
1548 (SUB64rr GR64:$src1, GR64:$src2)>;
1550 // Register-Memory Subtraction with Overflow
1551 def : Pat<(parallel (X86sub_ovf GR64:$src1, (load addr:$src2)),
1553 (SUB64rm GR64:$src1, addr:$src2)>;
1555 // Register-Integer Subtraction with Overflow
1556 def : Pat<(parallel (X86sub_ovf GR64:$src1, i64immSExt32:$src2),
1558 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1559 def : Pat<(parallel (X86sub_ovf GR64:$src1, i64immSExt8:$src2),
1561 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1563 // Memory-Register Subtraction with Overflow
1564 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR64:$src2),
1567 (SUB64mr addr:$dst, GR64:$src2)>;
1569 // Memory-Integer Subtraction with Overflow
1570 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i64immSExt32:$src2),
1573 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1574 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i64immSExt8:$src2),
1577 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1579 // Register-Register Signed Integer Multiplication with Overflow
1580 def : Pat<(parallel (X86smul_ovf GR64:$src1, GR64:$src2),
1582 (IMUL64rr GR64:$src1, GR64:$src2)>;
1584 // Register-Memory Signed Integer Multiplication with Overflow
1585 def : Pat<(parallel (X86smul_ovf GR64:$src1, (load addr:$src2)),
1587 (IMUL64rm GR64:$src1, addr:$src2)>;
1589 // Register-Integer Signed Integer Multiplication with Overflow
1590 def : Pat<(parallel (X86smul_ovf GR64:$src1, i64immSExt32:$src2),
1592 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1593 def : Pat<(parallel (X86smul_ovf GR64:$src1, i64immSExt8:$src2),
1595 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1597 // Memory-Integer Signed Integer Multiplication with Overflow
1598 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i64immSExt32:$src2),
1600 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1601 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i64immSExt8:$src2),
1603 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1605 //===----------------------------------------------------------------------===//
1606 // X86-64 SSE Instructions
1607 //===----------------------------------------------------------------------===//
1609 // Move instructions...
1611 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1612 "mov{d|q}\t{$src, $dst|$dst, $src}",
1614 (v2i64 (scalar_to_vector GR64:$src)))]>;
1615 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1616 "mov{d|q}\t{$src, $dst|$dst, $src}",
1617 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1620 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1621 "mov{d|q}\t{$src, $dst|$dst, $src}",
1622 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1623 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1624 "movq\t{$src, $dst|$dst, $src}",
1625 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1627 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1628 "mov{d|q}\t{$src, $dst|$dst, $src}",
1629 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1630 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1631 "movq\t{$src, $dst|$dst, $src}",
1632 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1634 //===----------------------------------------------------------------------===//
1635 // X86-64 SSE4.1 Instructions
1636 //===----------------------------------------------------------------------===//
1638 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1639 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
1640 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
1641 (ins VR128:$src1, i32i8imm:$src2),
1642 !strconcat(OpcodeStr,
1643 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1645 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
1646 def mr : SS4AIi8<opc, MRMDestMem, (outs),
1647 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
1648 !strconcat(OpcodeStr,
1649 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1650 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
1651 addr:$dst)]>, OpSize, REX_W;
1654 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
1656 let isTwoAddress = 1 in {
1657 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
1658 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
1659 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
1660 !strconcat(OpcodeStr,
1661 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1663 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
1665 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
1666 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
1667 !strconcat(OpcodeStr,
1668 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1670 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
1671 imm:$src3)))]>, OpSize, REX_W;
1675 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;