1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
27 let ParserMatchClass = X86AbsMemAsmOperand;
31 // 64-bits but only 8 bits are significant.
32 def i64i8imm : Operand<i64> {
33 let ParserMatchClass = ImmSExt8AsmOperand;
36 // Special i64mem for addresses of load folding tail calls. These are not
37 // allowed to use callee-saved registers since they must be scheduled
38 // after callee-saved register are popped.
39 def i64mem_TC : Operand<i64> {
40 let PrintMethod = "printi64mem";
41 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
42 let ParserMatchClass = X86MemAsmOperand;
45 def lea64mem : Operand<i64> {
46 let PrintMethod = "printlea64mem";
47 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
48 let ParserMatchClass = X86NoSegMemAsmOperand;
51 def lea64_32mem : Operand<i32> {
52 let PrintMethod = "printlea64_32mem";
53 let AsmOperandLowerMethod = "lower_lea64_32mem";
54 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
55 let ParserMatchClass = X86NoSegMemAsmOperand;
58 //===----------------------------------------------------------------------===//
59 // Complex Pattern Definitions.
61 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
62 [add, sub, mul, X86mul_imm, shl, or, frameindex,
65 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
66 [tglobaltlsaddr], []>;
68 //===----------------------------------------------------------------------===//
72 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
74 def GetLo32XForm : SDNodeXForm<imm, [{
75 // Transformation function: get the low 32 bits.
76 return getI32Imm((unsigned)N->getZExtValue());
79 def i64immSExt32 : PatLeaf<(i64 imm), [{
80 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
81 // sign extended field.
82 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
86 def i64immZExt32 : PatLeaf<(i64 imm), [{
87 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
88 // unsignedsign extended field.
89 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
92 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
93 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
94 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
96 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
97 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
98 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
99 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
101 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
102 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
103 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
104 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
106 //===----------------------------------------------------------------------===//
107 // Instruction list...
110 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
111 // a stack adjustment and the codegen must know that they may modify the stack
112 // pointer before prolog-epilog rewriting occurs.
113 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
114 // sub / add which can clobber EFLAGS.
115 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
116 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
118 [(X86callseq_start timm:$amt)]>,
119 Requires<[In64BitMode]>;
120 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
122 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
123 Requires<[In64BitMode]>;
126 // Interrupt Instructions
127 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
129 //===----------------------------------------------------------------------===//
130 // Call Instructions...
133 // All calls clobber the non-callee saved registers. RSP is marked as
134 // a use to prevent stack-pointer assignments that appear immediately
135 // before calls from potentially appearing dead. Uses for argument
136 // registers are added manually.
137 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
138 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
139 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
140 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
141 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
144 // NOTE: this pattern doesn't match "X86call imm", because we do not know
145 // that the offset between an arbitrary immediate and the call will fit in
146 // the 32-bit pcrel field that we have.
147 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
148 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
149 "call{q}\t$dst", []>,
150 Requires<[In64BitMode, NotWin64]>;
151 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
152 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
153 Requires<[NotWin64]>;
154 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
155 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
156 Requires<[NotWin64]>;
158 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
159 "lcall{q}\t{*}$dst", []>;
162 // FIXME: We need to teach codegen about single list of call-clobbered
165 // All calls clobber the non-callee saved registers. RSP is marked as
166 // a use to prevent stack-pointer assignments that appear immediately
167 // before calls from potentially appearing dead. Uses for argument
168 // registers are added manually.
169 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
170 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
171 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
172 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
174 def WINCALL64pcrel32 : I<0xE8, RawFrm,
175 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
178 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
180 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
181 def WINCALL64m : I<0xFF, MRM2m, (outs),
182 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
183 [(X86call (loadi64 addr:$dst))]>,
188 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
189 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
190 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
191 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
192 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
193 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
195 def TCRETURNdi64 : I<0, Pseudo, (outs),
196 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
197 "#TC_RETURN $dst $offset", []>;
198 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64_TC:$dst, i32imm:$offset,
200 "#TC_RETURN $dst $offset", []>;
201 def TCRETURNmi64 : I<0, Pseudo, (outs),
202 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops),
203 "#TC_RETURN $dst $offset", []>;
205 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
206 (ins i64i32imm_pcrel:$dst, variable_ops),
207 "jmp\t$dst # TAILCALL", []>;
208 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64_TC:$dst, variable_ops),
209 "jmp{q}\t{*}$dst # TAILCALL", []>;
211 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
212 "jmp{q}\t{*}$dst # TAILCALL", []>;
216 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
217 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
219 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
220 [(brind GR64:$dst)]>;
221 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
222 [(brind (loadi64 addr:$dst))]>;
223 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
224 "ljmp{q}\t{*}$dst", []>;
227 //===----------------------------------------------------------------------===//
228 // EH Pseudo Instructions
230 let isTerminator = 1, isReturn = 1, isBarrier = 1,
231 hasCtrlDep = 1, isCodeGenOnly = 1 in {
232 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
233 "ret\t#eh_return, addr: $addr",
234 [(X86ehret GR64:$addr)]>;
238 //===----------------------------------------------------------------------===//
239 // Miscellaneous Instructions...
242 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
243 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
244 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
245 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
247 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
248 def LEAVE64 : I<0xC9, RawFrm,
249 (outs), (ins), "leave", []>;
250 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
252 def POP64r : I<0x58, AddRegFrm,
253 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
254 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
255 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
257 let mayStore = 1 in {
258 def PUSH64r : I<0x50, AddRegFrm,
259 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
260 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
261 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
265 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
266 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
267 "push{q}\t$imm", []>;
268 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
269 "push{q}\t$imm", []>;
270 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
271 "push{q}\t$imm", []>;
274 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
275 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
276 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
277 def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
279 def LEA64_32r : I<0x8D, MRMSrcMem,
280 (outs GR32:$dst), (ins lea64_32mem:$src),
281 "lea{l}\t{$src|$dst}, {$dst|$src}",
282 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
284 let isReMaterializable = 1 in
285 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
286 "lea{q}\t{$src|$dst}, {$dst|$src}",
287 [(set GR64:$dst, lea64addr:$src)]>;
289 let isTwoAddress = 1 in
290 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
292 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
294 // Bit scan instructions.
295 let Defs = [EFLAGS] in {
296 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
297 "bsf{q}\t{$src, $dst|$dst, $src}",
298 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
299 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
300 "bsf{q}\t{$src, $dst|$dst, $src}",
301 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
303 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
304 "bsr{q}\t{$src, $dst|$dst, $src}",
305 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
306 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
307 "bsr{q}\t{$src, $dst|$dst, $src}",
308 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
312 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
313 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
314 [(X86rep_movs i64)]>, REP;
315 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
316 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
317 [(X86rep_stos i64)]>, REP;
319 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
321 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
323 // Fast system-call instructions
324 def SYSEXIT64 : RI<0x35, RawFrm,
325 (outs), (ins), "sysexit", []>, TB;
327 //===----------------------------------------------------------------------===//
328 // Move Instructions...
331 let neverHasSideEffects = 1 in
332 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
333 "mov{q}\t{$src, $dst|$dst, $src}", []>;
335 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
336 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
337 "movabs{q}\t{$src, $dst|$dst, $src}",
338 [(set GR64:$dst, imm:$src)]>;
339 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
340 "mov{q}\t{$src, $dst|$dst, $src}",
341 [(set GR64:$dst, i64immSExt32:$src)]>;
344 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
345 "mov{q}\t{$src, $dst|$dst, $src}", []>;
347 let canFoldAsLoad = 1, isReMaterializable = 1 in
348 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
349 "mov{q}\t{$src, $dst|$dst, $src}",
350 [(set GR64:$dst, (load addr:$src))]>;
352 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
353 "mov{q}\t{$src, $dst|$dst, $src}",
354 [(store GR64:$src, addr:$dst)]>;
355 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
356 "mov{q}\t{$src, $dst|$dst, $src}",
357 [(store i64immSExt32:$src, addr:$dst)]>;
359 /// Versions of MOV64rr, MOV64rm, and MOV64mr for i64mem_TC and GR64_TC.
360 let neverHasSideEffects = 1 in
361 def MOV64rr_TC : RI<0x89, MRMDestReg, (outs GR64_TC:$dst), (ins GR64_TC:$src),
362 "mov{q}\t{$src, $dst|$dst, $src}", []>;
365 canFoldAsLoad = 1, isReMaterializable = 1 in
366 def MOV64rm_TC : RI<0x8B, MRMSrcMem, (outs GR64_TC:$dst), (ins i64mem_TC:$src),
367 "mov{q}\t{$src, $dst|$dst, $src}",
371 def MOV64mr_TC : RI<0x89, MRMDestMem, (outs), (ins i64mem_TC:$dst, GR64_TC:$src),
372 "mov{q}\t{$src, $dst|$dst, $src}",
375 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
376 "mov{q}\t{$src, %rax|%rax, $src}", []>;
377 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
378 "mov{q}\t{$src, %rax|%rax, $src}", []>;
379 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
380 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
381 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
382 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
384 // Moves to and from segment registers
385 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
386 "mov{q}\t{$src, $dst|$dst, $src}", []>;
387 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
388 "mov{q}\t{$src, $dst|$dst, $src}", []>;
389 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
390 "mov{q}\t{$src, $dst|$dst, $src}", []>;
391 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
392 "mov{q}\t{$src, $dst|$dst, $src}", []>;
394 // Moves to and from debug registers
395 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
396 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
397 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
398 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
400 // Moves to and from control registers
401 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
402 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
403 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
404 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
406 // Sign/Zero extenders
408 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
409 // operand, which makes it a rare instruction with an 8-bit register
410 // operand that can never access an h register. If support for h registers
411 // were generalized, this would require a special register class.
412 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
413 "movs{bq|x}\t{$src, $dst|$dst, $src}",
414 [(set GR64:$dst, (sext GR8:$src))]>, TB;
415 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
416 "movs{bq|x}\t{$src, $dst|$dst, $src}",
417 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
418 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
419 "movs{wq|x}\t{$src, $dst|$dst, $src}",
420 [(set GR64:$dst, (sext GR16:$src))]>, TB;
421 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
422 "movs{wq|x}\t{$src, $dst|$dst, $src}",
423 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
424 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
425 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
426 [(set GR64:$dst, (sext GR32:$src))]>;
427 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
428 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
429 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
431 // movzbq and movzwq encodings for the disassembler
432 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
433 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
434 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
435 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
436 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
437 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
438 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
439 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
441 // Use movzbl instead of movzbq when the destination is a register; it's
442 // equivalent due to implicit zero-extending, and it has a smaller encoding.
443 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
444 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
445 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
446 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
447 // Use movzwl instead of movzwq when the destination is a register; it's
448 // equivalent due to implicit zero-extending, and it has a smaller encoding.
449 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
450 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
451 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
452 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
454 // There's no movzlq instruction, but movl can be used for this purpose, using
455 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
456 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
457 // zero-extension, however this isn't possible when the 32-bit value is
458 // defined by a truncate or is copied from something where the high bits aren't
459 // necessarily all zero. In such cases, we fall back to these explicit zext
461 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
462 "", [(set GR64:$dst, (zext GR32:$src))]>;
463 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
464 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
466 // Any instruction that defines a 32-bit result leaves the high half of the
467 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
468 // be copying from a truncate. And x86's cmov doesn't do anything if the
469 // condition is false. But any other 32-bit operation will zero-extend
471 def def32 : PatLeaf<(i32 GR32:$src), [{
472 return N->getOpcode() != ISD::TRUNCATE &&
473 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
474 N->getOpcode() != ISD::CopyFromReg &&
475 N->getOpcode() != X86ISD::CMOV;
478 // In the case of a 32-bit def that is known to implicitly zero-extend,
479 // we can use a SUBREG_TO_REG.
480 def : Pat<(i64 (zext def32:$src)),
481 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
483 let neverHasSideEffects = 1 in {
484 let Defs = [RAX], Uses = [EAX] in
485 def CDQE : RI<0x98, RawFrm, (outs), (ins),
486 "{cltq|cdqe}", []>; // RAX = signext(EAX)
488 let Defs = [RAX,RDX], Uses = [RAX] in
489 def CQO : RI<0x99, RawFrm, (outs), (ins),
490 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
493 //===----------------------------------------------------------------------===//
494 // Arithmetic Instructions...
497 let Defs = [EFLAGS] in {
499 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i32imm:$src),
500 "add{q}\t{$src, %rax|%rax, $src}", []>;
502 let isTwoAddress = 1 in {
503 let isConvertibleToThreeAddress = 1 in {
504 let isCommutable = 1 in
505 // Register-Register Addition
506 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
507 (ins GR64:$src1, GR64:$src2),
508 "add{q}\t{$src2, $dst|$dst, $src2}",
509 [(set GR64:$dst, EFLAGS,
510 (X86add_flag GR64:$src1, GR64:$src2))]>;
512 // These are alternate spellings for use by the disassembler, we mark them as
513 // code gen only to ensure they aren't matched by the assembler.
514 let isCodeGenOnly = 1 in {
515 def ADD64rr_alt : RI<0x03, MRMSrcReg, (outs GR64:$dst),
516 (ins GR64:$src1, GR64:$src2),
517 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
520 // Register-Integer Addition
521 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
522 (ins GR64:$src1, i64i8imm:$src2),
523 "add{q}\t{$src2, $dst|$dst, $src2}",
524 [(set GR64:$dst, EFLAGS,
525 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
526 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
527 (ins GR64:$src1, i64i32imm:$src2),
528 "add{q}\t{$src2, $dst|$dst, $src2}",
529 [(set GR64:$dst, EFLAGS,
530 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
531 } // isConvertibleToThreeAddress
533 // Register-Memory Addition
534 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
535 (ins GR64:$src1, i64mem:$src2),
536 "add{q}\t{$src2, $dst|$dst, $src2}",
537 [(set GR64:$dst, EFLAGS,
538 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
542 // Memory-Register Addition
543 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
544 "add{q}\t{$src2, $dst|$dst, $src2}",
545 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
547 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
548 "add{q}\t{$src2, $dst|$dst, $src2}",
549 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
551 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
552 "add{q}\t{$src2, $dst|$dst, $src2}",
553 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
556 let Uses = [EFLAGS] in {
558 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i32imm:$src),
559 "adc{q}\t{$src, %rax|%rax, $src}", []>;
561 let isTwoAddress = 1 in {
562 let isCommutable = 1 in
563 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
564 (ins GR64:$src1, GR64:$src2),
565 "adc{q}\t{$src2, $dst|$dst, $src2}",
566 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
568 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
569 (ins GR64:$src1, GR64:$src2),
570 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
572 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
573 (ins GR64:$src1, i64mem:$src2),
574 "adc{q}\t{$src2, $dst|$dst, $src2}",
575 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
577 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
578 (ins GR64:$src1, i64i8imm:$src2),
579 "adc{q}\t{$src2, $dst|$dst, $src2}",
580 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
581 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
582 (ins GR64:$src1, i64i32imm:$src2),
583 "adc{q}\t{$src2, $dst|$dst, $src2}",
584 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
587 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
588 "adc{q}\t{$src2, $dst|$dst, $src2}",
589 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
590 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
591 "adc{q}\t{$src2, $dst|$dst, $src2}",
592 [(store (adde (load addr:$dst), i64immSExt8:$src2),
594 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
595 "adc{q}\t{$src2, $dst|$dst, $src2}",
596 [(store (adde (load addr:$dst), i64immSExt32:$src2),
600 let isTwoAddress = 1 in {
601 // Register-Register Subtraction
602 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
603 (ins GR64:$src1, GR64:$src2),
604 "sub{q}\t{$src2, $dst|$dst, $src2}",
605 [(set GR64:$dst, EFLAGS,
606 (X86sub_flag GR64:$src1, GR64:$src2))]>;
608 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
609 (ins GR64:$src1, GR64:$src2),
610 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
612 // Register-Memory Subtraction
613 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
614 (ins GR64:$src1, i64mem:$src2),
615 "sub{q}\t{$src2, $dst|$dst, $src2}",
616 [(set GR64:$dst, EFLAGS,
617 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
619 // Register-Integer Subtraction
620 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
621 (ins GR64:$src1, i64i8imm:$src2),
622 "sub{q}\t{$src2, $dst|$dst, $src2}",
623 [(set GR64:$dst, EFLAGS,
624 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
625 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
626 (ins GR64:$src1, i64i32imm:$src2),
627 "sub{q}\t{$src2, $dst|$dst, $src2}",
628 [(set GR64:$dst, EFLAGS,
629 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
632 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i32imm:$src),
633 "sub{q}\t{$src, %rax|%rax, $src}", []>;
635 // Memory-Register Subtraction
636 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
637 "sub{q}\t{$src2, $dst|$dst, $src2}",
638 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
641 // Memory-Integer Subtraction
642 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
643 "sub{q}\t{$src2, $dst|$dst, $src2}",
644 [(store (sub (load addr:$dst), i64immSExt8:$src2),
647 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
648 "sub{q}\t{$src2, $dst|$dst, $src2}",
649 [(store (sub (load addr:$dst), i64immSExt32:$src2),
653 let Uses = [EFLAGS] in {
654 let isTwoAddress = 1 in {
655 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
656 (ins GR64:$src1, GR64:$src2),
657 "sbb{q}\t{$src2, $dst|$dst, $src2}",
658 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
660 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
661 (ins GR64:$src1, GR64:$src2),
662 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
664 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
665 (ins GR64:$src1, i64mem:$src2),
666 "sbb{q}\t{$src2, $dst|$dst, $src2}",
667 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
669 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
670 (ins GR64:$src1, i64i8imm:$src2),
671 "sbb{q}\t{$src2, $dst|$dst, $src2}",
672 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
673 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
674 (ins GR64:$src1, i64i32imm:$src2),
675 "sbb{q}\t{$src2, $dst|$dst, $src2}",
676 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
679 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i32imm:$src),
680 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
682 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
683 "sbb{q}\t{$src2, $dst|$dst, $src2}",
684 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
685 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
686 "sbb{q}\t{$src2, $dst|$dst, $src2}",
687 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
688 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
689 "sbb{q}\t{$src2, $dst|$dst, $src2}",
690 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
694 // Unsigned multiplication
695 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
696 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
697 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
699 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
700 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
702 // Signed multiplication
703 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
704 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
706 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
707 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
710 let Defs = [EFLAGS] in {
711 let isTwoAddress = 1 in {
712 let isCommutable = 1 in
713 // Register-Register Signed Integer Multiplication
714 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
715 (ins GR64:$src1, GR64:$src2),
716 "imul{q}\t{$src2, $dst|$dst, $src2}",
717 [(set GR64:$dst, EFLAGS,
718 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
720 // Register-Memory Signed Integer Multiplication
721 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
722 (ins GR64:$src1, i64mem:$src2),
723 "imul{q}\t{$src2, $dst|$dst, $src2}",
724 [(set GR64:$dst, EFLAGS,
725 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
728 // Suprisingly enough, these are not two address instructions!
730 // Register-Integer Signed Integer Multiplication
731 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
732 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
733 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 [(set GR64:$dst, EFLAGS,
735 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
736 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
737 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
738 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
739 [(set GR64:$dst, EFLAGS,
740 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
742 // Memory-Integer Signed Integer Multiplication
743 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
744 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
745 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
746 [(set GR64:$dst, EFLAGS,
747 (X86smul_flag (load addr:$src1),
748 i64immSExt8:$src2))]>;
749 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
750 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
751 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
752 [(set GR64:$dst, EFLAGS,
753 (X86smul_flag (load addr:$src1),
754 i64immSExt32:$src2))]>;
757 // Unsigned division / remainder
758 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
759 // RDX:RAX/r64 = RAX,RDX
760 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
762 // Signed division / remainder
763 // RDX:RAX/r64 = RAX,RDX
764 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
765 "idiv{q}\t$src", []>;
767 // RDX:RAX/[mem64] = RAX,RDX
768 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
770 // RDX:RAX/[mem64] = RAX,RDX
771 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
772 "idiv{q}\t$src", []>;
776 // Unary instructions
777 let Defs = [EFLAGS], CodeSize = 2 in {
778 let isTwoAddress = 1 in
779 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
780 [(set GR64:$dst, (ineg GR64:$src)),
782 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
783 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
786 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
787 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
788 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src))]>;
789 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
790 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
793 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
794 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
795 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src))]>;
796 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
797 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
800 // In 64-bit mode, single byte INC and DEC cannot be encoded.
801 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
802 // Can transform into LEA.
803 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
805 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
806 OpSize, Requires<[In64BitMode]>;
807 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
809 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
810 Requires<[In64BitMode]>;
811 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
813 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
814 OpSize, Requires<[In64BitMode]>;
815 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
817 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
818 Requires<[In64BitMode]>;
819 } // isConvertibleToThreeAddress
821 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
822 // how to unfold them.
823 let isTwoAddress = 0, CodeSize = 2 in {
824 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
825 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
827 OpSize, Requires<[In64BitMode]>;
828 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
829 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
831 Requires<[In64BitMode]>;
832 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
833 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
835 OpSize, Requires<[In64BitMode]>;
836 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
837 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
839 Requires<[In64BitMode]>;
841 } // Defs = [EFLAGS], CodeSize
844 let Defs = [EFLAGS] in {
845 // Shift instructions
846 let isTwoAddress = 1 in {
848 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
849 "shl{q}\t{%cl, $dst|$dst, %CL}",
850 [(set GR64:$dst, (shl GR64:$src, CL))]>;
851 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
852 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
853 (ins GR64:$src1, i8imm:$src2),
854 "shl{q}\t{$src2, $dst|$dst, $src2}",
855 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
856 // NOTE: We don't include patterns for shifts of a register by one, because
857 // 'add reg,reg' is cheaper.
858 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
863 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
864 "shl{q}\t{%cl, $dst|$dst, %CL}",
865 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
866 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
867 "shl{q}\t{$src, $dst|$dst, $src}",
868 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
869 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
871 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
873 let isTwoAddress = 1 in {
875 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
876 "shr{q}\t{%cl, $dst|$dst, %CL}",
877 [(set GR64:$dst, (srl GR64:$src, CL))]>;
878 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
879 "shr{q}\t{$src2, $dst|$dst, $src2}",
880 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
881 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
883 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
887 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
888 "shr{q}\t{%cl, $dst|$dst, %CL}",
889 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
890 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
891 "shr{q}\t{$src, $dst|$dst, $src}",
892 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
893 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
895 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
897 let isTwoAddress = 1 in {
899 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
900 "sar{q}\t{%cl, $dst|$dst, %CL}",
901 [(set GR64:$dst, (sra GR64:$src, CL))]>;
902 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
903 (ins GR64:$src1, i8imm:$src2),
904 "sar{q}\t{$src2, $dst|$dst, $src2}",
905 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
906 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
908 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
912 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
913 "sar{q}\t{%cl, $dst|$dst, %CL}",
914 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
915 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
916 "sar{q}\t{$src, $dst|$dst, $src}",
917 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
918 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
920 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
922 // Rotate instructions
924 let isTwoAddress = 1 in {
925 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
926 "rcl{q}\t{1, $dst|$dst, 1}", []>;
927 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
928 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
930 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
931 "rcr{q}\t{1, $dst|$dst, 1}", []>;
932 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
933 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
936 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
937 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
938 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
939 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
943 let isTwoAddress = 0 in {
944 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
945 "rcl{q}\t{1, $dst|$dst, 1}", []>;
946 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
947 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
948 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
949 "rcr{q}\t{1, $dst|$dst, 1}", []>;
950 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
951 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
954 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
955 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
956 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
957 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
961 let isTwoAddress = 1 in {
963 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
964 "rol{q}\t{%cl, $dst|$dst, %CL}",
965 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
966 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
967 (ins GR64:$src1, i8imm:$src2),
968 "rol{q}\t{$src2, $dst|$dst, $src2}",
969 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
970 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
972 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
976 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
977 "rol{q}\t{%cl, $dst|$dst, %CL}",
978 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
979 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
980 "rol{q}\t{$src, $dst|$dst, $src}",
981 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
982 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
984 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
986 let isTwoAddress = 1 in {
988 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
989 "ror{q}\t{%cl, $dst|$dst, %CL}",
990 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
991 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
992 (ins GR64:$src1, i8imm:$src2),
993 "ror{q}\t{$src2, $dst|$dst, $src2}",
994 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
995 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
997 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
1001 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
1002 "ror{q}\t{%cl, $dst|$dst, %CL}",
1003 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
1004 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
1005 "ror{q}\t{$src, $dst|$dst, $src}",
1006 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1007 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
1009 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
1011 // Double shift instructions (generalizations of rotate)
1012 let isTwoAddress = 1 in {
1013 let Uses = [CL] in {
1014 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
1015 (ins GR64:$src1, GR64:$src2),
1016 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1017 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
1019 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
1020 (ins GR64:$src1, GR64:$src2),
1021 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1022 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
1026 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
1027 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
1029 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1030 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1031 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1034 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1036 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1037 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1038 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1044 let Uses = [CL] in {
1045 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1046 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1047 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1049 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1050 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1051 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1054 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1055 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1056 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1057 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1058 (i8 imm:$src3)), addr:$dst)]>,
1060 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1061 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1062 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1063 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1064 (i8 imm:$src3)), addr:$dst)]>,
1066 } // Defs = [EFLAGS]
1068 //===----------------------------------------------------------------------===//
1069 // Logical Instructions...
1072 let isTwoAddress = 1 , AddedComplexity = 15 in
1073 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1074 [(set GR64:$dst, (not GR64:$src))]>;
1075 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1076 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1078 let Defs = [EFLAGS] in {
1079 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i32imm:$src),
1080 "and{q}\t{$src, %rax|%rax, $src}", []>;
1082 let isTwoAddress = 1 in {
1083 let isCommutable = 1 in
1084 def AND64rr : RI<0x21, MRMDestReg,
1085 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1086 "and{q}\t{$src2, $dst|$dst, $src2}",
1087 [(set GR64:$dst, EFLAGS,
1088 (X86and_flag GR64:$src1, GR64:$src2))]>;
1089 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1090 (ins GR64:$src1, GR64:$src2),
1091 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
1092 def AND64rm : RI<0x23, MRMSrcMem,
1093 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1094 "and{q}\t{$src2, $dst|$dst, $src2}",
1095 [(set GR64:$dst, EFLAGS,
1096 (X86and_flag GR64:$src1, (load addr:$src2)))]>;
1097 def AND64ri8 : RIi8<0x83, MRM4r,
1098 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1099 "and{q}\t{$src2, $dst|$dst, $src2}",
1100 [(set GR64:$dst, EFLAGS,
1101 (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
1102 def AND64ri32 : RIi32<0x81, MRM4r,
1103 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1104 "and{q}\t{$src2, $dst|$dst, $src2}",
1105 [(set GR64:$dst, EFLAGS,
1106 (X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
1109 def AND64mr : RI<0x21, MRMDestMem,
1110 (outs), (ins i64mem:$dst, GR64:$src),
1111 "and{q}\t{$src, $dst|$dst, $src}",
1112 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
1113 (implicit EFLAGS)]>;
1114 def AND64mi8 : RIi8<0x83, MRM4m,
1115 (outs), (ins i64mem:$dst, i64i8imm :$src),
1116 "and{q}\t{$src, $dst|$dst, $src}",
1117 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1118 (implicit EFLAGS)]>;
1119 def AND64mi32 : RIi32<0x81, MRM4m,
1120 (outs), (ins i64mem:$dst, i64i32imm:$src),
1121 "and{q}\t{$src, $dst|$dst, $src}",
1122 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1123 (implicit EFLAGS)]>;
1125 let isTwoAddress = 1 in {
1126 let isCommutable = 1 in
1127 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1128 (ins GR64:$src1, GR64:$src2),
1129 "or{q}\t{$src2, $dst|$dst, $src2}",
1130 [(set GR64:$dst, EFLAGS,
1131 (X86or_flag GR64:$src1, GR64:$src2))]>;
1132 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1133 (ins GR64:$src1, GR64:$src2),
1134 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1135 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1136 (ins GR64:$src1, i64mem:$src2),
1137 "or{q}\t{$src2, $dst|$dst, $src2}",
1138 [(set GR64:$dst, EFLAGS,
1139 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
1140 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1141 (ins GR64:$src1, i64i8imm:$src2),
1142 "or{q}\t{$src2, $dst|$dst, $src2}",
1143 [(set GR64:$dst, EFLAGS,
1144 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
1145 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1146 (ins GR64:$src1, i64i32imm:$src2),
1147 "or{q}\t{$src2, $dst|$dst, $src2}",
1148 [(set GR64:$dst, EFLAGS,
1149 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
1152 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1153 "or{q}\t{$src, $dst|$dst, $src}",
1154 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1155 (implicit EFLAGS)]>;
1156 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1157 "or{q}\t{$src, $dst|$dst, $src}",
1158 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1159 (implicit EFLAGS)]>;
1160 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1161 "or{q}\t{$src, $dst|$dst, $src}",
1162 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1163 (implicit EFLAGS)]>;
1165 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1166 "or{q}\t{$src, %rax|%rax, $src}", []>;
1168 let isTwoAddress = 1 in {
1169 let isCommutable = 1 in
1170 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1171 (ins GR64:$src1, GR64:$src2),
1172 "xor{q}\t{$src2, $dst|$dst, $src2}",
1173 [(set GR64:$dst, EFLAGS,
1174 (X86xor_flag GR64:$src1, GR64:$src2))]>;
1175 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1176 (ins GR64:$src1, GR64:$src2),
1177 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1178 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1179 (ins GR64:$src1, i64mem:$src2),
1180 "xor{q}\t{$src2, $dst|$dst, $src2}",
1181 [(set GR64:$dst, EFLAGS,
1182 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
1183 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1184 (ins GR64:$src1, i64i8imm:$src2),
1185 "xor{q}\t{$src2, $dst|$dst, $src2}",
1186 [(set GR64:$dst, EFLAGS,
1187 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
1188 def XOR64ri32 : RIi32<0x81, MRM6r,
1189 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1190 "xor{q}\t{$src2, $dst|$dst, $src2}",
1191 [(set GR64:$dst, EFLAGS,
1192 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
1195 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1196 "xor{q}\t{$src, $dst|$dst, $src}",
1197 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1198 (implicit EFLAGS)]>;
1199 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1200 "xor{q}\t{$src, $dst|$dst, $src}",
1201 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1202 (implicit EFLAGS)]>;
1203 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1204 "xor{q}\t{$src, $dst|$dst, $src}",
1205 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1206 (implicit EFLAGS)]>;
1208 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1209 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1211 } // Defs = [EFLAGS]
1213 //===----------------------------------------------------------------------===//
1214 // Comparison Instructions...
1217 // Integer comparison
1218 let Defs = [EFLAGS] in {
1219 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i32imm:$src),
1220 "test{q}\t{$src, %rax|%rax, $src}", []>;
1221 let isCommutable = 1 in
1222 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1223 "test{q}\t{$src2, $src1|$src1, $src2}",
1224 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1225 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1226 "test{q}\t{$src2, $src1|$src1, $src2}",
1227 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1229 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1230 (ins GR64:$src1, i64i32imm:$src2),
1231 "test{q}\t{$src2, $src1|$src1, $src2}",
1232 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1234 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1235 (ins i64mem:$src1, i64i32imm:$src2),
1236 "test{q}\t{$src2, $src1|$src1, $src2}",
1237 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1238 i64immSExt32:$src2), 0))]>;
1241 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1242 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1243 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1244 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1245 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1247 // These are alternate spellings for use by the disassembler, we mark them as
1248 // code gen only to ensure they aren't matched by the assembler.
1249 let isCodeGenOnly = 1 in {
1250 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1251 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1254 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1255 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1256 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1257 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1258 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1259 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1260 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1261 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1262 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1263 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1264 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1265 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1266 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1267 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1268 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1269 i64immSExt8:$src2))]>;
1270 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1271 (ins i64mem:$src1, i64i32imm:$src2),
1272 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1273 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1274 i64immSExt32:$src2))]>;
1275 } // Defs = [EFLAGS]
1278 // TODO: BTC, BTR, and BTS
1279 let Defs = [EFLAGS] in {
1280 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1281 "bt{q}\t{$src2, $src1|$src1, $src2}",
1282 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1284 // Unlike with the register+register form, the memory+register form of the
1285 // bt instruction does not ignore the high bits of the index. From ISel's
1286 // perspective, this is pretty bizarre. Disable these instructions for now.
1287 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1288 "bt{q}\t{$src2, $src1|$src1, $src2}",
1289 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1290 // (implicit EFLAGS)]
1294 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1295 "bt{q}\t{$src2, $src1|$src1, $src2}",
1296 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1297 // Note that these instructions don't need FastBTMem because that
1298 // only applies when the other operand is in a register. When it's
1299 // an immediate, bt is still fast.
1300 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1301 "bt{q}\t{$src2, $src1|$src1, $src2}",
1302 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1303 i64immSExt8:$src2))]>, TB;
1305 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1306 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1307 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1308 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1309 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1310 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1311 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1312 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1314 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1315 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1316 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1317 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1318 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1319 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1320 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1321 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1323 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1324 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1325 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1326 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1327 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1328 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1329 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1330 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1331 } // Defs = [EFLAGS]
1333 // Conditional moves
1334 let Uses = [EFLAGS], isTwoAddress = 1 in {
1335 let isCommutable = 1 in {
1336 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1337 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1338 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1340 X86_COND_B, EFLAGS))]>, TB;
1341 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1342 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1343 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1344 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1345 X86_COND_AE, EFLAGS))]>, TB;
1346 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1347 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1348 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1350 X86_COND_E, EFLAGS))]>, TB;
1351 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1352 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1353 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1354 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1355 X86_COND_NE, EFLAGS))]>, TB;
1356 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1357 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1358 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1360 X86_COND_BE, EFLAGS))]>, TB;
1361 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1362 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1363 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1364 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1365 X86_COND_A, EFLAGS))]>, TB;
1366 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1367 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1368 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1369 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1370 X86_COND_L, EFLAGS))]>, TB;
1371 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1372 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1373 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1374 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1375 X86_COND_GE, EFLAGS))]>, TB;
1376 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1377 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1378 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1380 X86_COND_LE, EFLAGS))]>, TB;
1381 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1382 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1383 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1384 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1385 X86_COND_G, EFLAGS))]>, TB;
1386 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1387 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1388 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1389 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1390 X86_COND_S, EFLAGS))]>, TB;
1391 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1392 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1393 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1394 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1395 X86_COND_NS, EFLAGS))]>, TB;
1396 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1397 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1398 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1400 X86_COND_P, EFLAGS))]>, TB;
1401 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1402 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1403 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1404 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1405 X86_COND_NP, EFLAGS))]>, TB;
1406 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1407 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1408 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1410 X86_COND_O, EFLAGS))]>, TB;
1411 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1412 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1413 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1414 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1415 X86_COND_NO, EFLAGS))]>, TB;
1416 } // isCommutable = 1
1418 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1419 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1420 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1422 X86_COND_B, EFLAGS))]>, TB;
1423 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1424 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1425 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1426 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1427 X86_COND_AE, EFLAGS))]>, TB;
1428 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1429 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1430 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1431 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1432 X86_COND_E, EFLAGS))]>, TB;
1433 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1434 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1435 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1437 X86_COND_NE, EFLAGS))]>, TB;
1438 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1439 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1440 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1441 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1442 X86_COND_BE, EFLAGS))]>, TB;
1443 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1444 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1445 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1446 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1447 X86_COND_A, EFLAGS))]>, TB;
1448 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1449 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1450 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1452 X86_COND_L, EFLAGS))]>, TB;
1453 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1454 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1455 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1456 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1457 X86_COND_GE, EFLAGS))]>, TB;
1458 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1459 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1460 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1461 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1462 X86_COND_LE, EFLAGS))]>, TB;
1463 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1464 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1465 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1467 X86_COND_G, EFLAGS))]>, TB;
1468 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1469 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1470 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1472 X86_COND_S, EFLAGS))]>, TB;
1473 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1474 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1475 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1476 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1477 X86_COND_NS, EFLAGS))]>, TB;
1478 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1479 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1480 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1481 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1482 X86_COND_P, EFLAGS))]>, TB;
1483 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1484 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1485 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1486 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1487 X86_COND_NP, EFLAGS))]>, TB;
1488 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1489 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1490 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1491 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1492 X86_COND_O, EFLAGS))]>, TB;
1493 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1494 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1495 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1496 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1497 X86_COND_NO, EFLAGS))]>, TB;
1500 // Use sbb to materialize carry flag into a GPR.
1501 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1502 // However, Pat<> can't replicate the destination reg into the inputs of the
1504 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1506 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1507 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1508 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1510 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1513 //===----------------------------------------------------------------------===//
1514 // Conversion Instructions...
1517 // f64 -> signed i64
1518 def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1519 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1520 def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1521 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1522 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1523 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1525 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1526 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1528 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1529 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1530 (load addr:$src)))]>;
1531 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1532 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1533 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1534 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1535 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1536 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1537 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1538 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1540 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1541 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1543 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1545 (int_x86_sse2_cvttsd2si64
1546 (load addr:$src)))]>;
1548 // Signed i64 -> f64
1549 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1550 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1551 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1552 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1553 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1554 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1556 let isTwoAddress = 1 in {
1557 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1558 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1559 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1561 (int_x86_sse2_cvtsi642sd VR128:$src1,
1563 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1564 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1565 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1567 (int_x86_sse2_cvtsi642sd VR128:$src1,
1568 (loadi64 addr:$src2)))]>;
1571 // Signed i64 -> f32
1572 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1573 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1574 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1575 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1576 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1577 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1579 let isTwoAddress = 1 in {
1580 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1581 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1582 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1584 (int_x86_sse_cvtsi642ss VR128:$src1,
1586 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1588 (ins VR128:$src1, i64mem:$src2),
1589 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1591 (int_x86_sse_cvtsi642ss VR128:$src1,
1592 (loadi64 addr:$src2)))]>;
1595 // f32 -> signed i64
1596 def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1597 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1598 def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1599 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1600 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1601 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1603 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1604 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1605 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1606 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1607 (load addr:$src)))]>;
1608 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1609 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1610 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1611 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1612 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1613 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1614 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1615 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1617 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1618 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1620 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1624 // Descriptor-table support instructions
1626 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1628 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1629 "sldt{q}\t$dst", []>, TB;
1630 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1631 "sldt{q}\t$dst", []>, TB;
1633 //===----------------------------------------------------------------------===//
1634 // Alias Instructions
1635 //===----------------------------------------------------------------------===//
1637 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1638 // smaller encoding, but doing so at isel time interferes with rematerialization
1639 // in the current register allocator. For now, this is rewritten when the
1640 // instruction is lowered to an MCInst.
1641 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1642 // when we have a better way to specify isel priority.
1643 let Defs = [EFLAGS],
1644 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1645 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1646 [(set GR64:$dst, 0)]>;
1648 // Materialize i64 constant where top 32-bits are zero. This could theoretically
1649 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1650 // that would make it more difficult to rematerialize.
1651 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1652 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1653 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1655 //===----------------------------------------------------------------------===//
1656 // Thread Local Storage Instructions
1657 //===----------------------------------------------------------------------===//
1659 // All calls clobber the non-callee saved registers. RSP is marked as
1660 // a use to prevent stack-pointer assignments that appear immediately
1661 // before calls from potentially appearing dead.
1662 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1663 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1664 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1665 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1666 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1668 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1670 "leaq\t$sym(%rip), %rdi; "
1673 "call\t__tls_get_addr@PLT",
1674 [(X86tlsaddr tls64addr:$sym)]>,
1675 Requires<[In64BitMode]>;
1677 let AddedComplexity = 5, isCodeGenOnly = 1 in
1678 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1679 "movq\t%gs:$src, $dst",
1680 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1682 let AddedComplexity = 5, isCodeGenOnly = 1 in
1683 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1684 "movq\t%fs:$src, $dst",
1685 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1687 //===----------------------------------------------------------------------===//
1688 // Atomic Instructions
1689 //===----------------------------------------------------------------------===//
1691 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1692 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1694 "cmpxchgq\t$swap,$ptr",
1695 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1698 let Constraints = "$val = $dst" in {
1699 let Defs = [EFLAGS] in
1700 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1703 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1706 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1707 (ins GR64:$val,i64mem:$ptr),
1708 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1709 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1711 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1712 "xchg{q}\t{$val, $src|$src, $val}", []>;
1715 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1716 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1717 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1718 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1720 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1721 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1722 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1723 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1725 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1726 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1727 "cmpxchg16b\t$dst", []>, TB;
1729 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1730 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1732 // Optimized codegen when the non-memory output is not used.
1733 let Defs = [EFLAGS] in {
1734 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1735 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1737 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1738 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1739 (ins i64mem:$dst, i64i8imm :$src2),
1741 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1742 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1743 (ins i64mem:$dst, i64i32imm :$src2),
1745 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1746 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1748 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1749 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1750 (ins i64mem:$dst, i64i8imm :$src2),
1752 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1753 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1754 (ins i64mem:$dst, i64i32imm:$src2),
1756 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1757 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1759 "inc{q}\t$dst", []>, LOCK;
1760 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1762 "dec{q}\t$dst", []>, LOCK;
1764 // Atomic exchange, and, or, xor
1765 let Constraints = "$val = $dst", Defs = [EFLAGS],
1766 usesCustomInserter = 1 in {
1767 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1768 "#ATOMAND64 PSEUDO!",
1769 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1770 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1771 "#ATOMOR64 PSEUDO!",
1772 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1773 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1774 "#ATOMXOR64 PSEUDO!",
1775 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1776 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1777 "#ATOMNAND64 PSEUDO!",
1778 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1779 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1780 "#ATOMMIN64 PSEUDO!",
1781 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1782 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1783 "#ATOMMAX64 PSEUDO!",
1784 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1785 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1786 "#ATOMUMIN64 PSEUDO!",
1787 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1788 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1789 "#ATOMUMAX64 PSEUDO!",
1790 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1793 // Segmentation support instructions
1795 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1796 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1797 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1798 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1799 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1801 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1802 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1803 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1804 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1806 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1808 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1809 "push{q}\t%fs", []>, TB;
1810 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1811 "push{q}\t%gs", []>, TB;
1813 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1814 "pop{q}\t%fs", []>, TB;
1815 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1816 "pop{q}\t%gs", []>, TB;
1818 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1819 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1820 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1821 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1822 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1823 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1825 // Specialized register support
1827 // no m form encodable; use SMSW16m
1828 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1829 "smsw{q}\t$dst", []>, TB;
1831 // String manipulation instructions
1833 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1835 //===----------------------------------------------------------------------===//
1836 // Non-Instruction Patterns
1837 //===----------------------------------------------------------------------===//
1839 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1840 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1841 // 'movabs' predicate should handle this sort of thing.
1842 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1843 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1844 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1845 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1846 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1847 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1848 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1849 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1850 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1851 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1853 // In static codegen with small code model, we can get the address of a label
1854 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1855 // the MOV64ri64i32 should accept these.
1856 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1857 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1858 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1859 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1860 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1861 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1862 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1863 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1864 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1865 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1867 // In kernel code model, we can get the address of a label
1868 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1869 // the MOV64ri32 should accept these.
1870 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1871 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1872 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1873 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1874 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1875 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1876 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1877 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1878 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1879 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1881 // If we have small model and -static mode, it is safe to store global addresses
1882 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1883 // for MOV64mi32 should handle this sort of thing.
1884 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1885 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1886 Requires<[NearData, IsStatic]>;
1887 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1888 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1889 Requires<[NearData, IsStatic]>;
1890 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1891 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1892 Requires<[NearData, IsStatic]>;
1893 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1894 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1895 Requires<[NearData, IsStatic]>;
1896 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1897 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1898 Requires<[NearData, IsStatic]>;
1901 // Direct PC relative function call for small code model. 32-bit displacement
1902 // sign extended to 64-bit.
1903 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1904 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1905 def : Pat<(X86call (i64 texternalsym:$dst)),
1906 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1908 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1909 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1910 def : Pat<(X86call (i64 texternalsym:$dst)),
1911 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1914 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
1915 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
1916 Requires<[In64BitMode]>;
1918 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1919 (TCRETURNmi64 addr:$dst, imm:$off)>,
1920 Requires<[In64BitMode]>;
1922 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1923 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1924 Requires<[In64BitMode]>;
1926 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1927 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1928 Requires<[In64BitMode]>;
1932 // TEST R,R is smaller than CMP R,0
1933 def : Pat<(X86cmp GR64:$src1, 0),
1934 (TEST64rr GR64:$src1, GR64:$src1)>;
1936 // Conditional moves with folded loads with operands swapped and conditions
1938 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1939 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1940 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1941 (CMOVB64rm GR64:$src2, addr:$src1)>;
1942 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1943 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1944 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1945 (CMOVE64rm GR64:$src2, addr:$src1)>;
1946 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1947 (CMOVA64rm GR64:$src2, addr:$src1)>;
1948 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1949 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1950 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1951 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1952 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1953 (CMOVL64rm GR64:$src2, addr:$src1)>;
1954 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1955 (CMOVG64rm GR64:$src2, addr:$src1)>;
1956 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1957 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1958 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1959 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1960 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1961 (CMOVP64rm GR64:$src2, addr:$src1)>;
1962 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1963 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1964 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1965 (CMOVS64rm GR64:$src2, addr:$src1)>;
1966 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1967 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1968 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1969 (CMOVO64rm GR64:$src2, addr:$src1)>;
1971 // zextload bool -> zextload byte
1972 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1975 // When extloading from 16-bit and smaller memory locations into 64-bit
1976 // registers, use zero-extending loads so that the entire 64-bit register is
1977 // defined, avoiding partial-register updates.
1978 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1979 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1980 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1981 // For other extloads, use subregs, since the high contents of the register are
1982 // defined after an extload.
1983 def : Pat<(extloadi64i32 addr:$src),
1984 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1987 // anyext. Define these to do an explicit zero-extend to
1988 // avoid partial-register updates.
1989 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1990 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1991 def : Pat<(i64 (anyext GR32:$src)),
1992 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1994 //===----------------------------------------------------------------------===//
1996 //===----------------------------------------------------------------------===//
1998 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1999 // +128 doesn't, so in this special case use a sub instead of an add.
2000 def : Pat<(add GR64:$src1, 128),
2001 (SUB64ri8 GR64:$src1, -128)>;
2002 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
2003 (SUB64mi8 addr:$dst, -128)>;
2005 // The same trick applies for 32-bit immediate fields in 64-bit
2007 def : Pat<(add GR64:$src1, 0x0000000080000000),
2008 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
2009 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
2010 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
2012 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
2013 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
2014 // materialize that immediate in a register first.
2015 def : Pat<(and GR64:$src, i64immZExt32:$imm),
2019 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit),
2020 (i32 (GetLo32XForm imm:$imm))),
2023 // r & (2^32-1) ==> movz
2024 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
2025 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2026 // r & (2^16-1) ==> movz
2027 def : Pat<(and GR64:$src, 0xffff),
2028 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
2029 // r & (2^8-1) ==> movz
2030 def : Pat<(and GR64:$src, 0xff),
2031 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
2032 // r & (2^8-1) ==> movz
2033 def : Pat<(and GR32:$src1, 0xff),
2034 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
2035 Requires<[In64BitMode]>;
2036 // r & (2^8-1) ==> movz
2037 def : Pat<(and GR16:$src1, 0xff),
2038 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
2039 Requires<[In64BitMode]>;
2041 // sext_inreg patterns
2042 def : Pat<(sext_inreg GR64:$src, i32),
2043 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2044 def : Pat<(sext_inreg GR64:$src, i16),
2045 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2046 def : Pat<(sext_inreg GR64:$src, i8),
2047 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
2048 def : Pat<(sext_inreg GR32:$src, i8),
2049 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
2050 Requires<[In64BitMode]>;
2051 def : Pat<(sext_inreg GR16:$src, i8),
2052 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
2053 Requires<[In64BitMode]>;
2056 def : Pat<(i32 (trunc GR64:$src)),
2057 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
2058 def : Pat<(i16 (trunc GR64:$src)),
2059 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
2060 def : Pat<(i8 (trunc GR64:$src)),
2061 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
2062 def : Pat<(i8 (trunc GR32:$src)),
2063 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
2064 Requires<[In64BitMode]>;
2065 def : Pat<(i8 (trunc GR16:$src)),
2066 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
2067 Requires<[In64BitMode]>;
2069 // h-register tricks.
2070 // For now, be conservative on x86-64 and use an h-register extract only if the
2071 // value is immediately zero-extended or stored, which are somewhat common
2072 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
2073 // from being allocated in the same instruction as the h register, as there's
2074 // currently no way to describe this requirement to the register allocator.
2076 // h-register extract and zero-extend.
2077 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2081 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2082 x86_subreg_8bit_hi)),
2084 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2086 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2087 x86_subreg_8bit_hi))>,
2088 Requires<[In64BitMode]>;
2089 def : Pat<(srl GR16:$src, (i8 8)),
2092 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2093 x86_subreg_8bit_hi)),
2095 Requires<[In64BitMode]>;
2096 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2098 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2099 x86_subreg_8bit_hi))>,
2100 Requires<[In64BitMode]>;
2101 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2103 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2104 x86_subreg_8bit_hi))>,
2105 Requires<[In64BitMode]>;
2106 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2110 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2111 x86_subreg_8bit_hi)),
2113 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2117 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2118 x86_subreg_8bit_hi)),
2121 // h-register extract and store.
2122 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2125 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2126 x86_subreg_8bit_hi))>;
2127 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2130 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2131 x86_subreg_8bit_hi))>,
2132 Requires<[In64BitMode]>;
2133 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2136 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2137 x86_subreg_8bit_hi))>,
2138 Requires<[In64BitMode]>;
2140 // (shl x, 1) ==> (add x, x)
2141 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2143 // (shl x (and y, 63)) ==> (shl x, y)
2144 def : Pat<(shl GR64:$src1, (and CL, 63)),
2145 (SHL64rCL GR64:$src1)>;
2146 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2147 (SHL64mCL addr:$dst)>;
2149 def : Pat<(srl GR64:$src1, (and CL, 63)),
2150 (SHR64rCL GR64:$src1)>;
2151 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2152 (SHR64mCL addr:$dst)>;
2154 def : Pat<(sra GR64:$src1, (and CL, 63)),
2155 (SAR64rCL GR64:$src1)>;
2156 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2157 (SAR64mCL addr:$dst)>;
2159 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2160 let AddedComplexity = 5 in { // Try this before the selecting to OR
2161 def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
2162 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2163 def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
2164 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2165 def : Pat<(or_is_add GR64:$src1, GR64:$src2),
2166 (ADD64rr GR64:$src1, GR64:$src2)>;
2167 } // AddedComplexity
2169 // X86 specific add which produces a flag.
2170 def : Pat<(addc GR64:$src1, GR64:$src2),
2171 (ADD64rr GR64:$src1, GR64:$src2)>;
2172 def : Pat<(addc GR64:$src1, (load addr:$src2)),
2173 (ADD64rm GR64:$src1, addr:$src2)>;
2174 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2175 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2176 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2177 (ADD64ri32 GR64:$src1, imm:$src2)>;
2179 def : Pat<(subc GR64:$src1, GR64:$src2),
2180 (SUB64rr GR64:$src1, GR64:$src2)>;
2181 def : Pat<(subc GR64:$src1, (load addr:$src2)),
2182 (SUB64rm GR64:$src1, addr:$src2)>;
2183 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2184 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2185 def : Pat<(subc GR64:$src1, imm:$src2),
2186 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2188 //===----------------------------------------------------------------------===//
2189 // EFLAGS-defining Patterns
2190 //===----------------------------------------------------------------------===//
2193 def : Pat<(add GR64:$src1, GR64:$src2),
2194 (ADD64rr GR64:$src1, GR64:$src2)>;
2195 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
2196 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2197 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
2198 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2199 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
2200 (ADD64rm GR64:$src1, addr:$src2)>;
2203 def : Pat<(sub GR64:$src1, GR64:$src2),
2204 (SUB64rr GR64:$src1, GR64:$src2)>;
2205 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
2206 (SUB64rm GR64:$src1, addr:$src2)>;
2207 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
2208 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2209 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
2210 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2213 def : Pat<(mul GR64:$src1, GR64:$src2),
2214 (IMUL64rr GR64:$src1, GR64:$src2)>;
2215 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
2216 (IMUL64rm GR64:$src1, addr:$src2)>;
2217 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
2218 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2219 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
2220 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2221 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
2222 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2223 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
2224 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2227 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2228 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2229 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2230 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2231 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
2232 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
2235 def : Pat<(or GR64:$src1, GR64:$src2),
2236 (OR64rr GR64:$src1, GR64:$src2)>;
2237 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
2238 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2239 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
2240 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2241 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
2242 (OR64rm GR64:$src1, addr:$src2)>;
2245 def : Pat<(xor GR64:$src1, GR64:$src2),
2246 (XOR64rr GR64:$src1, GR64:$src2)>;
2247 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
2248 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2249 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
2250 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2251 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
2252 (XOR64rm GR64:$src1, addr:$src2)>;
2255 def : Pat<(and GR64:$src1, GR64:$src2),
2256 (AND64rr GR64:$src1, GR64:$src2)>;
2257 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
2258 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2259 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
2260 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2261 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
2262 (AND64rm GR64:$src1, addr:$src2)>;
2264 //===----------------------------------------------------------------------===//
2265 // X86-64 SSE Instructions
2266 //===----------------------------------------------------------------------===//
2268 // Move instructions...
2270 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2271 "mov{d|q}\t{$src, $dst|$dst, $src}",
2273 (v2i64 (scalar_to_vector GR64:$src)))]>;
2274 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2275 "mov{d|q}\t{$src, $dst|$dst, $src}",
2276 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2279 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2280 "mov{d|q}\t{$src, $dst|$dst, $src}",
2281 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2282 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2283 "movq\t{$src, $dst|$dst, $src}",
2284 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2286 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2287 "mov{d|q}\t{$src, $dst|$dst, $src}",
2288 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2289 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2290 "movq\t{$src, $dst|$dst, $src}",
2291 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2293 //===----------------------------------------------------------------------===//
2294 // X86-64 SSE4.1 Instructions
2295 //===----------------------------------------------------------------------===//
2297 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2298 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2299 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2300 (ins VR128:$src1, i32i8imm:$src2),
2301 !strconcat(OpcodeStr,
2302 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2304 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2305 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2306 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2307 !strconcat(OpcodeStr,
2308 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2309 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2310 addr:$dst)]>, OpSize, REX_W;
2313 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2315 let isTwoAddress = 1 in {
2316 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2317 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2318 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2319 !strconcat(OpcodeStr,
2320 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2322 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2324 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2325 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2326 !strconcat(OpcodeStr,
2327 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2329 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2330 imm:$src3)))]>, OpSize, REX_W;
2334 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2336 // -disable-16bit support.
2337 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
2338 (MOV16mi addr:$dst, imm:$src)>;
2339 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2340 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2341 def : Pat<(i64 (sextloadi16 addr:$dst)),
2342 (MOVSX64rm16 addr:$dst)>;
2343 def : Pat<(i64 (zextloadi16 addr:$dst)),
2344 (MOVZX64rm16 addr:$dst)>;
2345 def : Pat<(i64 (extloadi16 addr:$dst)),
2346 (MOVZX64rm16 addr:$dst)>;