1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions.
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
46 def i64immSExt8 : PatLeaf<(i64 imm), [{
47 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
48 // sign extended field.
49 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
52 def i64immSExt32 : PatLeaf<(i64 imm), [{
53 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // sign extended field.
55 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
58 def i64immZExt32 : PatLeaf<(i64 imm), [{
59 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
60 // unsignedsign extended field.
61 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
64 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
65 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
66 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
68 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
69 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
70 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
71 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
73 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
74 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
75 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
76 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
78 //===----------------------------------------------------------------------===//
79 // Instruction list...
82 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
83 // a stack adjustment and the codegen must know that they may modify the stack
84 // pointer before prolog-epilog rewriting occurs.
85 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
86 // sub / add which can clobber EFLAGS.
87 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
90 [(X86callseq_start timm:$amt)]>,
91 Requires<[In64BitMode]>;
92 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
94 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
95 Requires<[In64BitMode]>;
98 //===----------------------------------------------------------------------===//
99 // Call Instructions...
102 // All calls clobber the non-callee saved registers. RSP is marked as
103 // a use to prevent stack-pointer assignments that appear immediately
104 // before calls from potentially appearing dead. Uses for argument
105 // registers are added manually.
106 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
107 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
108 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
109 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
110 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
112 def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops),
113 "call\t${dst:call}", []>;
114 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
115 "call\t{*}$dst", [(X86call GR64:$dst)]>;
116 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
117 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>;
122 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
123 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
125 "#TC_RETURN $dst $offset",
128 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
129 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
131 "#TC_RETURN $dst $offset",
135 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
136 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
137 "jmp{q}\t{*}$dst # TAILCALL",
141 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
142 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
143 [(brind GR64:$dst)]>;
144 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
145 [(brind (loadi64 addr:$dst))]>;
148 //===----------------------------------------------------------------------===//
149 // EH Pseudo Instructions
151 let isTerminator = 1, isReturn = 1, isBarrier = 1,
153 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
154 "ret\t#eh_return, addr: $addr",
155 [(X86ehret GR64:$addr)]>;
159 //===----------------------------------------------------------------------===//
160 // Miscellaneous Instructions...
162 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
163 def LEAVE64 : I<0xC9, RawFrm,
164 (outs), (ins), "leave", []>;
165 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
167 def POP64r : I<0x58, AddRegFrm,
168 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
170 def PUSH64r : I<0x50, AddRegFrm,
171 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
174 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
175 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
176 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
177 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
179 def LEA64_32r : I<0x8D, MRMSrcMem,
180 (outs GR32:$dst), (ins lea64_32mem:$src),
181 "lea{l}\t{$src|$dst}, {$dst|$src}",
182 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
184 let isReMaterializable = 1 in
185 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
186 "lea{q}\t{$src|$dst}, {$dst|$src}",
187 [(set GR64:$dst, lea64addr:$src)]>;
189 let isTwoAddress = 1 in
190 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
192 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
194 // Bit scan instructions.
195 let Defs = [EFLAGS] in {
196 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
197 "bsf{q}\t{$src, $dst|$dst, $src}",
198 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
199 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
200 "bsf{q}\t{$src, $dst|$dst, $src}",
201 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
202 (implicit EFLAGS)]>, TB;
204 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
205 "bsr{q}\t{$src, $dst|$dst, $src}",
206 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
207 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
208 "bsr{q}\t{$src, $dst|$dst, $src}",
209 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
210 (implicit EFLAGS)]>, TB;
214 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
215 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
216 [(X86rep_movs i64)]>, REP;
217 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
218 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
219 [(X86rep_stos i64)]>, REP;
221 //===----------------------------------------------------------------------===//
222 // Move Instructions...
225 let neverHasSideEffects = 1 in
226 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
227 "mov{q}\t{$src, $dst|$dst, $src}", []>;
229 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
230 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
231 "movabs{q}\t{$src, $dst|$dst, $src}",
232 [(set GR64:$dst, imm:$src)]>;
233 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
234 "mov{q}\t{$src, $dst|$dst, $src}",
235 [(set GR64:$dst, i64immSExt32:$src)]>;
238 let canFoldAsLoad = 1 in
239 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
240 "mov{q}\t{$src, $dst|$dst, $src}",
241 [(set GR64:$dst, (load addr:$src))]>;
243 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
244 "mov{q}\t{$src, $dst|$dst, $src}",
245 [(store GR64:$src, addr:$dst)]>;
246 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
247 "mov{q}\t{$src, $dst|$dst, $src}",
248 [(store i64immSExt32:$src, addr:$dst)]>;
250 // Sign/Zero extenders
252 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
253 "movs{bq|x}\t{$src, $dst|$dst, $src}",
254 [(set GR64:$dst, (sext GR8:$src))]>, TB;
255 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
256 "movs{bq|x}\t{$src, $dst|$dst, $src}",
257 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
258 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
259 "movs{wq|x}\t{$src, $dst|$dst, $src}",
260 [(set GR64:$dst, (sext GR16:$src))]>, TB;
261 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
262 "movs{wq|x}\t{$src, $dst|$dst, $src}",
263 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
264 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
265 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
266 [(set GR64:$dst, (sext GR32:$src))]>;
267 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
268 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
269 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
271 // Use movzbl instead of movzbq when the destination is a register; it's
272 // equivalent due to implicit zero-extending, and it has a smaller encoding.
273 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
274 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
275 [(set GR64:$dst, (zext GR8:$src))]>, TB;
276 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
277 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
278 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
279 // Use movzwl instead of movzwq when the destination is a register; it's
280 // equivalent due to implicit zero-extending, and it has a smaller encoding.
281 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
282 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
283 [(set GR64:$dst, (zext GR16:$src))]>, TB;
284 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
285 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
286 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
288 // There's no movzlq instruction, but movl can be used for this purpose, using
289 // implicit zero-extension. We need this because the seeming alternative for
290 // implementing zext from 32 to 64, an EXTRACT_SUBREG/SUBREG_TO_REG pair, isn't
291 // safe because both instructions could be optimized away in the
292 // register-to-register case, leaving nothing behind to do the zero extension.
293 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
294 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
295 [(set GR64:$dst, (zext GR32:$src))]>;
296 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
297 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
298 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
300 let neverHasSideEffects = 1 in {
301 let Defs = [RAX], Uses = [EAX] in
302 def CDQE : RI<0x98, RawFrm, (outs), (ins),
303 "{cltq|cdqe}", []>; // RAX = signext(EAX)
305 let Defs = [RAX,RDX], Uses = [RAX] in
306 def CQO : RI<0x99, RawFrm, (outs), (ins),
307 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
310 //===----------------------------------------------------------------------===//
311 // Arithmetic Instructions...
314 let Defs = [EFLAGS] in {
315 let isTwoAddress = 1 in {
316 let isConvertibleToThreeAddress = 1 in {
317 let isCommutable = 1 in
318 // Register-Register Addition
319 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
320 "add{q}\t{$src2, $dst|$dst, $src2}",
321 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
324 // Register-Integer Addition
325 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
326 "add{q}\t{$src2, $dst|$dst, $src2}",
327 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
329 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
330 "add{q}\t{$src2, $dst|$dst, $src2}",
331 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
333 } // isConvertibleToThreeAddress
335 // Register-Memory Addition
336 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
337 "add{q}\t{$src2, $dst|$dst, $src2}",
338 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
342 // Memory-Register Addition
343 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
344 "add{q}\t{$src2, $dst|$dst, $src2}",
345 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
347 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
348 "add{q}\t{$src2, $dst|$dst, $src2}",
349 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
351 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
352 "add{q}\t{$src2, $dst|$dst, $src2}",
353 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
356 let Uses = [EFLAGS] in {
357 let isTwoAddress = 1 in {
358 let isCommutable = 1 in
359 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
360 "adc{q}\t{$src2, $dst|$dst, $src2}",
361 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
363 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
364 "adc{q}\t{$src2, $dst|$dst, $src2}",
365 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
367 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
368 "adc{q}\t{$src2, $dst|$dst, $src2}",
369 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
370 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
371 "adc{q}\t{$src2, $dst|$dst, $src2}",
372 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
375 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
376 "adc{q}\t{$src2, $dst|$dst, $src2}",
377 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
378 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
379 "adc{q}\t{$src2, $dst|$dst, $src2}",
380 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
381 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
382 "adc{q}\t{$src2, $dst|$dst, $src2}",
383 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
386 let isTwoAddress = 1 in {
387 // Register-Register Subtraction
388 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
389 "sub{q}\t{$src2, $dst|$dst, $src2}",
390 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
393 // Register-Memory Subtraction
394 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
395 "sub{q}\t{$src2, $dst|$dst, $src2}",
396 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
399 // Register-Integer Subtraction
400 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
401 (ins GR64:$src1, i64i8imm:$src2),
402 "sub{q}\t{$src2, $dst|$dst, $src2}",
403 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
405 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
406 (ins GR64:$src1, i64i32imm:$src2),
407 "sub{q}\t{$src2, $dst|$dst, $src2}",
408 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
412 // Memory-Register Subtraction
413 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
414 "sub{q}\t{$src2, $dst|$dst, $src2}",
415 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
418 // Memory-Integer Subtraction
419 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
420 "sub{q}\t{$src2, $dst|$dst, $src2}",
421 [(store (sub (load addr:$dst), i64immSExt8:$src2),
424 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
425 "sub{q}\t{$src2, $dst|$dst, $src2}",
426 [(store (sub (load addr:$dst), i64immSExt32:$src2),
430 let Uses = [EFLAGS] in {
431 let isTwoAddress = 1 in {
432 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
433 "sbb{q}\t{$src2, $dst|$dst, $src2}",
434 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
436 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
437 "sbb{q}\t{$src2, $dst|$dst, $src2}",
438 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
440 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
441 "sbb{q}\t{$src2, $dst|$dst, $src2}",
442 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
443 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
444 "sbb{q}\t{$src2, $dst|$dst, $src2}",
445 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
448 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
449 "sbb{q}\t{$src2, $dst|$dst, $src2}",
450 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
451 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
452 "sbb{q}\t{$src2, $dst|$dst, $src2}",
453 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
454 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
455 "sbb{q}\t{$src2, $dst|$dst, $src2}",
456 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
460 // Unsigned multiplication
461 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
462 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
463 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
465 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
466 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
468 // Signed multiplication
469 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
470 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
472 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
473 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
476 let Defs = [EFLAGS] in {
477 let isTwoAddress = 1 in {
478 let isCommutable = 1 in
479 // Register-Register Signed Integer Multiplication
480 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
481 (ins GR64:$src1, GR64:$src2),
482 "imul{q}\t{$src2, $dst|$dst, $src2}",
483 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
484 (implicit EFLAGS)]>, TB;
486 // Register-Memory Signed Integer Multiplication
487 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
488 (ins GR64:$src1, i64mem:$src2),
489 "imul{q}\t{$src2, $dst|$dst, $src2}",
490 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
491 (implicit EFLAGS)]>, TB;
494 // Suprisingly enough, these are not two address instructions!
496 // Register-Integer Signed Integer Multiplication
497 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
498 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
499 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
500 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
502 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
503 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
504 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
505 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
508 // Memory-Integer Signed Integer Multiplication
509 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
510 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
511 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
512 [(set GR64:$dst, (mul (load addr:$src1),
515 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
516 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
517 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
518 [(set GR64:$dst, (mul (load addr:$src1),
519 i64immSExt32:$src2)),
523 // Unsigned division / remainder
524 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
525 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
527 // Signed division / remainder
528 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
529 "idiv{q}\t$src", []>;
531 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
533 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
534 "idiv{q}\t$src", []>;
538 // Unary instructions
539 let Defs = [EFLAGS], CodeSize = 2 in {
540 let isTwoAddress = 1 in
541 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
542 [(set GR64:$dst, (ineg GR64:$src))]>;
543 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
544 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
546 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
547 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
548 [(set GR64:$dst, (add GR64:$src, 1))]>;
549 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
550 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
552 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
553 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
554 [(set GR64:$dst, (add GR64:$src, -1))]>;
555 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
556 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
558 // In 64-bit mode, single byte INC and DEC cannot be encoded.
559 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
560 // Can transform into LEA.
561 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
562 [(set GR16:$dst, (add GR16:$src, 1))]>,
563 OpSize, Requires<[In64BitMode]>;
564 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
565 [(set GR32:$dst, (add GR32:$src, 1))]>,
566 Requires<[In64BitMode]>;
567 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
568 [(set GR16:$dst, (add GR16:$src, -1))]>,
569 OpSize, Requires<[In64BitMode]>;
570 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
571 [(set GR32:$dst, (add GR32:$src, -1))]>,
572 Requires<[In64BitMode]>;
573 } // isConvertibleToThreeAddress
575 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
576 // how to unfold them.
577 let isTwoAddress = 0, CodeSize = 2 in {
578 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
579 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
580 OpSize, Requires<[In64BitMode]>;
581 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
582 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
583 Requires<[In64BitMode]>;
584 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
585 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
586 OpSize, Requires<[In64BitMode]>;
587 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
588 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
589 Requires<[In64BitMode]>;
591 } // Defs = [EFLAGS], CodeSize
594 let Defs = [EFLAGS] in {
595 // Shift instructions
596 let isTwoAddress = 1 in {
598 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
599 "shl{q}\t{%cl, $dst|$dst, %CL}",
600 [(set GR64:$dst, (shl GR64:$src, CL))]>;
601 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
602 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
603 "shl{q}\t{$src2, $dst|$dst, $src2}",
604 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
605 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
610 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
611 "shl{q}\t{%cl, $dst|$dst, %CL}",
612 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
613 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
614 "shl{q}\t{$src, $dst|$dst, $src}",
615 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
616 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
618 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
620 let isTwoAddress = 1 in {
622 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
623 "shr{q}\t{%cl, $dst|$dst, %CL}",
624 [(set GR64:$dst, (srl GR64:$src, CL))]>;
625 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
626 "shr{q}\t{$src2, $dst|$dst, $src2}",
627 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
628 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
630 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
634 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
635 "shr{q}\t{%cl, $dst|$dst, %CL}",
636 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
637 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
638 "shr{q}\t{$src, $dst|$dst, $src}",
639 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
640 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
642 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
644 let isTwoAddress = 1 in {
646 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
647 "sar{q}\t{%cl, $dst|$dst, %CL}",
648 [(set GR64:$dst, (sra GR64:$src, CL))]>;
649 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
650 "sar{q}\t{$src2, $dst|$dst, $src2}",
651 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
652 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
654 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
658 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
659 "sar{q}\t{%cl, $dst|$dst, %CL}",
660 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
661 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
662 "sar{q}\t{$src, $dst|$dst, $src}",
663 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
664 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
666 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
668 // Rotate instructions
669 let isTwoAddress = 1 in {
671 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
672 "rol{q}\t{%cl, $dst|$dst, %CL}",
673 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
674 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
675 "rol{q}\t{$src2, $dst|$dst, $src2}",
676 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
677 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
679 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
683 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
684 "rol{q}\t{%cl, $dst|$dst, %CL}",
685 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
686 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
687 "rol{q}\t{$src, $dst|$dst, $src}",
688 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
689 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
691 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
693 let isTwoAddress = 1 in {
695 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
696 "ror{q}\t{%cl, $dst|$dst, %CL}",
697 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
698 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
699 "ror{q}\t{$src2, $dst|$dst, $src2}",
700 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
701 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
703 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
707 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
708 "ror{q}\t{%cl, $dst|$dst, %CL}",
709 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
710 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
711 "ror{q}\t{$src, $dst|$dst, $src}",
712 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
713 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
715 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
717 // Double shift instructions (generalizations of rotate)
718 let isTwoAddress = 1 in {
720 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
721 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
722 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
723 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
724 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
725 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
728 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
729 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
730 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
731 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
732 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
735 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
736 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
737 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
738 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
745 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
746 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
747 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
749 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
750 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
751 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
754 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
755 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
756 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
757 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
758 (i8 imm:$src3)), addr:$dst)]>,
760 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
761 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
762 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
763 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
764 (i8 imm:$src3)), addr:$dst)]>,
768 //===----------------------------------------------------------------------===//
769 // Logical Instructions...
772 let isTwoAddress = 1 , AddedComplexity = 15 in
773 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
774 [(set GR64:$dst, (not GR64:$src))]>;
775 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
776 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
778 let Defs = [EFLAGS] in {
779 let isTwoAddress = 1 in {
780 let isCommutable = 1 in
781 def AND64rr : RI<0x21, MRMDestReg,
782 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
783 "and{q}\t{$src2, $dst|$dst, $src2}",
784 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
785 def AND64rm : RI<0x23, MRMSrcMem,
786 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
787 "and{q}\t{$src2, $dst|$dst, $src2}",
788 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
789 def AND64ri8 : RIi8<0x83, MRM4r,
790 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
791 "and{q}\t{$src2, $dst|$dst, $src2}",
792 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
793 def AND64ri32 : RIi32<0x81, MRM4r,
794 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
795 "and{q}\t{$src2, $dst|$dst, $src2}",
796 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
799 def AND64mr : RI<0x21, MRMDestMem,
800 (outs), (ins i64mem:$dst, GR64:$src),
801 "and{q}\t{$src, $dst|$dst, $src}",
802 [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
803 def AND64mi8 : RIi8<0x83, MRM4m,
804 (outs), (ins i64mem:$dst, i64i8imm :$src),
805 "and{q}\t{$src, $dst|$dst, $src}",
806 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
807 def AND64mi32 : RIi32<0x81, MRM4m,
808 (outs), (ins i64mem:$dst, i64i32imm:$src),
809 "and{q}\t{$src, $dst|$dst, $src}",
810 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
812 let isTwoAddress = 1 in {
813 let isCommutable = 1 in
814 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
815 "or{q}\t{$src2, $dst|$dst, $src2}",
816 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
817 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
818 "or{q}\t{$src2, $dst|$dst, $src2}",
819 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
820 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
821 "or{q}\t{$src2, $dst|$dst, $src2}",
822 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
823 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
824 "or{q}\t{$src2, $dst|$dst, $src2}",
825 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
828 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
829 "or{q}\t{$src, $dst|$dst, $src}",
830 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
831 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
832 "or{q}\t{$src, $dst|$dst, $src}",
833 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
834 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
835 "or{q}\t{$src, $dst|$dst, $src}",
836 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
838 let isTwoAddress = 1 in {
839 let isCommutable = 1 in
840 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
841 "xor{q}\t{$src2, $dst|$dst, $src2}",
842 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
843 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
844 "xor{q}\t{$src2, $dst|$dst, $src2}",
845 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
846 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
847 "xor{q}\t{$src2, $dst|$dst, $src2}",
848 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
849 def XOR64ri32 : RIi32<0x81, MRM6r,
850 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
851 "xor{q}\t{$src2, $dst|$dst, $src2}",
852 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
855 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
856 "xor{q}\t{$src, $dst|$dst, $src}",
857 [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
858 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
859 "xor{q}\t{$src, $dst|$dst, $src}",
860 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
861 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
862 "xor{q}\t{$src, $dst|$dst, $src}",
863 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
866 //===----------------------------------------------------------------------===//
867 // Comparison Instructions...
870 // Integer comparison
871 let Defs = [EFLAGS] in {
872 let isCommutable = 1 in
873 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
874 "test{q}\t{$src2, $src1|$src1, $src2}",
875 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
877 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
878 "test{q}\t{$src2, $src1|$src1, $src2}",
879 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
881 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
882 (ins GR64:$src1, i64i32imm:$src2),
883 "test{q}\t{$src2, $src1|$src1, $src2}",
884 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
886 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
887 (ins i64mem:$src1, i64i32imm:$src2),
888 "test{q}\t{$src2, $src1|$src1, $src2}",
889 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
892 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
893 "cmp{q}\t{$src2, $src1|$src1, $src2}",
894 [(X86cmp GR64:$src1, GR64:$src2),
896 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
897 "cmp{q}\t{$src2, $src1|$src1, $src2}",
898 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
900 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
901 "cmp{q}\t{$src2, $src1|$src1, $src2}",
902 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
904 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
905 "cmp{q}\t{$src2, $src1|$src1, $src2}",
906 [(X86cmp GR64:$src1, i64immSExt8:$src2),
908 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
909 "cmp{q}\t{$src2, $src1|$src1, $src2}",
910 [(X86cmp GR64:$src1, i64immSExt32:$src2),
912 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
913 "cmp{q}\t{$src2, $src1|$src1, $src2}",
914 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
916 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
917 (ins i64mem:$src1, i64i32imm:$src2),
918 "cmp{q}\t{$src2, $src1|$src1, $src2}",
919 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
924 // TODO: BTC, BTR, and BTS
925 let Defs = [EFLAGS] in {
926 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
927 "bt{q}\t{$src2, $src1|$src1, $src2}",
928 [(X86bt GR64:$src1, GR64:$src2),
929 (implicit EFLAGS)]>, TB;
931 // Unlike with the register+register form, the memory+register form of the
932 // bt instruction does not ignore the high bits of the index. From ISel's
933 // perspective, this is pretty bizarre. Disable these instructions for now.
934 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
935 // "bt{q}\t{$src2, $src1|$src1, $src2}",
936 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
937 // (implicit EFLAGS)]>, TB;
939 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
940 "bt{q}\t{$src2, $src1|$src1, $src2}",
941 [(X86bt GR64:$src1, i64immSExt8:$src2),
942 (implicit EFLAGS)]>, TB;
943 // Note that these instructions don't need FastBTMem because that
944 // only applies when the other operand is in a register. When it's
945 // an immediate, bt is still fast.
946 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
947 "bt{q}\t{$src2, $src1|$src1, $src2}",
948 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
949 (implicit EFLAGS)]>, TB;
953 let Uses = [EFLAGS], isTwoAddress = 1 in {
954 let isCommutable = 1 in {
955 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
956 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
957 "cmovb\t{$src2, $dst|$dst, $src2}",
958 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
959 X86_COND_B, EFLAGS))]>, TB;
960 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
961 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
962 "cmovae\t{$src2, $dst|$dst, $src2}",
963 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
964 X86_COND_AE, EFLAGS))]>, TB;
965 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
966 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
967 "cmove\t{$src2, $dst|$dst, $src2}",
968 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
969 X86_COND_E, EFLAGS))]>, TB;
970 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
971 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
972 "cmovne\t{$src2, $dst|$dst, $src2}",
973 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
974 X86_COND_NE, EFLAGS))]>, TB;
975 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
976 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
977 "cmovbe\t{$src2, $dst|$dst, $src2}",
978 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
979 X86_COND_BE, EFLAGS))]>, TB;
980 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
981 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
982 "cmova\t{$src2, $dst|$dst, $src2}",
983 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
984 X86_COND_A, EFLAGS))]>, TB;
985 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
986 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
987 "cmovl\t{$src2, $dst|$dst, $src2}",
988 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
989 X86_COND_L, EFLAGS))]>, TB;
990 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
991 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
992 "cmovge\t{$src2, $dst|$dst, $src2}",
993 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
994 X86_COND_GE, EFLAGS))]>, TB;
995 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
996 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
997 "cmovle\t{$src2, $dst|$dst, $src2}",
998 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
999 X86_COND_LE, EFLAGS))]>, TB;
1000 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1001 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1002 "cmovg\t{$src2, $dst|$dst, $src2}",
1003 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1004 X86_COND_G, EFLAGS))]>, TB;
1005 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1006 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1007 "cmovs\t{$src2, $dst|$dst, $src2}",
1008 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1009 X86_COND_S, EFLAGS))]>, TB;
1010 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1011 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1012 "cmovns\t{$src2, $dst|$dst, $src2}",
1013 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1014 X86_COND_NS, EFLAGS))]>, TB;
1015 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1016 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1017 "cmovp\t{$src2, $dst|$dst, $src2}",
1018 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1019 X86_COND_P, EFLAGS))]>, TB;
1020 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1021 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1022 "cmovnp\t{$src2, $dst|$dst, $src2}",
1023 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1024 X86_COND_NP, EFLAGS))]>, TB;
1025 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1026 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1027 "cmovo\t{$src2, $dst|$dst, $src2}",
1028 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1029 X86_COND_O, EFLAGS))]>, TB;
1030 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1031 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1032 "cmovno\t{$src2, $dst|$dst, $src2}",
1033 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1034 X86_COND_NO, EFLAGS))]>, TB;
1035 } // isCommutable = 1
1037 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1038 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1039 "cmovb\t{$src2, $dst|$dst, $src2}",
1040 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1041 X86_COND_B, EFLAGS))]>, TB;
1042 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1043 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1044 "cmovae\t{$src2, $dst|$dst, $src2}",
1045 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1046 X86_COND_AE, EFLAGS))]>, TB;
1047 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1048 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1049 "cmove\t{$src2, $dst|$dst, $src2}",
1050 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1051 X86_COND_E, EFLAGS))]>, TB;
1052 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1053 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1054 "cmovne\t{$src2, $dst|$dst, $src2}",
1055 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1056 X86_COND_NE, EFLAGS))]>, TB;
1057 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1058 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1059 "cmovbe\t{$src2, $dst|$dst, $src2}",
1060 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1061 X86_COND_BE, EFLAGS))]>, TB;
1062 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1063 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1064 "cmova\t{$src2, $dst|$dst, $src2}",
1065 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1066 X86_COND_A, EFLAGS))]>, TB;
1067 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1068 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1069 "cmovl\t{$src2, $dst|$dst, $src2}",
1070 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1071 X86_COND_L, EFLAGS))]>, TB;
1072 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1073 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1074 "cmovge\t{$src2, $dst|$dst, $src2}",
1075 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1076 X86_COND_GE, EFLAGS))]>, TB;
1077 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1078 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1079 "cmovle\t{$src2, $dst|$dst, $src2}",
1080 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1081 X86_COND_LE, EFLAGS))]>, TB;
1082 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1083 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1084 "cmovg\t{$src2, $dst|$dst, $src2}",
1085 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1086 X86_COND_G, EFLAGS))]>, TB;
1087 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1088 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1089 "cmovs\t{$src2, $dst|$dst, $src2}",
1090 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1091 X86_COND_S, EFLAGS))]>, TB;
1092 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1093 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1094 "cmovns\t{$src2, $dst|$dst, $src2}",
1095 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1096 X86_COND_NS, EFLAGS))]>, TB;
1097 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1098 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1099 "cmovp\t{$src2, $dst|$dst, $src2}",
1100 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1101 X86_COND_P, EFLAGS))]>, TB;
1102 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1103 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1104 "cmovnp\t{$src2, $dst|$dst, $src2}",
1105 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1106 X86_COND_NP, EFLAGS))]>, TB;
1107 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1108 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1109 "cmovo\t{$src2, $dst|$dst, $src2}",
1110 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1111 X86_COND_O, EFLAGS))]>, TB;
1112 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1113 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1114 "cmovno\t{$src2, $dst|$dst, $src2}",
1115 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1116 X86_COND_NO, EFLAGS))]>, TB;
1119 //===----------------------------------------------------------------------===//
1120 // Conversion Instructions...
1123 // f64 -> signed i64
1124 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1125 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1127 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1128 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1129 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1130 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1131 (load addr:$src)))]>;
1132 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1133 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1134 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1135 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1136 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1137 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1138 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1139 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1141 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1142 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1143 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1145 (int_x86_sse2_cvttsd2si64
1146 (load addr:$src)))]>;
1148 // Signed i64 -> f64
1149 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1150 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1151 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1152 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1153 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1154 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1156 let isTwoAddress = 1 in {
1157 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1158 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1159 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1161 (int_x86_sse2_cvtsi642sd VR128:$src1,
1163 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1165 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1167 (int_x86_sse2_cvtsi642sd VR128:$src1,
1168 (loadi64 addr:$src2)))]>;
1171 // Signed i64 -> f32
1172 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1173 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1174 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1175 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1176 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1177 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1179 let isTwoAddress = 1 in {
1180 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1181 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1182 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1184 (int_x86_sse_cvtsi642ss VR128:$src1,
1186 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1187 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1188 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1190 (int_x86_sse_cvtsi642ss VR128:$src1,
1191 (loadi64 addr:$src2)))]>;
1194 // f32 -> signed i64
1195 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1196 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1198 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1199 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1200 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1201 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1202 (load addr:$src)))]>;
1203 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1204 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1205 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1206 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1207 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1208 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1209 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1210 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1212 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1213 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1214 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1216 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1218 //===----------------------------------------------------------------------===//
1219 // Alias Instructions
1220 //===----------------------------------------------------------------------===//
1222 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1223 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1225 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1226 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1227 // when we have a better way to specify isel priority.
1228 let Defs = [EFLAGS], AddedComplexity = 1,
1229 isReMaterializable = 1, isAsCheapAsAMove = 1 in
1230 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1231 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1232 [(set GR64:$dst, 0)]>;
1234 // Materialize i64 constant where top 32-bits are zero.
1235 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1236 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1237 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1238 [(set GR64:$dst, i64immZExt32:$src)]>;
1240 //===----------------------------------------------------------------------===//
1241 // Thread Local Storage Instructions
1242 //===----------------------------------------------------------------------===//
1244 def TLS_addr64 : I<0, Pseudo, (outs GR64:$dst), (ins i64imm:$sym),
1245 ".byte\t0x66; leaq\t${sym:mem}(%rip), $dst; .word\t0x6666; rex64",
1246 [(set GR64:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
1248 let AddedComplexity = 5 in
1249 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1250 "movq\t%gs:$src, $dst",
1251 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1253 //===----------------------------------------------------------------------===//
1254 // Atomic Instructions
1255 //===----------------------------------------------------------------------===//
1257 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1258 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1259 "lock\n\tcmpxchgq\t$swap,$ptr",
1260 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1263 let Constraints = "$val = $dst" in {
1264 let Defs = [EFLAGS] in
1265 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1266 "lock\n\txadd\t$val, $ptr",
1267 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1269 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1271 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1274 // Atomic exchange, and, or, xor
1275 let Constraints = "$val = $dst", Defs = [EFLAGS],
1276 usesCustomDAGSchedInserter = 1 in {
1277 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1278 "#ATOMAND64 PSEUDO!",
1279 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1280 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1281 "#ATOMOR64 PSEUDO!",
1282 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1283 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1284 "#ATOMXOR64 PSEUDO!",
1285 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1286 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1287 "#ATOMNAND64 PSEUDO!",
1288 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1289 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1290 "#ATOMMIN64 PSEUDO!",
1291 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1292 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1293 "#ATOMMAX64 PSEUDO!",
1294 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1295 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1296 "#ATOMUMIN64 PSEUDO!",
1297 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1298 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1299 "#ATOMUMAX64 PSEUDO!",
1300 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1303 //===----------------------------------------------------------------------===//
1304 // Non-Instruction Patterns
1305 //===----------------------------------------------------------------------===//
1307 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1308 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1309 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1310 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1311 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1312 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1313 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1314 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1315 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1317 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1318 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1319 Requires<[SmallCode, IsStatic]>;
1320 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1321 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1322 Requires<[SmallCode, IsStatic]>;
1323 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1324 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1325 Requires<[SmallCode, IsStatic]>;
1326 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1327 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1328 Requires<[SmallCode, IsStatic]>;
1331 // Direct PC relative function call for small code model. 32-bit displacement
1332 // sign extended to 64-bit.
1333 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1334 (CALL64pcrel32 tglobaladdr:$dst)>;
1335 def : Pat<(X86call (i64 texternalsym:$dst)),
1336 (CALL64pcrel32 texternalsym:$dst)>;
1338 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1339 (CALL64pcrel32 tglobaladdr:$dst)>;
1340 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1341 (CALL64pcrel32 texternalsym:$dst)>;
1343 def : Pat<(X86tailcall GR64:$dst),
1344 (CALL64r GR64:$dst)>;
1348 def : Pat<(X86tailcall GR32:$dst),
1350 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1352 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1355 def : Pat<(X86tcret GR64:$dst, imm:$off),
1356 (TCRETURNri64 GR64:$dst, imm:$off)>;
1358 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1359 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1361 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1362 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1366 // TEST R,R is smaller than CMP R,0
1367 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1368 (TEST64rr GR64:$src1, GR64:$src1)>;
1370 // Conditional moves with folded loads with operands swapped and conditions
1372 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1373 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1374 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1375 (CMOVB64rm GR64:$src2, addr:$src1)>;
1376 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1377 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1378 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1379 (CMOVE64rm GR64:$src2, addr:$src1)>;
1380 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1381 (CMOVA64rm GR64:$src2, addr:$src1)>;
1382 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1383 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1384 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1385 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1386 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1387 (CMOVL64rm GR64:$src2, addr:$src1)>;
1388 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1389 (CMOVG64rm GR64:$src2, addr:$src1)>;
1390 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1391 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1392 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1393 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1394 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1395 (CMOVP64rm GR64:$src2, addr:$src1)>;
1396 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1397 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1398 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1399 (CMOVS64rm GR64:$src2, addr:$src1)>;
1400 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1401 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1402 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1403 (CMOVO64rm GR64:$src2, addr:$src1)>;
1406 def : Pat<(i64 (zext GR32:$src)),
1407 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1409 // zextload bool -> zextload byte
1410 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1413 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1414 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1415 // partial-register updates.
1416 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1417 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1418 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1419 // For other extloads, use subregs, since the high contents of the register are
1420 // defined after an extload.
1421 def : Pat<(extloadi64i32 addr:$src),
1422 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1424 def : Pat<(extloadi16i1 addr:$src),
1425 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1427 Requires<[In64BitMode]>;
1428 def : Pat<(extloadi16i8 addr:$src),
1429 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1431 Requires<[In64BitMode]>;
1434 def : Pat<(i64 (anyext GR8:$src)),
1435 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1436 def : Pat<(i64 (anyext GR16:$src)),
1437 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1438 def : Pat<(i64 (anyext GR32:$src)),
1439 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1440 def : Pat<(i16 (anyext GR8:$src)),
1441 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1442 Requires<[In64BitMode]>;
1443 def : Pat<(i32 (anyext GR8:$src)),
1444 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1445 Requires<[In64BitMode]>;
1447 //===----------------------------------------------------------------------===//
1449 //===----------------------------------------------------------------------===//
1451 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1452 // +128 doesn't, so in this special case use a sub instead of an add.
1453 def : Pat<(add GR64:$src1, 128),
1454 (SUB64ri8 GR64:$src1, -128)>;
1455 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1456 (SUB64mi8 addr:$dst, -128)>;
1458 // The same trick applies for 32-bit immediate fields in 64-bit
1460 def : Pat<(add GR64:$src1, 0x0000000080000000),
1461 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1462 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1463 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1465 // r & (2^32-1) ==> movz
1466 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1467 (MOVZX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1468 // r & (2^16-1) ==> movz
1469 def : Pat<(and GR64:$src, 0xffff),
1470 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1471 // r & (2^8-1) ==> movz
1472 def : Pat<(and GR64:$src, 0xff),
1473 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1474 // r & (2^8-1) ==> movz
1475 def : Pat<(and GR32:$src1, 0xff),
1476 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>,
1477 Requires<[In64BitMode]>;
1478 // r & (2^8-1) ==> movz
1479 def : Pat<(and GR16:$src1, 0xff),
1480 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1481 Requires<[In64BitMode]>;
1483 // sext_inreg patterns
1484 def : Pat<(sext_inreg GR64:$src, i32),
1485 (MOVSX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1486 def : Pat<(sext_inreg GR64:$src, i16),
1487 (MOVSX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1488 def : Pat<(sext_inreg GR64:$src, i8),
1489 (MOVSX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1490 def : Pat<(sext_inreg GR32:$src, i8),
1491 (MOVSX32rr8 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)))>,
1492 Requires<[In64BitMode]>;
1493 def : Pat<(sext_inreg GR16:$src, i8),
1494 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1495 Requires<[In64BitMode]>;
1498 def : Pat<(i32 (trunc GR64:$src)),
1499 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1500 def : Pat<(i16 (trunc GR64:$src)),
1501 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1502 def : Pat<(i8 (trunc GR64:$src)),
1503 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1504 def : Pat<(i8 (trunc GR32:$src)),
1505 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1506 Requires<[In64BitMode]>;
1507 def : Pat<(i8 (trunc GR16:$src)),
1508 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit))>,
1509 Requires<[In64BitMode]>;
1511 // (shl x, 1) ==> (add x, x)
1512 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1514 // (shl x (and y, 63)) ==> (shl x, y)
1515 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1516 (SHL64rCL GR64:$src1)>;
1517 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1518 (SHL64mCL addr:$dst)>;
1520 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1521 (SHR64rCL GR64:$src1)>;
1522 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1523 (SHR64mCL addr:$dst)>;
1525 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1526 (SAR64rCL GR64:$src1)>;
1527 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1528 (SAR64mCL addr:$dst)>;
1530 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1531 def : Pat<(or (srl GR64:$src1, CL:$amt),
1532 (shl GR64:$src2, (sub 64, CL:$amt))),
1533 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1535 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1536 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1537 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1539 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1540 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1541 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1543 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1544 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1546 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1548 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1549 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1551 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1552 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1553 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1555 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1556 def : Pat<(or (shl GR64:$src1, CL:$amt),
1557 (srl GR64:$src2, (sub 64, CL:$amt))),
1558 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1560 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1561 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1562 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1564 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1565 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1566 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1568 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1569 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1571 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1573 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1574 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1576 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1577 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1578 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1580 // X86 specific add which produces a flag.
1581 def : Pat<(addc GR64:$src1, GR64:$src2),
1582 (ADD64rr GR64:$src1, GR64:$src2)>;
1583 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1584 (ADD64rm GR64:$src1, addr:$src2)>;
1585 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1586 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1587 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1588 (ADD64ri32 GR64:$src1, imm:$src2)>;
1590 def : Pat<(subc GR64:$src1, GR64:$src2),
1591 (SUB64rr GR64:$src1, GR64:$src2)>;
1592 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1593 (SUB64rm GR64:$src1, addr:$src2)>;
1594 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1595 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1596 def : Pat<(subc GR64:$src1, imm:$src2),
1597 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1599 //===----------------------------------------------------------------------===//
1600 // Overflow Patterns
1601 //===----------------------------------------------------------------------===//
1603 // Register-Register Addition with Overflow
1604 def : Pat<(parallel (X86add_ovf GR64:$src1, GR64:$src2),
1606 (ADD64rr GR64:$src1, GR64:$src2)>;
1608 // Register-Integer Addition with Overflow
1609 def : Pat<(parallel (X86add_ovf GR64:$src1, i64immSExt8:$src2),
1611 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1612 def : Pat<(parallel (X86add_ovf GR64:$src1, i64immSExt32:$src2),
1614 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1616 // Register-Memory Addition with Overflow
1617 def : Pat<(parallel (X86add_ovf GR64:$src1, (load addr:$src2)),
1619 (ADD64rm GR64:$src1, addr:$src2)>;
1621 // Memory-Register Addition with Overflow
1622 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR64:$src2),
1625 (ADD64mr addr:$dst, GR64:$src2)>;
1626 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i64immSExt8:$src2),
1629 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1630 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i64immSExt32:$src2),
1633 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1635 // Register-Register Subtraction with Overflow
1636 def : Pat<(parallel (X86sub_ovf GR64:$src1, GR64:$src2),
1638 (SUB64rr GR64:$src1, GR64:$src2)>;
1640 // Register-Memory Subtraction with Overflow
1641 def : Pat<(parallel (X86sub_ovf GR64:$src1, (load addr:$src2)),
1643 (SUB64rm GR64:$src1, addr:$src2)>;
1645 // Register-Integer Subtraction with Overflow
1646 def : Pat<(parallel (X86sub_ovf GR64:$src1, i64immSExt8:$src2),
1648 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1649 def : Pat<(parallel (X86sub_ovf GR64:$src1, i64immSExt32:$src2),
1651 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1653 // Memory-Register Subtraction with Overflow
1654 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR64:$src2),
1657 (SUB64mr addr:$dst, GR64:$src2)>;
1659 // Memory-Integer Subtraction with Overflow
1660 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i64immSExt8:$src2),
1663 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1664 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i64immSExt32:$src2),
1667 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1669 // Register-Register Signed Integer Multiplication with Overflow
1670 def : Pat<(parallel (X86smul_ovf GR64:$src1, GR64:$src2),
1672 (IMUL64rr GR64:$src1, GR64:$src2)>;
1674 // Register-Memory Signed Integer Multiplication with Overflow
1675 def : Pat<(parallel (X86smul_ovf GR64:$src1, (load addr:$src2)),
1677 (IMUL64rm GR64:$src1, addr:$src2)>;
1679 // Register-Integer Signed Integer Multiplication with Overflow
1680 def : Pat<(parallel (X86smul_ovf GR64:$src1, i64immSExt8:$src2),
1682 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1683 def : Pat<(parallel (X86smul_ovf GR64:$src1, i64immSExt32:$src2),
1685 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1687 // Memory-Integer Signed Integer Multiplication with Overflow
1688 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i64immSExt8:$src2),
1690 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1691 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i64immSExt32:$src2),
1693 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1695 //===----------------------------------------------------------------------===//
1696 // X86-64 SSE Instructions
1697 //===----------------------------------------------------------------------===//
1699 // Move instructions...
1701 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1702 "mov{d|q}\t{$src, $dst|$dst, $src}",
1704 (v2i64 (scalar_to_vector GR64:$src)))]>;
1705 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1706 "mov{d|q}\t{$src, $dst|$dst, $src}",
1707 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1710 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1711 "mov{d|q}\t{$src, $dst|$dst, $src}",
1712 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1713 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1714 "movq\t{$src, $dst|$dst, $src}",
1715 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1717 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1718 "mov{d|q}\t{$src, $dst|$dst, $src}",
1719 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1720 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1721 "movq\t{$src, $dst|$dst, $src}",
1722 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1724 //===----------------------------------------------------------------------===//
1725 // X86-64 SSE4.1 Instructions
1726 //===----------------------------------------------------------------------===//
1728 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1729 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
1730 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
1731 (ins VR128:$src1, i32i8imm:$src2),
1732 !strconcat(OpcodeStr,
1733 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1735 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
1736 def mr : SS4AIi8<opc, MRMDestMem, (outs),
1737 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
1738 !strconcat(OpcodeStr,
1739 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1740 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
1741 addr:$dst)]>, OpSize, REX_W;
1744 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
1746 let isTwoAddress = 1 in {
1747 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
1748 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
1749 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
1750 !strconcat(OpcodeStr,
1751 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1753 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
1755 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
1756 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
1757 !strconcat(OpcodeStr,
1758 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1760 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
1761 imm:$src3)))]>, OpSize, REX_W;
1765 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;