1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printlea64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions.
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, X86mul_imm, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
46 def i64immSExt8 : PatLeaf<(i64 imm), [{
47 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
48 // sign extended field.
49 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
52 def i64immSExt32 : PatLeaf<(i64 imm), [{
53 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // sign extended field.
55 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
58 def i64immZExt32 : PatLeaf<(i64 imm), [{
59 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
60 // unsignedsign extended field.
61 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
64 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
65 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
66 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
68 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
69 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
70 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
71 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
73 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
74 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
75 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
76 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
78 //===----------------------------------------------------------------------===//
79 // Instruction list...
82 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
83 // a stack adjustment and the codegen must know that they may modify the stack
84 // pointer before prolog-epilog rewriting occurs.
85 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
86 // sub / add which can clobber EFLAGS.
87 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
90 [(X86callseq_start timm:$amt)]>,
91 Requires<[In64BitMode]>;
92 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
94 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
95 Requires<[In64BitMode]>;
98 //===----------------------------------------------------------------------===//
99 // Call Instructions...
102 // All calls clobber the non-callee saved registers. RSP is marked as
103 // a use to prevent stack-pointer assignments that appear immediately
104 // before calls from potentially appearing dead. Uses for argument
105 // registers are added manually.
106 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
107 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
108 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
109 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
110 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
113 // NOTE: this pattern doesn't match "X86call imm", because we do not know
114 // that the offset between an arbitrary immediate and the call will fit in
115 // the 32-bit pcrel field that we have.
116 def CALL64pcrel32 : I<0xE8, RawFrm,
117 (outs), (ins i64i32imm:$dst, variable_ops),
118 "call\t${dst:call}", []>,
119 Requires<[In64BitMode]>;
120 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
121 "call\t{*}$dst", [(X86call GR64:$dst)]>;
122 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
123 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>;
128 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
129 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
131 "#TC_RETURN $dst $offset",
134 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
135 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
137 "#TC_RETURN $dst $offset",
141 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
142 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
143 "jmp{q}\t{*}$dst # TAILCALL",
147 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
148 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
149 [(brind GR64:$dst)]>;
150 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
151 [(brind (loadi64 addr:$dst))]>;
154 //===----------------------------------------------------------------------===//
155 // EH Pseudo Instructions
157 let isTerminator = 1, isReturn = 1, isBarrier = 1,
159 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
160 "ret\t#eh_return, addr: $addr",
161 [(X86ehret GR64:$addr)]>;
165 //===----------------------------------------------------------------------===//
166 // Miscellaneous Instructions...
168 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
169 def LEAVE64 : I<0xC9, RawFrm,
170 (outs), (ins), "leave", []>;
171 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
173 def POP64r : I<0x58, AddRegFrm,
174 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
176 def PUSH64r : I<0x50, AddRegFrm,
177 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
180 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
181 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
182 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
183 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
185 def LEA64_32r : I<0x8D, MRMSrcMem,
186 (outs GR32:$dst), (ins lea64_32mem:$src),
187 "lea{l}\t{$src|$dst}, {$dst|$src}",
188 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
190 let isReMaterializable = 1 in
191 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
192 "lea{q}\t{$src|$dst}, {$dst|$src}",
193 [(set GR64:$dst, lea64addr:$src)]>;
195 let isTwoAddress = 1 in
196 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
198 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
200 // Bit scan instructions.
201 let Defs = [EFLAGS] in {
202 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
203 "bsf{q}\t{$src, $dst|$dst, $src}",
204 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
205 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
206 "bsf{q}\t{$src, $dst|$dst, $src}",
207 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
208 (implicit EFLAGS)]>, TB;
210 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
211 "bsr{q}\t{$src, $dst|$dst, $src}",
212 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
213 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
214 "bsr{q}\t{$src, $dst|$dst, $src}",
215 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
216 (implicit EFLAGS)]>, TB;
220 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
221 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
222 [(X86rep_movs i64)]>, REP;
223 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
224 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
225 [(X86rep_stos i64)]>, REP;
227 //===----------------------------------------------------------------------===//
228 // Move Instructions...
231 let neverHasSideEffects = 1 in
232 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
233 "mov{q}\t{$src, $dst|$dst, $src}", []>;
235 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
236 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
237 "movabs{q}\t{$src, $dst|$dst, $src}",
238 [(set GR64:$dst, imm:$src)]>;
239 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
240 "mov{q}\t{$src, $dst|$dst, $src}",
241 [(set GR64:$dst, i64immSExt32:$src)]>;
244 let canFoldAsLoad = 1 in
245 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
246 "mov{q}\t{$src, $dst|$dst, $src}",
247 [(set GR64:$dst, (load addr:$src))]>;
249 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
250 "mov{q}\t{$src, $dst|$dst, $src}",
251 [(store GR64:$src, addr:$dst)]>;
252 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
253 "mov{q}\t{$src, $dst|$dst, $src}",
254 [(store i64immSExt32:$src, addr:$dst)]>;
256 // Sign/Zero extenders
258 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
259 // operand, which makes it a rare instruction with an 8-bit register
260 // operand that can never access an h register. If support for h registers
261 // were generalized, this would require a special register class.
262 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
263 "movs{bq|x}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (sext GR8:$src))]>, TB;
265 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
266 "movs{bq|x}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
268 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
269 "movs{wq|x}\t{$src, $dst|$dst, $src}",
270 [(set GR64:$dst, (sext GR16:$src))]>, TB;
271 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
272 "movs{wq|x}\t{$src, $dst|$dst, $src}",
273 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
274 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
275 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
276 [(set GR64:$dst, (sext GR32:$src))]>;
277 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
278 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
279 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
281 // Use movzbl instead of movzbq when the destination is a register; it's
282 // equivalent due to implicit zero-extending, and it has a smaller encoding.
283 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
284 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
285 [(set GR64:$dst, (zext GR8:$src))]>, TB;
286 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
287 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
288 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
289 // Use movzwl instead of movzwq when the destination is a register; it's
290 // equivalent due to implicit zero-extending, and it has a smaller encoding.
291 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
292 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
293 [(set GR64:$dst, (zext GR16:$src))]>, TB;
294 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
295 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
296 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
298 // There's no movzlq instruction, but movl can be used for this purpose, using
299 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
300 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
301 // zero-extension, however this isn't possible when the 32-bit value is
302 // defined by a truncate or is copied from something where the high bits aren't
303 // necessarily all zero. In such cases, we fall back to these explicit zext
305 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
306 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
307 [(set GR64:$dst, (zext GR32:$src))]>;
308 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
309 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
310 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
312 // Any instruction that defines a 32-bit result leaves the high half of the
313 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
314 // be copying from a truncate, but any other 32-bit operation will zero-extend
316 def def32 : PatLeaf<(i32 GR32:$src), [{
317 return N->getOpcode() != ISD::TRUNCATE &&
318 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
319 N->getOpcode() != ISD::CopyFromReg;
322 // In the case of a 32-bit def that is known to implicitly zero-extend,
323 // we can use a SUBREG_TO_REG.
324 def : Pat<(i64 (zext def32:$src)),
325 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
327 let neverHasSideEffects = 1 in {
328 let Defs = [RAX], Uses = [EAX] in
329 def CDQE : RI<0x98, RawFrm, (outs), (ins),
330 "{cltq|cdqe}", []>; // RAX = signext(EAX)
332 let Defs = [RAX,RDX], Uses = [RAX] in
333 def CQO : RI<0x99, RawFrm, (outs), (ins),
334 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
337 //===----------------------------------------------------------------------===//
338 // Arithmetic Instructions...
341 let Defs = [EFLAGS] in {
342 let isTwoAddress = 1 in {
343 let isConvertibleToThreeAddress = 1 in {
344 let isCommutable = 1 in
345 // Register-Register Addition
346 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
347 "add{q}\t{$src2, $dst|$dst, $src2}",
348 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
351 // Register-Integer Addition
352 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
353 "add{q}\t{$src2, $dst|$dst, $src2}",
354 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
356 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
357 "add{q}\t{$src2, $dst|$dst, $src2}",
358 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
360 } // isConvertibleToThreeAddress
362 // Register-Memory Addition
363 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
364 "add{q}\t{$src2, $dst|$dst, $src2}",
365 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
369 // Memory-Register Addition
370 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
371 "add{q}\t{$src2, $dst|$dst, $src2}",
372 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
374 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
375 "add{q}\t{$src2, $dst|$dst, $src2}",
376 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
378 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
379 "add{q}\t{$src2, $dst|$dst, $src2}",
380 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
383 let Uses = [EFLAGS] in {
384 let isTwoAddress = 1 in {
385 let isCommutable = 1 in
386 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
387 (ins GR64:$src1, GR64:$src2),
388 "adc{q}\t{$src2, $dst|$dst, $src2}",
390 (X86adde_flag GR64:$src1, GR64:$src2, EFLAGS)),
393 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
394 (ins GR64:$src1, i64mem:$src2),
395 "adc{q}\t{$src2, $dst|$dst, $src2}",
397 (X86adde_flag GR64:$src1, (load addr:$src2), EFLAGS)),
400 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
401 (ins GR64:$src1, i64i8imm:$src2),
402 "adc{q}\t{$src2, $dst|$dst, $src2}",
404 (X86adde_flag GR64:$src1, i64immSExt8:$src2, EFLAGS)),
406 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
407 (ins GR64:$src1, i64i32imm:$src2),
408 "adc{q}\t{$src2, $dst|$dst, $src2}",
410 (X86adde_flag GR64:$src1, i64immSExt32:$src2,
415 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
416 "adc{q}\t{$src2, $dst|$dst, $src2}",
417 [(store (X86adde_flag (load addr:$dst), GR64:$src2, EFLAGS),
420 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
421 "adc{q}\t{$src2, $dst|$dst, $src2}",
422 [(store (X86adde_flag (load addr:$dst), i64immSExt8:$src2,
426 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
427 "adc{q}\t{$src2, $dst|$dst, $src2}",
428 [(store (X86adde_flag (load addr:$dst), i64immSExt8:$src2,
434 let isTwoAddress = 1 in {
435 // Register-Register Subtraction
436 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
437 "sub{q}\t{$src2, $dst|$dst, $src2}",
438 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
441 // Register-Memory Subtraction
442 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
443 "sub{q}\t{$src2, $dst|$dst, $src2}",
444 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
447 // Register-Integer Subtraction
448 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
449 (ins GR64:$src1, i64i8imm:$src2),
450 "sub{q}\t{$src2, $dst|$dst, $src2}",
451 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
453 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
454 (ins GR64:$src1, i64i32imm:$src2),
455 "sub{q}\t{$src2, $dst|$dst, $src2}",
456 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
460 // Memory-Register Subtraction
461 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
462 "sub{q}\t{$src2, $dst|$dst, $src2}",
463 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
466 // Memory-Integer Subtraction
467 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
468 "sub{q}\t{$src2, $dst|$dst, $src2}",
469 [(store (sub (load addr:$dst), i64immSExt8:$src2),
472 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
473 "sub{q}\t{$src2, $dst|$dst, $src2}",
474 [(store (sub (load addr:$dst), i64immSExt32:$src2),
478 let Uses = [EFLAGS] in {
479 let isTwoAddress = 1 in {
480 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
481 (ins GR64:$src1, GR64:$src2),
482 "sbb{q}\t{$src2, $dst|$dst, $src2}",
484 (X86sube_flag GR64:$src1, GR64:$src2, EFLAGS)),
487 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
488 (ins GR64:$src1, i64mem:$src2),
489 "sbb{q}\t{$src2, $dst|$dst, $src2}",
491 (X86sube_flag GR64:$src1, (load addr:$src2), EFLAGS)),
494 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
495 (ins GR64:$src1, i64i8imm:$src2),
496 "sbb{q}\t{$src2, $dst|$dst, $src2}",
498 (X86sube_flag GR64:$src1, i64immSExt8:$src2, EFLAGS)),
500 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
501 (ins GR64:$src1, i64i32imm:$src2),
502 "sbb{q}\t{$src2, $dst|$dst, $src2}",
504 (X86sube_flag GR64:$src1, i64immSExt32:$src2,
509 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
510 "sbb{q}\t{$src2, $dst|$dst, $src2}",
511 [(store (X86sube_flag (load addr:$dst), GR64:$src2, EFLAGS),
514 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
515 "sbb{q}\t{$src2, $dst|$dst, $src2}",
516 [(store (X86sube_flag (load addr:$dst), i64immSExt8:$src2,
520 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
521 "sbb{q}\t{$src2, $dst|$dst, $src2}",
522 [(store (X86sube_flag (load addr:$dst), i64immSExt32:$src2,
529 // Unsigned multiplication
530 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
531 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
532 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
534 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
535 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
537 // Signed multiplication
538 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
539 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
541 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
542 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
545 let Defs = [EFLAGS] in {
546 let isTwoAddress = 1 in {
547 let isCommutable = 1 in
548 // Register-Register Signed Integer Multiplication
549 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
550 (ins GR64:$src1, GR64:$src2),
551 "imul{q}\t{$src2, $dst|$dst, $src2}",
552 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
553 (implicit EFLAGS)]>, TB;
555 // Register-Memory Signed Integer Multiplication
556 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
557 (ins GR64:$src1, i64mem:$src2),
558 "imul{q}\t{$src2, $dst|$dst, $src2}",
559 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
560 (implicit EFLAGS)]>, TB;
563 // Suprisingly enough, these are not two address instructions!
565 // Register-Integer Signed Integer Multiplication
566 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
567 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
568 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
569 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
571 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
572 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
573 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
574 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
577 // Memory-Integer Signed Integer Multiplication
578 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
579 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
580 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
581 [(set GR64:$dst, (mul (load addr:$src1),
584 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
585 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
586 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
587 [(set GR64:$dst, (mul (load addr:$src1),
588 i64immSExt32:$src2)),
592 // Unsigned division / remainder
593 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
594 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
596 // Signed division / remainder
597 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
598 "idiv{q}\t$src", []>;
600 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
602 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
603 "idiv{q}\t$src", []>;
607 // Unary instructions
608 let Defs = [EFLAGS], CodeSize = 2 in {
609 let isTwoAddress = 1 in
610 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
611 [(set GR64:$dst, (ineg GR64:$src)),
613 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
614 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
617 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
618 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
619 [(set GR64:$dst, (add GR64:$src, 1)),
621 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
622 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
625 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
626 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
627 [(set GR64:$dst, (add GR64:$src, -1)),
629 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
630 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
633 // In 64-bit mode, single byte INC and DEC cannot be encoded.
634 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
635 // Can transform into LEA.
636 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
637 [(set GR16:$dst, (add GR16:$src, 1)),
639 OpSize, Requires<[In64BitMode]>;
640 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
641 [(set GR32:$dst, (add GR32:$src, 1)),
643 Requires<[In64BitMode]>;
644 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
645 [(set GR16:$dst, (add GR16:$src, -1)),
647 OpSize, Requires<[In64BitMode]>;
648 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
649 [(set GR32:$dst, (add GR32:$src, -1)),
651 Requires<[In64BitMode]>;
652 } // isConvertibleToThreeAddress
654 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
655 // how to unfold them.
656 let isTwoAddress = 0, CodeSize = 2 in {
657 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
658 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
660 OpSize, Requires<[In64BitMode]>;
661 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
662 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
664 Requires<[In64BitMode]>;
665 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
666 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
668 OpSize, Requires<[In64BitMode]>;
669 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
670 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
672 Requires<[In64BitMode]>;
674 } // Defs = [EFLAGS], CodeSize
677 let Defs = [EFLAGS] in {
678 // Shift instructions
679 let isTwoAddress = 1 in {
681 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
682 "shl{q}\t{%cl, $dst|$dst, %CL}",
683 [(set GR64:$dst, (shl GR64:$src, CL))]>;
684 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
685 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
686 "shl{q}\t{$src2, $dst|$dst, $src2}",
687 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
688 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
693 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
694 "shl{q}\t{%cl, $dst|$dst, %CL}",
695 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
696 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
697 "shl{q}\t{$src, $dst|$dst, $src}",
698 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
699 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
701 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
703 let isTwoAddress = 1 in {
705 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
706 "shr{q}\t{%cl, $dst|$dst, %CL}",
707 [(set GR64:$dst, (srl GR64:$src, CL))]>;
708 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
709 "shr{q}\t{$src2, $dst|$dst, $src2}",
710 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
711 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
713 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
717 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
718 "shr{q}\t{%cl, $dst|$dst, %CL}",
719 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
720 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
721 "shr{q}\t{$src, $dst|$dst, $src}",
722 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
723 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
725 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
727 let isTwoAddress = 1 in {
729 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
730 "sar{q}\t{%cl, $dst|$dst, %CL}",
731 [(set GR64:$dst, (sra GR64:$src, CL))]>;
732 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
733 "sar{q}\t{$src2, $dst|$dst, $src2}",
734 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
735 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
737 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
741 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
742 "sar{q}\t{%cl, $dst|$dst, %CL}",
743 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
744 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
745 "sar{q}\t{$src, $dst|$dst, $src}",
746 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
747 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
749 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
751 // Rotate instructions
752 let isTwoAddress = 1 in {
754 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
755 "rol{q}\t{%cl, $dst|$dst, %CL}",
756 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
757 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
758 "rol{q}\t{$src2, $dst|$dst, $src2}",
759 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
760 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
762 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
766 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
767 "rol{q}\t{%cl, $dst|$dst, %CL}",
768 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
769 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
770 "rol{q}\t{$src, $dst|$dst, $src}",
771 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
772 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
774 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
776 let isTwoAddress = 1 in {
778 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
779 "ror{q}\t{%cl, $dst|$dst, %CL}",
780 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
781 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
782 "ror{q}\t{$src2, $dst|$dst, $src2}",
783 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
784 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
786 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
790 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
791 "ror{q}\t{%cl, $dst|$dst, %CL}",
792 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
793 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
794 "ror{q}\t{$src, $dst|$dst, $src}",
795 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
796 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
798 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
800 // Double shift instructions (generalizations of rotate)
801 let isTwoAddress = 1 in {
803 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
804 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
805 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
806 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
807 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
808 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
811 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
812 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
813 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
814 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
815 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
818 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
819 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
820 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
821 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
828 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
829 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
830 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
832 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
833 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
834 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
837 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
838 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
839 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
840 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
841 (i8 imm:$src3)), addr:$dst)]>,
843 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
844 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
845 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
846 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
847 (i8 imm:$src3)), addr:$dst)]>,
851 //===----------------------------------------------------------------------===//
852 // Logical Instructions...
855 let isTwoAddress = 1 , AddedComplexity = 15 in
856 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
857 [(set GR64:$dst, (not GR64:$src))]>;
858 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
859 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
861 let Defs = [EFLAGS] in {
862 let isTwoAddress = 1 in {
863 let isCommutable = 1 in
864 def AND64rr : RI<0x21, MRMDestReg,
865 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
866 "and{q}\t{$src2, $dst|$dst, $src2}",
867 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
869 def AND64rm : RI<0x23, MRMSrcMem,
870 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
871 "and{q}\t{$src2, $dst|$dst, $src2}",
872 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
874 def AND64ri8 : RIi8<0x83, MRM4r,
875 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
876 "and{q}\t{$src2, $dst|$dst, $src2}",
877 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
879 def AND64ri32 : RIi32<0x81, MRM4r,
880 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
881 "and{q}\t{$src2, $dst|$dst, $src2}",
882 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
886 def AND64mr : RI<0x21, MRMDestMem,
887 (outs), (ins i64mem:$dst, GR64:$src),
888 "and{q}\t{$src, $dst|$dst, $src}",
889 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
891 def AND64mi8 : RIi8<0x83, MRM4m,
892 (outs), (ins i64mem:$dst, i64i8imm :$src),
893 "and{q}\t{$src, $dst|$dst, $src}",
894 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
896 def AND64mi32 : RIi32<0x81, MRM4m,
897 (outs), (ins i64mem:$dst, i64i32imm:$src),
898 "and{q}\t{$src, $dst|$dst, $src}",
899 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
902 let isTwoAddress = 1 in {
903 let isCommutable = 1 in
904 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
905 "or{q}\t{$src2, $dst|$dst, $src2}",
906 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
908 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
909 "or{q}\t{$src2, $dst|$dst, $src2}",
910 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
912 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
913 "or{q}\t{$src2, $dst|$dst, $src2}",
914 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
916 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
917 "or{q}\t{$src2, $dst|$dst, $src2}",
918 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
922 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
923 "or{q}\t{$src, $dst|$dst, $src}",
924 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
926 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
927 "or{q}\t{$src, $dst|$dst, $src}",
928 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
930 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
931 "or{q}\t{$src, $dst|$dst, $src}",
932 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
935 let isTwoAddress = 1 in {
936 let isCommutable = 1 in
937 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
938 "xor{q}\t{$src2, $dst|$dst, $src2}",
939 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
941 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
942 "xor{q}\t{$src2, $dst|$dst, $src2}",
943 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
945 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
946 "xor{q}\t{$src2, $dst|$dst, $src2}",
947 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
949 def XOR64ri32 : RIi32<0x81, MRM6r,
950 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
951 "xor{q}\t{$src2, $dst|$dst, $src2}",
952 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
956 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
957 "xor{q}\t{$src, $dst|$dst, $src}",
958 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
960 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
961 "xor{q}\t{$src, $dst|$dst, $src}",
962 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
964 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
965 "xor{q}\t{$src, $dst|$dst, $src}",
966 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
970 //===----------------------------------------------------------------------===//
971 // Comparison Instructions...
974 // Integer comparison
975 let Defs = [EFLAGS] in {
976 let isCommutable = 1 in
977 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
978 "test{q}\t{$src2, $src1|$src1, $src2}",
979 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
981 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
982 "test{q}\t{$src2, $src1|$src1, $src2}",
983 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
985 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
986 (ins GR64:$src1, i64i32imm:$src2),
987 "test{q}\t{$src2, $src1|$src1, $src2}",
988 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
990 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
991 (ins i64mem:$src1, i64i32imm:$src2),
992 "test{q}\t{$src2, $src1|$src1, $src2}",
993 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
996 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
997 "cmp{q}\t{$src2, $src1|$src1, $src2}",
998 [(X86cmp GR64:$src1, GR64:$src2),
1000 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1001 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1002 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1003 (implicit EFLAGS)]>;
1004 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1005 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1006 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1007 (implicit EFLAGS)]>;
1008 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1009 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1010 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1011 (implicit EFLAGS)]>;
1012 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1013 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1014 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1015 (implicit EFLAGS)]>;
1016 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1017 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1018 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1019 (implicit EFLAGS)]>;
1020 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1021 (ins i64mem:$src1, i64i32imm:$src2),
1022 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1023 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1024 (implicit EFLAGS)]>;
1025 } // Defs = [EFLAGS]
1028 // TODO: BTC, BTR, and BTS
1029 let Defs = [EFLAGS] in {
1030 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1031 "bt{q}\t{$src2, $src1|$src1, $src2}",
1032 [(X86bt GR64:$src1, GR64:$src2),
1033 (implicit EFLAGS)]>, TB;
1035 // Unlike with the register+register form, the memory+register form of the
1036 // bt instruction does not ignore the high bits of the index. From ISel's
1037 // perspective, this is pretty bizarre. Disable these instructions for now.
1038 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1039 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1040 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1041 // (implicit EFLAGS)]>, TB;
1043 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1044 "bt{q}\t{$src2, $src1|$src1, $src2}",
1045 [(X86bt GR64:$src1, i64immSExt8:$src2),
1046 (implicit EFLAGS)]>, TB;
1047 // Note that these instructions don't need FastBTMem because that
1048 // only applies when the other operand is in a register. When it's
1049 // an immediate, bt is still fast.
1050 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1051 "bt{q}\t{$src2, $src1|$src1, $src2}",
1052 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1053 (implicit EFLAGS)]>, TB;
1054 } // Defs = [EFLAGS]
1056 // Conditional moves
1057 let Uses = [EFLAGS], isTwoAddress = 1 in {
1058 let isCommutable = 1 in {
1059 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1060 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1061 "cmovb\t{$src2, $dst|$dst, $src2}",
1062 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1063 X86_COND_B, EFLAGS))]>, TB;
1064 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1065 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1066 "cmovae\t{$src2, $dst|$dst, $src2}",
1067 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1068 X86_COND_AE, EFLAGS))]>, TB;
1069 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1070 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1071 "cmove\t{$src2, $dst|$dst, $src2}",
1072 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1073 X86_COND_E, EFLAGS))]>, TB;
1074 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1075 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1076 "cmovne\t{$src2, $dst|$dst, $src2}",
1077 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1078 X86_COND_NE, EFLAGS))]>, TB;
1079 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1080 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1081 "cmovbe\t{$src2, $dst|$dst, $src2}",
1082 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1083 X86_COND_BE, EFLAGS))]>, TB;
1084 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1085 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1086 "cmova\t{$src2, $dst|$dst, $src2}",
1087 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1088 X86_COND_A, EFLAGS))]>, TB;
1089 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1090 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1091 "cmovl\t{$src2, $dst|$dst, $src2}",
1092 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1093 X86_COND_L, EFLAGS))]>, TB;
1094 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1095 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1096 "cmovge\t{$src2, $dst|$dst, $src2}",
1097 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1098 X86_COND_GE, EFLAGS))]>, TB;
1099 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1100 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1101 "cmovle\t{$src2, $dst|$dst, $src2}",
1102 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1103 X86_COND_LE, EFLAGS))]>, TB;
1104 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1105 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1106 "cmovg\t{$src2, $dst|$dst, $src2}",
1107 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1108 X86_COND_G, EFLAGS))]>, TB;
1109 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1110 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1111 "cmovs\t{$src2, $dst|$dst, $src2}",
1112 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1113 X86_COND_S, EFLAGS))]>, TB;
1114 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1115 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1116 "cmovns\t{$src2, $dst|$dst, $src2}",
1117 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1118 X86_COND_NS, EFLAGS))]>, TB;
1119 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1120 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1121 "cmovp\t{$src2, $dst|$dst, $src2}",
1122 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1123 X86_COND_P, EFLAGS))]>, TB;
1124 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1125 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1126 "cmovnp\t{$src2, $dst|$dst, $src2}",
1127 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1128 X86_COND_NP, EFLAGS))]>, TB;
1129 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1130 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1131 "cmovo\t{$src2, $dst|$dst, $src2}",
1132 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1133 X86_COND_O, EFLAGS))]>, TB;
1134 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1135 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1136 "cmovno\t{$src2, $dst|$dst, $src2}",
1137 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1138 X86_COND_NO, EFLAGS))]>, TB;
1139 } // isCommutable = 1
1141 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1142 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1143 "cmovb\t{$src2, $dst|$dst, $src2}",
1144 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1145 X86_COND_B, EFLAGS))]>, TB;
1146 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1147 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1148 "cmovae\t{$src2, $dst|$dst, $src2}",
1149 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1150 X86_COND_AE, EFLAGS))]>, TB;
1151 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1152 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1153 "cmove\t{$src2, $dst|$dst, $src2}",
1154 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1155 X86_COND_E, EFLAGS))]>, TB;
1156 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1157 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1158 "cmovne\t{$src2, $dst|$dst, $src2}",
1159 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1160 X86_COND_NE, EFLAGS))]>, TB;
1161 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1162 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1163 "cmovbe\t{$src2, $dst|$dst, $src2}",
1164 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1165 X86_COND_BE, EFLAGS))]>, TB;
1166 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1167 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1168 "cmova\t{$src2, $dst|$dst, $src2}",
1169 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1170 X86_COND_A, EFLAGS))]>, TB;
1171 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1172 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1173 "cmovl\t{$src2, $dst|$dst, $src2}",
1174 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1175 X86_COND_L, EFLAGS))]>, TB;
1176 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1177 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1178 "cmovge\t{$src2, $dst|$dst, $src2}",
1179 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1180 X86_COND_GE, EFLAGS))]>, TB;
1181 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1182 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1183 "cmovle\t{$src2, $dst|$dst, $src2}",
1184 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1185 X86_COND_LE, EFLAGS))]>, TB;
1186 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1187 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1188 "cmovg\t{$src2, $dst|$dst, $src2}",
1189 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1190 X86_COND_G, EFLAGS))]>, TB;
1191 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1192 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1193 "cmovs\t{$src2, $dst|$dst, $src2}",
1194 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1195 X86_COND_S, EFLAGS))]>, TB;
1196 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1197 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1198 "cmovns\t{$src2, $dst|$dst, $src2}",
1199 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1200 X86_COND_NS, EFLAGS))]>, TB;
1201 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1202 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1203 "cmovp\t{$src2, $dst|$dst, $src2}",
1204 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1205 X86_COND_P, EFLAGS))]>, TB;
1206 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1207 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1208 "cmovnp\t{$src2, $dst|$dst, $src2}",
1209 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1210 X86_COND_NP, EFLAGS))]>, TB;
1211 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1212 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1213 "cmovo\t{$src2, $dst|$dst, $src2}",
1214 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1215 X86_COND_O, EFLAGS))]>, TB;
1216 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1217 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1218 "cmovno\t{$src2, $dst|$dst, $src2}",
1219 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1220 X86_COND_NO, EFLAGS))]>, TB;
1223 //===----------------------------------------------------------------------===//
1224 // Conversion Instructions...
1227 // f64 -> signed i64
1228 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1229 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1231 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1232 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1233 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1234 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1235 (load addr:$src)))]>;
1236 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1237 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1238 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1239 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1240 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1241 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1242 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1243 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1245 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1246 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1247 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1249 (int_x86_sse2_cvttsd2si64
1250 (load addr:$src)))]>;
1252 // Signed i64 -> f64
1253 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1254 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1255 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1256 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1257 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1258 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1260 let isTwoAddress = 1 in {
1261 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1262 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1263 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1265 (int_x86_sse2_cvtsi642sd VR128:$src1,
1267 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1268 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1269 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1271 (int_x86_sse2_cvtsi642sd VR128:$src1,
1272 (loadi64 addr:$src2)))]>;
1275 // Signed i64 -> f32
1276 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1277 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1278 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1279 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1280 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1281 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1283 let isTwoAddress = 1 in {
1284 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1285 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1286 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1288 (int_x86_sse_cvtsi642ss VR128:$src1,
1290 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1291 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1292 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1294 (int_x86_sse_cvtsi642ss VR128:$src1,
1295 (loadi64 addr:$src2)))]>;
1298 // f32 -> signed i64
1299 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1300 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1302 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1303 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1304 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1305 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1306 (load addr:$src)))]>;
1307 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1308 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1309 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1310 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1311 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1312 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1313 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1314 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1316 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1317 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1318 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1320 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1322 //===----------------------------------------------------------------------===//
1323 // Alias Instructions
1324 //===----------------------------------------------------------------------===//
1326 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1327 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1329 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1330 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1331 // when we have a better way to specify isel priority.
1332 let Defs = [EFLAGS], AddedComplexity = 1,
1333 isReMaterializable = 1, isAsCheapAsAMove = 1 in
1334 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1335 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1336 [(set GR64:$dst, 0)]>;
1338 // Materialize i64 constant where top 32-bits are zero.
1339 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1340 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1341 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1342 [(set GR64:$dst, i64immZExt32:$src)]>;
1344 //===----------------------------------------------------------------------===//
1345 // Thread Local Storage Instructions
1346 //===----------------------------------------------------------------------===//
1348 // All calls clobber the non-callee saved registers. RSP is marked as
1349 // a use to prevent stack-pointer assignments that appear immediately
1350 // before calls from potentially appearing dead.
1351 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1352 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1353 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1354 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1355 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1357 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64imm:$sym),
1359 "leaq\t${sym:mem}(%rip), %rdi; "
1362 "call\t__tls_get_addr@PLT",
1363 [(X86tlsaddr tglobaltlsaddr:$sym)]>,
1364 Requires<[In64BitMode]>;
1366 let AddedComplexity = 5 in
1367 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1368 "movq\t%gs:$src, $dst",
1369 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1371 let AddedComplexity = 5 in
1372 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1373 "movq\t%fs:$src, $dst",
1374 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1376 //===----------------------------------------------------------------------===//
1377 // Atomic Instructions
1378 //===----------------------------------------------------------------------===//
1380 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1381 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1383 "cmpxchgq\t$swap,$ptr",
1384 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1387 let Constraints = "$val = $dst" in {
1388 let Defs = [EFLAGS] in
1389 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1392 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1394 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1396 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1399 // Atomic exchange, and, or, xor
1400 let Constraints = "$val = $dst", Defs = [EFLAGS],
1401 usesCustomDAGSchedInserter = 1 in {
1402 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1403 "#ATOMAND64 PSEUDO!",
1404 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1405 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1406 "#ATOMOR64 PSEUDO!",
1407 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1408 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1409 "#ATOMXOR64 PSEUDO!",
1410 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1411 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1412 "#ATOMNAND64 PSEUDO!",
1413 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1414 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1415 "#ATOMMIN64 PSEUDO!",
1416 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1417 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1418 "#ATOMMAX64 PSEUDO!",
1419 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1420 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1421 "#ATOMUMIN64 PSEUDO!",
1422 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1423 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1424 "#ATOMUMAX64 PSEUDO!",
1425 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1428 //===----------------------------------------------------------------------===//
1429 // Non-Instruction Patterns
1430 //===----------------------------------------------------------------------===//
1432 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1433 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1434 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1435 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1436 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1437 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1438 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1439 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1440 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1442 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1443 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1444 Requires<[SmallCode, IsStatic]>;
1445 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1446 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1447 Requires<[SmallCode, IsStatic]>;
1448 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1449 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1450 Requires<[SmallCode, IsStatic]>;
1451 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1452 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1453 Requires<[SmallCode, IsStatic]>;
1456 // Direct PC relative function call for small code model. 32-bit displacement
1457 // sign extended to 64-bit.
1458 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1459 (CALL64pcrel32 tglobaladdr:$dst)>;
1460 def : Pat<(X86call (i64 texternalsym:$dst)),
1461 (CALL64pcrel32 texternalsym:$dst)>;
1463 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1464 (CALL64pcrel32 tglobaladdr:$dst)>;
1465 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1466 (CALL64pcrel32 texternalsym:$dst)>;
1468 def : Pat<(X86tailcall GR64:$dst),
1469 (CALL64r GR64:$dst)>;
1473 def : Pat<(X86tailcall GR32:$dst),
1475 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1477 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1480 def : Pat<(X86tcret GR64:$dst, imm:$off),
1481 (TCRETURNri64 GR64:$dst, imm:$off)>;
1483 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1484 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1486 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1487 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1491 // TEST R,R is smaller than CMP R,0
1492 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1493 (TEST64rr GR64:$src1, GR64:$src1)>;
1495 // Conditional moves with folded loads with operands swapped and conditions
1497 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1498 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1499 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1500 (CMOVB64rm GR64:$src2, addr:$src1)>;
1501 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1502 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1503 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1504 (CMOVE64rm GR64:$src2, addr:$src1)>;
1505 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1506 (CMOVA64rm GR64:$src2, addr:$src1)>;
1507 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1508 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1509 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1510 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1511 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1512 (CMOVL64rm GR64:$src2, addr:$src1)>;
1513 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1514 (CMOVG64rm GR64:$src2, addr:$src1)>;
1515 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1516 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1517 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1518 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1519 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1520 (CMOVP64rm GR64:$src2, addr:$src1)>;
1521 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1522 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1523 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1524 (CMOVS64rm GR64:$src2, addr:$src1)>;
1525 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1526 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1527 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1528 (CMOVO64rm GR64:$src2, addr:$src1)>;
1530 // zextload bool -> zextload byte
1531 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1534 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1535 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1536 // partial-register updates.
1537 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1538 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1539 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1540 // For other extloads, use subregs, since the high contents of the register are
1541 // defined after an extload.
1542 def : Pat<(extloadi64i32 addr:$src),
1543 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1545 def : Pat<(extloadi16i1 addr:$src),
1546 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1548 Requires<[In64BitMode]>;
1549 def : Pat<(extloadi16i8 addr:$src),
1550 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1552 Requires<[In64BitMode]>;
1555 def : Pat<(i64 (anyext GR8:$src)),
1556 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1557 def : Pat<(i64 (anyext GR16:$src)),
1558 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1559 def : Pat<(i64 (anyext GR32:$src)),
1560 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1561 def : Pat<(i16 (anyext GR8:$src)),
1562 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1563 Requires<[In64BitMode]>;
1564 def : Pat<(i32 (anyext GR8:$src)),
1565 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1566 Requires<[In64BitMode]>;
1568 //===----------------------------------------------------------------------===//
1570 //===----------------------------------------------------------------------===//
1572 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1573 // +128 doesn't, so in this special case use a sub instead of an add.
1574 def : Pat<(add GR64:$src1, 128),
1575 (SUB64ri8 GR64:$src1, -128)>;
1576 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1577 (SUB64mi8 addr:$dst, -128)>;
1579 // The same trick applies for 32-bit immediate fields in 64-bit
1581 def : Pat<(add GR64:$src1, 0x0000000080000000),
1582 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1583 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1584 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1586 // r & (2^32-1) ==> movz
1587 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1588 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1589 // r & (2^16-1) ==> movz
1590 def : Pat<(and GR64:$src, 0xffff),
1591 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1592 // r & (2^8-1) ==> movz
1593 def : Pat<(and GR64:$src, 0xff),
1594 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1595 // r & (2^8-1) ==> movz
1596 def : Pat<(and GR32:$src1, 0xff),
1597 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1598 Requires<[In64BitMode]>;
1599 // r & (2^8-1) ==> movz
1600 def : Pat<(and GR16:$src1, 0xff),
1601 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1602 Requires<[In64BitMode]>;
1604 // sext_inreg patterns
1605 def : Pat<(sext_inreg GR64:$src, i32),
1606 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1607 def : Pat<(sext_inreg GR64:$src, i16),
1608 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1609 def : Pat<(sext_inreg GR64:$src, i8),
1610 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1611 def : Pat<(sext_inreg GR32:$src, i8),
1612 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1613 Requires<[In64BitMode]>;
1614 def : Pat<(sext_inreg GR16:$src, i8),
1615 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1616 Requires<[In64BitMode]>;
1619 def : Pat<(i32 (trunc GR64:$src)),
1620 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1621 def : Pat<(i16 (trunc GR64:$src)),
1622 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1623 def : Pat<(i8 (trunc GR64:$src)),
1624 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1625 def : Pat<(i8 (trunc GR32:$src)),
1626 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1627 Requires<[In64BitMode]>;
1628 def : Pat<(i8 (trunc GR16:$src)),
1629 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1630 Requires<[In64BitMode]>;
1632 // h-register tricks.
1633 // For now, be conservative on x86-64 and use an h-register extract only if the
1634 // value is immediately zero-extended or stored, which are somewhat common
1635 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1636 // from being allocated in the same instruction as the h register, as there's
1637 // currently no way to describe this requirement to the register allocator.
1639 // h-register extract and zero-extend.
1640 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1644 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1645 x86_subreg_8bit_hi)),
1647 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1649 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1650 x86_subreg_8bit_hi))>,
1651 Requires<[In64BitMode]>;
1652 def : Pat<(srl_su GR16:$src, (i8 8)),
1655 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1656 x86_subreg_8bit_hi)),
1658 Requires<[In64BitMode]>;
1659 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1661 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1662 x86_subreg_8bit_hi))>,
1663 Requires<[In64BitMode]>;
1664 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1668 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1669 x86_subreg_8bit_hi)),
1672 // h-register extract and store.
1673 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1676 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1677 x86_subreg_8bit_hi))>;
1678 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1681 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1682 x86_subreg_8bit_hi))>,
1683 Requires<[In64BitMode]>;
1684 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1687 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1688 x86_subreg_8bit_hi))>,
1689 Requires<[In64BitMode]>;
1691 // (shl x, 1) ==> (add x, x)
1692 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1694 // (shl x (and y, 63)) ==> (shl x, y)
1695 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1696 (SHL64rCL GR64:$src1)>;
1697 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1698 (SHL64mCL addr:$dst)>;
1700 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1701 (SHR64rCL GR64:$src1)>;
1702 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1703 (SHR64mCL addr:$dst)>;
1705 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1706 (SAR64rCL GR64:$src1)>;
1707 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1708 (SAR64mCL addr:$dst)>;
1710 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1711 def : Pat<(or (srl GR64:$src1, CL:$amt),
1712 (shl GR64:$src2, (sub 64, CL:$amt))),
1713 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1715 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1716 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1717 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1719 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1720 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1721 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1723 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1724 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1726 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1728 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1729 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1731 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1732 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1733 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1735 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1736 def : Pat<(or (shl GR64:$src1, CL:$amt),
1737 (srl GR64:$src2, (sub 64, CL:$amt))),
1738 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1740 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1741 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1742 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1744 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1745 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1746 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1748 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1749 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1751 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1753 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1754 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1756 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1757 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1758 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1760 // X86 specific add which produces a flag.
1761 def : Pat<(addc GR64:$src1, GR64:$src2),
1762 (ADD64rr GR64:$src1, GR64:$src2)>;
1763 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1764 (ADD64rm GR64:$src1, addr:$src2)>;
1765 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1766 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1767 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1768 (ADD64ri32 GR64:$src1, imm:$src2)>;
1770 def : Pat<(subc GR64:$src1, GR64:$src2),
1771 (SUB64rr GR64:$src1, GR64:$src2)>;
1772 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1773 (SUB64rm GR64:$src1, addr:$src2)>;
1774 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1775 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1776 def : Pat<(subc GR64:$src1, imm:$src2),
1777 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1779 //===----------------------------------------------------------------------===//
1780 // EFLAGS-defining Patterns
1781 //===----------------------------------------------------------------------===//
1783 // Register-Register Addition with EFLAGS result
1784 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1786 (ADD64rr GR64:$src1, GR64:$src2)>;
1788 // Register-Integer Addition with EFLAGS result
1789 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1791 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1792 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1794 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1796 // Register-Memory Addition with EFLAGS result
1797 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1799 (ADD64rm GR64:$src1, addr:$src2)>;
1801 // Memory-Register Addition with EFLAGS result
1802 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1805 (ADD64mr addr:$dst, GR64:$src2)>;
1806 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1809 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1810 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1813 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1815 // Register-Register Subtraction with EFLAGS result
1816 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1818 (SUB64rr GR64:$src1, GR64:$src2)>;
1820 // Register-Memory Subtraction with EFLAGS result
1821 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1823 (SUB64rm GR64:$src1, addr:$src2)>;
1825 // Register-Integer Subtraction with EFLAGS result
1826 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1828 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1829 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1831 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1833 // Memory-Register Subtraction with EFLAGS result
1834 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1837 (SUB64mr addr:$dst, GR64:$src2)>;
1839 // Memory-Integer Subtraction with EFLAGS result
1840 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1843 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1844 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1847 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1849 // Register-Register Signed Integer Multiplication with EFLAGS result
1850 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1852 (IMUL64rr GR64:$src1, GR64:$src2)>;
1854 // Register-Memory Signed Integer Multiplication with EFLAGS result
1855 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1857 (IMUL64rm GR64:$src1, addr:$src2)>;
1859 // Register-Integer Signed Integer Multiplication with EFLAGS result
1860 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1862 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1863 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1865 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1867 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1868 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1870 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1871 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1873 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1875 // INC and DEC with EFLAGS result. Note that these do not set CF.
1876 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1877 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1878 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1880 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1881 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1882 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1883 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1885 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1887 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1888 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1889 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1891 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1892 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1893 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1894 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1896 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1898 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1899 (INC64r GR64:$src)>;
1900 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1902 (INC64m addr:$dst)>;
1903 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1904 (DEC64r GR64:$src)>;
1905 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1907 (DEC64m addr:$dst)>;
1909 //===----------------------------------------------------------------------===//
1910 // X86-64 SSE Instructions
1911 //===----------------------------------------------------------------------===//
1913 // Move instructions...
1915 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1916 "mov{d|q}\t{$src, $dst|$dst, $src}",
1918 (v2i64 (scalar_to_vector GR64:$src)))]>;
1919 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1920 "mov{d|q}\t{$src, $dst|$dst, $src}",
1921 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1924 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1925 "mov{d|q}\t{$src, $dst|$dst, $src}",
1926 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1927 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1928 "movq\t{$src, $dst|$dst, $src}",
1929 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1931 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1932 "mov{d|q}\t{$src, $dst|$dst, $src}",
1933 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1934 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1935 "movq\t{$src, $dst|$dst, $src}",
1936 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1938 //===----------------------------------------------------------------------===//
1939 // X86-64 SSE4.1 Instructions
1940 //===----------------------------------------------------------------------===//
1942 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1943 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
1944 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
1945 (ins VR128:$src1, i32i8imm:$src2),
1946 !strconcat(OpcodeStr,
1947 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1949 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
1950 def mr : SS4AIi8<opc, MRMDestMem, (outs),
1951 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
1952 !strconcat(OpcodeStr,
1953 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1954 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
1955 addr:$dst)]>, OpSize, REX_W;
1958 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
1960 let isTwoAddress = 1 in {
1961 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
1962 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
1963 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
1964 !strconcat(OpcodeStr,
1965 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1967 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
1969 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
1970 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
1971 !strconcat(OpcodeStr,
1972 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1974 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
1975 imm:$src3)))]>, OpSize, REX_W;
1979 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;