1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
174 "#TC_RETURN $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
180 "#TC_RETURN $dst $offset",
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def PUSH64r : I<0x50, AddRegFrm,
222 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
225 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
226 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
227 "push{q}\t$imm", []>;
228 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
229 "push{q}\t$imm", []>;
230 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
231 "push{q}\t$imm", []>;
234 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
235 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
236 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
237 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
239 def LEA64_32r : I<0x8D, MRMSrcMem,
240 (outs GR32:$dst), (ins lea64_32mem:$src),
241 "lea{l}\t{$src|$dst}, {$dst|$src}",
242 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
244 let isReMaterializable = 1 in
245 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
246 "lea{q}\t{$src|$dst}, {$dst|$src}",
247 [(set GR64:$dst, lea64addr:$src)]>;
249 let isTwoAddress = 1 in
250 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
252 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
254 // Bit scan instructions.
255 let Defs = [EFLAGS] in {
256 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
257 "bsf{q}\t{$src, $dst|$dst, $src}",
258 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
259 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
260 "bsf{q}\t{$src, $dst|$dst, $src}",
261 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
262 (implicit EFLAGS)]>, TB;
264 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
265 "bsr{q}\t{$src, $dst|$dst, $src}",
266 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
267 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
268 "bsr{q}\t{$src, $dst|$dst, $src}",
269 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
270 (implicit EFLAGS)]>, TB;
274 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
275 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
276 [(X86rep_movs i64)]>, REP;
277 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
278 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
279 [(X86rep_stos i64)]>, REP;
281 // Fast system-call instructions
282 def SYSEXIT64 : RI<0x35, RawFrm,
283 (outs), (ins), "sysexit", []>, TB;
285 //===----------------------------------------------------------------------===//
286 // Move Instructions...
289 let neverHasSideEffects = 1 in
290 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
291 "mov{q}\t{$src, $dst|$dst, $src}", []>;
293 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
294 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
295 "movabs{q}\t{$src, $dst|$dst, $src}",
296 [(set GR64:$dst, imm:$src)]>;
297 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
298 "mov{q}\t{$src, $dst|$dst, $src}",
299 [(set GR64:$dst, i64immSExt32:$src)]>;
302 let canFoldAsLoad = 1 in
303 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
304 "mov{q}\t{$src, $dst|$dst, $src}",
305 [(set GR64:$dst, (load addr:$src))]>;
307 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
308 "mov{q}\t{$src, $dst|$dst, $src}",
309 [(store GR64:$src, addr:$dst)]>;
310 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
311 "mov{q}\t{$src, $dst|$dst, $src}",
312 [(store i64immSExt32:$src, addr:$dst)]>;
314 // Sign/Zero extenders
316 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
317 // operand, which makes it a rare instruction with an 8-bit register
318 // operand that can never access an h register. If support for h registers
319 // were generalized, this would require a special register class.
320 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
321 "movs{bq|x}\t{$src, $dst|$dst, $src}",
322 [(set GR64:$dst, (sext GR8:$src))]>, TB;
323 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
324 "movs{bq|x}\t{$src, $dst|$dst, $src}",
325 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
326 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
327 "movs{wq|x}\t{$src, $dst|$dst, $src}",
328 [(set GR64:$dst, (sext GR16:$src))]>, TB;
329 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
330 "movs{wq|x}\t{$src, $dst|$dst, $src}",
331 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
332 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
333 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
334 [(set GR64:$dst, (sext GR32:$src))]>;
335 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
336 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
337 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
339 // Use movzbl instead of movzbq when the destination is a register; it's
340 // equivalent due to implicit zero-extending, and it has a smaller encoding.
341 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
342 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
343 [(set GR64:$dst, (zext GR8:$src))]>, TB;
344 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
345 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
346 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
347 // Use movzwl instead of movzwq when the destination is a register; it's
348 // equivalent due to implicit zero-extending, and it has a smaller encoding.
349 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
350 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
351 [(set GR64:$dst, (zext GR16:$src))]>, TB;
352 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
353 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
354 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
356 // There's no movzlq instruction, but movl can be used for this purpose, using
357 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
358 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
359 // zero-extension, however this isn't possible when the 32-bit value is
360 // defined by a truncate or is copied from something where the high bits aren't
361 // necessarily all zero. In such cases, we fall back to these explicit zext
363 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
364 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
365 [(set GR64:$dst, (zext GR32:$src))]>;
366 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
367 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
368 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
370 // Any instruction that defines a 32-bit result leaves the high half of the
371 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
372 // be copying from a truncate, but any other 32-bit operation will zero-extend
374 def def32 : PatLeaf<(i32 GR32:$src), [{
375 return N->getOpcode() != ISD::TRUNCATE &&
376 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
377 N->getOpcode() != ISD::CopyFromReg;
380 // In the case of a 32-bit def that is known to implicitly zero-extend,
381 // we can use a SUBREG_TO_REG.
382 def : Pat<(i64 (zext def32:$src)),
383 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
385 let neverHasSideEffects = 1 in {
386 let Defs = [RAX], Uses = [EAX] in
387 def CDQE : RI<0x98, RawFrm, (outs), (ins),
388 "{cltq|cdqe}", []>; // RAX = signext(EAX)
390 let Defs = [RAX,RDX], Uses = [RAX] in
391 def CQO : RI<0x99, RawFrm, (outs), (ins),
392 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
395 //===----------------------------------------------------------------------===//
396 // Arithmetic Instructions...
399 let Defs = [EFLAGS] in {
401 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
402 "add{q}\t{$src, %rax|%rax, $src}", []>;
404 let isTwoAddress = 1 in {
405 let isConvertibleToThreeAddress = 1 in {
406 let isCommutable = 1 in
407 // Register-Register Addition
408 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
409 "add{q}\t{$src2, $dst|$dst, $src2}",
410 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
413 // Register-Integer Addition
414 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
415 "add{q}\t{$src2, $dst|$dst, $src2}",
416 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
418 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
419 "add{q}\t{$src2, $dst|$dst, $src2}",
420 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
422 } // isConvertibleToThreeAddress
424 // Register-Memory Addition
425 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
426 "add{q}\t{$src2, $dst|$dst, $src2}",
427 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
431 // Memory-Register Addition
432 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
433 "add{q}\t{$src2, $dst|$dst, $src2}",
434 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
436 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
437 "add{q}\t{$src2, $dst|$dst, $src2}",
438 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
440 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
441 "add{q}\t{$src2, $dst|$dst, $src2}",
442 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
445 let Uses = [EFLAGS] in {
446 let isTwoAddress = 1 in {
447 let isCommutable = 1 in
448 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
449 "adc{q}\t{$src2, $dst|$dst, $src2}",
450 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
452 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
453 "adc{q}\t{$src2, $dst|$dst, $src2}",
454 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
456 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
457 "adc{q}\t{$src2, $dst|$dst, $src2}",
458 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
459 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
460 "adc{q}\t{$src2, $dst|$dst, $src2}",
461 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
464 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
465 "adc{q}\t{$src2, $dst|$dst, $src2}",
466 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
467 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
468 "adc{q}\t{$src2, $dst|$dst, $src2}",
469 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
470 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
471 "adc{q}\t{$src2, $dst|$dst, $src2}",
472 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
475 let isTwoAddress = 1 in {
476 // Register-Register Subtraction
477 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
478 "sub{q}\t{$src2, $dst|$dst, $src2}",
479 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
482 // Register-Memory Subtraction
483 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
484 "sub{q}\t{$src2, $dst|$dst, $src2}",
485 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
488 // Register-Integer Subtraction
489 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
490 (ins GR64:$src1, i64i8imm:$src2),
491 "sub{q}\t{$src2, $dst|$dst, $src2}",
492 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
494 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
495 (ins GR64:$src1, i64i32imm:$src2),
496 "sub{q}\t{$src2, $dst|$dst, $src2}",
497 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
501 // Memory-Register Subtraction
502 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
503 "sub{q}\t{$src2, $dst|$dst, $src2}",
504 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
507 // Memory-Integer Subtraction
508 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
509 "sub{q}\t{$src2, $dst|$dst, $src2}",
510 [(store (sub (load addr:$dst), i64immSExt8:$src2),
513 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
514 "sub{q}\t{$src2, $dst|$dst, $src2}",
515 [(store (sub (load addr:$dst), i64immSExt32:$src2),
519 let Uses = [EFLAGS] in {
520 let isTwoAddress = 1 in {
521 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
522 "sbb{q}\t{$src2, $dst|$dst, $src2}",
523 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
525 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
526 "sbb{q}\t{$src2, $dst|$dst, $src2}",
527 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
529 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
530 "sbb{q}\t{$src2, $dst|$dst, $src2}",
531 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
532 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
533 "sbb{q}\t{$src2, $dst|$dst, $src2}",
534 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
537 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
538 "sbb{q}\t{$src2, $dst|$dst, $src2}",
539 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
540 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
541 "sbb{q}\t{$src2, $dst|$dst, $src2}",
542 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
543 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
544 "sbb{q}\t{$src2, $dst|$dst, $src2}",
545 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
549 // Unsigned multiplication
550 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
551 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
552 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
554 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
555 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
557 // Signed multiplication
558 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
559 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
561 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
562 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
565 let Defs = [EFLAGS] in {
566 let isTwoAddress = 1 in {
567 let isCommutable = 1 in
568 // Register-Register Signed Integer Multiplication
569 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
570 (ins GR64:$src1, GR64:$src2),
571 "imul{q}\t{$src2, $dst|$dst, $src2}",
572 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
573 (implicit EFLAGS)]>, TB;
575 // Register-Memory Signed Integer Multiplication
576 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
577 (ins GR64:$src1, i64mem:$src2),
578 "imul{q}\t{$src2, $dst|$dst, $src2}",
579 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
580 (implicit EFLAGS)]>, TB;
583 // Suprisingly enough, these are not two address instructions!
585 // Register-Integer Signed Integer Multiplication
586 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
587 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
588 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
589 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
591 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
592 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
593 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
594 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
597 // Memory-Integer Signed Integer Multiplication
598 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
599 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
600 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 [(set GR64:$dst, (mul (load addr:$src1),
604 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
605 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
606 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
607 [(set GR64:$dst, (mul (load addr:$src1),
608 i64immSExt32:$src2)),
612 // Unsigned division / remainder
613 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
614 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
616 // Signed division / remainder
617 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
618 "idiv{q}\t$src", []>;
620 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
622 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
623 "idiv{q}\t$src", []>;
627 // Unary instructions
628 let Defs = [EFLAGS], CodeSize = 2 in {
629 let isTwoAddress = 1 in
630 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
631 [(set GR64:$dst, (ineg GR64:$src)),
633 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
634 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
637 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
638 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
639 [(set GR64:$dst, (add GR64:$src, 1)),
641 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
642 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
645 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
646 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
647 [(set GR64:$dst, (add GR64:$src, -1)),
649 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
650 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
653 // In 64-bit mode, single byte INC and DEC cannot be encoded.
654 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
655 // Can transform into LEA.
656 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
657 [(set GR16:$dst, (add GR16:$src, 1)),
659 OpSize, Requires<[In64BitMode]>;
660 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
661 [(set GR32:$dst, (add GR32:$src, 1)),
663 Requires<[In64BitMode]>;
664 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
665 [(set GR16:$dst, (add GR16:$src, -1)),
667 OpSize, Requires<[In64BitMode]>;
668 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
669 [(set GR32:$dst, (add GR32:$src, -1)),
671 Requires<[In64BitMode]>;
672 } // isConvertibleToThreeAddress
674 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
675 // how to unfold them.
676 let isTwoAddress = 0, CodeSize = 2 in {
677 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
678 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
680 OpSize, Requires<[In64BitMode]>;
681 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
682 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
684 Requires<[In64BitMode]>;
685 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
686 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
688 OpSize, Requires<[In64BitMode]>;
689 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
690 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
692 Requires<[In64BitMode]>;
694 } // Defs = [EFLAGS], CodeSize
697 let Defs = [EFLAGS] in {
698 // Shift instructions
699 let isTwoAddress = 1 in {
701 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
702 "shl{q}\t{%cl, $dst|$dst, %CL}",
703 [(set GR64:$dst, (shl GR64:$src, CL))]>;
704 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
705 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
706 "shl{q}\t{$src2, $dst|$dst, $src2}",
707 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
708 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
713 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
714 "shl{q}\t{%cl, $dst|$dst, %CL}",
715 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
716 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
717 "shl{q}\t{$src, $dst|$dst, $src}",
718 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
719 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
721 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
723 let isTwoAddress = 1 in {
725 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
726 "shr{q}\t{%cl, $dst|$dst, %CL}",
727 [(set GR64:$dst, (srl GR64:$src, CL))]>;
728 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
729 "shr{q}\t{$src2, $dst|$dst, $src2}",
730 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
731 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
733 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
737 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
738 "shr{q}\t{%cl, $dst|$dst, %CL}",
739 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
740 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
741 "shr{q}\t{$src, $dst|$dst, $src}",
742 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
743 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
745 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
747 let isTwoAddress = 1 in {
749 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
750 "sar{q}\t{%cl, $dst|$dst, %CL}",
751 [(set GR64:$dst, (sra GR64:$src, CL))]>;
752 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
753 "sar{q}\t{$src2, $dst|$dst, $src2}",
754 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
755 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
757 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
761 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
762 "sar{q}\t{%cl, $dst|$dst, %CL}",
763 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
764 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
765 "sar{q}\t{$src, $dst|$dst, $src}",
766 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
767 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
769 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
771 // Rotate instructions
772 let isTwoAddress = 1 in {
774 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
775 "rol{q}\t{%cl, $dst|$dst, %CL}",
776 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
777 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
778 "rol{q}\t{$src2, $dst|$dst, $src2}",
779 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
780 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
782 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
786 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
787 "rol{q}\t{%cl, $dst|$dst, %CL}",
788 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
789 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
790 "rol{q}\t{$src, $dst|$dst, $src}",
791 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
792 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
794 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
796 let isTwoAddress = 1 in {
798 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
799 "ror{q}\t{%cl, $dst|$dst, %CL}",
800 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
801 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
802 "ror{q}\t{$src2, $dst|$dst, $src2}",
803 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
804 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
806 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
810 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
811 "ror{q}\t{%cl, $dst|$dst, %CL}",
812 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
813 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
814 "ror{q}\t{$src, $dst|$dst, $src}",
815 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
816 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
818 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
820 // Double shift instructions (generalizations of rotate)
821 let isTwoAddress = 1 in {
823 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
824 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
825 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
826 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
827 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
828 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
831 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
832 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
833 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
834 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
835 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
838 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
839 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
840 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
841 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
848 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
849 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
850 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
852 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
853 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
854 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
857 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
858 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
859 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
860 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
861 (i8 imm:$src3)), addr:$dst)]>,
863 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
864 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
865 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
866 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
867 (i8 imm:$src3)), addr:$dst)]>,
871 //===----------------------------------------------------------------------===//
872 // Logical Instructions...
875 let isTwoAddress = 1 , AddedComplexity = 15 in
876 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
877 [(set GR64:$dst, (not GR64:$src))]>;
878 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
879 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
881 let Defs = [EFLAGS] in {
882 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
883 "and{q}\t{$src, %rax|%rax, $src}", []>;
885 let isTwoAddress = 1 in {
886 let isCommutable = 1 in
887 def AND64rr : RI<0x21, MRMDestReg,
888 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
889 "and{q}\t{$src2, $dst|$dst, $src2}",
890 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
892 def AND64rm : RI<0x23, MRMSrcMem,
893 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
894 "and{q}\t{$src2, $dst|$dst, $src2}",
895 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
897 def AND64ri8 : RIi8<0x83, MRM4r,
898 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
899 "and{q}\t{$src2, $dst|$dst, $src2}",
900 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
902 def AND64ri32 : RIi32<0x81, MRM4r,
903 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
904 "and{q}\t{$src2, $dst|$dst, $src2}",
905 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
909 def AND64mr : RI<0x21, MRMDestMem,
910 (outs), (ins i64mem:$dst, GR64:$src),
911 "and{q}\t{$src, $dst|$dst, $src}",
912 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
914 def AND64mi8 : RIi8<0x83, MRM4m,
915 (outs), (ins i64mem:$dst, i64i8imm :$src),
916 "and{q}\t{$src, $dst|$dst, $src}",
917 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
919 def AND64mi32 : RIi32<0x81, MRM4m,
920 (outs), (ins i64mem:$dst, i64i32imm:$src),
921 "and{q}\t{$src, $dst|$dst, $src}",
922 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
925 let isTwoAddress = 1 in {
926 let isCommutable = 1 in
927 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
928 "or{q}\t{$src2, $dst|$dst, $src2}",
929 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
931 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
932 "or{q}\t{$src2, $dst|$dst, $src2}",
933 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
935 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
936 "or{q}\t{$src2, $dst|$dst, $src2}",
937 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
939 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
940 "or{q}\t{$src2, $dst|$dst, $src2}",
941 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
945 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
946 "or{q}\t{$src, $dst|$dst, $src}",
947 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
949 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
950 "or{q}\t{$src, $dst|$dst, $src}",
951 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
953 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
954 "or{q}\t{$src, $dst|$dst, $src}",
955 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
958 let isTwoAddress = 1 in {
959 let isCommutable = 1 in
960 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
961 "xor{q}\t{$src2, $dst|$dst, $src2}",
962 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
964 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
965 "xor{q}\t{$src2, $dst|$dst, $src2}",
966 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
968 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
969 "xor{q}\t{$src2, $dst|$dst, $src2}",
970 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
972 def XOR64ri32 : RIi32<0x81, MRM6r,
973 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
974 "xor{q}\t{$src2, $dst|$dst, $src2}",
975 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
979 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
980 "xor{q}\t{$src, $dst|$dst, $src}",
981 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
983 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
984 "xor{q}\t{$src, $dst|$dst, $src}",
985 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
987 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
988 "xor{q}\t{$src, $dst|$dst, $src}",
989 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
993 //===----------------------------------------------------------------------===//
994 // Comparison Instructions...
997 // Integer comparison
998 let Defs = [EFLAGS] in {
999 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1000 "test{q}\t{$src, %rax|%rax, $src}", []>;
1001 let isCommutable = 1 in
1002 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1003 "test{q}\t{$src2, $src1|$src1, $src2}",
1004 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1005 (implicit EFLAGS)]>;
1006 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1007 "test{q}\t{$src2, $src1|$src1, $src2}",
1008 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1009 (implicit EFLAGS)]>;
1010 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1011 (ins GR64:$src1, i64i32imm:$src2),
1012 "test{q}\t{$src2, $src1|$src1, $src2}",
1013 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1014 (implicit EFLAGS)]>;
1015 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1016 (ins i64mem:$src1, i64i32imm:$src2),
1017 "test{q}\t{$src2, $src1|$src1, $src2}",
1018 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1019 (implicit EFLAGS)]>;
1022 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1023 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1024 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1025 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1026 [(X86cmp GR64:$src1, GR64:$src2),
1027 (implicit EFLAGS)]>;
1028 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1029 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1030 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1031 (implicit EFLAGS)]>;
1032 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1033 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1034 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1035 (implicit EFLAGS)]>;
1036 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1037 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1038 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1039 (implicit EFLAGS)]>;
1040 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1041 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1042 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1043 (implicit EFLAGS)]>;
1044 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1045 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1046 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1047 (implicit EFLAGS)]>;
1048 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1049 (ins i64mem:$src1, i64i32imm:$src2),
1050 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1051 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1052 (implicit EFLAGS)]>;
1053 } // Defs = [EFLAGS]
1056 // TODO: BTC, BTR, and BTS
1057 let Defs = [EFLAGS] in {
1058 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1059 "bt{q}\t{$src2, $src1|$src1, $src2}",
1060 [(X86bt GR64:$src1, GR64:$src2),
1061 (implicit EFLAGS)]>, TB;
1063 // Unlike with the register+register form, the memory+register form of the
1064 // bt instruction does not ignore the high bits of the index. From ISel's
1065 // perspective, this is pretty bizarre. Disable these instructions for now.
1066 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1067 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1068 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1069 // (implicit EFLAGS)]>, TB;
1071 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1072 "bt{q}\t{$src2, $src1|$src1, $src2}",
1073 [(X86bt GR64:$src1, i64immSExt8:$src2),
1074 (implicit EFLAGS)]>, TB;
1075 // Note that these instructions don't need FastBTMem because that
1076 // only applies when the other operand is in a register. When it's
1077 // an immediate, bt is still fast.
1078 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1079 "bt{q}\t{$src2, $src1|$src1, $src2}",
1080 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1081 (implicit EFLAGS)]>, TB;
1082 } // Defs = [EFLAGS]
1084 // Conditional moves
1085 let Uses = [EFLAGS], isTwoAddress = 1 in {
1086 let isCommutable = 1 in {
1087 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1088 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1089 "cmovb\t{$src2, $dst|$dst, $src2}",
1090 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1091 X86_COND_B, EFLAGS))]>, TB;
1092 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1093 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1094 "cmovae\t{$src2, $dst|$dst, $src2}",
1095 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1096 X86_COND_AE, EFLAGS))]>, TB;
1097 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1098 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1099 "cmove\t{$src2, $dst|$dst, $src2}",
1100 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1101 X86_COND_E, EFLAGS))]>, TB;
1102 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1103 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1104 "cmovne\t{$src2, $dst|$dst, $src2}",
1105 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1106 X86_COND_NE, EFLAGS))]>, TB;
1107 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1108 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1109 "cmovbe\t{$src2, $dst|$dst, $src2}",
1110 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1111 X86_COND_BE, EFLAGS))]>, TB;
1112 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1113 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1114 "cmova\t{$src2, $dst|$dst, $src2}",
1115 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1116 X86_COND_A, EFLAGS))]>, TB;
1117 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1118 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1119 "cmovl\t{$src2, $dst|$dst, $src2}",
1120 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1121 X86_COND_L, EFLAGS))]>, TB;
1122 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1123 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1124 "cmovge\t{$src2, $dst|$dst, $src2}",
1125 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1126 X86_COND_GE, EFLAGS))]>, TB;
1127 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1128 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1129 "cmovle\t{$src2, $dst|$dst, $src2}",
1130 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1131 X86_COND_LE, EFLAGS))]>, TB;
1132 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1133 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1134 "cmovg\t{$src2, $dst|$dst, $src2}",
1135 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1136 X86_COND_G, EFLAGS))]>, TB;
1137 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1138 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1139 "cmovs\t{$src2, $dst|$dst, $src2}",
1140 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1141 X86_COND_S, EFLAGS))]>, TB;
1142 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1143 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1144 "cmovns\t{$src2, $dst|$dst, $src2}",
1145 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1146 X86_COND_NS, EFLAGS))]>, TB;
1147 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1148 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1149 "cmovp\t{$src2, $dst|$dst, $src2}",
1150 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1151 X86_COND_P, EFLAGS))]>, TB;
1152 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1153 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1154 "cmovnp\t{$src2, $dst|$dst, $src2}",
1155 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1156 X86_COND_NP, EFLAGS))]>, TB;
1157 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1158 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1159 "cmovo\t{$src2, $dst|$dst, $src2}",
1160 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1161 X86_COND_O, EFLAGS))]>, TB;
1162 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1163 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1164 "cmovno\t{$src2, $dst|$dst, $src2}",
1165 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1166 X86_COND_NO, EFLAGS))]>, TB;
1167 } // isCommutable = 1
1169 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1170 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1171 "cmovb\t{$src2, $dst|$dst, $src2}",
1172 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1173 X86_COND_B, EFLAGS))]>, TB;
1174 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1175 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1176 "cmovae\t{$src2, $dst|$dst, $src2}",
1177 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1178 X86_COND_AE, EFLAGS))]>, TB;
1179 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1180 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1181 "cmove\t{$src2, $dst|$dst, $src2}",
1182 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1183 X86_COND_E, EFLAGS))]>, TB;
1184 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1185 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1186 "cmovne\t{$src2, $dst|$dst, $src2}",
1187 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1188 X86_COND_NE, EFLAGS))]>, TB;
1189 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1190 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1191 "cmovbe\t{$src2, $dst|$dst, $src2}",
1192 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1193 X86_COND_BE, EFLAGS))]>, TB;
1194 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1195 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1196 "cmova\t{$src2, $dst|$dst, $src2}",
1197 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1198 X86_COND_A, EFLAGS))]>, TB;
1199 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1200 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1201 "cmovl\t{$src2, $dst|$dst, $src2}",
1202 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1203 X86_COND_L, EFLAGS))]>, TB;
1204 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1205 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1206 "cmovge\t{$src2, $dst|$dst, $src2}",
1207 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1208 X86_COND_GE, EFLAGS))]>, TB;
1209 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1210 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1211 "cmovle\t{$src2, $dst|$dst, $src2}",
1212 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1213 X86_COND_LE, EFLAGS))]>, TB;
1214 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1215 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1216 "cmovg\t{$src2, $dst|$dst, $src2}",
1217 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1218 X86_COND_G, EFLAGS))]>, TB;
1219 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1220 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1221 "cmovs\t{$src2, $dst|$dst, $src2}",
1222 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1223 X86_COND_S, EFLAGS))]>, TB;
1224 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1225 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1226 "cmovns\t{$src2, $dst|$dst, $src2}",
1227 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1228 X86_COND_NS, EFLAGS))]>, TB;
1229 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1230 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1231 "cmovp\t{$src2, $dst|$dst, $src2}",
1232 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1233 X86_COND_P, EFLAGS))]>, TB;
1234 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1235 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1236 "cmovnp\t{$src2, $dst|$dst, $src2}",
1237 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1238 X86_COND_NP, EFLAGS))]>, TB;
1239 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1240 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1241 "cmovo\t{$src2, $dst|$dst, $src2}",
1242 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1243 X86_COND_O, EFLAGS))]>, TB;
1244 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1245 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1246 "cmovno\t{$src2, $dst|$dst, $src2}",
1247 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1248 X86_COND_NO, EFLAGS))]>, TB;
1251 //===----------------------------------------------------------------------===//
1252 // Conversion Instructions...
1255 // f64 -> signed i64
1256 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1257 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1259 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1260 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1261 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1262 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1263 (load addr:$src)))]>;
1264 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1265 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1266 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1267 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1268 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1269 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1270 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1271 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1273 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1274 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1275 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1277 (int_x86_sse2_cvttsd2si64
1278 (load addr:$src)))]>;
1280 // Signed i64 -> f64
1281 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1282 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1283 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1284 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1285 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1286 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1288 let isTwoAddress = 1 in {
1289 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1290 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1291 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1293 (int_x86_sse2_cvtsi642sd VR128:$src1,
1295 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1296 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1297 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1299 (int_x86_sse2_cvtsi642sd VR128:$src1,
1300 (loadi64 addr:$src2)))]>;
1303 // Signed i64 -> f32
1304 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1305 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1306 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1307 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1308 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1309 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1311 let isTwoAddress = 1 in {
1312 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1313 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1314 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1316 (int_x86_sse_cvtsi642ss VR128:$src1,
1318 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1319 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1320 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1322 (int_x86_sse_cvtsi642ss VR128:$src1,
1323 (loadi64 addr:$src2)))]>;
1326 // f32 -> signed i64
1327 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1328 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1330 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1331 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1332 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1333 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1334 (load addr:$src)))]>;
1335 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1336 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1337 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1338 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1339 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1340 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1341 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1342 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1344 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1345 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1346 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1348 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1350 //===----------------------------------------------------------------------===//
1351 // Alias Instructions
1352 //===----------------------------------------------------------------------===//
1354 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1355 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1357 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1358 // when we have a better way to specify isel priority.
1359 let AddedComplexity = 1 in
1361 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1364 // Materialize i64 constant where top 32-bits are zero.
1365 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1366 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1367 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1368 [(set GR64:$dst, i64immZExt32:$src)]>;
1370 //===----------------------------------------------------------------------===//
1371 // Thread Local Storage Instructions
1372 //===----------------------------------------------------------------------===//
1374 // All calls clobber the non-callee saved registers. RSP is marked as
1375 // a use to prevent stack-pointer assignments that appear immediately
1376 // before calls from potentially appearing dead.
1377 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1378 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1379 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1380 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1381 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1383 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1385 "leaq\t$sym(%rip), %rdi; "
1388 "call\t__tls_get_addr@PLT",
1389 [(X86tlsaddr tls64addr:$sym)]>,
1390 Requires<[In64BitMode]>;
1392 let AddedComplexity = 5, isCodeGenOnly = 1 in
1393 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1394 "movq\t%gs:$src, $dst",
1395 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1397 let AddedComplexity = 5, isCodeGenOnly = 1 in
1398 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1399 "movq\t%fs:$src, $dst",
1400 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1402 //===----------------------------------------------------------------------===//
1403 // Atomic Instructions
1404 //===----------------------------------------------------------------------===//
1406 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1407 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1409 "cmpxchgq\t$swap,$ptr",
1410 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1413 let Constraints = "$val = $dst" in {
1414 let Defs = [EFLAGS] in
1415 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1418 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1421 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1423 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1426 // Optimized codegen when the non-memory output is not used.
1427 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1428 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1430 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1431 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1432 (ins i64mem:$dst, i64i8imm :$src2),
1434 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1435 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1436 (ins i64mem:$dst, i64i32imm :$src2),
1438 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1439 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1441 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1442 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1443 (ins i64mem:$dst, i64i8imm :$src2),
1445 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1446 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1447 (ins i64mem:$dst, i64i32imm:$src2),
1449 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1450 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1452 "inc{q}\t$dst", []>, LOCK;
1453 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1455 "dec{q}\t$dst", []>, LOCK;
1457 // Atomic exchange, and, or, xor
1458 let Constraints = "$val = $dst", Defs = [EFLAGS],
1459 usesCustomDAGSchedInserter = 1 in {
1460 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1461 "#ATOMAND64 PSEUDO!",
1462 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1463 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1464 "#ATOMOR64 PSEUDO!",
1465 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1466 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1467 "#ATOMXOR64 PSEUDO!",
1468 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1469 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1470 "#ATOMNAND64 PSEUDO!",
1471 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1472 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1473 "#ATOMMIN64 PSEUDO!",
1474 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1475 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1476 "#ATOMMAX64 PSEUDO!",
1477 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1478 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1479 "#ATOMUMIN64 PSEUDO!",
1480 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1481 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1482 "#ATOMUMAX64 PSEUDO!",
1483 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1486 //===----------------------------------------------------------------------===//
1487 // Non-Instruction Patterns
1488 //===----------------------------------------------------------------------===//
1490 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1491 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1492 // 'movabs' predicate should handle this sort of thing.
1493 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1494 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1495 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1496 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1497 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1498 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1499 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1500 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1502 // In static codegen with small code model, we can get the address of a label
1503 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1504 // the MOV64ri64i32 should accept these.
1505 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1506 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1507 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1508 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1509 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1510 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1511 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1512 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1514 // In kernel code model, we can get the address of a label
1515 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1516 // the MOV64ri32 should accept these.
1517 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1518 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1519 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1520 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1521 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1522 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1523 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1524 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1526 // If we have small model and -static mode, it is safe to store global addresses
1527 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1528 // for MOV64mi32 should handle this sort of thing.
1529 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1530 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1531 Requires<[NearData, IsStatic]>;
1532 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1533 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1534 Requires<[NearData, IsStatic]>;
1535 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1536 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1537 Requires<[NearData, IsStatic]>;
1538 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1539 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1540 Requires<[NearData, IsStatic]>;
1543 // Direct PC relative function call for small code model. 32-bit displacement
1544 // sign extended to 64-bit.
1545 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1546 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1547 def : Pat<(X86call (i64 texternalsym:$dst)),
1548 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1550 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1551 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1552 def : Pat<(X86call (i64 texternalsym:$dst)),
1553 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1556 def : Pat<(X86tcret GR64:$dst, imm:$off),
1557 (TCRETURNri64 GR64:$dst, imm:$off)>;
1559 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1560 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1562 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1563 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1567 // TEST R,R is smaller than CMP R,0
1568 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1569 (TEST64rr GR64:$src1, GR64:$src1)>;
1571 // Conditional moves with folded loads with operands swapped and conditions
1573 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1574 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1575 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1576 (CMOVB64rm GR64:$src2, addr:$src1)>;
1577 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1578 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1579 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1580 (CMOVE64rm GR64:$src2, addr:$src1)>;
1581 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1582 (CMOVA64rm GR64:$src2, addr:$src1)>;
1583 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1584 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1585 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1586 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1587 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1588 (CMOVL64rm GR64:$src2, addr:$src1)>;
1589 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1590 (CMOVG64rm GR64:$src2, addr:$src1)>;
1591 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1592 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1593 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1594 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1595 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1596 (CMOVP64rm GR64:$src2, addr:$src1)>;
1597 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1598 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1599 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1600 (CMOVS64rm GR64:$src2, addr:$src1)>;
1601 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1602 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1603 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1604 (CMOVO64rm GR64:$src2, addr:$src1)>;
1606 // zextload bool -> zextload byte
1607 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1610 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1611 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1612 // partial-register updates.
1613 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1614 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1615 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1616 // For other extloads, use subregs, since the high contents of the register are
1617 // defined after an extload.
1618 def : Pat<(extloadi64i32 addr:$src),
1619 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1622 // anyext. Define these to do an explicit zero-extend to
1623 // avoid partial-register updates.
1624 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1625 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1626 def : Pat<(i64 (anyext GR32:$src)),
1627 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1629 //===----------------------------------------------------------------------===//
1631 //===----------------------------------------------------------------------===//
1633 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1634 // +128 doesn't, so in this special case use a sub instead of an add.
1635 def : Pat<(add GR64:$src1, 128),
1636 (SUB64ri8 GR64:$src1, -128)>;
1637 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1638 (SUB64mi8 addr:$dst, -128)>;
1640 // The same trick applies for 32-bit immediate fields in 64-bit
1642 def : Pat<(add GR64:$src1, 0x0000000080000000),
1643 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1644 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1645 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1647 // r & (2^32-1) ==> movz
1648 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1649 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1650 // r & (2^16-1) ==> movz
1651 def : Pat<(and GR64:$src, 0xffff),
1652 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1653 // r & (2^8-1) ==> movz
1654 def : Pat<(and GR64:$src, 0xff),
1655 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1656 // r & (2^8-1) ==> movz
1657 def : Pat<(and GR32:$src1, 0xff),
1658 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1659 Requires<[In64BitMode]>;
1660 // r & (2^8-1) ==> movz
1661 def : Pat<(and GR16:$src1, 0xff),
1662 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1663 Requires<[In64BitMode]>;
1665 // sext_inreg patterns
1666 def : Pat<(sext_inreg GR64:$src, i32),
1667 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1668 def : Pat<(sext_inreg GR64:$src, i16),
1669 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1670 def : Pat<(sext_inreg GR64:$src, i8),
1671 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1672 def : Pat<(sext_inreg GR32:$src, i8),
1673 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1674 Requires<[In64BitMode]>;
1675 def : Pat<(sext_inreg GR16:$src, i8),
1676 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1677 Requires<[In64BitMode]>;
1680 def : Pat<(i32 (trunc GR64:$src)),
1681 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1682 def : Pat<(i16 (trunc GR64:$src)),
1683 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1684 def : Pat<(i8 (trunc GR64:$src)),
1685 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1686 def : Pat<(i8 (trunc GR32:$src)),
1687 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1688 Requires<[In64BitMode]>;
1689 def : Pat<(i8 (trunc GR16:$src)),
1690 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1691 Requires<[In64BitMode]>;
1693 // h-register tricks.
1694 // For now, be conservative on x86-64 and use an h-register extract only if the
1695 // value is immediately zero-extended or stored, which are somewhat common
1696 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1697 // from being allocated in the same instruction as the h register, as there's
1698 // currently no way to describe this requirement to the register allocator.
1700 // h-register extract and zero-extend.
1701 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1705 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1706 x86_subreg_8bit_hi)),
1708 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1710 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1711 x86_subreg_8bit_hi))>,
1712 Requires<[In64BitMode]>;
1713 def : Pat<(srl_su GR16:$src, (i8 8)),
1716 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1717 x86_subreg_8bit_hi)),
1719 Requires<[In64BitMode]>;
1720 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1722 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1723 x86_subreg_8bit_hi))>,
1724 Requires<[In64BitMode]>;
1725 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1727 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1728 x86_subreg_8bit_hi))>,
1729 Requires<[In64BitMode]>;
1730 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1734 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1735 x86_subreg_8bit_hi)),
1737 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1741 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1742 x86_subreg_8bit_hi)),
1745 // h-register extract and store.
1746 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1749 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1750 x86_subreg_8bit_hi))>;
1751 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1754 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1755 x86_subreg_8bit_hi))>,
1756 Requires<[In64BitMode]>;
1757 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1760 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1761 x86_subreg_8bit_hi))>,
1762 Requires<[In64BitMode]>;
1764 // (shl x, 1) ==> (add x, x)
1765 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1767 // (shl x (and y, 63)) ==> (shl x, y)
1768 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1769 (SHL64rCL GR64:$src1)>;
1770 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1771 (SHL64mCL addr:$dst)>;
1773 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1774 (SHR64rCL GR64:$src1)>;
1775 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1776 (SHR64mCL addr:$dst)>;
1778 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1779 (SAR64rCL GR64:$src1)>;
1780 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1781 (SAR64mCL addr:$dst)>;
1783 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1784 def : Pat<(or (srl GR64:$src1, CL:$amt),
1785 (shl GR64:$src2, (sub 64, CL:$amt))),
1786 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1788 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1789 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1790 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1792 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1793 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1794 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1796 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1797 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1799 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1801 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1802 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1804 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1805 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1806 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1808 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1809 def : Pat<(or (shl GR64:$src1, CL:$amt),
1810 (srl GR64:$src2, (sub 64, CL:$amt))),
1811 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1813 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1814 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1815 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1817 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1818 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1819 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1821 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1822 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1824 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1826 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1827 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1829 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1830 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1831 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1833 // X86 specific add which produces a flag.
1834 def : Pat<(addc GR64:$src1, GR64:$src2),
1835 (ADD64rr GR64:$src1, GR64:$src2)>;
1836 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1837 (ADD64rm GR64:$src1, addr:$src2)>;
1838 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1839 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1840 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1841 (ADD64ri32 GR64:$src1, imm:$src2)>;
1843 def : Pat<(subc GR64:$src1, GR64:$src2),
1844 (SUB64rr GR64:$src1, GR64:$src2)>;
1845 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1846 (SUB64rm GR64:$src1, addr:$src2)>;
1847 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1848 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1849 def : Pat<(subc GR64:$src1, imm:$src2),
1850 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1852 //===----------------------------------------------------------------------===//
1853 // EFLAGS-defining Patterns
1854 //===----------------------------------------------------------------------===//
1856 // Register-Register Addition with EFLAGS result
1857 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1859 (ADD64rr GR64:$src1, GR64:$src2)>;
1861 // Register-Integer Addition with EFLAGS result
1862 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1864 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1865 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1867 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1869 // Register-Memory Addition with EFLAGS result
1870 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1872 (ADD64rm GR64:$src1, addr:$src2)>;
1874 // Memory-Register Addition with EFLAGS result
1875 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1878 (ADD64mr addr:$dst, GR64:$src2)>;
1879 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1882 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1883 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1886 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1888 // Register-Register Subtraction with EFLAGS result
1889 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1891 (SUB64rr GR64:$src1, GR64:$src2)>;
1893 // Register-Memory Subtraction with EFLAGS result
1894 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1896 (SUB64rm GR64:$src1, addr:$src2)>;
1898 // Register-Integer Subtraction with EFLAGS result
1899 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1901 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1902 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1904 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1906 // Memory-Register Subtraction with EFLAGS result
1907 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1910 (SUB64mr addr:$dst, GR64:$src2)>;
1912 // Memory-Integer Subtraction with EFLAGS result
1913 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1916 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1917 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1920 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1922 // Register-Register Signed Integer Multiplication with EFLAGS result
1923 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1925 (IMUL64rr GR64:$src1, GR64:$src2)>;
1927 // Register-Memory Signed Integer Multiplication with EFLAGS result
1928 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1930 (IMUL64rm GR64:$src1, addr:$src2)>;
1932 // Register-Integer Signed Integer Multiplication with EFLAGS result
1933 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1935 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1936 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1938 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1940 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1941 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1943 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1944 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1946 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1948 // INC and DEC with EFLAGS result. Note that these do not set CF.
1949 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1950 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1951 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1953 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1954 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1955 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1956 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1958 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1960 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1961 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1962 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1964 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1965 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1966 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1967 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1969 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1971 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1972 (INC64r GR64:$src)>;
1973 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1975 (INC64m addr:$dst)>;
1976 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1977 (DEC64r GR64:$src)>;
1978 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1980 (DEC64m addr:$dst)>;
1982 //===----------------------------------------------------------------------===//
1983 // X86-64 SSE Instructions
1984 //===----------------------------------------------------------------------===//
1986 // Move instructions...
1988 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1989 "mov{d|q}\t{$src, $dst|$dst, $src}",
1991 (v2i64 (scalar_to_vector GR64:$src)))]>;
1992 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1993 "mov{d|q}\t{$src, $dst|$dst, $src}",
1994 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1997 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1998 "mov{d|q}\t{$src, $dst|$dst, $src}",
1999 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2000 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2001 "movq\t{$src, $dst|$dst, $src}",
2002 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2004 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2005 "mov{d|q}\t{$src, $dst|$dst, $src}",
2006 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2007 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2008 "movq\t{$src, $dst|$dst, $src}",
2009 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2011 //===----------------------------------------------------------------------===//
2012 // X86-64 SSE4.1 Instructions
2013 //===----------------------------------------------------------------------===//
2015 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2016 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2017 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2018 (ins VR128:$src1, i32i8imm:$src2),
2019 !strconcat(OpcodeStr,
2020 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2022 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2023 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2024 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2025 !strconcat(OpcodeStr,
2026 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2027 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2028 addr:$dst)]>, OpSize, REX_W;
2031 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2033 let isTwoAddress = 1 in {
2034 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2035 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2036 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2037 !strconcat(OpcodeStr,
2038 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2040 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2042 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2043 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2044 !strconcat(OpcodeStr,
2045 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2047 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2048 imm:$src3)))]>, OpSize, REX_W;
2052 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2054 // -disable-16bit support.
2055 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2056 (MOV16mi addr:$dst, imm:$src)>;
2057 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2058 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2059 def : Pat<(i64 (sextloadi16 addr:$dst)),
2060 (MOVSX64rm16 addr:$dst)>;
2061 def : Pat<(i64 (zextloadi16 addr:$dst)),
2062 (MOVZX64rm16 addr:$dst)>;
2063 def : Pat<(i64 (extloadi16 addr:$dst)),
2064 (MOVZX64rm16 addr:$dst)>;