1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def GetLo32XForm : SDNodeXForm<imm, [{
69 // Transformation function: get the low 32 bits.
70 return getI32Imm((unsigned)N->getZExtValue());
73 def i64immSExt32 : PatLeaf<(i64 imm), [{
74 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
75 // sign extended field.
76 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
80 def i64immZExt32 : PatLeaf<(i64 imm), [{
81 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
82 // unsignedsign extended field.
83 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
86 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
87 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
88 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
90 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
91 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
92 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
93 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
95 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
96 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
97 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
98 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
100 //===----------------------------------------------------------------------===//
101 // Instruction list...
104 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
105 // a stack adjustment and the codegen must know that they may modify the stack
106 // pointer before prolog-epilog rewriting occurs.
107 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
108 // sub / add which can clobber EFLAGS.
109 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
110 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
112 [(X86callseq_start timm:$amt)]>,
113 Requires<[In64BitMode]>;
114 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
116 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
117 Requires<[In64BitMode]>;
120 // Interrupt Instructions
121 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
123 //===----------------------------------------------------------------------===//
124 // Call Instructions...
127 // All calls clobber the non-callee saved registers. RSP is marked as
128 // a use to prevent stack-pointer assignments that appear immediately
129 // before calls from potentially appearing dead. Uses for argument
130 // registers are added manually.
131 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
132 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
133 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
134 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
135 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
138 // NOTE: this pattern doesn't match "X86call imm", because we do not know
139 // that the offset between an arbitrary immediate and the call will fit in
140 // the 32-bit pcrel field that we have.
141 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
142 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
143 "call{q}\t$dst", []>,
144 Requires<[In64BitMode, NotWin64]>;
145 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
146 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
147 Requires<[NotWin64]>;
148 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
149 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
150 Requires<[NotWin64]>;
152 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
153 "lcall{q}\t{*}$dst", []>;
156 // FIXME: We need to teach codegen about single list of call-clobbered
159 // All calls clobber the non-callee saved registers. RSP is marked as
160 // a use to prevent stack-pointer assignments that appear immediately
161 // before calls from potentially appearing dead. Uses for argument
162 // registers are added manually.
163 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
164 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
165 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
166 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
168 def WINCALL64pcrel32 : I<0xE8, RawFrm,
169 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
172 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
174 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
175 def WINCALL64m : I<0xFF, MRM2m, (outs),
176 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
177 [(X86call (loadi64 addr:$dst))]>,
182 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
183 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
185 "#TC_RETURN $dst $offset",
188 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
189 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
191 "#TC_RETURN $dst $offset",
195 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
196 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst, variable_ops),
197 "jmp{q}\t{*}$dst # TAILCALL",
201 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
202 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
204 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
205 [(brind GR64:$dst)]>;
206 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
207 [(brind (loadi64 addr:$dst))]>;
208 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
209 "ljmp{q}\t{*}$dst", []>;
212 //===----------------------------------------------------------------------===//
213 // EH Pseudo Instructions
215 let isTerminator = 1, isReturn = 1, isBarrier = 1,
216 hasCtrlDep = 1, isCodeGenOnly = 1 in {
217 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
218 "ret\t#eh_return, addr: $addr",
219 [(X86ehret GR64:$addr)]>;
223 //===----------------------------------------------------------------------===//
224 // Miscellaneous Instructions...
227 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
228 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
229 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
230 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
232 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
233 def LEAVE64 : I<0xC9, RawFrm,
234 (outs), (ins), "leave", []>;
235 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
237 def POP64r : I<0x58, AddRegFrm,
238 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
239 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
240 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
242 let mayStore = 1 in {
243 def PUSH64r : I<0x50, AddRegFrm,
244 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
245 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
246 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
250 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
251 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
252 "push{q}\t$imm", []>;
253 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
254 "push{q}\t$imm", []>;
255 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
256 "push{q}\t$imm", []>;
259 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
260 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
261 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
262 def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
264 def LEA64_32r : I<0x8D, MRMSrcMem,
265 (outs GR32:$dst), (ins lea64_32mem:$src),
266 "lea{l}\t{$src|$dst}, {$dst|$src}",
267 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
269 let isReMaterializable = 1 in
270 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
271 "lea{q}\t{$src|$dst}, {$dst|$src}",
272 [(set GR64:$dst, lea64addr:$src)]>;
274 let isTwoAddress = 1 in
275 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
277 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
279 // Bit scan instructions.
280 let Defs = [EFLAGS] in {
281 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
282 "bsf{q}\t{$src, $dst|$dst, $src}",
283 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
284 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
285 "bsf{q}\t{$src, $dst|$dst, $src}",
286 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
287 (implicit EFLAGS)]>, TB;
289 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
290 "bsr{q}\t{$src, $dst|$dst, $src}",
291 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
292 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
293 "bsr{q}\t{$src, $dst|$dst, $src}",
294 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
295 (implicit EFLAGS)]>, TB;
299 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
300 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
301 [(X86rep_movs i64)]>, REP;
302 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
303 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
304 [(X86rep_stos i64)]>, REP;
306 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
308 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
310 // Fast system-call instructions
311 def SYSEXIT64 : RI<0x35, RawFrm,
312 (outs), (ins), "sysexit", []>, TB;
314 //===----------------------------------------------------------------------===//
315 // Move Instructions...
318 let neverHasSideEffects = 1 in
319 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
320 "mov{q}\t{$src, $dst|$dst, $src}", []>;
322 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
323 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
324 "movabs{q}\t{$src, $dst|$dst, $src}",
325 [(set GR64:$dst, imm:$src)]>;
326 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
327 "mov{q}\t{$src, $dst|$dst, $src}",
328 [(set GR64:$dst, i64immSExt32:$src)]>;
331 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
332 "mov{q}\t{$src, $dst|$dst, $src}", []>;
334 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
335 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
336 "mov{q}\t{$src, $dst|$dst, $src}",
337 [(set GR64:$dst, (load addr:$src))]>;
339 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
340 "mov{q}\t{$src, $dst|$dst, $src}",
341 [(store GR64:$src, addr:$dst)]>;
342 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
343 "mov{q}\t{$src, $dst|$dst, $src}",
344 [(store i64immSExt32:$src, addr:$dst)]>;
346 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
347 "mov{q}\t{$src, %rax|%rax, $src}", []>;
348 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
349 "mov{q}\t{$src, %rax|%rax, $src}", []>;
350 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
351 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
352 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
353 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
355 // Moves to and from segment registers
356 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
357 "mov{q}\t{$src, $dst|$dst, $src}", []>;
358 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
359 "mov{q}\t{$src, $dst|$dst, $src}", []>;
360 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
361 "mov{q}\t{$src, $dst|$dst, $src}", []>;
362 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
363 "mov{q}\t{$src, $dst|$dst, $src}", []>;
365 // Moves to and from debug registers
366 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
367 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
368 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
369 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
371 // Moves to and from control registers
372 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
373 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
374 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
375 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
377 // Sign/Zero extenders
379 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
380 // operand, which makes it a rare instruction with an 8-bit register
381 // operand that can never access an h register. If support for h registers
382 // were generalized, this would require a special register class.
383 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
384 "movs{bq|x}\t{$src, $dst|$dst, $src}",
385 [(set GR64:$dst, (sext GR8:$src))]>, TB;
386 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
387 "movs{bq|x}\t{$src, $dst|$dst, $src}",
388 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
389 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
390 "movs{wq|x}\t{$src, $dst|$dst, $src}",
391 [(set GR64:$dst, (sext GR16:$src))]>, TB;
392 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
393 "movs{wq|x}\t{$src, $dst|$dst, $src}",
394 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
395 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
396 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
397 [(set GR64:$dst, (sext GR32:$src))]>;
398 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
399 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
400 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
402 // movzbq and movzwq encodings for the disassembler
403 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
404 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
405 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
406 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
407 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
408 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
409 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
410 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
412 // Use movzbl instead of movzbq when the destination is a register; it's
413 // equivalent due to implicit zero-extending, and it has a smaller encoding.
414 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
415 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
416 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
417 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
418 // Use movzwl instead of movzwq when the destination is a register; it's
419 // equivalent due to implicit zero-extending, and it has a smaller encoding.
420 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
421 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
422 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
423 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
425 // There's no movzlq instruction, but movl can be used for this purpose, using
426 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
427 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
428 // zero-extension, however this isn't possible when the 32-bit value is
429 // defined by a truncate or is copied from something where the high bits aren't
430 // necessarily all zero. In such cases, we fall back to these explicit zext
432 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
433 "", [(set GR64:$dst, (zext GR32:$src))]>;
434 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
435 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
437 // Any instruction that defines a 32-bit result leaves the high half of the
438 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
439 // be copying from a truncate. And x86's cmov doesn't do anything if the
440 // condition is false. But any other 32-bit operation will zero-extend
442 def def32 : PatLeaf<(i32 GR32:$src), [{
443 return N->getOpcode() != ISD::TRUNCATE &&
444 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
445 N->getOpcode() != ISD::CopyFromReg &&
446 N->getOpcode() != X86ISD::CMOV;
449 // In the case of a 32-bit def that is known to implicitly zero-extend,
450 // we can use a SUBREG_TO_REG.
451 def : Pat<(i64 (zext def32:$src)),
452 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
454 let neverHasSideEffects = 1 in {
455 let Defs = [RAX], Uses = [EAX] in
456 def CDQE : RI<0x98, RawFrm, (outs), (ins),
457 "{cltq|cdqe}", []>; // RAX = signext(EAX)
459 let Defs = [RAX,RDX], Uses = [RAX] in
460 def CQO : RI<0x99, RawFrm, (outs), (ins),
461 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
464 //===----------------------------------------------------------------------===//
465 // Arithmetic Instructions...
468 let Defs = [EFLAGS] in {
470 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
471 "add{q}\t{$src, %rax|%rax, $src}", []>;
473 let isTwoAddress = 1 in {
474 let isConvertibleToThreeAddress = 1 in {
475 let isCommutable = 1 in
476 // Register-Register Addition
477 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
478 (ins GR64:$src1, GR64:$src2),
479 "add{q}\t{$src2, $dst|$dst, $src2}",
480 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
483 // Register-Integer Addition
484 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
485 (ins GR64:$src1, i64i8imm:$src2),
486 "add{q}\t{$src2, $dst|$dst, $src2}",
487 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
489 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
490 (ins GR64:$src1, i64i32imm:$src2),
491 "add{q}\t{$src2, $dst|$dst, $src2}",
492 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
494 } // isConvertibleToThreeAddress
496 // Register-Memory Addition
497 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
498 (ins GR64:$src1, i64mem:$src2),
499 "add{q}\t{$src2, $dst|$dst, $src2}",
500 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
503 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
504 // differently encoded.
505 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
506 (ins GR64:$src1, GR64:$src2),
507 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
511 // Memory-Register Addition
512 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
513 "add{q}\t{$src2, $dst|$dst, $src2}",
514 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
516 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
517 "add{q}\t{$src2, $dst|$dst, $src2}",
518 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
520 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
521 "add{q}\t{$src2, $dst|$dst, $src2}",
522 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
525 let Uses = [EFLAGS] in {
527 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
528 "adc{q}\t{$src, %rax|%rax, $src}", []>;
530 let isTwoAddress = 1 in {
531 let isCommutable = 1 in
532 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
533 (ins GR64:$src1, GR64:$src2),
534 "adc{q}\t{$src2, $dst|$dst, $src2}",
535 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
537 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
538 (ins GR64:$src1, GR64:$src2),
539 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
541 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
542 (ins GR64:$src1, i64mem:$src2),
543 "adc{q}\t{$src2, $dst|$dst, $src2}",
544 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
546 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
547 (ins GR64:$src1, i64i8imm:$src2),
548 "adc{q}\t{$src2, $dst|$dst, $src2}",
549 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
550 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
551 (ins GR64:$src1, i64i32imm:$src2),
552 "adc{q}\t{$src2, $dst|$dst, $src2}",
553 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
556 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
557 "adc{q}\t{$src2, $dst|$dst, $src2}",
558 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
559 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
560 "adc{q}\t{$src2, $dst|$dst, $src2}",
561 [(store (adde (load addr:$dst), i64immSExt8:$src2),
563 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
564 "adc{q}\t{$src2, $dst|$dst, $src2}",
565 [(store (adde (load addr:$dst), i64immSExt32:$src2),
569 let isTwoAddress = 1 in {
570 // Register-Register Subtraction
571 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
572 (ins GR64:$src1, GR64:$src2),
573 "sub{q}\t{$src2, $dst|$dst, $src2}",
574 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
577 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
578 (ins GR64:$src1, GR64:$src2),
579 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
581 // Register-Memory Subtraction
582 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
583 (ins GR64:$src1, i64mem:$src2),
584 "sub{q}\t{$src2, $dst|$dst, $src2}",
585 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
588 // Register-Integer Subtraction
589 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
590 (ins GR64:$src1, i64i8imm:$src2),
591 "sub{q}\t{$src2, $dst|$dst, $src2}",
592 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
594 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
595 (ins GR64:$src1, i64i32imm:$src2),
596 "sub{q}\t{$src2, $dst|$dst, $src2}",
597 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
601 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
602 "sub{q}\t{$src, %rax|%rax, $src}", []>;
604 // Memory-Register Subtraction
605 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
606 "sub{q}\t{$src2, $dst|$dst, $src2}",
607 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
610 // Memory-Integer Subtraction
611 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
612 "sub{q}\t{$src2, $dst|$dst, $src2}",
613 [(store (sub (load addr:$dst), i64immSExt8:$src2),
616 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
617 "sub{q}\t{$src2, $dst|$dst, $src2}",
618 [(store (sub (load addr:$dst), i64immSExt32:$src2),
622 let Uses = [EFLAGS] in {
623 let isTwoAddress = 1 in {
624 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
625 (ins GR64:$src1, GR64:$src2),
626 "sbb{q}\t{$src2, $dst|$dst, $src2}",
627 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
629 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
630 (ins GR64:$src1, GR64:$src2),
631 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
633 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
634 (ins GR64:$src1, i64mem:$src2),
635 "sbb{q}\t{$src2, $dst|$dst, $src2}",
636 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
638 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
639 (ins GR64:$src1, i64i8imm:$src2),
640 "sbb{q}\t{$src2, $dst|$dst, $src2}",
641 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
642 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
643 (ins GR64:$src1, i64i32imm:$src2),
644 "sbb{q}\t{$src2, $dst|$dst, $src2}",
645 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
648 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
649 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
651 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
652 "sbb{q}\t{$src2, $dst|$dst, $src2}",
653 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
654 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
655 "sbb{q}\t{$src2, $dst|$dst, $src2}",
656 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
657 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
658 "sbb{q}\t{$src2, $dst|$dst, $src2}",
659 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
663 // Unsigned multiplication
664 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
665 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
666 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
668 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
669 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
671 // Signed multiplication
672 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
673 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
675 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
676 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
679 let Defs = [EFLAGS] in {
680 let isTwoAddress = 1 in {
681 let isCommutable = 1 in
682 // Register-Register Signed Integer Multiplication
683 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
684 (ins GR64:$src1, GR64:$src2),
685 "imul{q}\t{$src2, $dst|$dst, $src2}",
686 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
687 (implicit EFLAGS)]>, TB;
689 // Register-Memory Signed Integer Multiplication
690 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
691 (ins GR64:$src1, i64mem:$src2),
692 "imul{q}\t{$src2, $dst|$dst, $src2}",
693 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
694 (implicit EFLAGS)]>, TB;
697 // Suprisingly enough, these are not two address instructions!
699 // Register-Integer Signed Integer Multiplication
700 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
701 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
702 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
703 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
705 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
706 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
707 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
708 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
711 // Memory-Integer Signed Integer Multiplication
712 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
713 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
714 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 [(set GR64:$dst, (mul (load addr:$src1),
718 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
719 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
720 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
721 [(set GR64:$dst, (mul (load addr:$src1),
722 i64immSExt32:$src2)),
726 // Unsigned division / remainder
727 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
728 // RDX:RAX/r64 = RAX,RDX
729 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
731 // Signed division / remainder
732 // RDX:RAX/r64 = RAX,RDX
733 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
734 "idiv{q}\t$src", []>;
736 // RDX:RAX/[mem64] = RAX,RDX
737 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
739 // RDX:RAX/[mem64] = RAX,RDX
740 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
741 "idiv{q}\t$src", []>;
745 // Unary instructions
746 let Defs = [EFLAGS], CodeSize = 2 in {
747 let isTwoAddress = 1 in
748 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
749 [(set GR64:$dst, (ineg GR64:$src)),
751 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
752 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
755 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
756 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
757 [(set GR64:$dst, (add GR64:$src, 1)),
759 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
760 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
763 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
764 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
765 [(set GR64:$dst, (add GR64:$src, -1)),
767 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
768 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
771 // In 64-bit mode, single byte INC and DEC cannot be encoded.
772 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
773 // Can transform into LEA.
774 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
776 [(set GR16:$dst, (add GR16:$src, 1)),
778 OpSize, Requires<[In64BitMode]>;
779 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
781 [(set GR32:$dst, (add GR32:$src, 1)),
783 Requires<[In64BitMode]>;
784 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
786 [(set GR16:$dst, (add GR16:$src, -1)),
788 OpSize, Requires<[In64BitMode]>;
789 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
791 [(set GR32:$dst, (add GR32:$src, -1)),
793 Requires<[In64BitMode]>;
794 } // isConvertibleToThreeAddress
796 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
797 // how to unfold them.
798 let isTwoAddress = 0, CodeSize = 2 in {
799 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
800 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
802 OpSize, Requires<[In64BitMode]>;
803 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
804 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
806 Requires<[In64BitMode]>;
807 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
808 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
810 OpSize, Requires<[In64BitMode]>;
811 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
812 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
814 Requires<[In64BitMode]>;
816 } // Defs = [EFLAGS], CodeSize
819 let Defs = [EFLAGS] in {
820 // Shift instructions
821 let isTwoAddress = 1 in {
823 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
824 "shl{q}\t{%cl, $dst|$dst, %CL}",
825 [(set GR64:$dst, (shl GR64:$src, CL))]>;
826 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
827 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
828 (ins GR64:$src1, i8imm:$src2),
829 "shl{q}\t{$src2, $dst|$dst, $src2}",
830 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
831 // NOTE: We don't include patterns for shifts of a register by one, because
832 // 'add reg,reg' is cheaper.
833 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
838 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
839 "shl{q}\t{%cl, $dst|$dst, %CL}",
840 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
841 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
842 "shl{q}\t{$src, $dst|$dst, $src}",
843 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
844 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
846 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
848 let isTwoAddress = 1 in {
850 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
851 "shr{q}\t{%cl, $dst|$dst, %CL}",
852 [(set GR64:$dst, (srl GR64:$src, CL))]>;
853 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
854 "shr{q}\t{$src2, $dst|$dst, $src2}",
855 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
856 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
858 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
862 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
863 "shr{q}\t{%cl, $dst|$dst, %CL}",
864 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
865 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
866 "shr{q}\t{$src, $dst|$dst, $src}",
867 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
868 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
870 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
872 let isTwoAddress = 1 in {
874 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
875 "sar{q}\t{%cl, $dst|$dst, %CL}",
876 [(set GR64:$dst, (sra GR64:$src, CL))]>;
877 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
878 (ins GR64:$src1, i8imm:$src2),
879 "sar{q}\t{$src2, $dst|$dst, $src2}",
880 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
881 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
883 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
887 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
888 "sar{q}\t{%cl, $dst|$dst, %CL}",
889 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
890 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
891 "sar{q}\t{$src, $dst|$dst, $src}",
892 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
893 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
895 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
897 // Rotate instructions
899 let isTwoAddress = 1 in {
900 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
901 "rcl{q}\t{1, $dst|$dst, 1}", []>;
902 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
903 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
905 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
906 "rcr{q}\t{1, $dst|$dst, 1}", []>;
907 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
908 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
911 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
912 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
913 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
914 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
918 let isTwoAddress = 0 in {
919 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
920 "rcl{q}\t{1, $dst|$dst, 1}", []>;
921 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
922 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
923 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
924 "rcr{q}\t{1, $dst|$dst, 1}", []>;
925 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
926 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
929 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
930 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
931 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
932 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
936 let isTwoAddress = 1 in {
938 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
939 "rol{q}\t{%cl, $dst|$dst, %CL}",
940 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
941 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
942 (ins GR64:$src1, i8imm:$src2),
943 "rol{q}\t{$src2, $dst|$dst, $src2}",
944 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
945 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
947 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
951 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
952 "rol{q}\t{%cl, $dst|$dst, %CL}",
953 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
954 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
955 "rol{q}\t{$src, $dst|$dst, $src}",
956 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
957 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
959 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
961 let isTwoAddress = 1 in {
963 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
964 "ror{q}\t{%cl, $dst|$dst, %CL}",
965 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
966 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
967 (ins GR64:$src1, i8imm:$src2),
968 "ror{q}\t{$src2, $dst|$dst, $src2}",
969 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
970 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
972 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
976 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
977 "ror{q}\t{%cl, $dst|$dst, %CL}",
978 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
979 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
980 "ror{q}\t{$src, $dst|$dst, $src}",
981 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
982 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
984 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
986 // Double shift instructions (generalizations of rotate)
987 let isTwoAddress = 1 in {
989 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
990 (ins GR64:$src1, GR64:$src2),
991 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
992 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
994 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
995 (ins GR64:$src1, GR64:$src2),
996 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
997 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
1001 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
1002 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
1004 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1005 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1006 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1009 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1011 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1012 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1013 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1019 let Uses = [CL] in {
1020 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1021 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1022 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1024 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1025 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1026 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1029 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1030 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1031 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1032 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1033 (i8 imm:$src3)), addr:$dst)]>,
1035 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1036 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1037 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1038 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1039 (i8 imm:$src3)), addr:$dst)]>,
1041 } // Defs = [EFLAGS]
1043 //===----------------------------------------------------------------------===//
1044 // Logical Instructions...
1047 let isTwoAddress = 1 , AddedComplexity = 15 in
1048 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1049 [(set GR64:$dst, (not GR64:$src))]>;
1050 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1051 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1053 let Defs = [EFLAGS] in {
1054 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
1055 "and{q}\t{$src, %rax|%rax, $src}", []>;
1057 let isTwoAddress = 1 in {
1058 let isCommutable = 1 in
1059 def AND64rr : RI<0x21, MRMDestReg,
1060 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1061 "and{q}\t{$src2, $dst|$dst, $src2}",
1062 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
1063 (implicit EFLAGS)]>;
1064 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1065 (ins GR64:$src1, GR64:$src2),
1066 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
1067 def AND64rm : RI<0x23, MRMSrcMem,
1068 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1069 "and{q}\t{$src2, $dst|$dst, $src2}",
1070 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
1071 (implicit EFLAGS)]>;
1072 def AND64ri8 : RIi8<0x83, MRM4r,
1073 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1074 "and{q}\t{$src2, $dst|$dst, $src2}",
1075 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
1076 (implicit EFLAGS)]>;
1077 def AND64ri32 : RIi32<0x81, MRM4r,
1078 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1079 "and{q}\t{$src2, $dst|$dst, $src2}",
1080 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
1081 (implicit EFLAGS)]>;
1084 def AND64mr : RI<0x21, MRMDestMem,
1085 (outs), (ins i64mem:$dst, GR64:$src),
1086 "and{q}\t{$src, $dst|$dst, $src}",
1087 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
1088 (implicit EFLAGS)]>;
1089 def AND64mi8 : RIi8<0x83, MRM4m,
1090 (outs), (ins i64mem:$dst, i64i8imm :$src),
1091 "and{q}\t{$src, $dst|$dst, $src}",
1092 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1093 (implicit EFLAGS)]>;
1094 def AND64mi32 : RIi32<0x81, MRM4m,
1095 (outs), (ins i64mem:$dst, i64i32imm:$src),
1096 "and{q}\t{$src, $dst|$dst, $src}",
1097 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1098 (implicit EFLAGS)]>;
1100 let isTwoAddress = 1 in {
1101 let isCommutable = 1 in
1102 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1103 (ins GR64:$src1, GR64:$src2),
1104 "or{q}\t{$src2, $dst|$dst, $src2}",
1105 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
1106 (implicit EFLAGS)]>;
1107 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1108 (ins GR64:$src1, GR64:$src2),
1109 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1110 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1111 (ins GR64:$src1, i64mem:$src2),
1112 "or{q}\t{$src2, $dst|$dst, $src2}",
1113 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
1114 (implicit EFLAGS)]>;
1115 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1116 (ins GR64:$src1, i64i8imm:$src2),
1117 "or{q}\t{$src2, $dst|$dst, $src2}",
1118 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
1119 (implicit EFLAGS)]>;
1120 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1121 (ins GR64:$src1, i64i32imm:$src2),
1122 "or{q}\t{$src2, $dst|$dst, $src2}",
1123 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
1124 (implicit EFLAGS)]>;
1127 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1128 "or{q}\t{$src, $dst|$dst, $src}",
1129 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1130 (implicit EFLAGS)]>;
1131 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1132 "or{q}\t{$src, $dst|$dst, $src}",
1133 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1134 (implicit EFLAGS)]>;
1135 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1136 "or{q}\t{$src, $dst|$dst, $src}",
1137 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1138 (implicit EFLAGS)]>;
1140 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1141 "or{q}\t{$src, %rax|%rax, $src}", []>;
1143 let isTwoAddress = 1 in {
1144 let isCommutable = 1 in
1145 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1146 (ins GR64:$src1, GR64:$src2),
1147 "xor{q}\t{$src2, $dst|$dst, $src2}",
1148 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1149 (implicit EFLAGS)]>;
1150 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1151 (ins GR64:$src1, GR64:$src2),
1152 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1153 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1154 (ins GR64:$src1, i64mem:$src2),
1155 "xor{q}\t{$src2, $dst|$dst, $src2}",
1156 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1157 (implicit EFLAGS)]>;
1158 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1159 (ins GR64:$src1, i64i8imm:$src2),
1160 "xor{q}\t{$src2, $dst|$dst, $src2}",
1161 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1162 (implicit EFLAGS)]>;
1163 def XOR64ri32 : RIi32<0x81, MRM6r,
1164 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1165 "xor{q}\t{$src2, $dst|$dst, $src2}",
1166 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1167 (implicit EFLAGS)]>;
1170 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1171 "xor{q}\t{$src, $dst|$dst, $src}",
1172 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1173 (implicit EFLAGS)]>;
1174 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1175 "xor{q}\t{$src, $dst|$dst, $src}",
1176 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1177 (implicit EFLAGS)]>;
1178 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1179 "xor{q}\t{$src, $dst|$dst, $src}",
1180 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1181 (implicit EFLAGS)]>;
1183 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1184 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1186 } // Defs = [EFLAGS]
1188 //===----------------------------------------------------------------------===//
1189 // Comparison Instructions...
1192 // Integer comparison
1193 let Defs = [EFLAGS] in {
1194 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1195 "test{q}\t{$src, %rax|%rax, $src}", []>;
1196 let isCommutable = 1 in
1197 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1198 "test{q}\t{$src2, $src1|$src1, $src2}",
1199 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1200 (implicit EFLAGS)]>;
1201 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1202 "test{q}\t{$src2, $src1|$src1, $src2}",
1203 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1204 (implicit EFLAGS)]>;
1205 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1206 (ins GR64:$src1, i64i32imm:$src2),
1207 "test{q}\t{$src2, $src1|$src1, $src2}",
1208 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1209 (implicit EFLAGS)]>;
1210 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1211 (ins i64mem:$src1, i64i32imm:$src2),
1212 "test{q}\t{$src2, $src1|$src1, $src2}",
1213 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1214 (implicit EFLAGS)]>;
1217 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1218 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1219 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1220 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1221 [(X86cmp GR64:$src1, GR64:$src2),
1222 (implicit EFLAGS)]>;
1223 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1224 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1225 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1226 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1227 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1228 (implicit EFLAGS)]>;
1229 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1230 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1231 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1232 (implicit EFLAGS)]>;
1233 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1234 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1235 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1236 (implicit EFLAGS)]>;
1237 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1238 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1239 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1240 (implicit EFLAGS)]>;
1241 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1242 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1243 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1244 (implicit EFLAGS)]>;
1245 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1246 (ins i64mem:$src1, i64i32imm:$src2),
1247 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1248 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1249 (implicit EFLAGS)]>;
1250 } // Defs = [EFLAGS]
1253 // TODO: BTC, BTR, and BTS
1254 let Defs = [EFLAGS] in {
1255 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1256 "bt{q}\t{$src2, $src1|$src1, $src2}",
1257 [(X86bt GR64:$src1, GR64:$src2),
1258 (implicit EFLAGS)]>, TB;
1260 // Unlike with the register+register form, the memory+register form of the
1261 // bt instruction does not ignore the high bits of the index. From ISel's
1262 // perspective, this is pretty bizarre. Disable these instructions for now.
1263 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1264 "bt{q}\t{$src2, $src1|$src1, $src2}",
1265 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1266 // (implicit EFLAGS)]
1270 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1271 "bt{q}\t{$src2, $src1|$src1, $src2}",
1272 [(X86bt GR64:$src1, i64immSExt8:$src2),
1273 (implicit EFLAGS)]>, TB;
1274 // Note that these instructions don't need FastBTMem because that
1275 // only applies when the other operand is in a register. When it's
1276 // an immediate, bt is still fast.
1277 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1278 "bt{q}\t{$src2, $src1|$src1, $src2}",
1279 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1280 (implicit EFLAGS)]>, TB;
1282 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1283 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1284 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1285 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1286 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1287 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1288 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1289 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1291 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1292 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1293 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1294 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1295 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1296 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1297 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1298 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1300 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1301 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1302 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1303 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1304 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1305 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1306 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1307 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1308 } // Defs = [EFLAGS]
1310 // Conditional moves
1311 let Uses = [EFLAGS], isTwoAddress = 1 in {
1312 let isCommutable = 1 in {
1313 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1314 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1315 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1316 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1317 X86_COND_B, EFLAGS))]>, TB;
1318 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1319 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1320 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1321 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1322 X86_COND_AE, EFLAGS))]>, TB;
1323 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1324 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1325 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1327 X86_COND_E, EFLAGS))]>, TB;
1328 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1329 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1330 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1332 X86_COND_NE, EFLAGS))]>, TB;
1333 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1334 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1335 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1336 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1337 X86_COND_BE, EFLAGS))]>, TB;
1338 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1339 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1340 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1342 X86_COND_A, EFLAGS))]>, TB;
1343 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1344 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1345 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1347 X86_COND_L, EFLAGS))]>, TB;
1348 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1349 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1350 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1351 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1352 X86_COND_GE, EFLAGS))]>, TB;
1353 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1354 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1355 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1356 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1357 X86_COND_LE, EFLAGS))]>, TB;
1358 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1359 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1360 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1362 X86_COND_G, EFLAGS))]>, TB;
1363 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1364 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1365 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1366 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1367 X86_COND_S, EFLAGS))]>, TB;
1368 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1369 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1370 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1371 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1372 X86_COND_NS, EFLAGS))]>, TB;
1373 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1374 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1375 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1377 X86_COND_P, EFLAGS))]>, TB;
1378 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1379 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1380 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1381 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1382 X86_COND_NP, EFLAGS))]>, TB;
1383 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1384 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1385 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1386 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1387 X86_COND_O, EFLAGS))]>, TB;
1388 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1389 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1390 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1392 X86_COND_NO, EFLAGS))]>, TB;
1393 } // isCommutable = 1
1395 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1396 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1397 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1398 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1399 X86_COND_B, EFLAGS))]>, TB;
1400 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1401 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1402 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1404 X86_COND_AE, EFLAGS))]>, TB;
1405 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1406 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1407 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1408 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1409 X86_COND_E, EFLAGS))]>, TB;
1410 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1411 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1412 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1413 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1414 X86_COND_NE, EFLAGS))]>, TB;
1415 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1416 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1417 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1418 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1419 X86_COND_BE, EFLAGS))]>, TB;
1420 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1421 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1422 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1424 X86_COND_A, EFLAGS))]>, TB;
1425 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1426 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1427 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1428 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1429 X86_COND_L, EFLAGS))]>, TB;
1430 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1431 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1432 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1434 X86_COND_GE, EFLAGS))]>, TB;
1435 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1436 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1437 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1438 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1439 X86_COND_LE, EFLAGS))]>, TB;
1440 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1441 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1442 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1443 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1444 X86_COND_G, EFLAGS))]>, TB;
1445 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1446 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1447 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1449 X86_COND_S, EFLAGS))]>, TB;
1450 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1451 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1452 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1454 X86_COND_NS, EFLAGS))]>, TB;
1455 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1456 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1457 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1458 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1459 X86_COND_P, EFLAGS))]>, TB;
1460 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1461 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1462 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1464 X86_COND_NP, EFLAGS))]>, TB;
1465 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1466 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1467 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1469 X86_COND_O, EFLAGS))]>, TB;
1470 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1471 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1472 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1473 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1474 X86_COND_NO, EFLAGS))]>, TB;
1477 // Use sbb to materialize carry flag into a GPR.
1478 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1479 // However, Pat<> can't replicate the destination reg into the inputs of the
1481 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1483 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1484 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1485 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1487 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1490 //===----------------------------------------------------------------------===//
1491 // Conversion Instructions...
1494 // f64 -> signed i64
1495 def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1496 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1497 def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1498 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1499 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1500 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1502 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1503 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1505 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1506 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1507 (load addr:$src)))]>;
1508 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1509 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1510 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1511 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1512 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1513 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1514 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1515 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1517 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1518 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1520 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1522 (int_x86_sse2_cvttsd2si64
1523 (load addr:$src)))]>;
1525 // Signed i64 -> f64
1526 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1527 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1528 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1529 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1530 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1531 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1533 let isTwoAddress = 1 in {
1534 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1535 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1536 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1538 (int_x86_sse2_cvtsi642sd VR128:$src1,
1540 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1541 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1542 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1544 (int_x86_sse2_cvtsi642sd VR128:$src1,
1545 (loadi64 addr:$src2)))]>;
1548 // Signed i64 -> f32
1549 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1550 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1551 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1552 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1553 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1554 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1556 let isTwoAddress = 1 in {
1557 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1558 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1559 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1561 (int_x86_sse_cvtsi642ss VR128:$src1,
1563 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1565 (ins VR128:$src1, i64mem:$src2),
1566 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1568 (int_x86_sse_cvtsi642ss VR128:$src1,
1569 (loadi64 addr:$src2)))]>;
1572 // f32 -> signed i64
1573 def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1574 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1575 def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1576 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1577 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1578 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1580 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1581 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1582 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1583 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1584 (load addr:$src)))]>;
1585 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1586 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1587 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1588 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1589 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1590 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1591 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1592 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1594 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1595 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1597 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1599 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1601 // Descriptor-table support instructions
1603 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1605 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1606 "sldt{q}\t$dst", []>, TB;
1607 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1608 "sldt{q}\t$dst", []>, TB;
1610 //===----------------------------------------------------------------------===//
1611 // Alias Instructions
1612 //===----------------------------------------------------------------------===//
1614 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1615 // smaller encoding, but doing so at isel time interferes with rematerialization
1616 // in the current register allocator. For now, this is rewritten when the
1617 // instruction is lowered to an MCInst.
1618 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1619 // when we have a better way to specify isel priority.
1620 let Defs = [EFLAGS],
1621 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1622 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1623 [(set GR64:$dst, 0)]>;
1625 // Materialize i64 constant where top 32-bits are zero. This could theoretically
1626 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1627 // that would make it more difficult to rematerialize.
1628 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1629 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1630 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1632 //===----------------------------------------------------------------------===//
1633 // Thread Local Storage Instructions
1634 //===----------------------------------------------------------------------===//
1636 // All calls clobber the non-callee saved registers. RSP is marked as
1637 // a use to prevent stack-pointer assignments that appear immediately
1638 // before calls from potentially appearing dead.
1639 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1640 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1641 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1642 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1643 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1645 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1647 "leaq\t$sym(%rip), %rdi; "
1650 "call\t__tls_get_addr@PLT",
1651 [(X86tlsaddr tls64addr:$sym)]>,
1652 Requires<[In64BitMode]>;
1654 let AddedComplexity = 5, isCodeGenOnly = 1 in
1655 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1656 "movq\t%gs:$src, $dst",
1657 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1659 let AddedComplexity = 5, isCodeGenOnly = 1 in
1660 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1661 "movq\t%fs:$src, $dst",
1662 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1664 //===----------------------------------------------------------------------===//
1665 // Atomic Instructions
1666 //===----------------------------------------------------------------------===//
1668 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1669 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1671 "cmpxchgq\t$swap,$ptr",
1672 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1675 let Constraints = "$val = $dst" in {
1676 let Defs = [EFLAGS] in
1677 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1680 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1683 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1684 (ins GR64:$val,i64mem:$ptr),
1685 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1686 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1688 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1689 "xchg{q}\t{$val, $src|$src, $val}", []>;
1692 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1693 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1694 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1695 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1697 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1698 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1699 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1700 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1702 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1703 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1704 "cmpxchg16b\t$dst", []>, TB;
1706 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1707 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1709 // Optimized codegen when the non-memory output is not used.
1710 let Defs = [EFLAGS] in {
1711 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1712 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1714 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1715 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1716 (ins i64mem:$dst, i64i8imm :$src2),
1718 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1719 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1720 (ins i64mem:$dst, i64i32imm :$src2),
1722 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1723 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1725 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1726 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1727 (ins i64mem:$dst, i64i8imm :$src2),
1729 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1730 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1731 (ins i64mem:$dst, i64i32imm:$src2),
1733 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1734 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1736 "inc{q}\t$dst", []>, LOCK;
1737 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1739 "dec{q}\t$dst", []>, LOCK;
1741 // Atomic exchange, and, or, xor
1742 let Constraints = "$val = $dst", Defs = [EFLAGS],
1743 usesCustomInserter = 1 in {
1744 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1745 "#ATOMAND64 PSEUDO!",
1746 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1747 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1748 "#ATOMOR64 PSEUDO!",
1749 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1750 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1751 "#ATOMXOR64 PSEUDO!",
1752 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1753 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1754 "#ATOMNAND64 PSEUDO!",
1755 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1756 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1757 "#ATOMMIN64 PSEUDO!",
1758 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1759 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1760 "#ATOMMAX64 PSEUDO!",
1761 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1762 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1763 "#ATOMUMIN64 PSEUDO!",
1764 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1765 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1766 "#ATOMUMAX64 PSEUDO!",
1767 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1770 // Segmentation support instructions
1772 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1773 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1774 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1775 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1776 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1778 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1779 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1780 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1781 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1783 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1785 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1786 "push{q}\t%fs", []>, TB;
1787 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1788 "push{q}\t%gs", []>, TB;
1790 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1791 "pop{q}\t%fs", []>, TB;
1792 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1793 "pop{q}\t%gs", []>, TB;
1795 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1796 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1797 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1798 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1799 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1800 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1802 // Specialized register support
1804 // no m form encodable; use SMSW16m
1805 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1806 "smsw{q}\t$dst", []>, TB;
1808 // String manipulation instructions
1810 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1812 //===----------------------------------------------------------------------===//
1813 // Non-Instruction Patterns
1814 //===----------------------------------------------------------------------===//
1816 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1817 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1818 // 'movabs' predicate should handle this sort of thing.
1819 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1820 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1821 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1822 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1823 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1824 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1825 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1826 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1827 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1828 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1830 // In static codegen with small code model, we can get the address of a label
1831 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1832 // the MOV64ri64i32 should accept these.
1833 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1834 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1835 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1836 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1837 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1838 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1839 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1840 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1841 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1842 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1844 // In kernel code model, we can get the address of a label
1845 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1846 // the MOV64ri32 should accept these.
1847 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1848 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1849 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1850 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1851 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1852 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1853 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1854 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1855 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1856 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1858 // If we have small model and -static mode, it is safe to store global addresses
1859 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1860 // for MOV64mi32 should handle this sort of thing.
1861 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1862 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1863 Requires<[NearData, IsStatic]>;
1864 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1865 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1866 Requires<[NearData, IsStatic]>;
1867 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1868 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1869 Requires<[NearData, IsStatic]>;
1870 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1871 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1872 Requires<[NearData, IsStatic]>;
1873 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1874 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1875 Requires<[NearData, IsStatic]>;
1878 // Direct PC relative function call for small code model. 32-bit displacement
1879 // sign extended to 64-bit.
1880 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1881 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1882 def : Pat<(X86call (i64 texternalsym:$dst)),
1883 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1885 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1886 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1887 def : Pat<(X86call (i64 texternalsym:$dst)),
1888 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1891 def : Pat<(X86tcret GR64:$dst, imm:$off),
1892 (TCRETURNri64 GR64:$dst, imm:$off)>;
1894 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1895 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>;
1897 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1898 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1902 // TEST R,R is smaller than CMP R,0
1903 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1904 (TEST64rr GR64:$src1, GR64:$src1)>;
1906 // Conditional moves with folded loads with operands swapped and conditions
1908 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1909 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1910 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1911 (CMOVB64rm GR64:$src2, addr:$src1)>;
1912 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1913 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1914 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1915 (CMOVE64rm GR64:$src2, addr:$src1)>;
1916 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1917 (CMOVA64rm GR64:$src2, addr:$src1)>;
1918 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1919 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1920 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1921 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1922 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1923 (CMOVL64rm GR64:$src2, addr:$src1)>;
1924 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1925 (CMOVG64rm GR64:$src2, addr:$src1)>;
1926 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1927 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1928 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1929 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1930 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1931 (CMOVP64rm GR64:$src2, addr:$src1)>;
1932 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1933 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1934 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1935 (CMOVS64rm GR64:$src2, addr:$src1)>;
1936 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1937 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1938 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1939 (CMOVO64rm GR64:$src2, addr:$src1)>;
1941 // zextload bool -> zextload byte
1942 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1945 // When extloading from 16-bit and smaller memory locations into 64-bit
1946 // registers, use zero-extending loads so that the entire 64-bit register is
1947 // defined, avoiding partial-register updates.
1948 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1949 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1950 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1951 // For other extloads, use subregs, since the high contents of the register are
1952 // defined after an extload.
1953 def : Pat<(extloadi64i32 addr:$src),
1954 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1957 // anyext. Define these to do an explicit zero-extend to
1958 // avoid partial-register updates.
1959 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1960 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1961 def : Pat<(i64 (anyext GR32:$src)),
1962 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1964 //===----------------------------------------------------------------------===//
1966 //===----------------------------------------------------------------------===//
1968 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1969 // +128 doesn't, so in this special case use a sub instead of an add.
1970 def : Pat<(add GR64:$src1, 128),
1971 (SUB64ri8 GR64:$src1, -128)>;
1972 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1973 (SUB64mi8 addr:$dst, -128)>;
1975 // The same trick applies for 32-bit immediate fields in 64-bit
1977 def : Pat<(add GR64:$src1, 0x0000000080000000),
1978 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1979 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1980 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1982 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
1983 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
1984 // materialize that immediate in a register first.
1985 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1989 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit),
1990 (i32 (GetLo32XForm imm:$imm))),
1993 // r & (2^32-1) ==> movz
1994 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1995 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1996 // r & (2^16-1) ==> movz
1997 def : Pat<(and GR64:$src, 0xffff),
1998 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1999 // r & (2^8-1) ==> movz
2000 def : Pat<(and GR64:$src, 0xff),
2001 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
2002 // r & (2^8-1) ==> movz
2003 def : Pat<(and GR32:$src1, 0xff),
2004 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
2005 Requires<[In64BitMode]>;
2006 // r & (2^8-1) ==> movz
2007 def : Pat<(and GR16:$src1, 0xff),
2008 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
2009 Requires<[In64BitMode]>;
2011 // sext_inreg patterns
2012 def : Pat<(sext_inreg GR64:$src, i32),
2013 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2014 def : Pat<(sext_inreg GR64:$src, i16),
2015 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2016 def : Pat<(sext_inreg GR64:$src, i8),
2017 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
2018 def : Pat<(sext_inreg GR32:$src, i8),
2019 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
2020 Requires<[In64BitMode]>;
2021 def : Pat<(sext_inreg GR16:$src, i8),
2022 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
2023 Requires<[In64BitMode]>;
2026 def : Pat<(i32 (trunc GR64:$src)),
2027 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
2028 def : Pat<(i16 (trunc GR64:$src)),
2029 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
2030 def : Pat<(i8 (trunc GR64:$src)),
2031 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
2032 def : Pat<(i8 (trunc GR32:$src)),
2033 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
2034 Requires<[In64BitMode]>;
2035 def : Pat<(i8 (trunc GR16:$src)),
2036 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
2037 Requires<[In64BitMode]>;
2039 // h-register tricks.
2040 // For now, be conservative on x86-64 and use an h-register extract only if the
2041 // value is immediately zero-extended or stored, which are somewhat common
2042 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
2043 // from being allocated in the same instruction as the h register, as there's
2044 // currently no way to describe this requirement to the register allocator.
2046 // h-register extract and zero-extend.
2047 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2051 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2052 x86_subreg_8bit_hi)),
2054 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2056 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2057 x86_subreg_8bit_hi))>,
2058 Requires<[In64BitMode]>;
2059 def : Pat<(srl GR16:$src, (i8 8)),
2062 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2063 x86_subreg_8bit_hi)),
2065 Requires<[In64BitMode]>;
2066 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2068 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2069 x86_subreg_8bit_hi))>,
2070 Requires<[In64BitMode]>;
2071 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2073 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2074 x86_subreg_8bit_hi))>,
2075 Requires<[In64BitMode]>;
2076 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2080 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2081 x86_subreg_8bit_hi)),
2083 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2087 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2088 x86_subreg_8bit_hi)),
2091 // h-register extract and store.
2092 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2095 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2096 x86_subreg_8bit_hi))>;
2097 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2100 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2101 x86_subreg_8bit_hi))>,
2102 Requires<[In64BitMode]>;
2103 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2106 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2107 x86_subreg_8bit_hi))>,
2108 Requires<[In64BitMode]>;
2110 // (shl x, 1) ==> (add x, x)
2111 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2113 // (shl x (and y, 63)) ==> (shl x, y)
2114 def : Pat<(shl GR64:$src1, (and CL, 63)),
2115 (SHL64rCL GR64:$src1)>;
2116 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2117 (SHL64mCL addr:$dst)>;
2119 def : Pat<(srl GR64:$src1, (and CL, 63)),
2120 (SHR64rCL GR64:$src1)>;
2121 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2122 (SHR64mCL addr:$dst)>;
2124 def : Pat<(sra GR64:$src1, (and CL, 63)),
2125 (SAR64rCL GR64:$src1)>;
2126 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2127 (SAR64mCL addr:$dst)>;
2129 // Double shift patterns
2130 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2131 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2133 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
2134 GR64:$src2, (i8 imm)), addr:$dst),
2135 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2137 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2138 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2140 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
2141 GR64:$src2, (i8 imm)), addr:$dst),
2142 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2144 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2145 let AddedComplexity = 5 in { // Try this before the selecting to OR
2146 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt8:$src2),
2148 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2149 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt32:$src2),
2151 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2152 def : Pat<(parallel (or_is_add GR64:$src1, GR64:$src2),
2154 (ADD64rr GR64:$src1, GR64:$src2)>;
2155 } // AddedComplexity
2157 // X86 specific add which produces a flag.
2158 def : Pat<(addc GR64:$src1, GR64:$src2),
2159 (ADD64rr GR64:$src1, GR64:$src2)>;
2160 def : Pat<(addc GR64:$src1, (load addr:$src2)),
2161 (ADD64rm GR64:$src1, addr:$src2)>;
2162 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2163 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2164 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2165 (ADD64ri32 GR64:$src1, imm:$src2)>;
2167 def : Pat<(subc GR64:$src1, GR64:$src2),
2168 (SUB64rr GR64:$src1, GR64:$src2)>;
2169 def : Pat<(subc GR64:$src1, (load addr:$src2)),
2170 (SUB64rm GR64:$src1, addr:$src2)>;
2171 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2172 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2173 def : Pat<(subc GR64:$src1, imm:$src2),
2174 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2176 //===----------------------------------------------------------------------===//
2177 // EFLAGS-defining Patterns
2178 //===----------------------------------------------------------------------===//
2180 // Register-Register Addition with EFLAGS result
2181 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
2183 (ADD64rr GR64:$src1, GR64:$src2)>;
2185 // Register-Integer Addition with EFLAGS result
2186 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
2188 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2189 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
2191 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2193 // Register-Memory Addition with EFLAGS result
2194 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
2196 (ADD64rm GR64:$src1, addr:$src2)>;
2198 // Memory-Register Addition with EFLAGS result
2199 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
2202 (ADD64mr addr:$dst, GR64:$src2)>;
2203 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2206 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
2207 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
2208 i64immSExt32:$src2),
2211 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
2213 // Register-Register Subtraction with EFLAGS result
2214 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
2216 (SUB64rr GR64:$src1, GR64:$src2)>;
2218 // Register-Memory Subtraction with EFLAGS result
2219 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
2221 (SUB64rm GR64:$src1, addr:$src2)>;
2223 // Register-Integer Subtraction with EFLAGS result
2224 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
2226 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2227 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
2229 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2231 // Memory-Register Subtraction with EFLAGS result
2232 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
2235 (SUB64mr addr:$dst, GR64:$src2)>;
2237 // Memory-Integer Subtraction with EFLAGS result
2238 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2242 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2243 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2244 i64immSExt32:$src2),
2247 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
2249 // Register-Register Signed Integer Multiplication with EFLAGS result
2250 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
2252 (IMUL64rr GR64:$src1, GR64:$src2)>;
2254 // Register-Memory Signed Integer Multiplication with EFLAGS result
2255 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
2257 (IMUL64rm GR64:$src1, addr:$src2)>;
2259 // Register-Integer Signed Integer Multiplication with EFLAGS result
2260 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2262 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2263 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2265 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2267 // Memory-Integer Signed Integer Multiplication with EFLAGS result
2268 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2270 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2271 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2273 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2275 // INC and DEC with EFLAGS result. Note that these do not set CF.
2276 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2277 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2278 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2280 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2281 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2282 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2283 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2285 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2287 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2288 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2289 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2291 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2292 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2293 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2294 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2296 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2298 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2299 (INC64r GR64:$src)>;
2300 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2302 (INC64m addr:$dst)>;
2303 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2304 (DEC64r GR64:$src)>;
2305 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2307 (DEC64m addr:$dst)>;
2309 // Register-Register Logical Or with EFLAGS result
2310 def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2312 (OR64rr GR64:$src1, GR64:$src2)>;
2314 // Register-Integer Logical Or with EFLAGS result
2315 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2317 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2318 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2320 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2322 // Register-Memory Logical Or with EFLAGS result
2323 def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2325 (OR64rm GR64:$src1, addr:$src2)>;
2327 // Memory-Register Logical Or with EFLAGS result
2328 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2331 (OR64mr addr:$dst, GR64:$src2)>;
2332 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2335 (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2336 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2339 (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2341 // Register-Register Logical XOr with EFLAGS result
2342 def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2344 (XOR64rr GR64:$src1, GR64:$src2)>;
2346 // Register-Integer Logical XOr with EFLAGS result
2347 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2349 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2350 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2352 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2354 // Register-Memory Logical XOr with EFLAGS result
2355 def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2357 (XOR64rm GR64:$src1, addr:$src2)>;
2359 // Memory-Register Logical XOr with EFLAGS result
2360 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2363 (XOR64mr addr:$dst, GR64:$src2)>;
2364 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2367 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2368 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
2369 i64immSExt32:$src2),
2372 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2374 // Register-Register Logical And with EFLAGS result
2375 def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2377 (AND64rr GR64:$src1, GR64:$src2)>;
2379 // Register-Integer Logical And with EFLAGS result
2380 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2382 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2383 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2385 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2387 // Register-Memory Logical And with EFLAGS result
2388 def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2390 (AND64rm GR64:$src1, addr:$src2)>;
2392 // Memory-Register Logical And with EFLAGS result
2393 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2396 (AND64mr addr:$dst, GR64:$src2)>;
2397 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2400 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2401 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
2402 i64immSExt32:$src2),
2405 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2407 //===----------------------------------------------------------------------===//
2408 // X86-64 SSE Instructions
2409 //===----------------------------------------------------------------------===//
2411 // Move instructions...
2413 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2414 "mov{d|q}\t{$src, $dst|$dst, $src}",
2416 (v2i64 (scalar_to_vector GR64:$src)))]>;
2417 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2418 "mov{d|q}\t{$src, $dst|$dst, $src}",
2419 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2422 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2423 "mov{d|q}\t{$src, $dst|$dst, $src}",
2424 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2425 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2426 "movq\t{$src, $dst|$dst, $src}",
2427 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2429 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2430 "mov{d|q}\t{$src, $dst|$dst, $src}",
2431 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2432 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2433 "movq\t{$src, $dst|$dst, $src}",
2434 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2436 //===----------------------------------------------------------------------===//
2437 // X86-64 SSE4.1 Instructions
2438 //===----------------------------------------------------------------------===//
2440 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2441 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2442 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2443 (ins VR128:$src1, i32i8imm:$src2),
2444 !strconcat(OpcodeStr,
2445 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2447 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2448 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2449 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2450 !strconcat(OpcodeStr,
2451 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2452 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2453 addr:$dst)]>, OpSize, REX_W;
2456 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2458 let isTwoAddress = 1 in {
2459 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2460 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2461 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2462 !strconcat(OpcodeStr,
2463 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2465 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2467 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2468 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2469 !strconcat(OpcodeStr,
2470 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2472 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2473 imm:$src3)))]>, OpSize, REX_W;
2477 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2479 // -disable-16bit support.
2480 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2481 (MOV16mi addr:$dst, imm:$src)>;
2482 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2483 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2484 def : Pat<(i64 (sextloadi16 addr:$dst)),
2485 (MOVSX64rm16 addr:$dst)>;
2486 def : Pat<(i64 (zextloadi16 addr:$dst)),
2487 (MOVZX64rm16 addr:$dst)>;
2488 def : Pat<(i64 (extloadi16 addr:$dst)),
2489 (MOVZX64rm16 addr:$dst)>;