1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
27 let ParserMatchClass = X86AbsMemAsmOperand;
31 // 64-bits but only 8 bits are significant.
32 def i64i8imm : Operand<i64> {
33 let ParserMatchClass = ImmSExt8AsmOperand;
36 // Special i64mem for addresses of load folding tail calls. These are not
37 // allowed to use callee-saved registers since they must be scheduled
38 // after callee-saved register are popped.
39 def i64mem_TC : Operand<i64> {
40 let PrintMethod = "printi64mem";
41 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
42 let ParserMatchClass = X86MemAsmOperand;
45 def lea64mem : Operand<i64> {
46 let PrintMethod = "printlea64mem";
47 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
48 let ParserMatchClass = X86NoSegMemAsmOperand;
51 def lea64_32mem : Operand<i32> {
52 let PrintMethod = "printlea64_32mem";
53 let AsmOperandLowerMethod = "lower_lea64_32mem";
54 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
55 let ParserMatchClass = X86NoSegMemAsmOperand;
58 //===----------------------------------------------------------------------===//
59 // Complex Pattern Definitions.
61 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
62 [add, sub, mul, X86mul_imm, shl, or, frameindex,
65 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
66 [tglobaltlsaddr], []>;
68 //===----------------------------------------------------------------------===//
72 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
74 def GetLo32XForm : SDNodeXForm<imm, [{
75 // Transformation function: get the low 32 bits.
76 return getI32Imm((unsigned)N->getZExtValue());
79 def i64immSExt32 : PatLeaf<(i64 imm), [{
80 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
81 // sign extended field.
82 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
86 def i64immZExt32 : PatLeaf<(i64 imm), [{
87 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
88 // unsignedsign extended field.
89 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
92 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
93 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
94 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
96 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
97 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
98 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
99 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
101 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
102 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
103 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
104 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
106 //===----------------------------------------------------------------------===//
107 // Instruction list...
110 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
111 // a stack adjustment and the codegen must know that they may modify the stack
112 // pointer before prolog-epilog rewriting occurs.
113 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
114 // sub / add which can clobber EFLAGS.
115 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
116 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
118 [(X86callseq_start timm:$amt)]>,
119 Requires<[In64BitMode]>;
120 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
122 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
123 Requires<[In64BitMode]>;
126 // Interrupt Instructions
127 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
129 //===----------------------------------------------------------------------===//
130 // Call Instructions...
133 // All calls clobber the non-callee saved registers. RSP is marked as
134 // a use to prevent stack-pointer assignments that appear immediately
135 // before calls from potentially appearing dead. Uses for argument
136 // registers are added manually.
137 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
138 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
139 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
140 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
141 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
144 // NOTE: this pattern doesn't match "X86call imm", because we do not know
145 // that the offset between an arbitrary immediate and the call will fit in
146 // the 32-bit pcrel field that we have.
147 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
148 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
149 "call{q}\t$dst", []>,
150 Requires<[In64BitMode, NotWin64]>;
151 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
152 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
153 Requires<[NotWin64]>;
154 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
155 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
156 Requires<[NotWin64]>;
158 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
159 "lcall{q}\t{*}$dst", []>;
162 // FIXME: We need to teach codegen about single list of call-clobbered
165 // All calls clobber the non-callee saved registers. RSP is marked as
166 // a use to prevent stack-pointer assignments that appear immediately
167 // before calls from potentially appearing dead. Uses for argument
168 // registers are added manually.
169 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
170 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
171 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
172 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
174 def WINCALL64pcrel32 : I<0xE8, RawFrm,
175 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
178 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
180 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
181 def WINCALL64m : I<0xFF, MRM2m, (outs),
182 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
183 [(X86call (loadi64 addr:$dst))]>,
188 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
189 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
190 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
191 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
192 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
193 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
195 def TCRETURNdi64 : I<0, Pseudo, (outs),
196 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
197 "#TC_RETURN $dst $offset", []>;
198 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64_TC:$dst, i32imm:$offset,
200 "#TC_RETURN $dst $offset", []>;
201 def TCRETURNmi64 : I<0, Pseudo, (outs),
202 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops),
203 "#TC_RETURN $dst $offset", []>;
205 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
206 (ins i64i32imm_pcrel:$dst, variable_ops),
207 "jmp\t$dst # TAILCALL", []>;
208 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64_TC:$dst, variable_ops),
209 "jmp{q}\t{*}$dst # TAILCALL", []>;
211 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
212 "jmp{q}\t{*}$dst # TAILCALL", []>;
216 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
217 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
219 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
220 [(brind GR64:$dst)]>;
221 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
222 [(brind (loadi64 addr:$dst))]>;
223 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
224 "ljmp{q}\t{*}$dst", []>;
227 //===----------------------------------------------------------------------===//
228 // EH Pseudo Instructions
230 let isTerminator = 1, isReturn = 1, isBarrier = 1,
231 hasCtrlDep = 1, isCodeGenOnly = 1 in {
232 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
233 "ret\t#eh_return, addr: $addr",
234 [(X86ehret GR64:$addr)]>;
238 //===----------------------------------------------------------------------===//
239 // Miscellaneous Instructions...
242 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
243 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
244 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
245 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
247 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
248 def LEAVE64 : I<0xC9, RawFrm,
249 (outs), (ins), "leave", []>;
250 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
252 def POP64r : I<0x58, AddRegFrm,
253 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
254 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
255 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
257 let mayStore = 1 in {
258 def PUSH64r : I<0x50, AddRegFrm,
259 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
260 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
261 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
265 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
266 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
267 "push{q}\t$imm", []>;
268 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
269 "push{q}\t$imm", []>;
270 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
271 "push{q}\t$imm", []>;
274 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
275 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
276 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
277 def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
279 def LEA64_32r : I<0x8D, MRMSrcMem,
280 (outs GR32:$dst), (ins lea64_32mem:$src),
281 "lea{l}\t{$src|$dst}, {$dst|$src}",
282 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
284 let isReMaterializable = 1 in
285 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
286 "lea{q}\t{$src|$dst}, {$dst|$src}",
287 [(set GR64:$dst, lea64addr:$src)]>;
289 let isTwoAddress = 1 in
290 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
292 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
294 // Bit scan instructions.
295 let Defs = [EFLAGS] in {
296 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
297 "bsf{q}\t{$src, $dst|$dst, $src}",
298 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
299 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
300 "bsf{q}\t{$src, $dst|$dst, $src}",
301 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
302 (implicit EFLAGS)]>, TB;
304 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
305 "bsr{q}\t{$src, $dst|$dst, $src}",
306 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
307 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
308 "bsr{q}\t{$src, $dst|$dst, $src}",
309 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
310 (implicit EFLAGS)]>, TB;
314 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
315 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
316 [(X86rep_movs i64)]>, REP;
317 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
318 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
319 [(X86rep_stos i64)]>, REP;
321 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
323 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
325 // Fast system-call instructions
326 def SYSEXIT64 : RI<0x35, RawFrm,
327 (outs), (ins), "sysexit", []>, TB;
329 //===----------------------------------------------------------------------===//
330 // Move Instructions...
333 let neverHasSideEffects = 1 in
334 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
335 "mov{q}\t{$src, $dst|$dst, $src}", []>;
337 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
338 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
339 "movabs{q}\t{$src, $dst|$dst, $src}",
340 [(set GR64:$dst, imm:$src)]>;
341 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
342 "mov{q}\t{$src, $dst|$dst, $src}",
343 [(set GR64:$dst, i64immSExt32:$src)]>;
346 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
347 "mov{q}\t{$src, $dst|$dst, $src}", []>;
349 let canFoldAsLoad = 1, isReMaterializable = 1 in
350 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
351 "mov{q}\t{$src, $dst|$dst, $src}",
352 [(set GR64:$dst, (load addr:$src))]>;
354 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
355 "mov{q}\t{$src, $dst|$dst, $src}",
356 [(store GR64:$src, addr:$dst)]>;
357 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
358 "mov{q}\t{$src, $dst|$dst, $src}",
359 [(store i64immSExt32:$src, addr:$dst)]>;
361 /// Versions of MOV64rr, MOV64rm, and MOV64mr for i64mem_TC and GR64_TC.
362 let neverHasSideEffects = 1 in
363 def MOV64rr_TC : RI<0x89, MRMDestReg, (outs GR64_TC:$dst), (ins GR64_TC:$src),
364 "mov{q}\t{$src, $dst|$dst, $src}", []>;
367 canFoldAsLoad = 1, isReMaterializable = 1 in
368 def MOV64rm_TC : RI<0x8B, MRMSrcMem, (outs GR64_TC:$dst), (ins i64mem_TC:$src),
369 "mov{q}\t{$src, $dst|$dst, $src}",
373 def MOV64mr_TC : RI<0x89, MRMDestMem, (outs), (ins i64mem_TC:$dst, GR64_TC:$src),
374 "mov{q}\t{$src, $dst|$dst, $src}",
377 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
378 "mov{q}\t{$src, %rax|%rax, $src}", []>;
379 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
380 "mov{q}\t{$src, %rax|%rax, $src}", []>;
381 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
382 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
383 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
384 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
386 // Moves to and from segment registers
387 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
388 "mov{q}\t{$src, $dst|$dst, $src}", []>;
389 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
390 "mov{q}\t{$src, $dst|$dst, $src}", []>;
391 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
392 "mov{q}\t{$src, $dst|$dst, $src}", []>;
393 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
394 "mov{q}\t{$src, $dst|$dst, $src}", []>;
396 // Moves to and from debug registers
397 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
398 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
399 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
400 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
402 // Moves to and from control registers
403 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
404 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
405 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
406 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
408 // Sign/Zero extenders
410 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
411 // operand, which makes it a rare instruction with an 8-bit register
412 // operand that can never access an h register. If support for h registers
413 // were generalized, this would require a special register class.
414 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
415 "movs{bq|x}\t{$src, $dst|$dst, $src}",
416 [(set GR64:$dst, (sext GR8:$src))]>, TB;
417 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
418 "movs{bq|x}\t{$src, $dst|$dst, $src}",
419 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
420 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
421 "movs{wq|x}\t{$src, $dst|$dst, $src}",
422 [(set GR64:$dst, (sext GR16:$src))]>, TB;
423 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
424 "movs{wq|x}\t{$src, $dst|$dst, $src}",
425 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
426 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
427 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
428 [(set GR64:$dst, (sext GR32:$src))]>;
429 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
430 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
431 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
433 // movzbq and movzwq encodings for the disassembler
434 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
435 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
436 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
437 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
438 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
439 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
440 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
441 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
443 // Use movzbl instead of movzbq when the destination is a register; it's
444 // equivalent due to implicit zero-extending, and it has a smaller encoding.
445 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
446 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
447 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
448 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
449 // Use movzwl instead of movzwq when the destination is a register; it's
450 // equivalent due to implicit zero-extending, and it has a smaller encoding.
451 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
452 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
453 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
454 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
456 // There's no movzlq instruction, but movl can be used for this purpose, using
457 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
458 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
459 // zero-extension, however this isn't possible when the 32-bit value is
460 // defined by a truncate or is copied from something where the high bits aren't
461 // necessarily all zero. In such cases, we fall back to these explicit zext
463 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
464 "", [(set GR64:$dst, (zext GR32:$src))]>;
465 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
466 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
468 // Any instruction that defines a 32-bit result leaves the high half of the
469 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
470 // be copying from a truncate. And x86's cmov doesn't do anything if the
471 // condition is false. But any other 32-bit operation will zero-extend
473 def def32 : PatLeaf<(i32 GR32:$src), [{
474 return N->getOpcode() != ISD::TRUNCATE &&
475 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
476 N->getOpcode() != ISD::CopyFromReg &&
477 N->getOpcode() != X86ISD::CMOV;
480 // In the case of a 32-bit def that is known to implicitly zero-extend,
481 // we can use a SUBREG_TO_REG.
482 def : Pat<(i64 (zext def32:$src)),
483 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
485 let neverHasSideEffects = 1 in {
486 let Defs = [RAX], Uses = [EAX] in
487 def CDQE : RI<0x98, RawFrm, (outs), (ins),
488 "{cltq|cdqe}", []>; // RAX = signext(EAX)
490 let Defs = [RAX,RDX], Uses = [RAX] in
491 def CQO : RI<0x99, RawFrm, (outs), (ins),
492 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
495 //===----------------------------------------------------------------------===//
496 // Arithmetic Instructions...
499 let Defs = [EFLAGS] in {
501 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i32imm:$src),
502 "add{q}\t{$src, %rax|%rax, $src}", []>;
504 let isTwoAddress = 1 in {
505 let isConvertibleToThreeAddress = 1 in {
506 let isCommutable = 1 in
507 // Register-Register Addition
508 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
509 (ins GR64:$src1, GR64:$src2),
510 "add{q}\t{$src2, $dst|$dst, $src2}",
511 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
514 // Register-Integer Addition
515 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
516 (ins GR64:$src1, i64i8imm:$src2),
517 "add{q}\t{$src2, $dst|$dst, $src2}",
518 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
520 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
521 (ins GR64:$src1, i64i32imm:$src2),
522 "add{q}\t{$src2, $dst|$dst, $src2}",
523 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
525 } // isConvertibleToThreeAddress
527 // Register-Memory Addition
528 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
529 (ins GR64:$src1, i64mem:$src2),
530 "add{q}\t{$src2, $dst|$dst, $src2}",
531 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
534 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
535 // differently encoded.
536 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
537 (ins GR64:$src1, GR64:$src2),
538 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
542 // Memory-Register Addition
543 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
544 "add{q}\t{$src2, $dst|$dst, $src2}",
545 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
547 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
548 "add{q}\t{$src2, $dst|$dst, $src2}",
549 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
551 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
552 "add{q}\t{$src2, $dst|$dst, $src2}",
553 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
556 let Uses = [EFLAGS] in {
558 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i32imm:$src),
559 "adc{q}\t{$src, %rax|%rax, $src}", []>;
561 let isTwoAddress = 1 in {
562 let isCommutable = 1 in
563 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
564 (ins GR64:$src1, GR64:$src2),
565 "adc{q}\t{$src2, $dst|$dst, $src2}",
566 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
568 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
569 (ins GR64:$src1, GR64:$src2),
570 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
572 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
573 (ins GR64:$src1, i64mem:$src2),
574 "adc{q}\t{$src2, $dst|$dst, $src2}",
575 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
577 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
578 (ins GR64:$src1, i64i8imm:$src2),
579 "adc{q}\t{$src2, $dst|$dst, $src2}",
580 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
581 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
582 (ins GR64:$src1, i64i32imm:$src2),
583 "adc{q}\t{$src2, $dst|$dst, $src2}",
584 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
587 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
588 "adc{q}\t{$src2, $dst|$dst, $src2}",
589 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
590 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
591 "adc{q}\t{$src2, $dst|$dst, $src2}",
592 [(store (adde (load addr:$dst), i64immSExt8:$src2),
594 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
595 "adc{q}\t{$src2, $dst|$dst, $src2}",
596 [(store (adde (load addr:$dst), i64immSExt32:$src2),
600 let isTwoAddress = 1 in {
601 // Register-Register Subtraction
602 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
603 (ins GR64:$src1, GR64:$src2),
604 "sub{q}\t{$src2, $dst|$dst, $src2}",
605 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
608 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
609 (ins GR64:$src1, GR64:$src2),
610 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
612 // Register-Memory Subtraction
613 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
614 (ins GR64:$src1, i64mem:$src2),
615 "sub{q}\t{$src2, $dst|$dst, $src2}",
616 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
619 // Register-Integer Subtraction
620 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
621 (ins GR64:$src1, i64i8imm:$src2),
622 "sub{q}\t{$src2, $dst|$dst, $src2}",
623 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
625 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
626 (ins GR64:$src1, i64i32imm:$src2),
627 "sub{q}\t{$src2, $dst|$dst, $src2}",
628 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
632 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i32imm:$src),
633 "sub{q}\t{$src, %rax|%rax, $src}", []>;
635 // Memory-Register Subtraction
636 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
637 "sub{q}\t{$src2, $dst|$dst, $src2}",
638 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
641 // Memory-Integer Subtraction
642 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
643 "sub{q}\t{$src2, $dst|$dst, $src2}",
644 [(store (sub (load addr:$dst), i64immSExt8:$src2),
647 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
648 "sub{q}\t{$src2, $dst|$dst, $src2}",
649 [(store (sub (load addr:$dst), i64immSExt32:$src2),
653 let Uses = [EFLAGS] in {
654 let isTwoAddress = 1 in {
655 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
656 (ins GR64:$src1, GR64:$src2),
657 "sbb{q}\t{$src2, $dst|$dst, $src2}",
658 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
660 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
661 (ins GR64:$src1, GR64:$src2),
662 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
664 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
665 (ins GR64:$src1, i64mem:$src2),
666 "sbb{q}\t{$src2, $dst|$dst, $src2}",
667 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
669 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
670 (ins GR64:$src1, i64i8imm:$src2),
671 "sbb{q}\t{$src2, $dst|$dst, $src2}",
672 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
673 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
674 (ins GR64:$src1, i64i32imm:$src2),
675 "sbb{q}\t{$src2, $dst|$dst, $src2}",
676 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
679 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i32imm:$src),
680 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
682 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
683 "sbb{q}\t{$src2, $dst|$dst, $src2}",
684 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
685 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
686 "sbb{q}\t{$src2, $dst|$dst, $src2}",
687 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
688 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
689 "sbb{q}\t{$src2, $dst|$dst, $src2}",
690 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
694 // Unsigned multiplication
695 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
696 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
697 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
699 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
700 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
702 // Signed multiplication
703 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
704 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
706 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
707 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
710 let Defs = [EFLAGS] in {
711 let isTwoAddress = 1 in {
712 let isCommutable = 1 in
713 // Register-Register Signed Integer Multiplication
714 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
715 (ins GR64:$src1, GR64:$src2),
716 "imul{q}\t{$src2, $dst|$dst, $src2}",
717 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
718 (implicit EFLAGS)]>, TB;
720 // Register-Memory Signed Integer Multiplication
721 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
722 (ins GR64:$src1, i64mem:$src2),
723 "imul{q}\t{$src2, $dst|$dst, $src2}",
724 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
725 (implicit EFLAGS)]>, TB;
728 // Suprisingly enough, these are not two address instructions!
730 // Register-Integer Signed Integer Multiplication
731 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
732 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
733 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
736 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
737 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
738 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
739 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
742 // Memory-Integer Signed Integer Multiplication
743 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
744 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
745 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
746 [(set GR64:$dst, (mul (load addr:$src1),
749 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
750 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
751 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
752 [(set GR64:$dst, (mul (load addr:$src1),
753 i64immSExt32:$src2)),
757 // Unsigned division / remainder
758 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
759 // RDX:RAX/r64 = RAX,RDX
760 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
762 // Signed division / remainder
763 // RDX:RAX/r64 = RAX,RDX
764 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
765 "idiv{q}\t$src", []>;
767 // RDX:RAX/[mem64] = RAX,RDX
768 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
770 // RDX:RAX/[mem64] = RAX,RDX
771 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
772 "idiv{q}\t$src", []>;
776 // Unary instructions
777 let Defs = [EFLAGS], CodeSize = 2 in {
778 let isTwoAddress = 1 in
779 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
780 [(set GR64:$dst, (ineg GR64:$src)),
782 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
783 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
786 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
787 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
788 [(set GR64:$dst, (add GR64:$src, 1)),
790 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
791 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
794 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
795 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
796 [(set GR64:$dst, (add GR64:$src, -1)),
798 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
799 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
802 // In 64-bit mode, single byte INC and DEC cannot be encoded.
803 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
804 // Can transform into LEA.
805 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
807 [(set GR16:$dst, (add GR16:$src, 1)),
809 OpSize, Requires<[In64BitMode]>;
810 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
812 [(set GR32:$dst, (add GR32:$src, 1)),
814 Requires<[In64BitMode]>;
815 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
817 [(set GR16:$dst, (add GR16:$src, -1)),
819 OpSize, Requires<[In64BitMode]>;
820 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
822 [(set GR32:$dst, (add GR32:$src, -1)),
824 Requires<[In64BitMode]>;
825 } // isConvertibleToThreeAddress
827 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
828 // how to unfold them.
829 let isTwoAddress = 0, CodeSize = 2 in {
830 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
831 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
833 OpSize, Requires<[In64BitMode]>;
834 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
835 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
837 Requires<[In64BitMode]>;
838 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
839 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
841 OpSize, Requires<[In64BitMode]>;
842 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
843 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
845 Requires<[In64BitMode]>;
847 } // Defs = [EFLAGS], CodeSize
850 let Defs = [EFLAGS] in {
851 // Shift instructions
852 let isTwoAddress = 1 in {
854 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
855 "shl{q}\t{%cl, $dst|$dst, %CL}",
856 [(set GR64:$dst, (shl GR64:$src, CL))]>;
857 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
858 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
859 (ins GR64:$src1, i8imm:$src2),
860 "shl{q}\t{$src2, $dst|$dst, $src2}",
861 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
862 // NOTE: We don't include patterns for shifts of a register by one, because
863 // 'add reg,reg' is cheaper.
864 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
869 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
870 "shl{q}\t{%cl, $dst|$dst, %CL}",
871 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
872 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
873 "shl{q}\t{$src, $dst|$dst, $src}",
874 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
875 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
877 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
879 let isTwoAddress = 1 in {
881 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
882 "shr{q}\t{%cl, $dst|$dst, %CL}",
883 [(set GR64:$dst, (srl GR64:$src, CL))]>;
884 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
885 "shr{q}\t{$src2, $dst|$dst, $src2}",
886 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
887 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
889 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
893 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
894 "shr{q}\t{%cl, $dst|$dst, %CL}",
895 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
896 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
897 "shr{q}\t{$src, $dst|$dst, $src}",
898 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
899 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
901 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
903 let isTwoAddress = 1 in {
905 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
906 "sar{q}\t{%cl, $dst|$dst, %CL}",
907 [(set GR64:$dst, (sra GR64:$src, CL))]>;
908 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
909 (ins GR64:$src1, i8imm:$src2),
910 "sar{q}\t{$src2, $dst|$dst, $src2}",
911 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
912 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
914 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
918 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
919 "sar{q}\t{%cl, $dst|$dst, %CL}",
920 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
921 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
922 "sar{q}\t{$src, $dst|$dst, $src}",
923 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
924 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
926 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
928 // Rotate instructions
930 let isTwoAddress = 1 in {
931 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
932 "rcl{q}\t{1, $dst|$dst, 1}", []>;
933 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
934 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
936 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
937 "rcr{q}\t{1, $dst|$dst, 1}", []>;
938 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
939 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
942 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
943 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
944 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
945 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
949 let isTwoAddress = 0 in {
950 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
951 "rcl{q}\t{1, $dst|$dst, 1}", []>;
952 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
953 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
954 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
955 "rcr{q}\t{1, $dst|$dst, 1}", []>;
956 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
957 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
960 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
961 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
962 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
963 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
967 let isTwoAddress = 1 in {
969 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
970 "rol{q}\t{%cl, $dst|$dst, %CL}",
971 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
972 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
973 (ins GR64:$src1, i8imm:$src2),
974 "rol{q}\t{$src2, $dst|$dst, $src2}",
975 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
976 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
978 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
982 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
983 "rol{q}\t{%cl, $dst|$dst, %CL}",
984 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
985 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
986 "rol{q}\t{$src, $dst|$dst, $src}",
987 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
988 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
990 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
992 let isTwoAddress = 1 in {
994 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
995 "ror{q}\t{%cl, $dst|$dst, %CL}",
996 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
997 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
998 (ins GR64:$src1, i8imm:$src2),
999 "ror{q}\t{$src2, $dst|$dst, $src2}",
1000 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
1001 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
1003 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
1007 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
1008 "ror{q}\t{%cl, $dst|$dst, %CL}",
1009 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
1010 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
1011 "ror{q}\t{$src, $dst|$dst, $src}",
1012 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1013 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
1015 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
1017 // Double shift instructions (generalizations of rotate)
1018 let isTwoAddress = 1 in {
1019 let Uses = [CL] in {
1020 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
1021 (ins GR64:$src1, GR64:$src2),
1022 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1023 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
1025 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
1026 (ins GR64:$src1, GR64:$src2),
1027 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1028 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
1032 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
1033 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
1035 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1036 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1037 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1040 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1042 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1043 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1044 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1050 let Uses = [CL] in {
1051 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1052 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1053 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1055 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1056 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1057 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1060 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1061 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1062 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1063 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1064 (i8 imm:$src3)), addr:$dst)]>,
1066 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1067 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1068 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1069 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1070 (i8 imm:$src3)), addr:$dst)]>,
1072 } // Defs = [EFLAGS]
1074 //===----------------------------------------------------------------------===//
1075 // Logical Instructions...
1078 let isTwoAddress = 1 , AddedComplexity = 15 in
1079 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1080 [(set GR64:$dst, (not GR64:$src))]>;
1081 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1082 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1084 let Defs = [EFLAGS] in {
1085 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i32imm:$src),
1086 "and{q}\t{$src, %rax|%rax, $src}", []>;
1088 let isTwoAddress = 1 in {
1089 let isCommutable = 1 in
1090 def AND64rr : RI<0x21, MRMDestReg,
1091 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1092 "and{q}\t{$src2, $dst|$dst, $src2}",
1093 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
1094 (implicit EFLAGS)]>;
1095 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1096 (ins GR64:$src1, GR64:$src2),
1097 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
1098 def AND64rm : RI<0x23, MRMSrcMem,
1099 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1100 "and{q}\t{$src2, $dst|$dst, $src2}",
1101 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
1102 (implicit EFLAGS)]>;
1103 def AND64ri8 : RIi8<0x83, MRM4r,
1104 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1105 "and{q}\t{$src2, $dst|$dst, $src2}",
1106 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
1107 (implicit EFLAGS)]>;
1108 def AND64ri32 : RIi32<0x81, MRM4r,
1109 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1110 "and{q}\t{$src2, $dst|$dst, $src2}",
1111 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
1112 (implicit EFLAGS)]>;
1115 def AND64mr : RI<0x21, MRMDestMem,
1116 (outs), (ins i64mem:$dst, GR64:$src),
1117 "and{q}\t{$src, $dst|$dst, $src}",
1118 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
1119 (implicit EFLAGS)]>;
1120 def AND64mi8 : RIi8<0x83, MRM4m,
1121 (outs), (ins i64mem:$dst, i64i8imm :$src),
1122 "and{q}\t{$src, $dst|$dst, $src}",
1123 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1124 (implicit EFLAGS)]>;
1125 def AND64mi32 : RIi32<0x81, MRM4m,
1126 (outs), (ins i64mem:$dst, i64i32imm:$src),
1127 "and{q}\t{$src, $dst|$dst, $src}",
1128 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1129 (implicit EFLAGS)]>;
1131 let isTwoAddress = 1 in {
1132 let isCommutable = 1 in
1133 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1134 (ins GR64:$src1, GR64:$src2),
1135 "or{q}\t{$src2, $dst|$dst, $src2}",
1136 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
1137 (implicit EFLAGS)]>;
1138 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1139 (ins GR64:$src1, GR64:$src2),
1140 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1141 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1142 (ins GR64:$src1, i64mem:$src2),
1143 "or{q}\t{$src2, $dst|$dst, $src2}",
1144 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
1145 (implicit EFLAGS)]>;
1146 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1147 (ins GR64:$src1, i64i8imm:$src2),
1148 "or{q}\t{$src2, $dst|$dst, $src2}",
1149 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
1150 (implicit EFLAGS)]>;
1151 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1152 (ins GR64:$src1, i64i32imm:$src2),
1153 "or{q}\t{$src2, $dst|$dst, $src2}",
1154 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
1155 (implicit EFLAGS)]>;
1158 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1159 "or{q}\t{$src, $dst|$dst, $src}",
1160 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1161 (implicit EFLAGS)]>;
1162 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1163 "or{q}\t{$src, $dst|$dst, $src}",
1164 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1165 (implicit EFLAGS)]>;
1166 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1167 "or{q}\t{$src, $dst|$dst, $src}",
1168 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1169 (implicit EFLAGS)]>;
1171 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1172 "or{q}\t{$src, %rax|%rax, $src}", []>;
1174 let isTwoAddress = 1 in {
1175 let isCommutable = 1 in
1176 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1177 (ins GR64:$src1, GR64:$src2),
1178 "xor{q}\t{$src2, $dst|$dst, $src2}",
1179 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1180 (implicit EFLAGS)]>;
1181 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1182 (ins GR64:$src1, GR64:$src2),
1183 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1184 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1185 (ins GR64:$src1, i64mem:$src2),
1186 "xor{q}\t{$src2, $dst|$dst, $src2}",
1187 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1188 (implicit EFLAGS)]>;
1189 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1190 (ins GR64:$src1, i64i8imm:$src2),
1191 "xor{q}\t{$src2, $dst|$dst, $src2}",
1192 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1193 (implicit EFLAGS)]>;
1194 def XOR64ri32 : RIi32<0x81, MRM6r,
1195 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1196 "xor{q}\t{$src2, $dst|$dst, $src2}",
1197 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1198 (implicit EFLAGS)]>;
1201 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1202 "xor{q}\t{$src, $dst|$dst, $src}",
1203 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1204 (implicit EFLAGS)]>;
1205 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1206 "xor{q}\t{$src, $dst|$dst, $src}",
1207 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1208 (implicit EFLAGS)]>;
1209 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1210 "xor{q}\t{$src, $dst|$dst, $src}",
1211 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1212 (implicit EFLAGS)]>;
1214 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1215 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1217 } // Defs = [EFLAGS]
1219 //===----------------------------------------------------------------------===//
1220 // Comparison Instructions...
1223 // Integer comparison
1224 let Defs = [EFLAGS] in {
1225 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i32imm:$src),
1226 "test{q}\t{$src, %rax|%rax, $src}", []>;
1227 let isCommutable = 1 in
1228 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1229 "test{q}\t{$src2, $src1|$src1, $src2}",
1230 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1231 (implicit EFLAGS)]>;
1232 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1233 "test{q}\t{$src2, $src1|$src1, $src2}",
1234 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1235 (implicit EFLAGS)]>;
1236 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1237 (ins GR64:$src1, i64i32imm:$src2),
1238 "test{q}\t{$src2, $src1|$src1, $src2}",
1239 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1240 (implicit EFLAGS)]>;
1241 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1242 (ins i64mem:$src1, i64i32imm:$src2),
1243 "test{q}\t{$src2, $src1|$src1, $src2}",
1244 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1245 (implicit EFLAGS)]>;
1248 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1249 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1250 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1251 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1252 [(X86cmp GR64:$src1, GR64:$src2),
1253 (implicit EFLAGS)]>;
1254 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1255 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1256 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1257 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1258 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1259 (implicit EFLAGS)]>;
1260 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1261 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1262 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1263 (implicit EFLAGS)]>;
1264 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1265 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1266 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1267 (implicit EFLAGS)]>;
1268 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1269 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1270 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1271 (implicit EFLAGS)]>;
1272 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1273 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1274 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1275 (implicit EFLAGS)]>;
1276 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1277 (ins i64mem:$src1, i64i32imm:$src2),
1278 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1279 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1280 (implicit EFLAGS)]>;
1281 } // Defs = [EFLAGS]
1284 // TODO: BTC, BTR, and BTS
1285 let Defs = [EFLAGS] in {
1286 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1287 "bt{q}\t{$src2, $src1|$src1, $src2}",
1288 [(X86bt GR64:$src1, GR64:$src2),
1289 (implicit EFLAGS)]>, TB;
1291 // Unlike with the register+register form, the memory+register form of the
1292 // bt instruction does not ignore the high bits of the index. From ISel's
1293 // perspective, this is pretty bizarre. Disable these instructions for now.
1294 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1295 "bt{q}\t{$src2, $src1|$src1, $src2}",
1296 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1297 // (implicit EFLAGS)]
1301 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1302 "bt{q}\t{$src2, $src1|$src1, $src2}",
1303 [(X86bt GR64:$src1, i64immSExt8:$src2),
1304 (implicit EFLAGS)]>, TB;
1305 // Note that these instructions don't need FastBTMem because that
1306 // only applies when the other operand is in a register. When it's
1307 // an immediate, bt is still fast.
1308 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1309 "bt{q}\t{$src2, $src1|$src1, $src2}",
1310 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1311 (implicit EFLAGS)]>, TB;
1313 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1314 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1315 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1316 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1317 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1318 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1319 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1320 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1322 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1323 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1324 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1325 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1326 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1327 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1328 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1329 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1331 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1332 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1333 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1334 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1335 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1336 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1337 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1338 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1339 } // Defs = [EFLAGS]
1341 // Conditional moves
1342 let Uses = [EFLAGS], isTwoAddress = 1 in {
1343 let isCommutable = 1 in {
1344 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1345 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1346 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1347 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1348 X86_COND_B, EFLAGS))]>, TB;
1349 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1350 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1351 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1352 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1353 X86_COND_AE, EFLAGS))]>, TB;
1354 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1355 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1356 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1357 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1358 X86_COND_E, EFLAGS))]>, TB;
1359 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1360 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1361 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1362 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1363 X86_COND_NE, EFLAGS))]>, TB;
1364 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1365 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1366 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1368 X86_COND_BE, EFLAGS))]>, TB;
1369 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1370 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1371 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1372 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1373 X86_COND_A, EFLAGS))]>, TB;
1374 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1375 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1376 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1377 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1378 X86_COND_L, EFLAGS))]>, TB;
1379 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1380 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1381 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1383 X86_COND_GE, EFLAGS))]>, TB;
1384 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1385 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1386 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1387 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1388 X86_COND_LE, EFLAGS))]>, TB;
1389 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1390 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1391 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1393 X86_COND_G, EFLAGS))]>, TB;
1394 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1395 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1396 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1398 X86_COND_S, EFLAGS))]>, TB;
1399 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1400 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1401 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1403 X86_COND_NS, EFLAGS))]>, TB;
1404 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1405 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1406 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1408 X86_COND_P, EFLAGS))]>, TB;
1409 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1410 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1411 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1412 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1413 X86_COND_NP, EFLAGS))]>, TB;
1414 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1415 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1416 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1418 X86_COND_O, EFLAGS))]>, TB;
1419 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1420 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1421 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1422 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1423 X86_COND_NO, EFLAGS))]>, TB;
1424 } // isCommutable = 1
1426 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1427 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1428 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1430 X86_COND_B, EFLAGS))]>, TB;
1431 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1432 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1433 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1434 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1435 X86_COND_AE, EFLAGS))]>, TB;
1436 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1437 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1438 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1439 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1440 X86_COND_E, EFLAGS))]>, TB;
1441 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1442 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1443 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1444 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1445 X86_COND_NE, EFLAGS))]>, TB;
1446 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1447 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1448 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1449 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1450 X86_COND_BE, EFLAGS))]>, TB;
1451 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1452 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1453 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1455 X86_COND_A, EFLAGS))]>, TB;
1456 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1457 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1458 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1460 X86_COND_L, EFLAGS))]>, TB;
1461 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1462 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1463 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1465 X86_COND_GE, EFLAGS))]>, TB;
1466 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1467 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1468 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1470 X86_COND_LE, EFLAGS))]>, TB;
1471 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1472 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1473 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1475 X86_COND_G, EFLAGS))]>, TB;
1476 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1477 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1478 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1479 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1480 X86_COND_S, EFLAGS))]>, TB;
1481 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1482 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1483 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1484 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1485 X86_COND_NS, EFLAGS))]>, TB;
1486 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1487 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1488 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1490 X86_COND_P, EFLAGS))]>, TB;
1491 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1492 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1493 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1494 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1495 X86_COND_NP, EFLAGS))]>, TB;
1496 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1497 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1498 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1499 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1500 X86_COND_O, EFLAGS))]>, TB;
1501 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1502 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1503 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1504 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1505 X86_COND_NO, EFLAGS))]>, TB;
1508 // Use sbb to materialize carry flag into a GPR.
1509 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1510 // However, Pat<> can't replicate the destination reg into the inputs of the
1512 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1514 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1515 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1516 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1518 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1521 //===----------------------------------------------------------------------===//
1522 // Conversion Instructions...
1525 // f64 -> signed i64
1526 def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1527 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1528 def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1529 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1530 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1531 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1533 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1534 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1536 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1537 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1538 (load addr:$src)))]>;
1539 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1540 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1541 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1542 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1543 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1544 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1545 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1546 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1549 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1551 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1553 (int_x86_sse2_cvttsd2si64
1554 (load addr:$src)))]>;
1556 // Signed i64 -> f64
1557 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1558 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1559 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1560 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1561 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1562 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1564 let isTwoAddress = 1 in {
1565 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1566 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1567 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1569 (int_x86_sse2_cvtsi642sd VR128:$src1,
1571 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1572 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1573 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1575 (int_x86_sse2_cvtsi642sd VR128:$src1,
1576 (loadi64 addr:$src2)))]>;
1579 // Signed i64 -> f32
1580 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1581 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1582 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1583 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1584 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1585 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1587 let isTwoAddress = 1 in {
1588 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1589 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1590 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1592 (int_x86_sse_cvtsi642ss VR128:$src1,
1594 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1596 (ins VR128:$src1, i64mem:$src2),
1597 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1599 (int_x86_sse_cvtsi642ss VR128:$src1,
1600 (loadi64 addr:$src2)))]>;
1603 // f32 -> signed i64
1604 def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1605 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1606 def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1607 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1608 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1609 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1611 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1612 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1613 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1614 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1615 (load addr:$src)))]>;
1616 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1617 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1618 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1619 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1620 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1621 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1622 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1623 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1625 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1626 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1628 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1630 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1632 // Descriptor-table support instructions
1634 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1636 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1637 "sldt{q}\t$dst", []>, TB;
1638 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1639 "sldt{q}\t$dst", []>, TB;
1641 //===----------------------------------------------------------------------===//
1642 // Alias Instructions
1643 //===----------------------------------------------------------------------===//
1645 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1646 // smaller encoding, but doing so at isel time interferes with rematerialization
1647 // in the current register allocator. For now, this is rewritten when the
1648 // instruction is lowered to an MCInst.
1649 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1650 // when we have a better way to specify isel priority.
1651 let Defs = [EFLAGS],
1652 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1653 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1654 [(set GR64:$dst, 0)]>;
1656 // Materialize i64 constant where top 32-bits are zero. This could theoretically
1657 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1658 // that would make it more difficult to rematerialize.
1659 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1660 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1661 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1663 //===----------------------------------------------------------------------===//
1664 // Thread Local Storage Instructions
1665 //===----------------------------------------------------------------------===//
1667 // All calls clobber the non-callee saved registers. RSP is marked as
1668 // a use to prevent stack-pointer assignments that appear immediately
1669 // before calls from potentially appearing dead.
1670 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1671 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1672 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1673 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1674 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1676 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1678 "leaq\t$sym(%rip), %rdi; "
1681 "call\t__tls_get_addr@PLT",
1682 [(X86tlsaddr tls64addr:$sym)]>,
1683 Requires<[In64BitMode]>;
1685 let AddedComplexity = 5, isCodeGenOnly = 1 in
1686 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1687 "movq\t%gs:$src, $dst",
1688 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1690 let AddedComplexity = 5, isCodeGenOnly = 1 in
1691 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1692 "movq\t%fs:$src, $dst",
1693 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1695 //===----------------------------------------------------------------------===//
1696 // Atomic Instructions
1697 //===----------------------------------------------------------------------===//
1699 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1700 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1702 "cmpxchgq\t$swap,$ptr",
1703 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1706 let Constraints = "$val = $dst" in {
1707 let Defs = [EFLAGS] in
1708 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1711 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1714 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1715 (ins GR64:$val,i64mem:$ptr),
1716 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1717 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1719 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1720 "xchg{q}\t{$val, $src|$src, $val}", []>;
1723 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1724 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1725 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1726 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1728 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1729 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1730 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1731 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1733 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1734 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1735 "cmpxchg16b\t$dst", []>, TB;
1737 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1738 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1740 // Optimized codegen when the non-memory output is not used.
1741 let Defs = [EFLAGS] in {
1742 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1743 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1745 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1746 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1747 (ins i64mem:$dst, i64i8imm :$src2),
1749 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1750 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1751 (ins i64mem:$dst, i64i32imm :$src2),
1753 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1754 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1756 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1757 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1758 (ins i64mem:$dst, i64i8imm :$src2),
1760 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1761 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1762 (ins i64mem:$dst, i64i32imm:$src2),
1764 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1765 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1767 "inc{q}\t$dst", []>, LOCK;
1768 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1770 "dec{q}\t$dst", []>, LOCK;
1772 // Atomic exchange, and, or, xor
1773 let Constraints = "$val = $dst", Defs = [EFLAGS],
1774 usesCustomInserter = 1 in {
1775 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1776 "#ATOMAND64 PSEUDO!",
1777 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1778 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1779 "#ATOMOR64 PSEUDO!",
1780 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1781 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1782 "#ATOMXOR64 PSEUDO!",
1783 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1784 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1785 "#ATOMNAND64 PSEUDO!",
1786 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1787 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1788 "#ATOMMIN64 PSEUDO!",
1789 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1790 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1791 "#ATOMMAX64 PSEUDO!",
1792 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1793 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1794 "#ATOMUMIN64 PSEUDO!",
1795 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1796 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1797 "#ATOMUMAX64 PSEUDO!",
1798 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1801 // Segmentation support instructions
1803 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1804 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1805 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1806 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1807 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1809 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1810 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1811 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1812 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1814 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1816 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1817 "push{q}\t%fs", []>, TB;
1818 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1819 "push{q}\t%gs", []>, TB;
1821 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1822 "pop{q}\t%fs", []>, TB;
1823 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1824 "pop{q}\t%gs", []>, TB;
1826 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1827 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1828 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1829 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1830 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1831 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1833 // Specialized register support
1835 // no m form encodable; use SMSW16m
1836 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1837 "smsw{q}\t$dst", []>, TB;
1839 // String manipulation instructions
1841 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1843 //===----------------------------------------------------------------------===//
1844 // Non-Instruction Patterns
1845 //===----------------------------------------------------------------------===//
1847 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1848 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1849 // 'movabs' predicate should handle this sort of thing.
1850 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1851 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1852 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1853 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1854 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1855 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1856 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1857 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1858 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1859 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1861 // In static codegen with small code model, we can get the address of a label
1862 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1863 // the MOV64ri64i32 should accept these.
1864 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1865 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1866 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1867 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1868 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1869 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1870 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1871 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1872 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1873 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1875 // In kernel code model, we can get the address of a label
1876 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1877 // the MOV64ri32 should accept these.
1878 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1879 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1880 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1881 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1882 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1883 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1884 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1885 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1886 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1887 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1889 // If we have small model and -static mode, it is safe to store global addresses
1890 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1891 // for MOV64mi32 should handle this sort of thing.
1892 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1893 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1894 Requires<[NearData, IsStatic]>;
1895 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1896 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1897 Requires<[NearData, IsStatic]>;
1898 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1899 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1900 Requires<[NearData, IsStatic]>;
1901 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1902 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1903 Requires<[NearData, IsStatic]>;
1904 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1905 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1906 Requires<[NearData, IsStatic]>;
1909 // Direct PC relative function call for small code model. 32-bit displacement
1910 // sign extended to 64-bit.
1911 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1912 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1913 def : Pat<(X86call (i64 texternalsym:$dst)),
1914 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1916 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1917 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1918 def : Pat<(X86call (i64 texternalsym:$dst)),
1919 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1922 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
1923 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
1924 Requires<[In64BitMode]>;
1926 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1927 (TCRETURNmi64 addr:$dst, imm:$off)>,
1928 Requires<[In64BitMode]>;
1930 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1931 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1932 Requires<[In64BitMode]>;
1934 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1935 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1936 Requires<[In64BitMode]>;
1940 // TEST R,R is smaller than CMP R,0
1941 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1942 (TEST64rr GR64:$src1, GR64:$src1)>;
1944 // Conditional moves with folded loads with operands swapped and conditions
1946 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1947 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1948 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1949 (CMOVB64rm GR64:$src2, addr:$src1)>;
1950 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1951 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1952 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1953 (CMOVE64rm GR64:$src2, addr:$src1)>;
1954 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1955 (CMOVA64rm GR64:$src2, addr:$src1)>;
1956 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1957 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1958 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1959 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1960 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1961 (CMOVL64rm GR64:$src2, addr:$src1)>;
1962 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1963 (CMOVG64rm GR64:$src2, addr:$src1)>;
1964 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1965 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1966 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1967 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1968 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1969 (CMOVP64rm GR64:$src2, addr:$src1)>;
1970 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1971 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1972 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1973 (CMOVS64rm GR64:$src2, addr:$src1)>;
1974 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1975 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1976 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1977 (CMOVO64rm GR64:$src2, addr:$src1)>;
1979 // zextload bool -> zextload byte
1980 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1983 // When extloading from 16-bit and smaller memory locations into 64-bit
1984 // registers, use zero-extending loads so that the entire 64-bit register is
1985 // defined, avoiding partial-register updates.
1986 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1987 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1988 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1989 // For other extloads, use subregs, since the high contents of the register are
1990 // defined after an extload.
1991 def : Pat<(extloadi64i32 addr:$src),
1992 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1995 // anyext. Define these to do an explicit zero-extend to
1996 // avoid partial-register updates.
1997 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1998 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1999 def : Pat<(i64 (anyext GR32:$src)),
2000 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
2002 //===----------------------------------------------------------------------===//
2004 //===----------------------------------------------------------------------===//
2006 // Odd encoding trick: -128 fits into an 8-bit immediate field while
2007 // +128 doesn't, so in this special case use a sub instead of an add.
2008 def : Pat<(add GR64:$src1, 128),
2009 (SUB64ri8 GR64:$src1, -128)>;
2010 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
2011 (SUB64mi8 addr:$dst, -128)>;
2013 // The same trick applies for 32-bit immediate fields in 64-bit
2015 def : Pat<(add GR64:$src1, 0x0000000080000000),
2016 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
2017 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
2018 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
2020 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
2021 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
2022 // materialize that immediate in a register first.
2023 def : Pat<(and GR64:$src, i64immZExt32:$imm),
2027 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit),
2028 (i32 (GetLo32XForm imm:$imm))),
2031 // r & (2^32-1) ==> movz
2032 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
2033 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2034 // r & (2^16-1) ==> movz
2035 def : Pat<(and GR64:$src, 0xffff),
2036 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
2037 // r & (2^8-1) ==> movz
2038 def : Pat<(and GR64:$src, 0xff),
2039 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
2040 // r & (2^8-1) ==> movz
2041 def : Pat<(and GR32:$src1, 0xff),
2042 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
2043 Requires<[In64BitMode]>;
2044 // r & (2^8-1) ==> movz
2045 def : Pat<(and GR16:$src1, 0xff),
2046 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
2047 Requires<[In64BitMode]>;
2049 // sext_inreg patterns
2050 def : Pat<(sext_inreg GR64:$src, i32),
2051 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2052 def : Pat<(sext_inreg GR64:$src, i16),
2053 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2054 def : Pat<(sext_inreg GR64:$src, i8),
2055 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
2056 def : Pat<(sext_inreg GR32:$src, i8),
2057 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
2058 Requires<[In64BitMode]>;
2059 def : Pat<(sext_inreg GR16:$src, i8),
2060 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
2061 Requires<[In64BitMode]>;
2064 def : Pat<(i32 (trunc GR64:$src)),
2065 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
2066 def : Pat<(i16 (trunc GR64:$src)),
2067 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
2068 def : Pat<(i8 (trunc GR64:$src)),
2069 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
2070 def : Pat<(i8 (trunc GR32:$src)),
2071 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
2072 Requires<[In64BitMode]>;
2073 def : Pat<(i8 (trunc GR16:$src)),
2074 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
2075 Requires<[In64BitMode]>;
2077 // h-register tricks.
2078 // For now, be conservative on x86-64 and use an h-register extract only if the
2079 // value is immediately zero-extended or stored, which are somewhat common
2080 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
2081 // from being allocated in the same instruction as the h register, as there's
2082 // currently no way to describe this requirement to the register allocator.
2084 // h-register extract and zero-extend.
2085 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2089 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2090 x86_subreg_8bit_hi)),
2092 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2094 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2095 x86_subreg_8bit_hi))>,
2096 Requires<[In64BitMode]>;
2097 def : Pat<(srl GR16:$src, (i8 8)),
2100 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2101 x86_subreg_8bit_hi)),
2103 Requires<[In64BitMode]>;
2104 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2106 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2107 x86_subreg_8bit_hi))>,
2108 Requires<[In64BitMode]>;
2109 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2111 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2112 x86_subreg_8bit_hi))>,
2113 Requires<[In64BitMode]>;
2114 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2118 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2119 x86_subreg_8bit_hi)),
2121 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2125 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2126 x86_subreg_8bit_hi)),
2129 // h-register extract and store.
2130 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2133 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2134 x86_subreg_8bit_hi))>;
2135 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2138 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2139 x86_subreg_8bit_hi))>,
2140 Requires<[In64BitMode]>;
2141 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2144 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2145 x86_subreg_8bit_hi))>,
2146 Requires<[In64BitMode]>;
2148 // (shl x, 1) ==> (add x, x)
2149 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2151 // (shl x (and y, 63)) ==> (shl x, y)
2152 def : Pat<(shl GR64:$src1, (and CL, 63)),
2153 (SHL64rCL GR64:$src1)>;
2154 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2155 (SHL64mCL addr:$dst)>;
2157 def : Pat<(srl GR64:$src1, (and CL, 63)),
2158 (SHR64rCL GR64:$src1)>;
2159 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2160 (SHR64mCL addr:$dst)>;
2162 def : Pat<(sra GR64:$src1, (and CL, 63)),
2163 (SAR64rCL GR64:$src1)>;
2164 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2165 (SAR64mCL addr:$dst)>;
2167 // Double shift patterns
2168 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2169 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2171 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
2172 GR64:$src2, (i8 imm)), addr:$dst),
2173 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2175 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2176 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2178 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
2179 GR64:$src2, (i8 imm)), addr:$dst),
2180 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2182 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2183 let AddedComplexity = 5 in { // Try this before the selecting to OR
2184 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt8:$src2),
2186 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2187 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt32:$src2),
2189 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2190 def : Pat<(parallel (or_is_add GR64:$src1, GR64:$src2),
2192 (ADD64rr GR64:$src1, GR64:$src2)>;
2193 } // AddedComplexity
2195 // X86 specific add which produces a flag.
2196 def : Pat<(addc GR64:$src1, GR64:$src2),
2197 (ADD64rr GR64:$src1, GR64:$src2)>;
2198 def : Pat<(addc GR64:$src1, (load addr:$src2)),
2199 (ADD64rm GR64:$src1, addr:$src2)>;
2200 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2201 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2202 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2203 (ADD64ri32 GR64:$src1, imm:$src2)>;
2205 def : Pat<(subc GR64:$src1, GR64:$src2),
2206 (SUB64rr GR64:$src1, GR64:$src2)>;
2207 def : Pat<(subc GR64:$src1, (load addr:$src2)),
2208 (SUB64rm GR64:$src1, addr:$src2)>;
2209 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2210 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2211 def : Pat<(subc GR64:$src1, imm:$src2),
2212 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2214 //===----------------------------------------------------------------------===//
2215 // EFLAGS-defining Patterns
2216 //===----------------------------------------------------------------------===//
2218 // Register-Register Addition with EFLAGS result
2219 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
2221 (ADD64rr GR64:$src1, GR64:$src2)>;
2223 // Register-Integer Addition with EFLAGS result
2224 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
2226 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2227 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
2229 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2231 // Register-Memory Addition with EFLAGS result
2232 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
2234 (ADD64rm GR64:$src1, addr:$src2)>;
2236 // Memory-Register Addition with EFLAGS result
2237 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
2240 (ADD64mr addr:$dst, GR64:$src2)>;
2241 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2244 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
2245 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
2246 i64immSExt32:$src2),
2249 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
2251 // Register-Register Subtraction with EFLAGS result
2252 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
2254 (SUB64rr GR64:$src1, GR64:$src2)>;
2256 // Register-Memory Subtraction with EFLAGS result
2257 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
2259 (SUB64rm GR64:$src1, addr:$src2)>;
2261 // Register-Integer Subtraction with EFLAGS result
2262 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
2264 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2265 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
2267 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2269 // Memory-Register Subtraction with EFLAGS result
2270 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
2273 (SUB64mr addr:$dst, GR64:$src2)>;
2275 // Memory-Integer Subtraction with EFLAGS result
2276 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2280 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2281 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2282 i64immSExt32:$src2),
2285 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
2287 // Register-Register Signed Integer Multiplication with EFLAGS result
2288 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
2290 (IMUL64rr GR64:$src1, GR64:$src2)>;
2292 // Register-Memory Signed Integer Multiplication with EFLAGS result
2293 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
2295 (IMUL64rm GR64:$src1, addr:$src2)>;
2297 // Register-Integer Signed Integer Multiplication with EFLAGS result
2298 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2300 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2301 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2303 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2305 // Memory-Integer Signed Integer Multiplication with EFLAGS result
2306 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2308 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2309 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2311 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2313 // INC and DEC with EFLAGS result. Note that these do not set CF.
2314 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2315 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2316 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2318 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2319 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2320 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2321 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2323 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2325 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2326 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2327 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2329 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2330 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2331 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2332 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2334 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2336 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2337 (INC64r GR64:$src)>;
2338 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2340 (INC64m addr:$dst)>;
2341 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2342 (DEC64r GR64:$src)>;
2343 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2345 (DEC64m addr:$dst)>;
2347 // Register-Register Logical Or with EFLAGS result
2348 def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2350 (OR64rr GR64:$src1, GR64:$src2)>;
2352 // Register-Integer Logical Or with EFLAGS result
2353 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2355 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2356 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2358 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2360 // Register-Memory Logical Or with EFLAGS result
2361 def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2363 (OR64rm GR64:$src1, addr:$src2)>;
2365 // Memory-Register Logical Or with EFLAGS result
2366 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2369 (OR64mr addr:$dst, GR64:$src2)>;
2370 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2373 (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2374 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2377 (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2379 // Register-Register Logical XOr with EFLAGS result
2380 def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2382 (XOR64rr GR64:$src1, GR64:$src2)>;
2384 // Register-Integer Logical XOr with EFLAGS result
2385 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2387 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2388 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2390 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2392 // Register-Memory Logical XOr with EFLAGS result
2393 def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2395 (XOR64rm GR64:$src1, addr:$src2)>;
2397 // Memory-Register Logical XOr with EFLAGS result
2398 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2401 (XOR64mr addr:$dst, GR64:$src2)>;
2402 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2405 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2406 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
2407 i64immSExt32:$src2),
2410 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2412 // Register-Register Logical And with EFLAGS result
2413 def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2415 (AND64rr GR64:$src1, GR64:$src2)>;
2417 // Register-Integer Logical And with EFLAGS result
2418 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2420 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2421 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2423 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2425 // Register-Memory Logical And with EFLAGS result
2426 def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2428 (AND64rm GR64:$src1, addr:$src2)>;
2430 // Memory-Register Logical And with EFLAGS result
2431 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2434 (AND64mr addr:$dst, GR64:$src2)>;
2435 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2438 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2439 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
2440 i64immSExt32:$src2),
2443 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2445 //===----------------------------------------------------------------------===//
2446 // X86-64 SSE Instructions
2447 //===----------------------------------------------------------------------===//
2449 // Move instructions...
2451 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2452 "mov{d|q}\t{$src, $dst|$dst, $src}",
2454 (v2i64 (scalar_to_vector GR64:$src)))]>;
2455 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2456 "mov{d|q}\t{$src, $dst|$dst, $src}",
2457 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2460 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2461 "mov{d|q}\t{$src, $dst|$dst, $src}",
2462 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2463 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2464 "movq\t{$src, $dst|$dst, $src}",
2465 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2467 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2468 "mov{d|q}\t{$src, $dst|$dst, $src}",
2469 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2470 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2471 "movq\t{$src, $dst|$dst, $src}",
2472 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2474 //===----------------------------------------------------------------------===//
2475 // X86-64 SSE4.1 Instructions
2476 //===----------------------------------------------------------------------===//
2478 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2479 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2480 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2481 (ins VR128:$src1, i32i8imm:$src2),
2482 !strconcat(OpcodeStr,
2483 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2485 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2486 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2487 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2488 !strconcat(OpcodeStr,
2489 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2490 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2491 addr:$dst)]>, OpSize, REX_W;
2494 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2496 let isTwoAddress = 1 in {
2497 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2498 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2499 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2500 !strconcat(OpcodeStr,
2501 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2503 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2505 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2506 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2507 !strconcat(OpcodeStr,
2508 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2510 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2511 imm:$src3)))]>, OpSize, REX_W;
2515 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2517 // -disable-16bit support.
2518 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
2519 (MOV16mi addr:$dst, imm:$src)>;
2520 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2521 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2522 def : Pat<(i64 (sextloadi16 addr:$dst)),
2523 (MOVSX64rm16 addr:$dst)>;
2524 def : Pat<(i64 (zextloadi16 addr:$dst)),
2525 (MOVZX64rm16 addr:$dst)>;
2526 def : Pat<(i64 (extloadi16 addr:$dst)),
2527 (MOVZX64rm16 addr:$dst)>;