1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64>;
33 def lea64mem : Operand<i64> {
34 let PrintMethod = "printlea64mem";
35 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
38 def lea64_32mem : Operand<i32> {
39 let PrintMethod = "printlea64_32mem";
40 let AsmOperandLowerMethod = "lower_lea64_32mem";
41 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
44 //===----------------------------------------------------------------------===//
45 // Complex Pattern Definitions.
47 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
48 [add, sub, mul, X86mul_imm, shl, or, frameindex,
51 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
52 [tglobaltlsaddr], []>;
54 //===----------------------------------------------------------------------===//
58 def i64immSExt8 : PatLeaf<(i64 imm), [{
59 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
60 // sign extended field.
61 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
64 def i64immSExt32 : PatLeaf<(i64 imm), [{
65 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
66 // sign extended field.
67 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
70 def i64immZExt32 : PatLeaf<(i64 imm), [{
71 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
72 // unsignedsign extended field.
73 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
76 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
77 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
78 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
80 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
81 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
82 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
83 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
85 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
86 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
87 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
88 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
90 //===----------------------------------------------------------------------===//
91 // Instruction list...
94 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
95 // a stack adjustment and the codegen must know that they may modify the stack
96 // pointer before prolog-epilog rewriting occurs.
97 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
98 // sub / add which can clobber EFLAGS.
99 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
100 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
102 [(X86callseq_start timm:$amt)]>,
103 Requires<[In64BitMode]>;
104 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
106 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
107 Requires<[In64BitMode]>;
110 //===----------------------------------------------------------------------===//
111 // Call Instructions...
114 // All calls clobber the non-callee saved registers. RSP is marked as
115 // a use to prevent stack-pointer assignments that appear immediately
116 // before calls from potentially appearing dead. Uses for argument
117 // registers are added manually.
118 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
119 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
120 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
121 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
122 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
125 // NOTE: this pattern doesn't match "X86call imm", because we do not know
126 // that the offset between an arbitrary immediate and the call will fit in
127 // the 32-bit pcrel field that we have.
128 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
129 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
131 Requires<[In64BitMode, NotWin64]>;
132 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
133 "call\t{*}$dst", [(X86call GR64:$dst)]>,
134 Requires<[NotWin64]>;
135 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
136 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
137 Requires<[NotWin64]>;
140 // FIXME: We need to teach codegen about single list of call-clobbered registers.
142 // All calls clobber the non-callee saved registers. RSP is marked as
143 // a use to prevent stack-pointer assignments that appear immediately
144 // before calls from potentially appearing dead. Uses for argument
145 // registers are added manually.
146 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
147 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
148 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
149 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
151 def WINCALL64pcrel32 : I<0xE8, RawFrm,
152 (outs), (ins i64i32imm:$dst, variable_ops),
153 "call\t${dst:call}", [(X86call imm:$dst)]>,
155 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
157 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
158 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
160 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
164 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
165 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
167 "#TC_RETURN $dst $offset",
170 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
171 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
173 "#TC_RETURN $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
179 "jmp{q}\t{*}$dst # TAILCALL",
183 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
184 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
185 [(brind GR64:$dst)]>;
186 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
187 [(brind (loadi64 addr:$dst))]>;
190 //===----------------------------------------------------------------------===//
191 // EH Pseudo Instructions
193 let isTerminator = 1, isReturn = 1, isBarrier = 1,
195 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
196 "ret\t#eh_return, addr: $addr",
197 [(X86ehret GR64:$addr)]>;
201 //===----------------------------------------------------------------------===//
202 // Miscellaneous Instructions...
204 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
205 def LEAVE64 : I<0xC9, RawFrm,
206 (outs), (ins), "leave", []>;
207 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
209 def POP64r : I<0x58, AddRegFrm,
210 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
212 def PUSH64r : I<0x50, AddRegFrm,
213 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
217 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
218 "push{q}\t$imm", []>;
219 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
220 "push{q}\t$imm", []>;
221 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
222 "push{q}\t$imm", []>;
225 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
226 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
227 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
228 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
230 def LEA64_32r : I<0x8D, MRMSrcMem,
231 (outs GR32:$dst), (ins lea64_32mem:$src),
232 "lea{l}\t{$src|$dst}, {$dst|$src}",
233 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
235 let isReMaterializable = 1 in
236 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
237 "lea{q}\t{$src|$dst}, {$dst|$src}",
238 [(set GR64:$dst, lea64addr:$src)]>;
240 let isTwoAddress = 1 in
241 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
243 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
245 // Bit scan instructions.
246 let Defs = [EFLAGS] in {
247 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
248 "bsf{q}\t{$src, $dst|$dst, $src}",
249 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
250 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
251 "bsf{q}\t{$src, $dst|$dst, $src}",
252 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
253 (implicit EFLAGS)]>, TB;
255 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
256 "bsr{q}\t{$src, $dst|$dst, $src}",
257 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
258 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
259 "bsr{q}\t{$src, $dst|$dst, $src}",
260 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
261 (implicit EFLAGS)]>, TB;
265 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
266 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
267 [(X86rep_movs i64)]>, REP;
268 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
269 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
270 [(X86rep_stos i64)]>, REP;
272 // Fast system-call instructions
273 def SYSCALL : I<0x05, RawFrm,
274 (outs), (ins), "syscall", []>, TB;
275 def SYSENTER : I<0x34, RawFrm,
276 (outs), (ins), "sysenter", []>, TB;
277 def SYSEXIT : I<0x35, RawFrm,
278 (outs), (ins), "sysexit", []>, TB;
279 def SYSEXIT64 : RI<0x35, RawFrm,
280 (outs), (ins), "sysexit", []>, TB;
281 def SYSRET : I<0x07, RawFrm,
282 (outs), (ins), "sysret", []>, TB;
284 //===----------------------------------------------------------------------===//
285 // Move Instructions...
288 let neverHasSideEffects = 1 in
289 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
290 "mov{q}\t{$src, $dst|$dst, $src}", []>;
292 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
293 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
294 "movabs{q}\t{$src, $dst|$dst, $src}",
295 [(set GR64:$dst, imm:$src)]>;
296 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
297 "mov{q}\t{$src, $dst|$dst, $src}",
298 [(set GR64:$dst, i64immSExt32:$src)]>;
301 let canFoldAsLoad = 1 in
302 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
303 "mov{q}\t{$src, $dst|$dst, $src}",
304 [(set GR64:$dst, (load addr:$src))]>;
306 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
307 "mov{q}\t{$src, $dst|$dst, $src}",
308 [(store GR64:$src, addr:$dst)]>;
309 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
310 "mov{q}\t{$src, $dst|$dst, $src}",
311 [(store i64immSExt32:$src, addr:$dst)]>;
313 // Sign/Zero extenders
315 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
316 // operand, which makes it a rare instruction with an 8-bit register
317 // operand that can never access an h register. If support for h registers
318 // were generalized, this would require a special register class.
319 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
320 "movs{bq|x}\t{$src, $dst|$dst, $src}",
321 [(set GR64:$dst, (sext GR8:$src))]>, TB;
322 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
323 "movs{bq|x}\t{$src, $dst|$dst, $src}",
324 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
325 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
326 "movs{wq|x}\t{$src, $dst|$dst, $src}",
327 [(set GR64:$dst, (sext GR16:$src))]>, TB;
328 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
329 "movs{wq|x}\t{$src, $dst|$dst, $src}",
330 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
331 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
332 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
333 [(set GR64:$dst, (sext GR32:$src))]>;
334 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
335 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
336 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
338 // Use movzbl instead of movzbq when the destination is a register; it's
339 // equivalent due to implicit zero-extending, and it has a smaller encoding.
340 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
341 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
342 [(set GR64:$dst, (zext GR8:$src))]>, TB;
343 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
344 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
345 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
346 // Use movzwl instead of movzwq when the destination is a register; it's
347 // equivalent due to implicit zero-extending, and it has a smaller encoding.
348 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
349 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
350 [(set GR64:$dst, (zext GR16:$src))]>, TB;
351 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
352 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
353 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
355 // There's no movzlq instruction, but movl can be used for this purpose, using
356 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
357 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
358 // zero-extension, however this isn't possible when the 32-bit value is
359 // defined by a truncate or is copied from something where the high bits aren't
360 // necessarily all zero. In such cases, we fall back to these explicit zext
362 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
363 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
364 [(set GR64:$dst, (zext GR32:$src))]>;
365 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
366 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
367 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
369 // Any instruction that defines a 32-bit result leaves the high half of the
370 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
371 // be copying from a truncate, but any other 32-bit operation will zero-extend
373 def def32 : PatLeaf<(i32 GR32:$src), [{
374 return N->getOpcode() != ISD::TRUNCATE &&
375 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
376 N->getOpcode() != ISD::CopyFromReg;
379 // In the case of a 32-bit def that is known to implicitly zero-extend,
380 // we can use a SUBREG_TO_REG.
381 def : Pat<(i64 (zext def32:$src)),
382 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
384 let neverHasSideEffects = 1 in {
385 let Defs = [RAX], Uses = [EAX] in
386 def CDQE : RI<0x98, RawFrm, (outs), (ins),
387 "{cltq|cdqe}", []>; // RAX = signext(EAX)
389 let Defs = [RAX,RDX], Uses = [RAX] in
390 def CQO : RI<0x99, RawFrm, (outs), (ins),
391 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
394 //===----------------------------------------------------------------------===//
395 // Arithmetic Instructions...
398 let Defs = [EFLAGS] in {
399 let isTwoAddress = 1 in {
400 let isConvertibleToThreeAddress = 1 in {
401 let isCommutable = 1 in
402 // Register-Register Addition
403 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
404 "add{q}\t{$src2, $dst|$dst, $src2}",
405 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
408 // Register-Integer Addition
409 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
410 "add{q}\t{$src2, $dst|$dst, $src2}",
411 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
413 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
414 "add{q}\t{$src2, $dst|$dst, $src2}",
415 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
417 } // isConvertibleToThreeAddress
419 // Register-Memory Addition
420 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
421 "add{q}\t{$src2, $dst|$dst, $src2}",
422 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
426 // Memory-Register Addition
427 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
428 "add{q}\t{$src2, $dst|$dst, $src2}",
429 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
431 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
432 "add{q}\t{$src2, $dst|$dst, $src2}",
433 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
435 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
436 "add{q}\t{$src2, $dst|$dst, $src2}",
437 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
440 let Uses = [EFLAGS] in {
441 let isTwoAddress = 1 in {
442 let isCommutable = 1 in
443 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
444 "adc{q}\t{$src2, $dst|$dst, $src2}",
445 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
447 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
448 "adc{q}\t{$src2, $dst|$dst, $src2}",
449 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
451 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
452 "adc{q}\t{$src2, $dst|$dst, $src2}",
453 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
454 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
455 "adc{q}\t{$src2, $dst|$dst, $src2}",
456 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
459 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
460 "adc{q}\t{$src2, $dst|$dst, $src2}",
461 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
462 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
463 "adc{q}\t{$src2, $dst|$dst, $src2}",
464 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
465 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
466 "adc{q}\t{$src2, $dst|$dst, $src2}",
467 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
470 let isTwoAddress = 1 in {
471 // Register-Register Subtraction
472 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
473 "sub{q}\t{$src2, $dst|$dst, $src2}",
474 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
477 // Register-Memory Subtraction
478 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
479 "sub{q}\t{$src2, $dst|$dst, $src2}",
480 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
483 // Register-Integer Subtraction
484 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
485 (ins GR64:$src1, i64i8imm:$src2),
486 "sub{q}\t{$src2, $dst|$dst, $src2}",
487 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
489 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
490 (ins GR64:$src1, i64i32imm:$src2),
491 "sub{q}\t{$src2, $dst|$dst, $src2}",
492 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
496 // Memory-Register Subtraction
497 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
498 "sub{q}\t{$src2, $dst|$dst, $src2}",
499 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
502 // Memory-Integer Subtraction
503 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
504 "sub{q}\t{$src2, $dst|$dst, $src2}",
505 [(store (sub (load addr:$dst), i64immSExt8:$src2),
508 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
509 "sub{q}\t{$src2, $dst|$dst, $src2}",
510 [(store (sub (load addr:$dst), i64immSExt32:$src2),
514 let Uses = [EFLAGS] in {
515 let isTwoAddress = 1 in {
516 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
517 "sbb{q}\t{$src2, $dst|$dst, $src2}",
518 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
520 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
521 "sbb{q}\t{$src2, $dst|$dst, $src2}",
522 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
524 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
525 "sbb{q}\t{$src2, $dst|$dst, $src2}",
526 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
527 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
528 "sbb{q}\t{$src2, $dst|$dst, $src2}",
529 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
532 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
533 "sbb{q}\t{$src2, $dst|$dst, $src2}",
534 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
535 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
536 "sbb{q}\t{$src2, $dst|$dst, $src2}",
537 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
538 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
539 "sbb{q}\t{$src2, $dst|$dst, $src2}",
540 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
544 // Unsigned multiplication
545 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
546 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
547 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
549 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
550 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
552 // Signed multiplication
553 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
554 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
556 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
557 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
560 let Defs = [EFLAGS] in {
561 let isTwoAddress = 1 in {
562 let isCommutable = 1 in
563 // Register-Register Signed Integer Multiplication
564 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
565 (ins GR64:$src1, GR64:$src2),
566 "imul{q}\t{$src2, $dst|$dst, $src2}",
567 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
568 (implicit EFLAGS)]>, TB;
570 // Register-Memory Signed Integer Multiplication
571 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
572 (ins GR64:$src1, i64mem:$src2),
573 "imul{q}\t{$src2, $dst|$dst, $src2}",
574 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
575 (implicit EFLAGS)]>, TB;
578 // Suprisingly enough, these are not two address instructions!
580 // Register-Integer Signed Integer Multiplication
581 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
582 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
583 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
584 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
586 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
587 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
588 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
589 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
592 // Memory-Integer Signed Integer Multiplication
593 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
594 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
595 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
596 [(set GR64:$dst, (mul (load addr:$src1),
599 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
600 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
601 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
602 [(set GR64:$dst, (mul (load addr:$src1),
603 i64immSExt32:$src2)),
607 // Unsigned division / remainder
608 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
609 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
611 // Signed division / remainder
612 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
613 "idiv{q}\t$src", []>;
615 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
617 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
618 "idiv{q}\t$src", []>;
622 // Unary instructions
623 let Defs = [EFLAGS], CodeSize = 2 in {
624 let isTwoAddress = 1 in
625 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
626 [(set GR64:$dst, (ineg GR64:$src)),
628 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
629 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
632 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
633 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
634 [(set GR64:$dst, (add GR64:$src, 1)),
636 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
637 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
640 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
641 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
642 [(set GR64:$dst, (add GR64:$src, -1)),
644 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
645 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
648 // In 64-bit mode, single byte INC and DEC cannot be encoded.
649 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
650 // Can transform into LEA.
651 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
652 [(set GR16:$dst, (add GR16:$src, 1)),
654 OpSize, Requires<[In64BitMode]>;
655 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
656 [(set GR32:$dst, (add GR32:$src, 1)),
658 Requires<[In64BitMode]>;
659 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
660 [(set GR16:$dst, (add GR16:$src, -1)),
662 OpSize, Requires<[In64BitMode]>;
663 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
664 [(set GR32:$dst, (add GR32:$src, -1)),
666 Requires<[In64BitMode]>;
667 } // isConvertibleToThreeAddress
669 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
670 // how to unfold them.
671 let isTwoAddress = 0, CodeSize = 2 in {
672 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
673 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
675 OpSize, Requires<[In64BitMode]>;
676 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
677 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
679 Requires<[In64BitMode]>;
680 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
681 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
683 OpSize, Requires<[In64BitMode]>;
684 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
685 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
687 Requires<[In64BitMode]>;
689 } // Defs = [EFLAGS], CodeSize
692 let Defs = [EFLAGS] in {
693 // Shift instructions
694 let isTwoAddress = 1 in {
696 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
697 "shl{q}\t{%cl, $dst|$dst, %CL}",
698 [(set GR64:$dst, (shl GR64:$src, CL))]>;
699 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
700 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
701 "shl{q}\t{$src2, $dst|$dst, $src2}",
702 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
703 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
708 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
709 "shl{q}\t{%cl, $dst|$dst, %CL}",
710 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
711 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
712 "shl{q}\t{$src, $dst|$dst, $src}",
713 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
714 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
716 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
718 let isTwoAddress = 1 in {
720 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
721 "shr{q}\t{%cl, $dst|$dst, %CL}",
722 [(set GR64:$dst, (srl GR64:$src, CL))]>;
723 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
724 "shr{q}\t{$src2, $dst|$dst, $src2}",
725 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
726 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
728 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
732 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
733 "shr{q}\t{%cl, $dst|$dst, %CL}",
734 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
735 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
736 "shr{q}\t{$src, $dst|$dst, $src}",
737 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
738 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
740 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
742 let isTwoAddress = 1 in {
744 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
745 "sar{q}\t{%cl, $dst|$dst, %CL}",
746 [(set GR64:$dst, (sra GR64:$src, CL))]>;
747 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
748 "sar{q}\t{$src2, $dst|$dst, $src2}",
749 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
750 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
752 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
756 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
757 "sar{q}\t{%cl, $dst|$dst, %CL}",
758 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
759 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
760 "sar{q}\t{$src, $dst|$dst, $src}",
761 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
762 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
764 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
766 // Rotate instructions
767 let isTwoAddress = 1 in {
769 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
770 "rol{q}\t{%cl, $dst|$dst, %CL}",
771 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
772 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
773 "rol{q}\t{$src2, $dst|$dst, $src2}",
774 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
775 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
777 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
781 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
782 "rol{q}\t{%cl, $dst|$dst, %CL}",
783 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
784 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
785 "rol{q}\t{$src, $dst|$dst, $src}",
786 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
787 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
789 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
791 let isTwoAddress = 1 in {
793 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
794 "ror{q}\t{%cl, $dst|$dst, %CL}",
795 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
796 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
797 "ror{q}\t{$src2, $dst|$dst, $src2}",
798 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
799 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
801 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
805 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
806 "ror{q}\t{%cl, $dst|$dst, %CL}",
807 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
808 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
809 "ror{q}\t{$src, $dst|$dst, $src}",
810 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
811 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
813 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
815 // Double shift instructions (generalizations of rotate)
816 let isTwoAddress = 1 in {
818 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
819 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
820 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
821 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
822 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
823 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
826 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
827 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
828 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
829 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
830 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
833 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
834 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
835 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
836 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
843 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
844 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
845 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
847 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
848 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
849 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
852 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
853 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
854 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
855 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
856 (i8 imm:$src3)), addr:$dst)]>,
858 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
859 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
860 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
861 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
862 (i8 imm:$src3)), addr:$dst)]>,
866 //===----------------------------------------------------------------------===//
867 // Logical Instructions...
870 let isTwoAddress = 1 , AddedComplexity = 15 in
871 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
872 [(set GR64:$dst, (not GR64:$src))]>;
873 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
874 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
876 let Defs = [EFLAGS] in {
877 let isTwoAddress = 1 in {
878 let isCommutable = 1 in
879 def AND64rr : RI<0x21, MRMDestReg,
880 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
881 "and{q}\t{$src2, $dst|$dst, $src2}",
882 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
884 def AND64rm : RI<0x23, MRMSrcMem,
885 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
886 "and{q}\t{$src2, $dst|$dst, $src2}",
887 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
889 def AND64ri8 : RIi8<0x83, MRM4r,
890 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
891 "and{q}\t{$src2, $dst|$dst, $src2}",
892 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
894 def AND64ri32 : RIi32<0x81, MRM4r,
895 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
896 "and{q}\t{$src2, $dst|$dst, $src2}",
897 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
901 def AND64mr : RI<0x21, MRMDestMem,
902 (outs), (ins i64mem:$dst, GR64:$src),
903 "and{q}\t{$src, $dst|$dst, $src}",
904 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
906 def AND64mi8 : RIi8<0x83, MRM4m,
907 (outs), (ins i64mem:$dst, i64i8imm :$src),
908 "and{q}\t{$src, $dst|$dst, $src}",
909 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
911 def AND64mi32 : RIi32<0x81, MRM4m,
912 (outs), (ins i64mem:$dst, i64i32imm:$src),
913 "and{q}\t{$src, $dst|$dst, $src}",
914 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
917 let isTwoAddress = 1 in {
918 let isCommutable = 1 in
919 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
920 "or{q}\t{$src2, $dst|$dst, $src2}",
921 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
923 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
924 "or{q}\t{$src2, $dst|$dst, $src2}",
925 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
927 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
928 "or{q}\t{$src2, $dst|$dst, $src2}",
929 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
931 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
932 "or{q}\t{$src2, $dst|$dst, $src2}",
933 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
937 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
938 "or{q}\t{$src, $dst|$dst, $src}",
939 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
941 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
942 "or{q}\t{$src, $dst|$dst, $src}",
943 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
945 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
946 "or{q}\t{$src, $dst|$dst, $src}",
947 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
950 let isTwoAddress = 1 in {
951 let isCommutable = 1 in
952 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
953 "xor{q}\t{$src2, $dst|$dst, $src2}",
954 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
956 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
957 "xor{q}\t{$src2, $dst|$dst, $src2}",
958 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
960 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
961 "xor{q}\t{$src2, $dst|$dst, $src2}",
962 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
964 def XOR64ri32 : RIi32<0x81, MRM6r,
965 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
966 "xor{q}\t{$src2, $dst|$dst, $src2}",
967 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
971 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
972 "xor{q}\t{$src, $dst|$dst, $src}",
973 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
975 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
976 "xor{q}\t{$src, $dst|$dst, $src}",
977 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
979 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
980 "xor{q}\t{$src, $dst|$dst, $src}",
981 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
985 //===----------------------------------------------------------------------===//
986 // Comparison Instructions...
989 // Integer comparison
990 let Defs = [EFLAGS] in {
991 let isCommutable = 1 in
992 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
993 "test{q}\t{$src2, $src1|$src1, $src2}",
994 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
996 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
997 "test{q}\t{$src2, $src1|$src1, $src2}",
998 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1000 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1001 (ins GR64:$src1, i64i32imm:$src2),
1002 "test{q}\t{$src2, $src1|$src1, $src2}",
1003 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1004 (implicit EFLAGS)]>;
1005 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1006 (ins i64mem:$src1, i64i32imm:$src2),
1007 "test{q}\t{$src2, $src1|$src1, $src2}",
1008 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1009 (implicit EFLAGS)]>;
1011 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1012 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1013 [(X86cmp GR64:$src1, GR64:$src2),
1014 (implicit EFLAGS)]>;
1015 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1016 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1017 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1018 (implicit EFLAGS)]>;
1019 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1020 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1021 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1022 (implicit EFLAGS)]>;
1023 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1024 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1025 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1026 (implicit EFLAGS)]>;
1027 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1028 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1029 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1030 (implicit EFLAGS)]>;
1031 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1032 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1033 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1034 (implicit EFLAGS)]>;
1035 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1036 (ins i64mem:$src1, i64i32imm:$src2),
1037 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1038 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1039 (implicit EFLAGS)]>;
1040 } // Defs = [EFLAGS]
1043 // TODO: BTC, BTR, and BTS
1044 let Defs = [EFLAGS] in {
1045 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1046 "bt{q}\t{$src2, $src1|$src1, $src2}",
1047 [(X86bt GR64:$src1, GR64:$src2),
1048 (implicit EFLAGS)]>, TB;
1050 // Unlike with the register+register form, the memory+register form of the
1051 // bt instruction does not ignore the high bits of the index. From ISel's
1052 // perspective, this is pretty bizarre. Disable these instructions for now.
1053 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1054 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1055 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1056 // (implicit EFLAGS)]>, TB;
1058 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1059 "bt{q}\t{$src2, $src1|$src1, $src2}",
1060 [(X86bt GR64:$src1, i64immSExt8:$src2),
1061 (implicit EFLAGS)]>, TB;
1062 // Note that these instructions don't need FastBTMem because that
1063 // only applies when the other operand is in a register. When it's
1064 // an immediate, bt is still fast.
1065 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1066 "bt{q}\t{$src2, $src1|$src1, $src2}",
1067 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1068 (implicit EFLAGS)]>, TB;
1069 } // Defs = [EFLAGS]
1071 // Conditional moves
1072 let Uses = [EFLAGS], isTwoAddress = 1 in {
1073 let isCommutable = 1 in {
1074 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1075 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1076 "cmovb\t{$src2, $dst|$dst, $src2}",
1077 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1078 X86_COND_B, EFLAGS))]>, TB;
1079 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1080 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1081 "cmovae\t{$src2, $dst|$dst, $src2}",
1082 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1083 X86_COND_AE, EFLAGS))]>, TB;
1084 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1085 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1086 "cmove\t{$src2, $dst|$dst, $src2}",
1087 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1088 X86_COND_E, EFLAGS))]>, TB;
1089 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1090 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1091 "cmovne\t{$src2, $dst|$dst, $src2}",
1092 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1093 X86_COND_NE, EFLAGS))]>, TB;
1094 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1095 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1096 "cmovbe\t{$src2, $dst|$dst, $src2}",
1097 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1098 X86_COND_BE, EFLAGS))]>, TB;
1099 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1100 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1101 "cmova\t{$src2, $dst|$dst, $src2}",
1102 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1103 X86_COND_A, EFLAGS))]>, TB;
1104 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1105 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1106 "cmovl\t{$src2, $dst|$dst, $src2}",
1107 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1108 X86_COND_L, EFLAGS))]>, TB;
1109 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1110 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1111 "cmovge\t{$src2, $dst|$dst, $src2}",
1112 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1113 X86_COND_GE, EFLAGS))]>, TB;
1114 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1115 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1116 "cmovle\t{$src2, $dst|$dst, $src2}",
1117 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1118 X86_COND_LE, EFLAGS))]>, TB;
1119 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1120 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1121 "cmovg\t{$src2, $dst|$dst, $src2}",
1122 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1123 X86_COND_G, EFLAGS))]>, TB;
1124 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1125 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1126 "cmovs\t{$src2, $dst|$dst, $src2}",
1127 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1128 X86_COND_S, EFLAGS))]>, TB;
1129 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1130 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1131 "cmovns\t{$src2, $dst|$dst, $src2}",
1132 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1133 X86_COND_NS, EFLAGS))]>, TB;
1134 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1135 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1136 "cmovp\t{$src2, $dst|$dst, $src2}",
1137 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1138 X86_COND_P, EFLAGS))]>, TB;
1139 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1140 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1141 "cmovnp\t{$src2, $dst|$dst, $src2}",
1142 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1143 X86_COND_NP, EFLAGS))]>, TB;
1144 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1145 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1146 "cmovo\t{$src2, $dst|$dst, $src2}",
1147 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1148 X86_COND_O, EFLAGS))]>, TB;
1149 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1150 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1151 "cmovno\t{$src2, $dst|$dst, $src2}",
1152 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1153 X86_COND_NO, EFLAGS))]>, TB;
1154 } // isCommutable = 1
1156 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1157 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1158 "cmovb\t{$src2, $dst|$dst, $src2}",
1159 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1160 X86_COND_B, EFLAGS))]>, TB;
1161 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1162 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1163 "cmovae\t{$src2, $dst|$dst, $src2}",
1164 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1165 X86_COND_AE, EFLAGS))]>, TB;
1166 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1167 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1168 "cmove\t{$src2, $dst|$dst, $src2}",
1169 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1170 X86_COND_E, EFLAGS))]>, TB;
1171 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1172 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1173 "cmovne\t{$src2, $dst|$dst, $src2}",
1174 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1175 X86_COND_NE, EFLAGS))]>, TB;
1176 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1177 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1178 "cmovbe\t{$src2, $dst|$dst, $src2}",
1179 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1180 X86_COND_BE, EFLAGS))]>, TB;
1181 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1182 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1183 "cmova\t{$src2, $dst|$dst, $src2}",
1184 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1185 X86_COND_A, EFLAGS))]>, TB;
1186 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1187 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1188 "cmovl\t{$src2, $dst|$dst, $src2}",
1189 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1190 X86_COND_L, EFLAGS))]>, TB;
1191 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1192 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1193 "cmovge\t{$src2, $dst|$dst, $src2}",
1194 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1195 X86_COND_GE, EFLAGS))]>, TB;
1196 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1197 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1198 "cmovle\t{$src2, $dst|$dst, $src2}",
1199 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1200 X86_COND_LE, EFLAGS))]>, TB;
1201 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1202 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1203 "cmovg\t{$src2, $dst|$dst, $src2}",
1204 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1205 X86_COND_G, EFLAGS))]>, TB;
1206 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1207 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1208 "cmovs\t{$src2, $dst|$dst, $src2}",
1209 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1210 X86_COND_S, EFLAGS))]>, TB;
1211 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1212 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1213 "cmovns\t{$src2, $dst|$dst, $src2}",
1214 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1215 X86_COND_NS, EFLAGS))]>, TB;
1216 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1217 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1218 "cmovp\t{$src2, $dst|$dst, $src2}",
1219 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1220 X86_COND_P, EFLAGS))]>, TB;
1221 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1222 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1223 "cmovnp\t{$src2, $dst|$dst, $src2}",
1224 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1225 X86_COND_NP, EFLAGS))]>, TB;
1226 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1227 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1228 "cmovo\t{$src2, $dst|$dst, $src2}",
1229 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1230 X86_COND_O, EFLAGS))]>, TB;
1231 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1232 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1233 "cmovno\t{$src2, $dst|$dst, $src2}",
1234 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1235 X86_COND_NO, EFLAGS))]>, TB;
1238 //===----------------------------------------------------------------------===//
1239 // Conversion Instructions...
1242 // f64 -> signed i64
1243 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1244 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1246 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1247 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1248 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1249 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1250 (load addr:$src)))]>;
1251 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1252 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1253 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1254 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1255 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1256 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1257 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1258 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1260 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1261 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1262 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1264 (int_x86_sse2_cvttsd2si64
1265 (load addr:$src)))]>;
1267 // Signed i64 -> f64
1268 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1269 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1270 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1271 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1272 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1273 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1275 let isTwoAddress = 1 in {
1276 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1277 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1278 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1280 (int_x86_sse2_cvtsi642sd VR128:$src1,
1282 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1283 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1284 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1286 (int_x86_sse2_cvtsi642sd VR128:$src1,
1287 (loadi64 addr:$src2)))]>;
1290 // Signed i64 -> f32
1291 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1292 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1293 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1294 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1295 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1296 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1298 let isTwoAddress = 1 in {
1299 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1300 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1301 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1303 (int_x86_sse_cvtsi642ss VR128:$src1,
1305 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1306 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1307 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1309 (int_x86_sse_cvtsi642ss VR128:$src1,
1310 (loadi64 addr:$src2)))]>;
1313 // f32 -> signed i64
1314 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1315 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1317 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1318 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1319 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1320 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1321 (load addr:$src)))]>;
1322 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1323 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1324 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1325 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1326 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1327 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1328 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1329 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1331 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1332 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1333 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1335 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1337 //===----------------------------------------------------------------------===//
1338 // Alias Instructions
1339 //===----------------------------------------------------------------------===//
1341 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1342 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1344 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1345 // when we have a better way to specify isel priority.
1346 let AddedComplexity = 1 in
1348 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1351 // Materialize i64 constant where top 32-bits are zero.
1352 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1353 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1354 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1355 [(set GR64:$dst, i64immZExt32:$src)]>;
1357 //===----------------------------------------------------------------------===//
1358 // Thread Local Storage Instructions
1359 //===----------------------------------------------------------------------===//
1361 // All calls clobber the non-callee saved registers. RSP is marked as
1362 // a use to prevent stack-pointer assignments that appear immediately
1363 // before calls from potentially appearing dead.
1364 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1365 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1366 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1367 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1368 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1370 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1372 "leaq\t$sym(%rip), %rdi; "
1375 "call\t__tls_get_addr@PLT",
1376 [(X86tlsaddr tls64addr:$sym)]>,
1377 Requires<[In64BitMode]>;
1379 let AddedComplexity = 5 in
1380 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1381 "movq\t%gs:$src, $dst",
1382 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1384 let AddedComplexity = 5 in
1385 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1386 "movq\t%fs:$src, $dst",
1387 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1389 //===----------------------------------------------------------------------===//
1390 // Atomic Instructions
1391 //===----------------------------------------------------------------------===//
1393 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1394 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1396 "cmpxchgq\t$swap,$ptr",
1397 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1400 let Constraints = "$val = $dst" in {
1401 let Defs = [EFLAGS] in
1402 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1405 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1408 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1410 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1413 // Optimized codegen when the non-memory output is not used.
1414 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1415 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1417 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1418 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1419 (ins i64mem:$dst, i64i8imm :$src2),
1421 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1422 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1423 (ins i64mem:$dst, i64i32imm :$src2),
1425 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1426 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1428 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1429 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1430 (ins i64mem:$dst, i64i8imm :$src2),
1432 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1433 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1434 (ins i64mem:$dst, i64i32imm:$src2),
1436 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1437 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1439 "inc{q}\t$dst", []>, LOCK;
1440 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1442 "dec{q}\t$dst", []>, LOCK;
1444 // Atomic exchange, and, or, xor
1445 let Constraints = "$val = $dst", Defs = [EFLAGS],
1446 usesCustomDAGSchedInserter = 1 in {
1447 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1448 "#ATOMAND64 PSEUDO!",
1449 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1450 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1451 "#ATOMOR64 PSEUDO!",
1452 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1453 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1454 "#ATOMXOR64 PSEUDO!",
1455 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1456 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1457 "#ATOMNAND64 PSEUDO!",
1458 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1459 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1460 "#ATOMMIN64 PSEUDO!",
1461 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1462 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1463 "#ATOMMAX64 PSEUDO!",
1464 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1465 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1466 "#ATOMUMIN64 PSEUDO!",
1467 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1468 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1469 "#ATOMUMAX64 PSEUDO!",
1470 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1473 //===----------------------------------------------------------------------===//
1474 // Non-Instruction Patterns
1475 //===----------------------------------------------------------------------===//
1477 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1478 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1479 // 'movabs' predicate should handle this sort of thing.
1480 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1481 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1482 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1483 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1484 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1485 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1486 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1487 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1489 // In static codegen with small code model, we can get the address of a label
1490 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1491 // the MOV64ri64i32 should accept these.
1492 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1493 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1494 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1495 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1496 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1497 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1498 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1499 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1502 // If we have small model and -static mode, it is safe to store global addresses
1503 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1504 // for MOV64mi32 should handle this sort of thing.
1505 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1506 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1507 Requires<[SmallCode, IsStatic]>;
1508 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1509 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1510 Requires<[SmallCode, IsStatic]>;
1511 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1512 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1513 Requires<[SmallCode, IsStatic]>;
1514 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1515 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1516 Requires<[SmallCode, IsStatic]>;
1519 // Direct PC relative function call for small code model. 32-bit displacement
1520 // sign extended to 64-bit.
1521 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1522 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1523 def : Pat<(X86call (i64 texternalsym:$dst)),
1524 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1526 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1527 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1528 def : Pat<(X86call (i64 texternalsym:$dst)),
1529 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1532 def : Pat<(X86tcret GR64:$dst, imm:$off),
1533 (TCRETURNri64 GR64:$dst, imm:$off)>;
1535 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1536 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1538 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1539 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1543 // TEST R,R is smaller than CMP R,0
1544 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1545 (TEST64rr GR64:$src1, GR64:$src1)>;
1547 // Conditional moves with folded loads with operands swapped and conditions
1549 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1550 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1551 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1552 (CMOVB64rm GR64:$src2, addr:$src1)>;
1553 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1554 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1555 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1556 (CMOVE64rm GR64:$src2, addr:$src1)>;
1557 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1558 (CMOVA64rm GR64:$src2, addr:$src1)>;
1559 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1560 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1561 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1562 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1563 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1564 (CMOVL64rm GR64:$src2, addr:$src1)>;
1565 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1566 (CMOVG64rm GR64:$src2, addr:$src1)>;
1567 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1568 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1569 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1570 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1571 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1572 (CMOVP64rm GR64:$src2, addr:$src1)>;
1573 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1574 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1575 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1576 (CMOVS64rm GR64:$src2, addr:$src1)>;
1577 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1578 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1579 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1580 (CMOVO64rm GR64:$src2, addr:$src1)>;
1582 // zextload bool -> zextload byte
1583 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1586 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1587 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1588 // partial-register updates.
1589 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1590 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1591 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1592 // For other extloads, use subregs, since the high contents of the register are
1593 // defined after an extload.
1594 def : Pat<(extloadi64i32 addr:$src),
1595 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1597 def : Pat<(extloadi16i1 addr:$src),
1598 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1600 Requires<[In64BitMode]>;
1601 def : Pat<(extloadi16i8 addr:$src),
1602 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1604 Requires<[In64BitMode]>;
1607 def : Pat<(i64 (anyext GR8:$src)),
1608 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1609 def : Pat<(i64 (anyext GR16:$src)),
1610 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1611 def : Pat<(i64 (anyext GR32:$src)),
1612 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1613 def : Pat<(i16 (anyext GR8:$src)),
1614 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1615 Requires<[In64BitMode]>;
1616 def : Pat<(i32 (anyext GR8:$src)),
1617 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1618 Requires<[In64BitMode]>;
1620 //===----------------------------------------------------------------------===//
1622 //===----------------------------------------------------------------------===//
1624 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1625 // +128 doesn't, so in this special case use a sub instead of an add.
1626 def : Pat<(add GR64:$src1, 128),
1627 (SUB64ri8 GR64:$src1, -128)>;
1628 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1629 (SUB64mi8 addr:$dst, -128)>;
1631 // The same trick applies for 32-bit immediate fields in 64-bit
1633 def : Pat<(add GR64:$src1, 0x0000000080000000),
1634 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1635 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1636 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1638 // r & (2^32-1) ==> movz
1639 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1640 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1641 // r & (2^16-1) ==> movz
1642 def : Pat<(and GR64:$src, 0xffff),
1643 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1644 // r & (2^8-1) ==> movz
1645 def : Pat<(and GR64:$src, 0xff),
1646 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1647 // r & (2^8-1) ==> movz
1648 def : Pat<(and GR32:$src1, 0xff),
1649 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1650 Requires<[In64BitMode]>;
1651 // r & (2^8-1) ==> movz
1652 def : Pat<(and GR16:$src1, 0xff),
1653 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1654 Requires<[In64BitMode]>;
1656 // sext_inreg patterns
1657 def : Pat<(sext_inreg GR64:$src, i32),
1658 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1659 def : Pat<(sext_inreg GR64:$src, i16),
1660 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1661 def : Pat<(sext_inreg GR64:$src, i8),
1662 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1663 def : Pat<(sext_inreg GR32:$src, i8),
1664 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1665 Requires<[In64BitMode]>;
1666 def : Pat<(sext_inreg GR16:$src, i8),
1667 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1668 Requires<[In64BitMode]>;
1671 def : Pat<(i32 (trunc GR64:$src)),
1672 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1673 def : Pat<(i16 (trunc GR64:$src)),
1674 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1675 def : Pat<(i8 (trunc GR64:$src)),
1676 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1677 def : Pat<(i8 (trunc GR32:$src)),
1678 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1679 Requires<[In64BitMode]>;
1680 def : Pat<(i8 (trunc GR16:$src)),
1681 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1682 Requires<[In64BitMode]>;
1684 // h-register tricks.
1685 // For now, be conservative on x86-64 and use an h-register extract only if the
1686 // value is immediately zero-extended or stored, which are somewhat common
1687 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1688 // from being allocated in the same instruction as the h register, as there's
1689 // currently no way to describe this requirement to the register allocator.
1691 // h-register extract and zero-extend.
1692 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1696 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1697 x86_subreg_8bit_hi)),
1699 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1701 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1702 x86_subreg_8bit_hi))>,
1703 Requires<[In64BitMode]>;
1704 def : Pat<(srl_su GR16:$src, (i8 8)),
1707 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1708 x86_subreg_8bit_hi)),
1710 Requires<[In64BitMode]>;
1711 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1713 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1714 x86_subreg_8bit_hi))>,
1715 Requires<[In64BitMode]>;
1716 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1720 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1721 x86_subreg_8bit_hi)),
1724 // h-register extract and store.
1725 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1728 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1729 x86_subreg_8bit_hi))>;
1730 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1733 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1734 x86_subreg_8bit_hi))>,
1735 Requires<[In64BitMode]>;
1736 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1739 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1740 x86_subreg_8bit_hi))>,
1741 Requires<[In64BitMode]>;
1743 // (shl x, 1) ==> (add x, x)
1744 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1746 // (shl x (and y, 63)) ==> (shl x, y)
1747 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1748 (SHL64rCL GR64:$src1)>;
1749 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1750 (SHL64mCL addr:$dst)>;
1752 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1753 (SHR64rCL GR64:$src1)>;
1754 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1755 (SHR64mCL addr:$dst)>;
1757 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1758 (SAR64rCL GR64:$src1)>;
1759 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1760 (SAR64mCL addr:$dst)>;
1762 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1763 def : Pat<(or (srl GR64:$src1, CL:$amt),
1764 (shl GR64:$src2, (sub 64, CL:$amt))),
1765 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1767 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1768 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1769 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1771 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1772 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1773 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1775 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1776 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1778 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1780 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1781 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1783 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1784 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1785 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1787 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1788 def : Pat<(or (shl GR64:$src1, CL:$amt),
1789 (srl GR64:$src2, (sub 64, CL:$amt))),
1790 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1792 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1793 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1794 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1796 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1797 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1798 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1800 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1801 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1803 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1805 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1806 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1808 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1809 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1810 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1812 // X86 specific add which produces a flag.
1813 def : Pat<(addc GR64:$src1, GR64:$src2),
1814 (ADD64rr GR64:$src1, GR64:$src2)>;
1815 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1816 (ADD64rm GR64:$src1, addr:$src2)>;
1817 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1818 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1819 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1820 (ADD64ri32 GR64:$src1, imm:$src2)>;
1822 def : Pat<(subc GR64:$src1, GR64:$src2),
1823 (SUB64rr GR64:$src1, GR64:$src2)>;
1824 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1825 (SUB64rm GR64:$src1, addr:$src2)>;
1826 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1827 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1828 def : Pat<(subc GR64:$src1, imm:$src2),
1829 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1831 //===----------------------------------------------------------------------===//
1832 // EFLAGS-defining Patterns
1833 //===----------------------------------------------------------------------===//
1835 // Register-Register Addition with EFLAGS result
1836 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1838 (ADD64rr GR64:$src1, GR64:$src2)>;
1840 // Register-Integer Addition with EFLAGS result
1841 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1843 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1844 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1846 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1848 // Register-Memory Addition with EFLAGS result
1849 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1851 (ADD64rm GR64:$src1, addr:$src2)>;
1853 // Memory-Register Addition with EFLAGS result
1854 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1857 (ADD64mr addr:$dst, GR64:$src2)>;
1858 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1861 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1862 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1865 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1867 // Register-Register Subtraction with EFLAGS result
1868 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1870 (SUB64rr GR64:$src1, GR64:$src2)>;
1872 // Register-Memory Subtraction with EFLAGS result
1873 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1875 (SUB64rm GR64:$src1, addr:$src2)>;
1877 // Register-Integer Subtraction with EFLAGS result
1878 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1880 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1881 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1883 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1885 // Memory-Register Subtraction with EFLAGS result
1886 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1889 (SUB64mr addr:$dst, GR64:$src2)>;
1891 // Memory-Integer Subtraction with EFLAGS result
1892 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1895 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1896 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1899 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1901 // Register-Register Signed Integer Multiplication with EFLAGS result
1902 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1904 (IMUL64rr GR64:$src1, GR64:$src2)>;
1906 // Register-Memory Signed Integer Multiplication with EFLAGS result
1907 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1909 (IMUL64rm GR64:$src1, addr:$src2)>;
1911 // Register-Integer Signed Integer Multiplication with EFLAGS result
1912 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1914 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1915 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1917 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1919 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1920 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1922 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1923 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1925 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1927 // INC and DEC with EFLAGS result. Note that these do not set CF.
1928 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1929 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1930 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1932 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1933 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1934 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1935 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1937 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1939 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1940 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1941 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1943 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1944 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1945 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1946 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1948 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1950 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1951 (INC64r GR64:$src)>;
1952 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1954 (INC64m addr:$dst)>;
1955 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1956 (DEC64r GR64:$src)>;
1957 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1959 (DEC64m addr:$dst)>;
1961 //===----------------------------------------------------------------------===//
1962 // X86-64 SSE Instructions
1963 //===----------------------------------------------------------------------===//
1965 // Move instructions...
1967 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1968 "mov{d|q}\t{$src, $dst|$dst, $src}",
1970 (v2i64 (scalar_to_vector GR64:$src)))]>;
1971 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1972 "mov{d|q}\t{$src, $dst|$dst, $src}",
1973 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1976 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1977 "mov{d|q}\t{$src, $dst|$dst, $src}",
1978 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1979 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1980 "movq\t{$src, $dst|$dst, $src}",
1981 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1983 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1984 "mov{d|q}\t{$src, $dst|$dst, $src}",
1985 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1986 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1987 "movq\t{$src, $dst|$dst, $src}",
1988 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1990 //===----------------------------------------------------------------------===//
1991 // X86-64 SSE4.1 Instructions
1992 //===----------------------------------------------------------------------===//
1994 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1995 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
1996 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
1997 (ins VR128:$src1, i32i8imm:$src2),
1998 !strconcat(OpcodeStr,
1999 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2001 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2002 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2003 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2004 !strconcat(OpcodeStr,
2005 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2006 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2007 addr:$dst)]>, OpSize, REX_W;
2010 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2012 let isTwoAddress = 1 in {
2013 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2014 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2015 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2016 !strconcat(OpcodeStr,
2017 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2019 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2021 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2022 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2023 !strconcat(OpcodeStr,
2024 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2026 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2027 imm:$src3)))]>, OpSize, REX_W;
2031 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;