1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions.
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
46 def i64immSExt32 : PatLeaf<(i64 imm), [{
47 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
48 // sign extended field.
49 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
52 def i64immZExt32 : PatLeaf<(i64 imm), [{
53 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // unsignedsign extended field.
55 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
58 def i64immSExt8 : PatLeaf<(i64 imm), [{
59 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
60 // sign extended field.
61 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
64 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
65 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
66 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
68 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
69 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
70 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
71 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
73 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
74 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
75 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
76 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
78 //===----------------------------------------------------------------------===//
79 // Instruction list...
82 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
83 // a stack adjustment and the codegen must know that they may modify the stack
84 // pointer before prolog-epilog rewriting occurs.
85 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
86 // sub / add which can clobber EFLAGS.
87 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
90 [(X86callseq_start timm:$amt)]>,
91 Requires<[In64BitMode]>;
92 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
94 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
95 Requires<[In64BitMode]>;
98 //===----------------------------------------------------------------------===//
99 // Call Instructions...
102 // All calls clobber the non-callee saved registers. RSP is marked as
103 // a use to prevent stack-pointer assignments that appear immediately
104 // before calls from potentially appearing dead. Uses for argument
105 // registers are added manually.
106 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
107 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
108 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
109 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
110 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
112 def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops),
113 "call\t${dst:call}", []>;
114 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
115 "call\t{*}$dst", [(X86call GR64:$dst)]>;
116 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
117 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>;
122 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
123 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset, variable_ops),
124 "#TC_RETURN $dst $offset",
127 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
128 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset, variable_ops),
129 "#TC_RETURN $dst $offset",
133 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
134 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst # TAILCALL",
138 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
139 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
140 [(brind GR64:$dst)]>;
141 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
142 [(brind (loadi64 addr:$dst))]>;
145 //===----------------------------------------------------------------------===//
146 // EH Pseudo Instructions
148 let isTerminator = 1, isReturn = 1, isBarrier = 1,
150 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
151 "ret\t#eh_return, addr: $addr",
152 [(X86ehret GR64:$addr)]>;
156 //===----------------------------------------------------------------------===//
157 // Miscellaneous Instructions...
159 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
160 def LEAVE64 : I<0xC9, RawFrm,
161 (outs), (ins), "leave", []>;
162 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
164 def POP64r : I<0x58, AddRegFrm,
165 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
167 def PUSH64r : I<0x50, AddRegFrm,
168 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
171 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
172 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
173 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
174 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
176 def LEA64_32r : I<0x8D, MRMSrcMem,
177 (outs GR32:$dst), (ins lea64_32mem:$src),
178 "lea{l}\t{$src|$dst}, {$dst|$src}",
179 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
181 let isReMaterializable = 1 in
182 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
183 "lea{q}\t{$src|$dst}, {$dst|$src}",
184 [(set GR64:$dst, lea64addr:$src)]>;
186 let isTwoAddress = 1 in
187 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
189 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
191 // Bit scan instructions.
192 let Defs = [EFLAGS] in {
193 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
194 "bsf{q}\t{$src, $dst|$dst, $src}",
195 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
196 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
197 "bsf{q}\t{$src, $dst|$dst, $src}",
198 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
199 (implicit EFLAGS)]>, TB;
201 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
202 "bsr{q}\t{$src, $dst|$dst, $src}",
203 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
204 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
205 "bsr{q}\t{$src, $dst|$dst, $src}",
206 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
207 (implicit EFLAGS)]>, TB;
211 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
212 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
213 [(X86rep_movs i64)]>, REP;
214 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
215 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
216 [(X86rep_stos i64)]>, REP;
218 //===----------------------------------------------------------------------===//
219 // Move Instructions...
222 let neverHasSideEffects = 1 in
223 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
224 "mov{q}\t{$src, $dst|$dst, $src}", []>;
226 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
227 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
228 "movabs{q}\t{$src, $dst|$dst, $src}",
229 [(set GR64:$dst, imm:$src)]>;
230 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
231 "mov{q}\t{$src, $dst|$dst, $src}",
232 [(set GR64:$dst, i64immSExt32:$src)]>;
235 let isSimpleLoad = 1 in
236 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
237 "mov{q}\t{$src, $dst|$dst, $src}",
238 [(set GR64:$dst, (load addr:$src))]>;
240 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
241 "mov{q}\t{$src, $dst|$dst, $src}",
242 [(store GR64:$src, addr:$dst)]>;
243 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
244 "mov{q}\t{$src, $dst|$dst, $src}",
245 [(store i64immSExt32:$src, addr:$dst)]>;
247 // Sign/Zero extenders
249 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
250 "movs{bq|x}\t{$src, $dst|$dst, $src}",
251 [(set GR64:$dst, (sext GR8:$src))]>, TB;
252 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
253 "movs{bq|x}\t{$src, $dst|$dst, $src}",
254 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
255 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
256 "movs{wq|x}\t{$src, $dst|$dst, $src}",
257 [(set GR64:$dst, (sext GR16:$src))]>, TB;
258 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
259 "movs{wq|x}\t{$src, $dst|$dst, $src}",
260 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
261 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
262 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
263 [(set GR64:$dst, (sext GR32:$src))]>;
264 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
265 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
266 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
268 // Use movzbl instead of movzbq when the destination is a register; it's
269 // equivalent due to implicit zero-extending, and it has a smaller encoding.
270 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
271 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
272 [(set GR64:$dst, (zext GR8:$src))]>, TB;
273 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
274 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
275 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
276 // Use movzwl instead of movzwq when the destination is a register; it's
277 // equivalent due to implicit zero-extending, and it has a smaller encoding.
278 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
279 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
280 [(set GR64:$dst, (zext GR16:$src))]>, TB;
281 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
282 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
283 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
285 // There's no movzlq instruction, but movl can be used for this purpose, using
286 // implicit zero-extension. We need this because the seeming alternative for
287 // implementing zext from 32 to 64, an EXTRACT_SUBREG/SUBREG_TO_REG pair, isn't
288 // safe because both instructions could be optimized away in the
289 // register-to-register case, leaving nothing behind to do the zero extension.
290 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
291 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
292 [(set GR64:$dst, (zext GR32:$src))]>;
293 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
294 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
295 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
297 let neverHasSideEffects = 1 in {
298 let Defs = [RAX], Uses = [EAX] in
299 def CDQE : RI<0x98, RawFrm, (outs), (ins),
300 "{cltq|cdqe}", []>; // RAX = signext(EAX)
302 let Defs = [RAX,RDX], Uses = [RAX] in
303 def CQO : RI<0x99, RawFrm, (outs), (ins),
304 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
307 //===----------------------------------------------------------------------===//
308 // Arithmetic Instructions...
311 let Defs = [EFLAGS] in {
312 let isTwoAddress = 1 in {
313 let isConvertibleToThreeAddress = 1 in {
314 let isCommutable = 1 in
315 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
316 "add{q}\t{$src2, $dst|$dst, $src2}",
317 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
320 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
321 "add{q}\t{$src2, $dst|$dst, $src2}",
322 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
324 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
325 "add{q}\t{$src2, $dst|$dst, $src2}",
326 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
328 } // isConvertibleToThreeAddress
330 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
331 "add{q}\t{$src2, $dst|$dst, $src2}",
332 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
336 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
337 "add{q}\t{$src2, $dst|$dst, $src2}",
338 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
340 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
341 "add{q}\t{$src2, $dst|$dst, $src2}",
342 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
344 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
345 "add{q}\t{$src2, $dst|$dst, $src2}",
346 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
349 let Uses = [EFLAGS] in {
350 let isTwoAddress = 1 in {
351 let isCommutable = 1 in
352 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
353 "adc{q}\t{$src2, $dst|$dst, $src2}",
354 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2)),
357 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
358 "adc{q}\t{$src2, $dst|$dst, $src2}",
359 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2))),
362 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
363 "adc{q}\t{$src2, $dst|$dst, $src2}",
364 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2)),
366 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
367 "adc{q}\t{$src2, $dst|$dst, $src2}",
368 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2)),
372 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
373 "adc{q}\t{$src2, $dst|$dst, $src2}",
374 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst),
376 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
377 "adc{q}\t{$src2, $dst|$dst, $src2}",
378 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst),
380 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
381 "adc{q}\t{$src2, $dst|$dst, $src2}",
382 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst),
386 let isTwoAddress = 1 in {
387 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
388 "sub{q}\t{$src2, $dst|$dst, $src2}",
389 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
391 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
392 "sub{q}\t{$src2, $dst|$dst, $src2}",
393 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>;
395 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
396 "sub{q}\t{$src2, $dst|$dst, $src2}",
397 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>;
398 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
399 "sub{q}\t{$src2, $dst|$dst, $src2}",
400 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>;
403 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
404 "sub{q}\t{$src2, $dst|$dst, $src2}",
405 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>;
406 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
407 "sub{q}\t{$src2, $dst|$dst, $src2}",
408 [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
409 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
410 "sub{q}\t{$src2, $dst|$dst, $src2}",
411 [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
413 let Uses = [EFLAGS] in {
414 let isTwoAddress = 1 in {
415 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
416 "sbb{q}\t{$src2, $dst|$dst, $src2}",
417 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
419 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
420 "sbb{q}\t{$src2, $dst|$dst, $src2}",
421 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
423 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
424 "sbb{q}\t{$src2, $dst|$dst, $src2}",
425 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
426 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
427 "sbb{q}\t{$src2, $dst|$dst, $src2}",
428 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
431 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
432 "sbb{q}\t{$src2, $dst|$dst, $src2}",
433 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
434 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
435 "sbb{q}\t{$src2, $dst|$dst, $src2}",
436 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
437 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
438 "sbb{q}\t{$src2, $dst|$dst, $src2}",
439 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
443 // Unsigned multiplication
444 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
445 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
446 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
448 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
449 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
451 // Signed multiplication
452 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
453 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
455 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
456 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
459 let Defs = [EFLAGS] in {
460 let isTwoAddress = 1 in {
461 let isCommutable = 1 in
462 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
463 "imul{q}\t{$src2, $dst|$dst, $src2}",
464 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB;
466 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
467 "imul{q}\t{$src2, $dst|$dst, $src2}",
468 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB;
471 // Suprisingly enough, these are not two address instructions!
472 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
473 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
474 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
475 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
476 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
477 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
478 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
479 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>;
480 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
481 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
482 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
483 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>;
484 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
485 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
486 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
487 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>;
490 // Unsigned division / remainder
491 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
492 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
494 // Signed division / remainder
495 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
496 "idiv{q}\t$src", []>;
498 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
500 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
501 "idiv{q}\t$src", []>;
505 // Unary instructions
506 let Defs = [EFLAGS], CodeSize = 2 in {
507 let isTwoAddress = 1 in
508 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
509 [(set GR64:$dst, (ineg GR64:$src))]>;
510 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
511 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
513 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
514 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
515 [(set GR64:$dst, (add GR64:$src, 1))]>;
516 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
517 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
519 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
520 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
521 [(set GR64:$dst, (add GR64:$src, -1))]>;
522 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
523 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
525 // In 64-bit mode, single byte INC and DEC cannot be encoded.
526 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
527 // Can transform into LEA.
528 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
529 [(set GR16:$dst, (add GR16:$src, 1))]>,
530 OpSize, Requires<[In64BitMode]>;
531 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
532 [(set GR32:$dst, (add GR32:$src, 1))]>,
533 Requires<[In64BitMode]>;
534 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
535 [(set GR16:$dst, (add GR16:$src, -1))]>,
536 OpSize, Requires<[In64BitMode]>;
537 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
538 [(set GR32:$dst, (add GR32:$src, -1))]>,
539 Requires<[In64BitMode]>;
540 } // isConvertibleToThreeAddress
542 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
543 // how to unfold them.
544 let isTwoAddress = 0, CodeSize = 2 in {
545 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
546 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
547 OpSize, Requires<[In64BitMode]>;
548 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
549 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
550 Requires<[In64BitMode]>;
551 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
552 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
553 OpSize, Requires<[In64BitMode]>;
554 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
555 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
556 Requires<[In64BitMode]>;
558 } // Defs = [EFLAGS], CodeSize
561 let Defs = [EFLAGS] in {
562 // Shift instructions
563 let isTwoAddress = 1 in {
565 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
566 "shl{q}\t{%cl, $dst|$dst, %CL}",
567 [(set GR64:$dst, (shl GR64:$src, CL))]>;
568 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
569 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
570 "shl{q}\t{$src2, $dst|$dst, $src2}",
571 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
572 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
577 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
578 "shl{q}\t{%cl, $dst|$dst, %CL}",
579 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
580 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
581 "shl{q}\t{$src, $dst|$dst, $src}",
582 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
583 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
585 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
587 let isTwoAddress = 1 in {
589 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
590 "shr{q}\t{%cl, $dst|$dst, %CL}",
591 [(set GR64:$dst, (srl GR64:$src, CL))]>;
592 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
593 "shr{q}\t{$src2, $dst|$dst, $src2}",
594 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
595 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
597 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
601 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
602 "shr{q}\t{%cl, $dst|$dst, %CL}",
603 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
604 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
605 "shr{q}\t{$src, $dst|$dst, $src}",
606 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
607 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
609 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
611 let isTwoAddress = 1 in {
613 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
614 "sar{q}\t{%cl, $dst|$dst, %CL}",
615 [(set GR64:$dst, (sra GR64:$src, CL))]>;
616 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
617 "sar{q}\t{$src2, $dst|$dst, $src2}",
618 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
619 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
621 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
625 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
626 "sar{q}\t{%cl, $dst|$dst, %CL}",
627 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
628 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
629 "sar{q}\t{$src, $dst|$dst, $src}",
630 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
631 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
633 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
635 // Rotate instructions
636 let isTwoAddress = 1 in {
638 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
639 "rol{q}\t{%cl, $dst|$dst, %CL}",
640 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
641 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
642 "rol{q}\t{$src2, $dst|$dst, $src2}",
643 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
644 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
646 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
650 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
651 "rol{q}\t{%cl, $dst|$dst, %CL}",
652 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
653 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
654 "rol{q}\t{$src, $dst|$dst, $src}",
655 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
656 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
658 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
660 let isTwoAddress = 1 in {
662 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
663 "ror{q}\t{%cl, $dst|$dst, %CL}",
664 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
665 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
666 "ror{q}\t{$src2, $dst|$dst, $src2}",
667 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
668 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
670 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
674 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
675 "ror{q}\t{%cl, $dst|$dst, %CL}",
676 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
677 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
678 "ror{q}\t{$src, $dst|$dst, $src}",
679 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
680 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
682 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
684 // Double shift instructions (generalizations of rotate)
685 let isTwoAddress = 1 in {
687 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
688 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
689 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
690 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
691 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
692 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
695 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
696 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
697 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
698 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
699 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
702 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
703 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
704 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
705 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
712 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
713 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
714 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
716 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
717 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
718 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
721 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
722 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
723 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
724 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
725 (i8 imm:$src3)), addr:$dst)]>,
727 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
728 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
729 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
730 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
731 (i8 imm:$src3)), addr:$dst)]>,
735 //===----------------------------------------------------------------------===//
736 // Logical Instructions...
739 let isTwoAddress = 1 in
740 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
741 [(set GR64:$dst, (not GR64:$src))]>;
742 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
743 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
745 let Defs = [EFLAGS] in {
746 let isTwoAddress = 1 in {
747 let isCommutable = 1 in
748 def AND64rr : RI<0x21, MRMDestReg,
749 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
750 "and{q}\t{$src2, $dst|$dst, $src2}",
751 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
752 def AND64rm : RI<0x23, MRMSrcMem,
753 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
754 "and{q}\t{$src2, $dst|$dst, $src2}",
755 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
756 def AND64ri32 : RIi32<0x81, MRM4r,
757 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
758 "and{q}\t{$src2, $dst|$dst, $src2}",
759 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
760 def AND64ri8 : RIi8<0x83, MRM4r,
761 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
762 "and{q}\t{$src2, $dst|$dst, $src2}",
763 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
766 def AND64mr : RI<0x21, MRMDestMem,
767 (outs), (ins i64mem:$dst, GR64:$src),
768 "and{q}\t{$src, $dst|$dst, $src}",
769 [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
770 def AND64mi32 : RIi32<0x81, MRM4m,
771 (outs), (ins i64mem:$dst, i64i32imm:$src),
772 "and{q}\t{$src, $dst|$dst, $src}",
773 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
774 def AND64mi8 : RIi8<0x83, MRM4m,
775 (outs), (ins i64mem:$dst, i64i8imm :$src),
776 "and{q}\t{$src, $dst|$dst, $src}",
777 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
779 let isTwoAddress = 1 in {
780 let isCommutable = 1 in
781 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
782 "or{q}\t{$src2, $dst|$dst, $src2}",
783 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
784 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
785 "or{q}\t{$src2, $dst|$dst, $src2}",
786 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
787 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
788 "or{q}\t{$src2, $dst|$dst, $src2}",
789 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
790 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
791 "or{q}\t{$src2, $dst|$dst, $src2}",
792 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
795 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
796 "or{q}\t{$src, $dst|$dst, $src}",
797 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
798 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
799 "or{q}\t{$src, $dst|$dst, $src}",
800 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
801 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
802 "or{q}\t{$src, $dst|$dst, $src}",
803 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
805 let isTwoAddress = 1 in {
806 let isCommutable = 1 in
807 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
808 "xor{q}\t{$src2, $dst|$dst, $src2}",
809 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
810 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
811 "xor{q}\t{$src2, $dst|$dst, $src2}",
812 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
813 def XOR64ri32 : RIi32<0x81, MRM6r,
814 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
815 "xor{q}\t{$src2, $dst|$dst, $src2}",
816 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
817 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
818 "xor{q}\t{$src2, $dst|$dst, $src2}",
819 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
822 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
823 "xor{q}\t{$src, $dst|$dst, $src}",
824 [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
825 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
826 "xor{q}\t{$src, $dst|$dst, $src}",
827 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
828 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
829 "xor{q}\t{$src, $dst|$dst, $src}",
830 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
833 //===----------------------------------------------------------------------===//
834 // Comparison Instructions...
837 // Integer comparison
838 let Defs = [EFLAGS] in {
839 let isCommutable = 1 in
840 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
841 "test{q}\t{$src2, $src1|$src1, $src2}",
842 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
844 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
845 "test{q}\t{$src2, $src1|$src1, $src2}",
846 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
848 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
849 (ins GR64:$src1, i64i32imm:$src2),
850 "test{q}\t{$src2, $src1|$src1, $src2}",
851 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
853 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
854 (ins i64mem:$src1, i64i32imm:$src2),
855 "test{q}\t{$src2, $src1|$src1, $src2}",
856 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
859 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
860 "cmp{q}\t{$src2, $src1|$src1, $src2}",
861 [(X86cmp GR64:$src1, GR64:$src2),
863 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
864 "cmp{q}\t{$src2, $src1|$src1, $src2}",
865 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
867 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
868 "cmp{q}\t{$src2, $src1|$src1, $src2}",
869 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
871 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
872 "cmp{q}\t{$src2, $src1|$src1, $src2}",
873 [(X86cmp GR64:$src1, i64immSExt32:$src2),
875 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
876 (ins i64mem:$src1, i64i32imm:$src2),
877 "cmp{q}\t{$src2, $src1|$src1, $src2}",
878 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
880 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
881 "cmp{q}\t{$src2, $src1|$src1, $src2}",
882 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
884 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
885 "cmp{q}\t{$src2, $src1|$src1, $src2}",
886 [(X86cmp GR64:$src1, i64immSExt8:$src2),
891 let Uses = [EFLAGS], isTwoAddress = 1 in {
892 let isCommutable = 1 in {
893 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
894 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
895 "cmovb\t{$src2, $dst|$dst, $src2}",
896 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
897 X86_COND_B, EFLAGS))]>, TB;
898 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
899 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
900 "cmovae\t{$src2, $dst|$dst, $src2}",
901 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
902 X86_COND_AE, EFLAGS))]>, TB;
903 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
904 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
905 "cmove\t{$src2, $dst|$dst, $src2}",
906 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
907 X86_COND_E, EFLAGS))]>, TB;
908 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
909 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
910 "cmovne\t{$src2, $dst|$dst, $src2}",
911 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
912 X86_COND_NE, EFLAGS))]>, TB;
913 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
914 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
915 "cmovbe\t{$src2, $dst|$dst, $src2}",
916 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
917 X86_COND_BE, EFLAGS))]>, TB;
918 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
919 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
920 "cmova\t{$src2, $dst|$dst, $src2}",
921 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
922 X86_COND_A, EFLAGS))]>, TB;
923 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
924 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
925 "cmovl\t{$src2, $dst|$dst, $src2}",
926 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
927 X86_COND_L, EFLAGS))]>, TB;
928 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
929 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
930 "cmovge\t{$src2, $dst|$dst, $src2}",
931 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
932 X86_COND_GE, EFLAGS))]>, TB;
933 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
934 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
935 "cmovle\t{$src2, $dst|$dst, $src2}",
936 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
937 X86_COND_LE, EFLAGS))]>, TB;
938 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
939 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
940 "cmovg\t{$src2, $dst|$dst, $src2}",
941 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
942 X86_COND_G, EFLAGS))]>, TB;
943 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
944 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
945 "cmovs\t{$src2, $dst|$dst, $src2}",
946 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
947 X86_COND_S, EFLAGS))]>, TB;
948 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
949 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
950 "cmovns\t{$src2, $dst|$dst, $src2}",
951 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
952 X86_COND_NS, EFLAGS))]>, TB;
953 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
954 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
955 "cmovp\t{$src2, $dst|$dst, $src2}",
956 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
957 X86_COND_P, EFLAGS))]>, TB;
958 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
959 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
960 "cmovnp\t{$src2, $dst|$dst, $src2}",
961 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
962 X86_COND_NP, EFLAGS))]>, TB;
963 } // isCommutable = 1
965 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
966 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
967 "cmovb\t{$src2, $dst|$dst, $src2}",
968 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
969 X86_COND_B, EFLAGS))]>, TB;
970 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
971 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
972 "cmovae\t{$src2, $dst|$dst, $src2}",
973 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
974 X86_COND_AE, EFLAGS))]>, TB;
975 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
976 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
977 "cmove\t{$src2, $dst|$dst, $src2}",
978 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
979 X86_COND_E, EFLAGS))]>, TB;
980 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
981 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
982 "cmovne\t{$src2, $dst|$dst, $src2}",
983 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
984 X86_COND_NE, EFLAGS))]>, TB;
985 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
986 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
987 "cmovbe\t{$src2, $dst|$dst, $src2}",
988 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
989 X86_COND_BE, EFLAGS))]>, TB;
990 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
991 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
992 "cmova\t{$src2, $dst|$dst, $src2}",
993 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
994 X86_COND_A, EFLAGS))]>, TB;
995 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
996 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
997 "cmovl\t{$src2, $dst|$dst, $src2}",
998 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
999 X86_COND_L, EFLAGS))]>, TB;
1000 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1001 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1002 "cmovge\t{$src2, $dst|$dst, $src2}",
1003 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1004 X86_COND_GE, EFLAGS))]>, TB;
1005 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1006 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1007 "cmovle\t{$src2, $dst|$dst, $src2}",
1008 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1009 X86_COND_LE, EFLAGS))]>, TB;
1010 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1011 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1012 "cmovg\t{$src2, $dst|$dst, $src2}",
1013 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1014 X86_COND_G, EFLAGS))]>, TB;
1015 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1016 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1017 "cmovs\t{$src2, $dst|$dst, $src2}",
1018 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1019 X86_COND_S, EFLAGS))]>, TB;
1020 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1021 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1022 "cmovns\t{$src2, $dst|$dst, $src2}",
1023 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1024 X86_COND_NS, EFLAGS))]>, TB;
1025 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1026 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1027 "cmovp\t{$src2, $dst|$dst, $src2}",
1028 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1029 X86_COND_P, EFLAGS))]>, TB;
1030 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1031 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1032 "cmovnp\t{$src2, $dst|$dst, $src2}",
1033 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1034 X86_COND_NP, EFLAGS))]>, TB;
1037 //===----------------------------------------------------------------------===//
1038 // Conversion Instructions...
1041 // f64 -> signed i64
1042 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1043 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1045 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1046 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1047 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1048 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1049 (load addr:$src)))]>;
1050 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1051 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1052 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1053 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1054 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1055 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1056 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1057 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1059 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1060 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1061 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1063 (int_x86_sse2_cvttsd2si64
1064 (load addr:$src)))]>;
1066 // Signed i64 -> f64
1067 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1068 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1069 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1070 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1071 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1072 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1074 let isTwoAddress = 1 in {
1075 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1076 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1077 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1079 (int_x86_sse2_cvtsi642sd VR128:$src1,
1081 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1082 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1083 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1085 (int_x86_sse2_cvtsi642sd VR128:$src1,
1086 (loadi64 addr:$src2)))]>;
1089 // Signed i64 -> f32
1090 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1091 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1092 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1093 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1094 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1095 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1097 let isTwoAddress = 1 in {
1098 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1099 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1100 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1102 (int_x86_sse_cvtsi642ss VR128:$src1,
1104 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1105 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1106 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1108 (int_x86_sse_cvtsi642ss VR128:$src1,
1109 (loadi64 addr:$src2)))]>;
1112 // f32 -> signed i64
1113 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1114 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1116 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1117 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1118 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1119 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1120 (load addr:$src)))]>;
1121 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1122 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1123 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1124 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1125 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1126 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1127 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1128 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1130 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1131 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1132 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1134 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1136 //===----------------------------------------------------------------------===//
1137 // Alias Instructions
1138 //===----------------------------------------------------------------------===//
1140 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1141 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1143 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1144 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1145 // when we have a better way to specify isel priority.
1146 let Defs = [EFLAGS], AddedComplexity = 1,
1147 isReMaterializable = 1, isAsCheapAsAMove = 1 in
1148 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1149 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1150 [(set GR64:$dst, 0)]>;
1152 // Materialize i64 constant where top 32-bits are zero.
1153 let AddedComplexity = 1, isReMaterializable = 1 in
1154 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1155 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1156 [(set GR64:$dst, i64immZExt32:$src)]>;
1158 //===----------------------------------------------------------------------===//
1159 // Thread Local Storage Instructions
1160 //===----------------------------------------------------------------------===//
1162 def TLS_addr64 : I<0, Pseudo, (outs GR64:$dst), (ins i64imm:$sym),
1163 ".byte\t0x66; leaq\t${sym:mem}(%rip), $dst; .word\t0x6666; rex64",
1164 [(set GR64:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
1166 //===----------------------------------------------------------------------===//
1167 // Atomic Instructions
1168 //===----------------------------------------------------------------------===//
1170 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1171 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1172 "lock\n\tcmpxchgq\t$swap,$ptr",
1173 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1176 let Constraints = "$val = $dst" in {
1177 let Defs = [EFLAGS] in
1178 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1179 "lock\n\txadd\t$val, $ptr",
1180 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1182 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1184 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1187 // Atomic exchange, and, or, xor
1188 let Constraints = "$val = $dst", Defs = [EFLAGS],
1189 usesCustomDAGSchedInserter = 1 in {
1190 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1191 "#ATOMAND64 PSUEDO!",
1192 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1193 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1194 "#ATOMOR64 PSUEDO!",
1195 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1196 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1197 "#ATOMXOR64 PSUEDO!",
1198 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1199 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1200 "#ATOMNAND64 PSUEDO!",
1201 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1202 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1203 "#ATOMMIN64 PSUEDO!",
1204 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1205 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1206 "#ATOMMAX64 PSUEDO!",
1207 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1208 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1209 "#ATOMUMIN64 PSUEDO!",
1210 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1211 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1212 "#ATOMUMAX64 PSUEDO!",
1213 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1216 //===----------------------------------------------------------------------===//
1217 // Non-Instruction Patterns
1218 //===----------------------------------------------------------------------===//
1220 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1221 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1222 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1223 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1224 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1225 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1226 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1227 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1228 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1230 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1231 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1232 Requires<[SmallCode, IsStatic]>;
1233 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1234 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1235 Requires<[SmallCode, IsStatic]>;
1236 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1237 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1238 Requires<[SmallCode, IsStatic]>;
1239 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1240 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1241 Requires<[SmallCode, IsStatic]>;
1244 // Direct PC relative function call for small code model. 32-bit displacement
1245 // sign extended to 64-bit.
1246 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1247 (CALL64pcrel32 tglobaladdr:$dst)>;
1248 def : Pat<(X86call (i64 texternalsym:$dst)),
1249 (CALL64pcrel32 texternalsym:$dst)>;
1251 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1252 (CALL64pcrel32 tglobaladdr:$dst)>;
1253 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1254 (CALL64pcrel32 texternalsym:$dst)>;
1256 def : Pat<(X86tailcall GR64:$dst),
1257 (CALL64r GR64:$dst)>;
1261 def : Pat<(X86tailcall GR32:$dst),
1263 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1265 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1268 def : Pat<(X86tcret GR64:$dst, imm:$off),
1269 (TCRETURNri64 GR64:$dst, imm:$off)>;
1271 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1272 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1274 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1275 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1279 // TEST R,R is smaller than CMP R,0
1280 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1281 (TEST64rr GR64:$src1, GR64:$src1)>;
1286 def : Pat<(i64 (zext GR32:$src)),
1287 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1289 // zextload bool -> zextload byte
1290 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1293 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1294 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1295 // partial-register updates.
1296 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1297 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1298 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1299 // For other extloads, use subregs, since the high contents of the register are
1300 // defined after an extload.
1301 def : Pat<(extloadi64i32 addr:$src),
1302 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1304 def : Pat<(extloadi16i1 addr:$src),
1305 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1307 Requires<[In64BitMode]>;
1308 def : Pat<(extloadi16i8 addr:$src),
1309 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1311 Requires<[In64BitMode]>;
1314 def : Pat<(i64 (anyext GR8:$src)),
1315 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1316 def : Pat<(i64 (anyext GR16:$src)),
1317 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1318 def : Pat<(i64 (anyext GR32:$src)),
1319 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1320 def : Pat<(i16 (anyext GR8:$src)),
1321 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1322 Requires<[In64BitMode]>;
1323 def : Pat<(i32 (anyext GR8:$src)),
1324 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1325 Requires<[In64BitMode]>;
1327 //===----------------------------------------------------------------------===//
1329 //===----------------------------------------------------------------------===//
1331 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1332 // +128 doesn't, so in this special case use a sub instead of an add.
1333 def : Pat<(add GR64:$src1, 128),
1334 (SUB64ri8 GR64:$src1, -128)>;
1335 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1336 (SUB64mi8 addr:$dst, -128)>;
1338 // The same trick applies for 32-bit immediate fields in 64-bit
1340 def : Pat<(add GR64:$src1, 0x0000000080000000),
1341 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1342 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1343 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1345 // r & (2^32-1) ==> movz
1346 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1347 (MOVZX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1348 // r & (2^16-1) ==> movz
1349 def : Pat<(and GR64:$src, 0xffff),
1350 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1351 // r & (2^8-1) ==> movz
1352 def : Pat<(and GR64:$src, 0xff),
1353 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1354 // r & (2^8-1) ==> movz
1355 def : Pat<(and GR32:$src1, 0xff),
1356 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>,
1357 Requires<[In64BitMode]>;
1358 // r & (2^8-1) ==> movz
1359 def : Pat<(and GR16:$src1, 0xff),
1360 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1361 Requires<[In64BitMode]>;
1363 // sext_inreg patterns
1364 def : Pat<(sext_inreg GR64:$src, i32),
1365 (MOVSX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1366 def : Pat<(sext_inreg GR64:$src, i16),
1367 (MOVSX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1368 def : Pat<(sext_inreg GR64:$src, i8),
1369 (MOVSX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1370 def : Pat<(sext_inreg GR32:$src, i8),
1371 (MOVSX32rr8 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)))>,
1372 Requires<[In64BitMode]>;
1373 def : Pat<(sext_inreg GR16:$src, i8),
1374 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1375 Requires<[In64BitMode]>;
1378 def : Pat<(i32 (trunc GR64:$src)),
1379 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1380 def : Pat<(i16 (trunc GR64:$src)),
1381 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1382 def : Pat<(i8 (trunc GR64:$src)),
1383 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1384 def : Pat<(i8 (trunc GR32:$src)),
1385 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1386 Requires<[In64BitMode]>;
1387 def : Pat<(i8 (trunc GR16:$src)),
1388 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit))>,
1389 Requires<[In64BitMode]>;
1391 // (shl x, 1) ==> (add x, x)
1392 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1394 // (shl x (and y, 63)) ==> (shl x, y)
1395 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1396 (SHL64rCL GR64:$src1)>;
1397 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1398 (SHL64mCL addr:$dst)>;
1400 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1401 (SHR64rCL GR64:$src1)>;
1402 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1403 (SHR64mCL addr:$dst)>;
1405 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1406 (SAR64rCL GR64:$src1)>;
1407 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1408 (SAR64mCL addr:$dst)>;
1410 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1411 def : Pat<(or (srl GR64:$src1, CL:$amt),
1412 (shl GR64:$src2, (sub 64, CL:$amt))),
1413 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1415 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1416 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1417 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1419 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1420 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1421 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1423 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1424 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1426 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1428 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1429 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1431 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1432 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1433 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1435 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1436 def : Pat<(or (shl GR64:$src1, CL:$amt),
1437 (srl GR64:$src2, (sub 64, CL:$amt))),
1438 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1440 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1441 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1442 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1444 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1445 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1446 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1448 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1449 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1451 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1453 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1454 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1456 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1457 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1458 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1460 // X86 specific add which produces a flag.
1461 def : Pat<(addc GR64:$src1, GR64:$src2),
1462 (ADD64rr GR64:$src1, GR64:$src2)>;
1463 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1464 (ADD64rm GR64:$src1, addr:$src2)>;
1465 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1466 (ADD64ri32 GR64:$src1, imm:$src2)>;
1467 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1468 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1470 def : Pat<(subc GR64:$src1, GR64:$src2),
1471 (SUB64rr GR64:$src1, GR64:$src2)>;
1472 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1473 (SUB64rm GR64:$src1, addr:$src2)>;
1474 def : Pat<(subc GR64:$src1, imm:$src2),
1475 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1476 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1477 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1480 //===----------------------------------------------------------------------===//
1481 // X86-64 SSE Instructions
1482 //===----------------------------------------------------------------------===//
1484 // Move instructions...
1486 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1487 "mov{d|q}\t{$src, $dst|$dst, $src}",
1489 (v2i64 (scalar_to_vector GR64:$src)))]>;
1490 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1491 "mov{d|q}\t{$src, $dst|$dst, $src}",
1492 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1495 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1496 "mov{d|q}\t{$src, $dst|$dst, $src}",
1497 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1498 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1499 "movq\t{$src, $dst|$dst, $src}",
1500 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1502 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1503 "mov{d|q}\t{$src, $dst|$dst, $src}",
1504 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1505 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1506 "movq\t{$src, $dst|$dst, $src}",
1507 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1509 //===----------------------------------------------------------------------===//
1510 // X86-64 SSE4.1 Instructions
1511 //===----------------------------------------------------------------------===//
1513 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1514 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
1515 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
1516 (ins VR128:$src1, i32i8imm:$src2),
1517 !strconcat(OpcodeStr,
1518 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1520 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
1521 def mr : SS4AIi8<opc, MRMDestMem, (outs),
1522 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
1523 !strconcat(OpcodeStr,
1524 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1525 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
1526 addr:$dst)]>, OpSize, REX_W;
1529 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
1531 let isTwoAddress = 1 in {
1532 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
1533 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
1534 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
1535 !strconcat(OpcodeStr,
1536 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1538 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
1540 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
1541 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
1542 !strconcat(OpcodeStr,
1543 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1545 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
1546 imm:$src3)))]>, OpSize, REX_W;
1550 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;