1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
174 "#TC_RETURN $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
180 "#TC_RETURN $dst $offset",
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
220 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
223 let mayStore = 1 in {
224 def PUSH64r : I<0x50, AddRegFrm,
225 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
226 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
227 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
231 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
232 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
233 "push{q}\t$imm", []>;
234 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
235 "push{q}\t$imm", []>;
236 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
237 "push{q}\t$imm", []>;
240 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
241 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
242 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
243 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
245 def LEA64_32r : I<0x8D, MRMSrcMem,
246 (outs GR32:$dst), (ins lea64_32mem:$src),
247 "lea{l}\t{$src|$dst}, {$dst|$src}",
248 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
250 let isReMaterializable = 1 in
251 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
252 "lea{q}\t{$src|$dst}, {$dst|$src}",
253 [(set GR64:$dst, lea64addr:$src)]>;
255 let isTwoAddress = 1 in
256 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
258 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
260 // Bit scan instructions.
261 let Defs = [EFLAGS] in {
262 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
263 "bsf{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
265 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
266 "bsf{q}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
268 (implicit EFLAGS)]>, TB;
270 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
271 "bsr{q}\t{$src, $dst|$dst, $src}",
272 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
273 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
274 "bsr{q}\t{$src, $dst|$dst, $src}",
275 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
276 (implicit EFLAGS)]>, TB;
280 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
281 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
282 [(X86rep_movs i64)]>, REP;
283 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
284 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
285 [(X86rep_stos i64)]>, REP;
287 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
289 // Fast system-call instructions
290 def SYSEXIT64 : RI<0x35, RawFrm,
291 (outs), (ins), "sysexit", []>, TB;
293 //===----------------------------------------------------------------------===//
294 // Move Instructions...
297 let neverHasSideEffects = 1 in
298 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
299 "mov{q}\t{$src, $dst|$dst, $src}", []>;
301 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
302 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
303 "movabs{q}\t{$src, $dst|$dst, $src}",
304 [(set GR64:$dst, imm:$src)]>;
305 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
306 "mov{q}\t{$src, $dst|$dst, $src}",
307 [(set GR64:$dst, i64immSExt32:$src)]>;
310 let canFoldAsLoad = 1 in
311 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
312 "mov{q}\t{$src, $dst|$dst, $src}",
313 [(set GR64:$dst, (load addr:$src))]>;
315 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
316 "mov{q}\t{$src, $dst|$dst, $src}",
317 [(store GR64:$src, addr:$dst)]>;
318 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
319 "mov{q}\t{$src, $dst|$dst, $src}",
320 [(store i64immSExt32:$src, addr:$dst)]>;
322 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
323 "mov{q}\t{$src, %rax|%rax, $src}", []>;
324 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
325 "mov{q}\t{$src, %rax|%rax, $src}", []>;
326 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
327 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
328 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
329 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
331 // Sign/Zero extenders
333 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
334 // operand, which makes it a rare instruction with an 8-bit register
335 // operand that can never access an h register. If support for h registers
336 // were generalized, this would require a special register class.
337 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
338 "movs{bq|x}\t{$src, $dst|$dst, $src}",
339 [(set GR64:$dst, (sext GR8:$src))]>, TB;
340 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
341 "movs{bq|x}\t{$src, $dst|$dst, $src}",
342 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
343 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
344 "movs{wq|x}\t{$src, $dst|$dst, $src}",
345 [(set GR64:$dst, (sext GR16:$src))]>, TB;
346 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
347 "movs{wq|x}\t{$src, $dst|$dst, $src}",
348 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
349 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
350 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
351 [(set GR64:$dst, (sext GR32:$src))]>;
352 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
353 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
354 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
356 // Use movzbl instead of movzbq when the destination is a register; it's
357 // equivalent due to implicit zero-extending, and it has a smaller encoding.
358 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
359 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
360 [(set GR64:$dst, (zext GR8:$src))]>, TB;
361 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
362 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
363 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
364 // Use movzwl instead of movzwq when the destination is a register; it's
365 // equivalent due to implicit zero-extending, and it has a smaller encoding.
366 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
367 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
368 [(set GR64:$dst, (zext GR16:$src))]>, TB;
369 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
370 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
371 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
373 // There's no movzlq instruction, but movl can be used for this purpose, using
374 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
375 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
376 // zero-extension, however this isn't possible when the 32-bit value is
377 // defined by a truncate or is copied from something where the high bits aren't
378 // necessarily all zero. In such cases, we fall back to these explicit zext
380 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
381 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
382 [(set GR64:$dst, (zext GR32:$src))]>;
383 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
384 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
385 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
387 // Any instruction that defines a 32-bit result leaves the high half of the
388 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
389 // be copying from a truncate, but any other 32-bit operation will zero-extend
391 def def32 : PatLeaf<(i32 GR32:$src), [{
392 return N->getOpcode() != ISD::TRUNCATE &&
393 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
394 N->getOpcode() != ISD::CopyFromReg;
397 // In the case of a 32-bit def that is known to implicitly zero-extend,
398 // we can use a SUBREG_TO_REG.
399 def : Pat<(i64 (zext def32:$src)),
400 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
402 let neverHasSideEffects = 1 in {
403 let Defs = [RAX], Uses = [EAX] in
404 def CDQE : RI<0x98, RawFrm, (outs), (ins),
405 "{cltq|cdqe}", []>; // RAX = signext(EAX)
407 let Defs = [RAX,RDX], Uses = [RAX] in
408 def CQO : RI<0x99, RawFrm, (outs), (ins),
409 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
412 //===----------------------------------------------------------------------===//
413 // Arithmetic Instructions...
416 let Defs = [EFLAGS] in {
418 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
419 "add{q}\t{$src, %rax|%rax, $src}", []>;
421 let isTwoAddress = 1 in {
422 let isConvertibleToThreeAddress = 1 in {
423 let isCommutable = 1 in
424 // Register-Register Addition
425 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
426 "add{q}\t{$src2, $dst|$dst, $src2}",
427 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
430 // Register-Integer Addition
431 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
432 "add{q}\t{$src2, $dst|$dst, $src2}",
433 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
435 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
436 "add{q}\t{$src2, $dst|$dst, $src2}",
437 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
439 } // isConvertibleToThreeAddress
441 // Register-Memory Addition
442 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
443 "add{q}\t{$src2, $dst|$dst, $src2}",
444 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
448 // Memory-Register Addition
449 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
450 "add{q}\t{$src2, $dst|$dst, $src2}",
451 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
453 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
454 "add{q}\t{$src2, $dst|$dst, $src2}",
455 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
457 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
458 "add{q}\t{$src2, $dst|$dst, $src2}",
459 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
462 let Uses = [EFLAGS] in {
464 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
465 "adc{q}\t{$src, %rax|%rax, $src}", []>;
467 let isTwoAddress = 1 in {
468 let isCommutable = 1 in
469 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
470 "adc{q}\t{$src2, $dst|$dst, $src2}",
471 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
473 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
474 "adc{q}\t{$src2, $dst|$dst, $src2}",
475 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
477 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
478 "adc{q}\t{$src2, $dst|$dst, $src2}",
479 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
480 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
481 "adc{q}\t{$src2, $dst|$dst, $src2}",
482 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
485 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
486 "adc{q}\t{$src2, $dst|$dst, $src2}",
487 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
488 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
489 "adc{q}\t{$src2, $dst|$dst, $src2}",
490 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
491 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
492 "adc{q}\t{$src2, $dst|$dst, $src2}",
493 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
496 let isTwoAddress = 1 in {
497 // Register-Register Subtraction
498 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
499 "sub{q}\t{$src2, $dst|$dst, $src2}",
500 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
503 // Register-Memory Subtraction
504 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
505 "sub{q}\t{$src2, $dst|$dst, $src2}",
506 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
509 // Register-Integer Subtraction
510 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
511 (ins GR64:$src1, i64i8imm:$src2),
512 "sub{q}\t{$src2, $dst|$dst, $src2}",
513 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
515 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
516 (ins GR64:$src1, i64i32imm:$src2),
517 "sub{q}\t{$src2, $dst|$dst, $src2}",
518 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
522 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
523 "sub{q}\t{$src, %rax|%rax, $src}", []>;
525 // Memory-Register Subtraction
526 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
527 "sub{q}\t{$src2, $dst|$dst, $src2}",
528 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
531 // Memory-Integer Subtraction
532 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
533 "sub{q}\t{$src2, $dst|$dst, $src2}",
534 [(store (sub (load addr:$dst), i64immSExt8:$src2),
537 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
538 "sub{q}\t{$src2, $dst|$dst, $src2}",
539 [(store (sub (load addr:$dst), i64immSExt32:$src2),
543 let Uses = [EFLAGS] in {
544 let isTwoAddress = 1 in {
545 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
546 "sbb{q}\t{$src2, $dst|$dst, $src2}",
547 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
549 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
550 "sbb{q}\t{$src2, $dst|$dst, $src2}",
551 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
553 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
554 "sbb{q}\t{$src2, $dst|$dst, $src2}",
555 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
556 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
557 "sbb{q}\t{$src2, $dst|$dst, $src2}",
558 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
561 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
562 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
564 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
565 "sbb{q}\t{$src2, $dst|$dst, $src2}",
566 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
567 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
568 "sbb{q}\t{$src2, $dst|$dst, $src2}",
569 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
570 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
571 "sbb{q}\t{$src2, $dst|$dst, $src2}",
572 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
576 // Unsigned multiplication
577 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
578 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
579 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
581 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
582 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
584 // Signed multiplication
585 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
586 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
588 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
589 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
592 let Defs = [EFLAGS] in {
593 let isTwoAddress = 1 in {
594 let isCommutable = 1 in
595 // Register-Register Signed Integer Multiplication
596 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
597 (ins GR64:$src1, GR64:$src2),
598 "imul{q}\t{$src2, $dst|$dst, $src2}",
599 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
600 (implicit EFLAGS)]>, TB;
602 // Register-Memory Signed Integer Multiplication
603 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
604 (ins GR64:$src1, i64mem:$src2),
605 "imul{q}\t{$src2, $dst|$dst, $src2}",
606 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
607 (implicit EFLAGS)]>, TB;
610 // Suprisingly enough, these are not two address instructions!
612 // Register-Integer Signed Integer Multiplication
613 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
614 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
615 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
616 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
618 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
619 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
620 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
621 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
624 // Memory-Integer Signed Integer Multiplication
625 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
626 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
627 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
628 [(set GR64:$dst, (mul (load addr:$src1),
631 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
632 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
633 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
634 [(set GR64:$dst, (mul (load addr:$src1),
635 i64immSExt32:$src2)),
639 // Unsigned division / remainder
640 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
641 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
643 // Signed division / remainder
644 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
645 "idiv{q}\t$src", []>;
647 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
649 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
650 "idiv{q}\t$src", []>;
654 // Unary instructions
655 let Defs = [EFLAGS], CodeSize = 2 in {
656 let isTwoAddress = 1 in
657 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
658 [(set GR64:$dst, (ineg GR64:$src)),
660 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
661 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
664 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
665 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
666 [(set GR64:$dst, (add GR64:$src, 1)),
668 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
669 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
672 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
673 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
674 [(set GR64:$dst, (add GR64:$src, -1)),
676 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
677 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
680 // In 64-bit mode, single byte INC and DEC cannot be encoded.
681 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
682 // Can transform into LEA.
683 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
684 [(set GR16:$dst, (add GR16:$src, 1)),
686 OpSize, Requires<[In64BitMode]>;
687 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
688 [(set GR32:$dst, (add GR32:$src, 1)),
690 Requires<[In64BitMode]>;
691 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
692 [(set GR16:$dst, (add GR16:$src, -1)),
694 OpSize, Requires<[In64BitMode]>;
695 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
696 [(set GR32:$dst, (add GR32:$src, -1)),
698 Requires<[In64BitMode]>;
699 } // isConvertibleToThreeAddress
701 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
702 // how to unfold them.
703 let isTwoAddress = 0, CodeSize = 2 in {
704 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
705 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
707 OpSize, Requires<[In64BitMode]>;
708 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
709 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
711 Requires<[In64BitMode]>;
712 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
713 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
715 OpSize, Requires<[In64BitMode]>;
716 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
717 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
719 Requires<[In64BitMode]>;
721 } // Defs = [EFLAGS], CodeSize
724 let Defs = [EFLAGS] in {
725 // Shift instructions
726 let isTwoAddress = 1 in {
728 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
729 "shl{q}\t{%cl, $dst|$dst, %CL}",
730 [(set GR64:$dst, (shl GR64:$src, CL))]>;
731 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
732 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
733 "shl{q}\t{$src2, $dst|$dst, $src2}",
734 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
735 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
740 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
741 "shl{q}\t{%cl, $dst|$dst, %CL}",
742 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
743 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
744 "shl{q}\t{$src, $dst|$dst, $src}",
745 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
746 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
748 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
750 let isTwoAddress = 1 in {
752 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
753 "shr{q}\t{%cl, $dst|$dst, %CL}",
754 [(set GR64:$dst, (srl GR64:$src, CL))]>;
755 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
756 "shr{q}\t{$src2, $dst|$dst, $src2}",
757 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
758 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
760 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
764 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
765 "shr{q}\t{%cl, $dst|$dst, %CL}",
766 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
767 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
768 "shr{q}\t{$src, $dst|$dst, $src}",
769 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
770 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
772 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
774 let isTwoAddress = 1 in {
776 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
777 "sar{q}\t{%cl, $dst|$dst, %CL}",
778 [(set GR64:$dst, (sra GR64:$src, CL))]>;
779 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
780 "sar{q}\t{$src2, $dst|$dst, $src2}",
781 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
782 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
784 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
788 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
789 "sar{q}\t{%cl, $dst|$dst, %CL}",
790 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
791 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
792 "sar{q}\t{$src, $dst|$dst, $src}",
793 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
794 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
796 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
798 // Rotate instructions
799 let isTwoAddress = 1 in {
801 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
802 "rol{q}\t{%cl, $dst|$dst, %CL}",
803 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
804 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
805 "rol{q}\t{$src2, $dst|$dst, $src2}",
806 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
807 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
809 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
813 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
814 "rol{q}\t{%cl, $dst|$dst, %CL}",
815 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
816 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
817 "rol{q}\t{$src, $dst|$dst, $src}",
818 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
819 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
821 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
823 let isTwoAddress = 1 in {
825 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
826 "ror{q}\t{%cl, $dst|$dst, %CL}",
827 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
828 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
829 "ror{q}\t{$src2, $dst|$dst, $src2}",
830 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
831 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
833 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
837 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
838 "ror{q}\t{%cl, $dst|$dst, %CL}",
839 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
840 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
841 "ror{q}\t{$src, $dst|$dst, $src}",
842 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
843 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
845 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
847 // Double shift instructions (generalizations of rotate)
848 let isTwoAddress = 1 in {
850 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
851 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
852 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
853 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
854 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
855 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
858 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
859 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
860 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
861 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
862 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
865 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
866 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
867 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
868 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
875 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
876 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
877 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
879 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
880 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
881 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
884 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
885 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
886 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
887 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
888 (i8 imm:$src3)), addr:$dst)]>,
890 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
891 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
892 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
893 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
894 (i8 imm:$src3)), addr:$dst)]>,
898 //===----------------------------------------------------------------------===//
899 // Logical Instructions...
902 let isTwoAddress = 1 , AddedComplexity = 15 in
903 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
904 [(set GR64:$dst, (not GR64:$src))]>;
905 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
906 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
908 let Defs = [EFLAGS] in {
909 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
910 "and{q}\t{$src, %rax|%rax, $src}", []>;
912 let isTwoAddress = 1 in {
913 let isCommutable = 1 in
914 def AND64rr : RI<0x21, MRMDestReg,
915 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
916 "and{q}\t{$src2, $dst|$dst, $src2}",
917 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
919 def AND64rm : RI<0x23, MRMSrcMem,
920 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
921 "and{q}\t{$src2, $dst|$dst, $src2}",
922 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
924 def AND64ri8 : RIi8<0x83, MRM4r,
925 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
926 "and{q}\t{$src2, $dst|$dst, $src2}",
927 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
929 def AND64ri32 : RIi32<0x81, MRM4r,
930 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
931 "and{q}\t{$src2, $dst|$dst, $src2}",
932 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
936 def AND64mr : RI<0x21, MRMDestMem,
937 (outs), (ins i64mem:$dst, GR64:$src),
938 "and{q}\t{$src, $dst|$dst, $src}",
939 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
941 def AND64mi8 : RIi8<0x83, MRM4m,
942 (outs), (ins i64mem:$dst, i64i8imm :$src),
943 "and{q}\t{$src, $dst|$dst, $src}",
944 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
946 def AND64mi32 : RIi32<0x81, MRM4m,
947 (outs), (ins i64mem:$dst, i64i32imm:$src),
948 "and{q}\t{$src, $dst|$dst, $src}",
949 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
952 let isTwoAddress = 1 in {
953 let isCommutable = 1 in
954 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
955 "or{q}\t{$src2, $dst|$dst, $src2}",
956 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
958 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
959 "or{q}\t{$src2, $dst|$dst, $src2}",
960 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
962 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
963 "or{q}\t{$src2, $dst|$dst, $src2}",
964 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
966 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
967 "or{q}\t{$src2, $dst|$dst, $src2}",
968 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
972 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
973 "or{q}\t{$src, $dst|$dst, $src}",
974 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
976 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
977 "or{q}\t{$src, $dst|$dst, $src}",
978 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
980 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
981 "or{q}\t{$src, $dst|$dst, $src}",
982 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
985 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
986 "or{q}\t{$src, %rax|%rax, $src}", []>;
988 let isTwoAddress = 1 in {
989 let isCommutable = 1 in
990 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
991 "xor{q}\t{$src2, $dst|$dst, $src2}",
992 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
994 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
995 "xor{q}\t{$src2, $dst|$dst, $src2}",
996 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
998 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
999 "xor{q}\t{$src2, $dst|$dst, $src2}",
1000 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1001 (implicit EFLAGS)]>;
1002 def XOR64ri32 : RIi32<0x81, MRM6r,
1003 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1004 "xor{q}\t{$src2, $dst|$dst, $src2}",
1005 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1006 (implicit EFLAGS)]>;
1009 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1010 "xor{q}\t{$src, $dst|$dst, $src}",
1011 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1012 (implicit EFLAGS)]>;
1013 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1014 "xor{q}\t{$src, $dst|$dst, $src}",
1015 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1016 (implicit EFLAGS)]>;
1017 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1018 "xor{q}\t{$src, $dst|$dst, $src}",
1019 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1020 (implicit EFLAGS)]>;
1022 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1023 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1025 } // Defs = [EFLAGS]
1027 //===----------------------------------------------------------------------===//
1028 // Comparison Instructions...
1031 // Integer comparison
1032 let Defs = [EFLAGS] in {
1033 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1034 "test{q}\t{$src, %rax|%rax, $src}", []>;
1035 let isCommutable = 1 in
1036 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1037 "test{q}\t{$src2, $src1|$src1, $src2}",
1038 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1039 (implicit EFLAGS)]>;
1040 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1041 "test{q}\t{$src2, $src1|$src1, $src2}",
1042 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1043 (implicit EFLAGS)]>;
1044 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1045 (ins GR64:$src1, i64i32imm:$src2),
1046 "test{q}\t{$src2, $src1|$src1, $src2}",
1047 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1048 (implicit EFLAGS)]>;
1049 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1050 (ins i64mem:$src1, i64i32imm:$src2),
1051 "test{q}\t{$src2, $src1|$src1, $src2}",
1052 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1053 (implicit EFLAGS)]>;
1056 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1057 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1058 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1059 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1060 [(X86cmp GR64:$src1, GR64:$src2),
1061 (implicit EFLAGS)]>;
1062 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1063 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1064 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1065 (implicit EFLAGS)]>;
1066 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1067 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1068 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1069 (implicit EFLAGS)]>;
1070 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1071 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1072 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1073 (implicit EFLAGS)]>;
1074 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1075 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1076 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1077 (implicit EFLAGS)]>;
1078 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1079 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1080 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1081 (implicit EFLAGS)]>;
1082 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1083 (ins i64mem:$src1, i64i32imm:$src2),
1084 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1085 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1086 (implicit EFLAGS)]>;
1087 } // Defs = [EFLAGS]
1090 // TODO: BTC, BTR, and BTS
1091 let Defs = [EFLAGS] in {
1092 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1093 "bt{q}\t{$src2, $src1|$src1, $src2}",
1094 [(X86bt GR64:$src1, GR64:$src2),
1095 (implicit EFLAGS)]>, TB;
1097 // Unlike with the register+register form, the memory+register form of the
1098 // bt instruction does not ignore the high bits of the index. From ISel's
1099 // perspective, this is pretty bizarre. Disable these instructions for now.
1100 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1101 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1102 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1103 // (implicit EFLAGS)]>, TB;
1105 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1106 "bt{q}\t{$src2, $src1|$src1, $src2}",
1107 [(X86bt GR64:$src1, i64immSExt8:$src2),
1108 (implicit EFLAGS)]>, TB;
1109 // Note that these instructions don't need FastBTMem because that
1110 // only applies when the other operand is in a register. When it's
1111 // an immediate, bt is still fast.
1112 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1113 "bt{q}\t{$src2, $src1|$src1, $src2}",
1114 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1115 (implicit EFLAGS)]>, TB;
1116 } // Defs = [EFLAGS]
1118 // Conditional moves
1119 let Uses = [EFLAGS], isTwoAddress = 1 in {
1120 let isCommutable = 1 in {
1121 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1122 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1123 "cmovb\t{$src2, $dst|$dst, $src2}",
1124 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1125 X86_COND_B, EFLAGS))]>, TB;
1126 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1127 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1128 "cmovae\t{$src2, $dst|$dst, $src2}",
1129 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1130 X86_COND_AE, EFLAGS))]>, TB;
1131 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1132 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1133 "cmove\t{$src2, $dst|$dst, $src2}",
1134 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1135 X86_COND_E, EFLAGS))]>, TB;
1136 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1137 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1138 "cmovne\t{$src2, $dst|$dst, $src2}",
1139 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1140 X86_COND_NE, EFLAGS))]>, TB;
1141 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1142 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1143 "cmovbe\t{$src2, $dst|$dst, $src2}",
1144 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1145 X86_COND_BE, EFLAGS))]>, TB;
1146 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1147 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1148 "cmova\t{$src2, $dst|$dst, $src2}",
1149 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1150 X86_COND_A, EFLAGS))]>, TB;
1151 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1152 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1153 "cmovl\t{$src2, $dst|$dst, $src2}",
1154 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1155 X86_COND_L, EFLAGS))]>, TB;
1156 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1157 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1158 "cmovge\t{$src2, $dst|$dst, $src2}",
1159 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1160 X86_COND_GE, EFLAGS))]>, TB;
1161 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1162 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1163 "cmovle\t{$src2, $dst|$dst, $src2}",
1164 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1165 X86_COND_LE, EFLAGS))]>, TB;
1166 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1167 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1168 "cmovg\t{$src2, $dst|$dst, $src2}",
1169 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1170 X86_COND_G, EFLAGS))]>, TB;
1171 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1172 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1173 "cmovs\t{$src2, $dst|$dst, $src2}",
1174 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1175 X86_COND_S, EFLAGS))]>, TB;
1176 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1177 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1178 "cmovns\t{$src2, $dst|$dst, $src2}",
1179 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1180 X86_COND_NS, EFLAGS))]>, TB;
1181 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1182 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1183 "cmovp\t{$src2, $dst|$dst, $src2}",
1184 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1185 X86_COND_P, EFLAGS))]>, TB;
1186 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1187 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1188 "cmovnp\t{$src2, $dst|$dst, $src2}",
1189 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1190 X86_COND_NP, EFLAGS))]>, TB;
1191 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1192 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1193 "cmovo\t{$src2, $dst|$dst, $src2}",
1194 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1195 X86_COND_O, EFLAGS))]>, TB;
1196 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1197 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1198 "cmovno\t{$src2, $dst|$dst, $src2}",
1199 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1200 X86_COND_NO, EFLAGS))]>, TB;
1201 } // isCommutable = 1
1203 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1204 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1205 "cmovb\t{$src2, $dst|$dst, $src2}",
1206 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1207 X86_COND_B, EFLAGS))]>, TB;
1208 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1209 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1210 "cmovae\t{$src2, $dst|$dst, $src2}",
1211 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1212 X86_COND_AE, EFLAGS))]>, TB;
1213 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1214 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1215 "cmove\t{$src2, $dst|$dst, $src2}",
1216 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1217 X86_COND_E, EFLAGS))]>, TB;
1218 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1219 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1220 "cmovne\t{$src2, $dst|$dst, $src2}",
1221 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1222 X86_COND_NE, EFLAGS))]>, TB;
1223 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1224 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1225 "cmovbe\t{$src2, $dst|$dst, $src2}",
1226 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1227 X86_COND_BE, EFLAGS))]>, TB;
1228 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1229 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1230 "cmova\t{$src2, $dst|$dst, $src2}",
1231 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1232 X86_COND_A, EFLAGS))]>, TB;
1233 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1234 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1235 "cmovl\t{$src2, $dst|$dst, $src2}",
1236 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1237 X86_COND_L, EFLAGS))]>, TB;
1238 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1239 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1240 "cmovge\t{$src2, $dst|$dst, $src2}",
1241 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1242 X86_COND_GE, EFLAGS))]>, TB;
1243 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1244 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1245 "cmovle\t{$src2, $dst|$dst, $src2}",
1246 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1247 X86_COND_LE, EFLAGS))]>, TB;
1248 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1249 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1250 "cmovg\t{$src2, $dst|$dst, $src2}",
1251 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1252 X86_COND_G, EFLAGS))]>, TB;
1253 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1254 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1255 "cmovs\t{$src2, $dst|$dst, $src2}",
1256 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1257 X86_COND_S, EFLAGS))]>, TB;
1258 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1259 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1260 "cmovns\t{$src2, $dst|$dst, $src2}",
1261 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1262 X86_COND_NS, EFLAGS))]>, TB;
1263 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1264 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1265 "cmovp\t{$src2, $dst|$dst, $src2}",
1266 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1267 X86_COND_P, EFLAGS))]>, TB;
1268 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1269 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1270 "cmovnp\t{$src2, $dst|$dst, $src2}",
1271 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1272 X86_COND_NP, EFLAGS))]>, TB;
1273 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1274 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1275 "cmovo\t{$src2, $dst|$dst, $src2}",
1276 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1277 X86_COND_O, EFLAGS))]>, TB;
1278 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1279 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1280 "cmovno\t{$src2, $dst|$dst, $src2}",
1281 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1282 X86_COND_NO, EFLAGS))]>, TB;
1285 //===----------------------------------------------------------------------===//
1286 // Conversion Instructions...
1289 // f64 -> signed i64
1290 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1291 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1293 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1294 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1295 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1296 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1297 (load addr:$src)))]>;
1298 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1299 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1300 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1301 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1302 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1303 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1304 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1305 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1307 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1308 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1309 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1311 (int_x86_sse2_cvttsd2si64
1312 (load addr:$src)))]>;
1314 // Signed i64 -> f64
1315 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1316 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1317 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1318 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1319 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1320 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1322 let isTwoAddress = 1 in {
1323 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1324 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1325 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1327 (int_x86_sse2_cvtsi642sd VR128:$src1,
1329 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1330 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1331 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1333 (int_x86_sse2_cvtsi642sd VR128:$src1,
1334 (loadi64 addr:$src2)))]>;
1337 // Signed i64 -> f32
1338 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1339 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1340 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1341 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1342 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1343 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1345 let isTwoAddress = 1 in {
1346 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1347 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1348 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1350 (int_x86_sse_cvtsi642ss VR128:$src1,
1352 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1353 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1354 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1356 (int_x86_sse_cvtsi642ss VR128:$src1,
1357 (loadi64 addr:$src2)))]>;
1360 // f32 -> signed i64
1361 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1362 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1364 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1365 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1366 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1367 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1368 (load addr:$src)))]>;
1369 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1370 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1371 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1372 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1373 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1374 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1375 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1376 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1378 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1379 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1380 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1382 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1384 //===----------------------------------------------------------------------===//
1385 // Alias Instructions
1386 //===----------------------------------------------------------------------===//
1388 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1389 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1391 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1392 // when we have a better way to specify isel priority.
1393 let AddedComplexity = 1 in
1395 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1398 // Materialize i64 constant where top 32-bits are zero.
1399 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1400 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1401 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1402 [(set GR64:$dst, i64immZExt32:$src)]>;
1404 //===----------------------------------------------------------------------===//
1405 // Thread Local Storage Instructions
1406 //===----------------------------------------------------------------------===//
1408 // All calls clobber the non-callee saved registers. RSP is marked as
1409 // a use to prevent stack-pointer assignments that appear immediately
1410 // before calls from potentially appearing dead.
1411 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1412 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1413 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1414 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1415 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1417 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1419 "leaq\t$sym(%rip), %rdi; "
1422 "call\t__tls_get_addr@PLT",
1423 [(X86tlsaddr tls64addr:$sym)]>,
1424 Requires<[In64BitMode]>;
1426 let AddedComplexity = 5, isCodeGenOnly = 1 in
1427 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1428 "movq\t%gs:$src, $dst",
1429 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1431 let AddedComplexity = 5, isCodeGenOnly = 1 in
1432 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1433 "movq\t%fs:$src, $dst",
1434 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1436 //===----------------------------------------------------------------------===//
1437 // Atomic Instructions
1438 //===----------------------------------------------------------------------===//
1440 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1441 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1443 "cmpxchgq\t$swap,$ptr",
1444 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1447 let Constraints = "$val = $dst" in {
1448 let Defs = [EFLAGS] in
1449 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1452 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1455 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1457 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1460 // Optimized codegen when the non-memory output is not used.
1461 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1462 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1464 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1465 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1466 (ins i64mem:$dst, i64i8imm :$src2),
1468 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1469 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1470 (ins i64mem:$dst, i64i32imm :$src2),
1472 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1473 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1475 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1476 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1477 (ins i64mem:$dst, i64i8imm :$src2),
1479 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1480 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1481 (ins i64mem:$dst, i64i32imm:$src2),
1483 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1484 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1486 "inc{q}\t$dst", []>, LOCK;
1487 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1489 "dec{q}\t$dst", []>, LOCK;
1491 // Atomic exchange, and, or, xor
1492 let Constraints = "$val = $dst", Defs = [EFLAGS],
1493 usesCustomDAGSchedInserter = 1 in {
1494 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1495 "#ATOMAND64 PSEUDO!",
1496 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1497 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1498 "#ATOMOR64 PSEUDO!",
1499 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1500 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1501 "#ATOMXOR64 PSEUDO!",
1502 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1503 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1504 "#ATOMNAND64 PSEUDO!",
1505 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1506 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1507 "#ATOMMIN64 PSEUDO!",
1508 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1509 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1510 "#ATOMMAX64 PSEUDO!",
1511 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1512 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1513 "#ATOMUMIN64 PSEUDO!",
1514 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1515 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1516 "#ATOMUMAX64 PSEUDO!",
1517 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1520 //===----------------------------------------------------------------------===//
1521 // Non-Instruction Patterns
1522 //===----------------------------------------------------------------------===//
1524 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1525 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1526 // 'movabs' predicate should handle this sort of thing.
1527 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1528 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1529 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1530 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1531 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1532 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1533 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1534 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1536 // In static codegen with small code model, we can get the address of a label
1537 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1538 // the MOV64ri64i32 should accept these.
1539 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1540 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1541 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1542 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1543 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1544 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1545 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1546 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1548 // In kernel code model, we can get the address of a label
1549 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1550 // the MOV64ri32 should accept these.
1551 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1552 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1553 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1554 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1555 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1556 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1557 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1558 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1560 // If we have small model and -static mode, it is safe to store global addresses
1561 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1562 // for MOV64mi32 should handle this sort of thing.
1563 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1564 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1565 Requires<[NearData, IsStatic]>;
1566 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1567 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1568 Requires<[NearData, IsStatic]>;
1569 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1570 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1571 Requires<[NearData, IsStatic]>;
1572 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1573 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1574 Requires<[NearData, IsStatic]>;
1577 // Direct PC relative function call for small code model. 32-bit displacement
1578 // sign extended to 64-bit.
1579 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1580 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1581 def : Pat<(X86call (i64 texternalsym:$dst)),
1582 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1584 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1585 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1586 def : Pat<(X86call (i64 texternalsym:$dst)),
1587 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1590 def : Pat<(X86tcret GR64:$dst, imm:$off),
1591 (TCRETURNri64 GR64:$dst, imm:$off)>;
1593 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1594 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1596 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1597 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1601 // TEST R,R is smaller than CMP R,0
1602 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1603 (TEST64rr GR64:$src1, GR64:$src1)>;
1605 // Conditional moves with folded loads with operands swapped and conditions
1607 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1608 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1609 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1610 (CMOVB64rm GR64:$src2, addr:$src1)>;
1611 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1612 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1613 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1614 (CMOVE64rm GR64:$src2, addr:$src1)>;
1615 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1616 (CMOVA64rm GR64:$src2, addr:$src1)>;
1617 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1618 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1619 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1620 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1621 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1622 (CMOVL64rm GR64:$src2, addr:$src1)>;
1623 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1624 (CMOVG64rm GR64:$src2, addr:$src1)>;
1625 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1626 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1627 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1628 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1629 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1630 (CMOVP64rm GR64:$src2, addr:$src1)>;
1631 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1632 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1633 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1634 (CMOVS64rm GR64:$src2, addr:$src1)>;
1635 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1636 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1637 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1638 (CMOVO64rm GR64:$src2, addr:$src1)>;
1640 // zextload bool -> zextload byte
1641 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1644 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1645 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1646 // partial-register updates.
1647 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1648 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1649 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1650 // For other extloads, use subregs, since the high contents of the register are
1651 // defined after an extload.
1652 def : Pat<(extloadi64i32 addr:$src),
1653 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1656 // anyext. Define these to do an explicit zero-extend to
1657 // avoid partial-register updates.
1658 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1659 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1660 def : Pat<(i64 (anyext GR32:$src)),
1661 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1663 //===----------------------------------------------------------------------===//
1665 //===----------------------------------------------------------------------===//
1667 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1668 // +128 doesn't, so in this special case use a sub instead of an add.
1669 def : Pat<(add GR64:$src1, 128),
1670 (SUB64ri8 GR64:$src1, -128)>;
1671 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1672 (SUB64mi8 addr:$dst, -128)>;
1674 // The same trick applies for 32-bit immediate fields in 64-bit
1676 def : Pat<(add GR64:$src1, 0x0000000080000000),
1677 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1678 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1679 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1681 // r & (2^32-1) ==> movz
1682 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1683 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1684 // r & (2^16-1) ==> movz
1685 def : Pat<(and GR64:$src, 0xffff),
1686 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1687 // r & (2^8-1) ==> movz
1688 def : Pat<(and GR64:$src, 0xff),
1689 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1690 // r & (2^8-1) ==> movz
1691 def : Pat<(and GR32:$src1, 0xff),
1692 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1693 Requires<[In64BitMode]>;
1694 // r & (2^8-1) ==> movz
1695 def : Pat<(and GR16:$src1, 0xff),
1696 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1697 Requires<[In64BitMode]>;
1699 // sext_inreg patterns
1700 def : Pat<(sext_inreg GR64:$src, i32),
1701 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1702 def : Pat<(sext_inreg GR64:$src, i16),
1703 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1704 def : Pat<(sext_inreg GR64:$src, i8),
1705 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1706 def : Pat<(sext_inreg GR32:$src, i8),
1707 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1708 Requires<[In64BitMode]>;
1709 def : Pat<(sext_inreg GR16:$src, i8),
1710 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1711 Requires<[In64BitMode]>;
1714 def : Pat<(i32 (trunc GR64:$src)),
1715 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1716 def : Pat<(i16 (trunc GR64:$src)),
1717 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1718 def : Pat<(i8 (trunc GR64:$src)),
1719 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1720 def : Pat<(i8 (trunc GR32:$src)),
1721 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1722 Requires<[In64BitMode]>;
1723 def : Pat<(i8 (trunc GR16:$src)),
1724 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1725 Requires<[In64BitMode]>;
1727 // h-register tricks.
1728 // For now, be conservative on x86-64 and use an h-register extract only if the
1729 // value is immediately zero-extended or stored, which are somewhat common
1730 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1731 // from being allocated in the same instruction as the h register, as there's
1732 // currently no way to describe this requirement to the register allocator.
1734 // h-register extract and zero-extend.
1735 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1739 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1740 x86_subreg_8bit_hi)),
1742 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1744 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1745 x86_subreg_8bit_hi))>,
1746 Requires<[In64BitMode]>;
1747 def : Pat<(srl_su GR16:$src, (i8 8)),
1750 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1751 x86_subreg_8bit_hi)),
1753 Requires<[In64BitMode]>;
1754 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1756 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1757 x86_subreg_8bit_hi))>,
1758 Requires<[In64BitMode]>;
1759 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1761 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1762 x86_subreg_8bit_hi))>,
1763 Requires<[In64BitMode]>;
1764 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1768 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1769 x86_subreg_8bit_hi)),
1771 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1775 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1776 x86_subreg_8bit_hi)),
1779 // h-register extract and store.
1780 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1783 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1784 x86_subreg_8bit_hi))>;
1785 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1788 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1789 x86_subreg_8bit_hi))>,
1790 Requires<[In64BitMode]>;
1791 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1794 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1795 x86_subreg_8bit_hi))>,
1796 Requires<[In64BitMode]>;
1798 // (shl x, 1) ==> (add x, x)
1799 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1801 // (shl x (and y, 63)) ==> (shl x, y)
1802 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1803 (SHL64rCL GR64:$src1)>;
1804 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1805 (SHL64mCL addr:$dst)>;
1807 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1808 (SHR64rCL GR64:$src1)>;
1809 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1810 (SHR64mCL addr:$dst)>;
1812 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1813 (SAR64rCL GR64:$src1)>;
1814 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1815 (SAR64mCL addr:$dst)>;
1817 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1818 def : Pat<(or (srl GR64:$src1, CL:$amt),
1819 (shl GR64:$src2, (sub 64, CL:$amt))),
1820 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1822 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1823 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1824 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1826 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1827 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1828 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1830 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1831 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1833 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1835 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1836 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1838 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1839 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1840 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1842 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1843 def : Pat<(or (shl GR64:$src1, CL:$amt),
1844 (srl GR64:$src2, (sub 64, CL:$amt))),
1845 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1847 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1848 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1849 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1851 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1852 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1853 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1855 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1856 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1858 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1860 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1861 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1863 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1864 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1865 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1867 // X86 specific add which produces a flag.
1868 def : Pat<(addc GR64:$src1, GR64:$src2),
1869 (ADD64rr GR64:$src1, GR64:$src2)>;
1870 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1871 (ADD64rm GR64:$src1, addr:$src2)>;
1872 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1873 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1874 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1875 (ADD64ri32 GR64:$src1, imm:$src2)>;
1877 def : Pat<(subc GR64:$src1, GR64:$src2),
1878 (SUB64rr GR64:$src1, GR64:$src2)>;
1879 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1880 (SUB64rm GR64:$src1, addr:$src2)>;
1881 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1882 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1883 def : Pat<(subc GR64:$src1, imm:$src2),
1884 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1886 //===----------------------------------------------------------------------===//
1887 // EFLAGS-defining Patterns
1888 //===----------------------------------------------------------------------===//
1890 // Register-Register Addition with EFLAGS result
1891 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1893 (ADD64rr GR64:$src1, GR64:$src2)>;
1895 // Register-Integer Addition with EFLAGS result
1896 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1898 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1899 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1901 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1903 // Register-Memory Addition with EFLAGS result
1904 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1906 (ADD64rm GR64:$src1, addr:$src2)>;
1908 // Memory-Register Addition with EFLAGS result
1909 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1912 (ADD64mr addr:$dst, GR64:$src2)>;
1913 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1916 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1917 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1920 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1922 // Register-Register Subtraction with EFLAGS result
1923 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1925 (SUB64rr GR64:$src1, GR64:$src2)>;
1927 // Register-Memory Subtraction with EFLAGS result
1928 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1930 (SUB64rm GR64:$src1, addr:$src2)>;
1932 // Register-Integer Subtraction with EFLAGS result
1933 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1935 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1936 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1938 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1940 // Memory-Register Subtraction with EFLAGS result
1941 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1944 (SUB64mr addr:$dst, GR64:$src2)>;
1946 // Memory-Integer Subtraction with EFLAGS result
1947 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1950 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1951 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1954 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1956 // Register-Register Signed Integer Multiplication with EFLAGS result
1957 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1959 (IMUL64rr GR64:$src1, GR64:$src2)>;
1961 // Register-Memory Signed Integer Multiplication with EFLAGS result
1962 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1964 (IMUL64rm GR64:$src1, addr:$src2)>;
1966 // Register-Integer Signed Integer Multiplication with EFLAGS result
1967 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1969 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1970 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1972 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1974 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1975 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1977 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1978 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1980 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1982 // INC and DEC with EFLAGS result. Note that these do not set CF.
1983 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1984 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1985 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1987 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1988 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1989 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1990 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1992 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1994 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1995 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1996 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1998 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1999 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2000 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2001 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2003 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2005 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2006 (INC64r GR64:$src)>;
2007 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2009 (INC64m addr:$dst)>;
2010 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2011 (DEC64r GR64:$src)>;
2012 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2014 (DEC64m addr:$dst)>;
2016 //===----------------------------------------------------------------------===//
2017 // X86-64 SSE Instructions
2018 //===----------------------------------------------------------------------===//
2020 // Move instructions...
2022 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2023 "mov{d|q}\t{$src, $dst|$dst, $src}",
2025 (v2i64 (scalar_to_vector GR64:$src)))]>;
2026 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2027 "mov{d|q}\t{$src, $dst|$dst, $src}",
2028 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2031 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2032 "mov{d|q}\t{$src, $dst|$dst, $src}",
2033 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2034 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2035 "movq\t{$src, $dst|$dst, $src}",
2036 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2038 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2039 "mov{d|q}\t{$src, $dst|$dst, $src}",
2040 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2041 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2042 "movq\t{$src, $dst|$dst, $src}",
2043 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2045 //===----------------------------------------------------------------------===//
2046 // X86-64 SSE4.1 Instructions
2047 //===----------------------------------------------------------------------===//
2049 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2050 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2051 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2052 (ins VR128:$src1, i32i8imm:$src2),
2053 !strconcat(OpcodeStr,
2054 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2056 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2057 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2058 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2059 !strconcat(OpcodeStr,
2060 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2061 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2062 addr:$dst)]>, OpSize, REX_W;
2065 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2067 let isTwoAddress = 1 in {
2068 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2069 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2070 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2071 !strconcat(OpcodeStr,
2072 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2074 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2076 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2077 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2078 !strconcat(OpcodeStr,
2079 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2081 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2082 imm:$src3)))]>, OpSize, REX_W;
2086 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2088 // -disable-16bit support.
2089 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2090 (MOV16mi addr:$dst, imm:$src)>;
2091 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2092 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2093 def : Pat<(i64 (sextloadi16 addr:$dst)),
2094 (MOVSX64rm16 addr:$dst)>;
2095 def : Pat<(i64 (zextloadi16 addr:$dst)),
2096 (MOVZX64rm16 addr:$dst)>;
2097 def : Pat<(i64 (extloadi16 addr:$dst)),
2098 (MOVZX64rm16 addr:$dst)>;