1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
27 let ParserMatchClass = X86AbsMemAsmOperand;
31 // 64-bits but only 8 bits are significant.
32 def i64i8imm : Operand<i64> {
33 let ParserMatchClass = ImmSExt8AsmOperand;
36 def lea64mem : Operand<i64> {
37 let PrintMethod = "printlea64mem";
38 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
39 let ParserMatchClass = X86NoSegMemAsmOperand;
42 def lea64_32mem : Operand<i32> {
43 let PrintMethod = "printlea64_32mem";
44 let AsmOperandLowerMethod = "lower_lea64_32mem";
45 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
46 let ParserMatchClass = X86NoSegMemAsmOperand;
49 //===----------------------------------------------------------------------===//
50 // Complex Pattern Definitions.
52 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
53 [add, sub, mul, X86mul_imm, shl, or, frameindex,
56 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
57 [tglobaltlsaddr], []>;
59 //===----------------------------------------------------------------------===//
63 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
65 def GetLo32XForm : SDNodeXForm<imm, [{
66 // Transformation function: get the low 32 bits.
67 return getI32Imm((unsigned)N->getZExtValue());
70 def i64immSExt32 : PatLeaf<(i64 imm), [{
71 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
72 // sign extended field.
73 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
77 def i64immZExt32 : PatLeaf<(i64 imm), [{
78 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
79 // unsignedsign extended field.
80 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
83 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
84 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
85 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
87 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
88 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
89 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
90 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
92 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
93 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
94 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
95 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
97 //===----------------------------------------------------------------------===//
98 // Instruction list...
101 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
102 // a stack adjustment and the codegen must know that they may modify the stack
103 // pointer before prolog-epilog rewriting occurs.
104 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
105 // sub / add which can clobber EFLAGS.
106 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
107 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
109 [(X86callseq_start timm:$amt)]>,
110 Requires<[In64BitMode]>;
111 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
113 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
114 Requires<[In64BitMode]>;
117 // Interrupt Instructions
118 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
120 //===----------------------------------------------------------------------===//
121 // Call Instructions...
124 // All calls clobber the non-callee saved registers. RSP is marked as
125 // a use to prevent stack-pointer assignments that appear immediately
126 // before calls from potentially appearing dead. Uses for argument
127 // registers are added manually.
128 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
129 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
130 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
131 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
132 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
135 // NOTE: this pattern doesn't match "X86call imm", because we do not know
136 // that the offset between an arbitrary immediate and the call will fit in
137 // the 32-bit pcrel field that we have.
138 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
139 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
140 "call{q}\t$dst", []>,
141 Requires<[In64BitMode, NotWin64]>;
142 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
143 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
144 Requires<[NotWin64]>;
145 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
146 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
147 Requires<[NotWin64]>;
149 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
150 "lcall{q}\t{*}$dst", []>;
153 // FIXME: We need to teach codegen about single list of call-clobbered
156 // All calls clobber the non-callee saved registers. RSP is marked as
157 // a use to prevent stack-pointer assignments that appear immediately
158 // before calls from potentially appearing dead. Uses for argument
159 // registers are added manually.
160 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
161 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
162 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
163 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
165 def WINCALL64pcrel32 : I<0xE8, RawFrm,
166 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
169 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
171 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
172 def WINCALL64m : I<0xFF, MRM2m, (outs),
173 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
174 [(X86call (loadi64 addr:$dst))]>,
179 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
180 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
182 "#TC_RETURN $dst $offset",
185 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
186 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
188 "#TC_RETURN $dst $offset",
192 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
193 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst, variable_ops),
194 "jmp{q}\t{*}$dst # TAILCALL",
198 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
199 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
201 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
202 [(brind GR64:$dst)]>;
203 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
204 [(brind (loadi64 addr:$dst))]>;
205 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
206 "ljmp{q}\t{*}$dst", []>;
209 //===----------------------------------------------------------------------===//
210 // EH Pseudo Instructions
212 let isTerminator = 1, isReturn = 1, isBarrier = 1,
213 hasCtrlDep = 1, isCodeGenOnly = 1 in {
214 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
215 "ret\t#eh_return, addr: $addr",
216 [(X86ehret GR64:$addr)]>;
220 //===----------------------------------------------------------------------===//
221 // Miscellaneous Instructions...
224 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
225 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
226 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
227 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
229 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
230 def LEAVE64 : I<0xC9, RawFrm,
231 (outs), (ins), "leave", []>;
232 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
234 def POP64r : I<0x58, AddRegFrm,
235 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
236 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
237 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
239 let mayStore = 1 in {
240 def PUSH64r : I<0x50, AddRegFrm,
241 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
242 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
243 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
247 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
248 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
249 "push{q}\t$imm", []>;
250 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
251 "push{q}\t$imm", []>;
252 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
253 "push{q}\t$imm", []>;
256 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
257 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
258 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
259 def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
261 def LEA64_32r : I<0x8D, MRMSrcMem,
262 (outs GR32:$dst), (ins lea64_32mem:$src),
263 "lea{l}\t{$src|$dst}, {$dst|$src}",
264 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
266 let isReMaterializable = 1 in
267 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
268 "lea{q}\t{$src|$dst}, {$dst|$src}",
269 [(set GR64:$dst, lea64addr:$src)]>;
271 let isTwoAddress = 1 in
272 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
274 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
276 // Bit scan instructions.
277 let Defs = [EFLAGS] in {
278 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
279 "bsf{q}\t{$src, $dst|$dst, $src}",
280 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
281 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
282 "bsf{q}\t{$src, $dst|$dst, $src}",
283 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
284 (implicit EFLAGS)]>, TB;
286 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
287 "bsr{q}\t{$src, $dst|$dst, $src}",
288 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
289 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
290 "bsr{q}\t{$src, $dst|$dst, $src}",
291 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
292 (implicit EFLAGS)]>, TB;
296 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
297 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
298 [(X86rep_movs i64)]>, REP;
299 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
300 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
301 [(X86rep_stos i64)]>, REP;
303 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
305 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
307 // Fast system-call instructions
308 def SYSEXIT64 : RI<0x35, RawFrm,
309 (outs), (ins), "sysexit", []>, TB;
311 //===----------------------------------------------------------------------===//
312 // Move Instructions...
315 let neverHasSideEffects = 1 in
316 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
317 "mov{q}\t{$src, $dst|$dst, $src}", []>;
319 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
320 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
321 "movabs{q}\t{$src, $dst|$dst, $src}",
322 [(set GR64:$dst, imm:$src)]>;
323 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
324 "mov{q}\t{$src, $dst|$dst, $src}",
325 [(set GR64:$dst, i64immSExt32:$src)]>;
328 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
329 "mov{q}\t{$src, $dst|$dst, $src}", []>;
331 let canFoldAsLoad = 1, isReMaterializable = 1 in
332 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
333 "mov{q}\t{$src, $dst|$dst, $src}",
334 [(set GR64:$dst, (load addr:$src))]>;
336 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
337 "mov{q}\t{$src, $dst|$dst, $src}",
338 [(store GR64:$src, addr:$dst)]>;
339 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
340 "mov{q}\t{$src, $dst|$dst, $src}",
341 [(store i64immSExt32:$src, addr:$dst)]>;
343 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
344 "mov{q}\t{$src, %rax|%rax, $src}", []>;
345 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
346 "mov{q}\t{$src, %rax|%rax, $src}", []>;
347 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
348 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
349 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
350 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
352 // Moves to and from segment registers
353 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
354 "mov{q}\t{$src, $dst|$dst, $src}", []>;
355 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
356 "mov{q}\t{$src, $dst|$dst, $src}", []>;
357 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
358 "mov{q}\t{$src, $dst|$dst, $src}", []>;
359 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
360 "mov{q}\t{$src, $dst|$dst, $src}", []>;
362 // Moves to and from debug registers
363 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
364 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
365 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
366 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
368 // Moves to and from control registers
369 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
370 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
371 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
372 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
374 // Sign/Zero extenders
376 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
377 // operand, which makes it a rare instruction with an 8-bit register
378 // operand that can never access an h register. If support for h registers
379 // were generalized, this would require a special register class.
380 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
381 "movs{bq|x}\t{$src, $dst|$dst, $src}",
382 [(set GR64:$dst, (sext GR8:$src))]>, TB;
383 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
384 "movs{bq|x}\t{$src, $dst|$dst, $src}",
385 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
386 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
387 "movs{wq|x}\t{$src, $dst|$dst, $src}",
388 [(set GR64:$dst, (sext GR16:$src))]>, TB;
389 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
390 "movs{wq|x}\t{$src, $dst|$dst, $src}",
391 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
392 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
393 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
394 [(set GR64:$dst, (sext GR32:$src))]>;
395 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
396 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
397 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
399 // movzbq and movzwq encodings for the disassembler
400 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
401 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
402 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
403 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
404 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
405 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
406 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
407 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
409 // Use movzbl instead of movzbq when the destination is a register; it's
410 // equivalent due to implicit zero-extending, and it has a smaller encoding.
411 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
412 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
413 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
414 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
415 // Use movzwl instead of movzwq when the destination is a register; it's
416 // equivalent due to implicit zero-extending, and it has a smaller encoding.
417 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
418 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
419 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
420 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
422 // There's no movzlq instruction, but movl can be used for this purpose, using
423 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
424 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
425 // zero-extension, however this isn't possible when the 32-bit value is
426 // defined by a truncate or is copied from something where the high bits aren't
427 // necessarily all zero. In such cases, we fall back to these explicit zext
429 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
430 "", [(set GR64:$dst, (zext GR32:$src))]>;
431 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
432 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
434 // Any instruction that defines a 32-bit result leaves the high half of the
435 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
436 // be copying from a truncate. And x86's cmov doesn't do anything if the
437 // condition is false. But any other 32-bit operation will zero-extend
439 def def32 : PatLeaf<(i32 GR32:$src), [{
440 return N->getOpcode() != ISD::TRUNCATE &&
441 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
442 N->getOpcode() != ISD::CopyFromReg &&
443 N->getOpcode() != X86ISD::CMOV;
446 // In the case of a 32-bit def that is known to implicitly zero-extend,
447 // we can use a SUBREG_TO_REG.
448 def : Pat<(i64 (zext def32:$src)),
449 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
451 let neverHasSideEffects = 1 in {
452 let Defs = [RAX], Uses = [EAX] in
453 def CDQE : RI<0x98, RawFrm, (outs), (ins),
454 "{cltq|cdqe}", []>; // RAX = signext(EAX)
456 let Defs = [RAX,RDX], Uses = [RAX] in
457 def CQO : RI<0x99, RawFrm, (outs), (ins),
458 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
461 //===----------------------------------------------------------------------===//
462 // Arithmetic Instructions...
465 let Defs = [EFLAGS] in {
467 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i32imm:$src),
468 "add{q}\t{$src, %rax|%rax, $src}", []>;
470 let isTwoAddress = 1 in {
471 let isConvertibleToThreeAddress = 1 in {
472 let isCommutable = 1 in
473 // Register-Register Addition
474 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
475 (ins GR64:$src1, GR64:$src2),
476 "add{q}\t{$src2, $dst|$dst, $src2}",
477 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
480 // Register-Integer Addition
481 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
482 (ins GR64:$src1, i64i8imm:$src2),
483 "add{q}\t{$src2, $dst|$dst, $src2}",
484 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
486 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
487 (ins GR64:$src1, i64i32imm:$src2),
488 "add{q}\t{$src2, $dst|$dst, $src2}",
489 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
491 } // isConvertibleToThreeAddress
493 // Register-Memory Addition
494 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
495 (ins GR64:$src1, i64mem:$src2),
496 "add{q}\t{$src2, $dst|$dst, $src2}",
497 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
500 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
501 // differently encoded.
502 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
503 (ins GR64:$src1, GR64:$src2),
504 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
508 // Memory-Register Addition
509 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
510 "add{q}\t{$src2, $dst|$dst, $src2}",
511 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
513 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
514 "add{q}\t{$src2, $dst|$dst, $src2}",
515 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
517 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
518 "add{q}\t{$src2, $dst|$dst, $src2}",
519 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
522 let Uses = [EFLAGS] in {
524 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i32imm:$src),
525 "adc{q}\t{$src, %rax|%rax, $src}", []>;
527 let isTwoAddress = 1 in {
528 let isCommutable = 1 in
529 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
530 (ins GR64:$src1, GR64:$src2),
531 "adc{q}\t{$src2, $dst|$dst, $src2}",
532 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
534 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
535 (ins GR64:$src1, GR64:$src2),
536 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
538 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
539 (ins GR64:$src1, i64mem:$src2),
540 "adc{q}\t{$src2, $dst|$dst, $src2}",
541 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
543 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
544 (ins GR64:$src1, i64i8imm:$src2),
545 "adc{q}\t{$src2, $dst|$dst, $src2}",
546 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
547 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
548 (ins GR64:$src1, i64i32imm:$src2),
549 "adc{q}\t{$src2, $dst|$dst, $src2}",
550 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
553 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
554 "adc{q}\t{$src2, $dst|$dst, $src2}",
555 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
556 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
557 "adc{q}\t{$src2, $dst|$dst, $src2}",
558 [(store (adde (load addr:$dst), i64immSExt8:$src2),
560 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
561 "adc{q}\t{$src2, $dst|$dst, $src2}",
562 [(store (adde (load addr:$dst), i64immSExt32:$src2),
566 let isTwoAddress = 1 in {
567 // Register-Register Subtraction
568 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
569 (ins GR64:$src1, GR64:$src2),
570 "sub{q}\t{$src2, $dst|$dst, $src2}",
571 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
574 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
575 (ins GR64:$src1, GR64:$src2),
576 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
578 // Register-Memory Subtraction
579 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
580 (ins GR64:$src1, i64mem:$src2),
581 "sub{q}\t{$src2, $dst|$dst, $src2}",
582 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
585 // Register-Integer Subtraction
586 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
587 (ins GR64:$src1, i64i8imm:$src2),
588 "sub{q}\t{$src2, $dst|$dst, $src2}",
589 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
591 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
592 (ins GR64:$src1, i64i32imm:$src2),
593 "sub{q}\t{$src2, $dst|$dst, $src2}",
594 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
598 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i32imm:$src),
599 "sub{q}\t{$src, %rax|%rax, $src}", []>;
601 // Memory-Register Subtraction
602 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
603 "sub{q}\t{$src2, $dst|$dst, $src2}",
604 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
607 // Memory-Integer Subtraction
608 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
609 "sub{q}\t{$src2, $dst|$dst, $src2}",
610 [(store (sub (load addr:$dst), i64immSExt8:$src2),
613 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
614 "sub{q}\t{$src2, $dst|$dst, $src2}",
615 [(store (sub (load addr:$dst), i64immSExt32:$src2),
619 let Uses = [EFLAGS] in {
620 let isTwoAddress = 1 in {
621 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
622 (ins GR64:$src1, GR64:$src2),
623 "sbb{q}\t{$src2, $dst|$dst, $src2}",
624 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
626 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
627 (ins GR64:$src1, GR64:$src2),
628 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
630 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
631 (ins GR64:$src1, i64mem:$src2),
632 "sbb{q}\t{$src2, $dst|$dst, $src2}",
633 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
635 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
636 (ins GR64:$src1, i64i8imm:$src2),
637 "sbb{q}\t{$src2, $dst|$dst, $src2}",
638 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
639 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
640 (ins GR64:$src1, i64i32imm:$src2),
641 "sbb{q}\t{$src2, $dst|$dst, $src2}",
642 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
645 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i32imm:$src),
646 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
648 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
649 "sbb{q}\t{$src2, $dst|$dst, $src2}",
650 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
651 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
652 "sbb{q}\t{$src2, $dst|$dst, $src2}",
653 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
654 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
655 "sbb{q}\t{$src2, $dst|$dst, $src2}",
656 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
660 // Unsigned multiplication
661 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
662 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
663 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
665 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
666 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
668 // Signed multiplication
669 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
670 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
672 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
673 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
676 let Defs = [EFLAGS] in {
677 let isTwoAddress = 1 in {
678 let isCommutable = 1 in
679 // Register-Register Signed Integer Multiplication
680 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
681 (ins GR64:$src1, GR64:$src2),
682 "imul{q}\t{$src2, $dst|$dst, $src2}",
683 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
684 (implicit EFLAGS)]>, TB;
686 // Register-Memory Signed Integer Multiplication
687 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
688 (ins GR64:$src1, i64mem:$src2),
689 "imul{q}\t{$src2, $dst|$dst, $src2}",
690 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
691 (implicit EFLAGS)]>, TB;
694 // Suprisingly enough, these are not two address instructions!
696 // Register-Integer Signed Integer Multiplication
697 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
698 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
699 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
700 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
702 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
703 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
704 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
705 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
708 // Memory-Integer Signed Integer Multiplication
709 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
710 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
711 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
712 [(set GR64:$dst, (mul (load addr:$src1),
715 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
716 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
717 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 [(set GR64:$dst, (mul (load addr:$src1),
719 i64immSExt32:$src2)),
723 // Unsigned division / remainder
724 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
725 // RDX:RAX/r64 = RAX,RDX
726 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
728 // Signed division / remainder
729 // RDX:RAX/r64 = RAX,RDX
730 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
731 "idiv{q}\t$src", []>;
733 // RDX:RAX/[mem64] = RAX,RDX
734 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
736 // RDX:RAX/[mem64] = RAX,RDX
737 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
738 "idiv{q}\t$src", []>;
742 // Unary instructions
743 let Defs = [EFLAGS], CodeSize = 2 in {
744 let isTwoAddress = 1 in
745 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
746 [(set GR64:$dst, (ineg GR64:$src)),
748 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
749 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
752 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
753 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
754 [(set GR64:$dst, (add GR64:$src, 1)),
756 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
757 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
760 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
761 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
762 [(set GR64:$dst, (add GR64:$src, -1)),
764 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
765 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
768 // In 64-bit mode, single byte INC and DEC cannot be encoded.
769 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
770 // Can transform into LEA.
771 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
773 [(set GR16:$dst, (add GR16:$src, 1)),
775 OpSize, Requires<[In64BitMode]>;
776 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
778 [(set GR32:$dst, (add GR32:$src, 1)),
780 Requires<[In64BitMode]>;
781 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
783 [(set GR16:$dst, (add GR16:$src, -1)),
785 OpSize, Requires<[In64BitMode]>;
786 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
788 [(set GR32:$dst, (add GR32:$src, -1)),
790 Requires<[In64BitMode]>;
791 } // isConvertibleToThreeAddress
793 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
794 // how to unfold them.
795 let isTwoAddress = 0, CodeSize = 2 in {
796 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
797 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
799 OpSize, Requires<[In64BitMode]>;
800 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
801 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
803 Requires<[In64BitMode]>;
804 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
805 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
807 OpSize, Requires<[In64BitMode]>;
808 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
809 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
811 Requires<[In64BitMode]>;
813 } // Defs = [EFLAGS], CodeSize
816 let Defs = [EFLAGS] in {
817 // Shift instructions
818 let isTwoAddress = 1 in {
820 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
821 "shl{q}\t{%cl, $dst|$dst, %CL}",
822 [(set GR64:$dst, (shl GR64:$src, CL))]>;
823 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
824 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
825 (ins GR64:$src1, i8imm:$src2),
826 "shl{q}\t{$src2, $dst|$dst, $src2}",
827 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
828 // NOTE: We don't include patterns for shifts of a register by one, because
829 // 'add reg,reg' is cheaper.
830 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
835 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
836 "shl{q}\t{%cl, $dst|$dst, %CL}",
837 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
838 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
839 "shl{q}\t{$src, $dst|$dst, $src}",
840 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
841 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
843 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
845 let isTwoAddress = 1 in {
847 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
848 "shr{q}\t{%cl, $dst|$dst, %CL}",
849 [(set GR64:$dst, (srl GR64:$src, CL))]>;
850 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
851 "shr{q}\t{$src2, $dst|$dst, $src2}",
852 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
853 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
855 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
859 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
860 "shr{q}\t{%cl, $dst|$dst, %CL}",
861 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
862 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
863 "shr{q}\t{$src, $dst|$dst, $src}",
864 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
865 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
867 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
869 let isTwoAddress = 1 in {
871 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
872 "sar{q}\t{%cl, $dst|$dst, %CL}",
873 [(set GR64:$dst, (sra GR64:$src, CL))]>;
874 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
875 (ins GR64:$src1, i8imm:$src2),
876 "sar{q}\t{$src2, $dst|$dst, $src2}",
877 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
878 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
880 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
884 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
885 "sar{q}\t{%cl, $dst|$dst, %CL}",
886 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
887 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
888 "sar{q}\t{$src, $dst|$dst, $src}",
889 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
890 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
892 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
894 // Rotate instructions
896 let isTwoAddress = 1 in {
897 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
898 "rcl{q}\t{1, $dst|$dst, 1}", []>;
899 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
900 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
902 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
903 "rcr{q}\t{1, $dst|$dst, 1}", []>;
904 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
905 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
908 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
909 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
910 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
911 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
915 let isTwoAddress = 0 in {
916 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
917 "rcl{q}\t{1, $dst|$dst, 1}", []>;
918 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
919 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
920 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
921 "rcr{q}\t{1, $dst|$dst, 1}", []>;
922 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
923 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
926 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
927 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
928 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
929 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
933 let isTwoAddress = 1 in {
935 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
936 "rol{q}\t{%cl, $dst|$dst, %CL}",
937 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
938 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
939 (ins GR64:$src1, i8imm:$src2),
940 "rol{q}\t{$src2, $dst|$dst, $src2}",
941 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
942 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
944 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
948 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
949 "rol{q}\t{%cl, $dst|$dst, %CL}",
950 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
951 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
952 "rol{q}\t{$src, $dst|$dst, $src}",
953 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
954 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
956 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
958 let isTwoAddress = 1 in {
960 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
961 "ror{q}\t{%cl, $dst|$dst, %CL}",
962 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
963 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
964 (ins GR64:$src1, i8imm:$src2),
965 "ror{q}\t{$src2, $dst|$dst, $src2}",
966 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
967 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
969 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
973 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
974 "ror{q}\t{%cl, $dst|$dst, %CL}",
975 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
976 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
977 "ror{q}\t{$src, $dst|$dst, $src}",
978 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
979 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
981 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
983 // Double shift instructions (generalizations of rotate)
984 let isTwoAddress = 1 in {
986 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
987 (ins GR64:$src1, GR64:$src2),
988 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
989 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
991 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
992 (ins GR64:$src1, GR64:$src2),
993 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
994 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
998 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
999 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
1001 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1002 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1003 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1006 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1008 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1009 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1010 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1016 let Uses = [CL] in {
1017 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1018 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1019 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1021 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1022 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1023 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1026 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1027 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1028 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1029 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1030 (i8 imm:$src3)), addr:$dst)]>,
1032 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1033 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1034 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1035 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1036 (i8 imm:$src3)), addr:$dst)]>,
1038 } // Defs = [EFLAGS]
1040 //===----------------------------------------------------------------------===//
1041 // Logical Instructions...
1044 let isTwoAddress = 1 , AddedComplexity = 15 in
1045 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1046 [(set GR64:$dst, (not GR64:$src))]>;
1047 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1048 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1050 let Defs = [EFLAGS] in {
1051 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i32imm:$src),
1052 "and{q}\t{$src, %rax|%rax, $src}", []>;
1054 let isTwoAddress = 1 in {
1055 let isCommutable = 1 in
1056 def AND64rr : RI<0x21, MRMDestReg,
1057 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1058 "and{q}\t{$src2, $dst|$dst, $src2}",
1059 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
1060 (implicit EFLAGS)]>;
1061 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1062 (ins GR64:$src1, GR64:$src2),
1063 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
1064 def AND64rm : RI<0x23, MRMSrcMem,
1065 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1066 "and{q}\t{$src2, $dst|$dst, $src2}",
1067 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
1068 (implicit EFLAGS)]>;
1069 def AND64ri8 : RIi8<0x83, MRM4r,
1070 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1071 "and{q}\t{$src2, $dst|$dst, $src2}",
1072 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
1073 (implicit EFLAGS)]>;
1074 def AND64ri32 : RIi32<0x81, MRM4r,
1075 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1076 "and{q}\t{$src2, $dst|$dst, $src2}",
1077 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
1078 (implicit EFLAGS)]>;
1081 def AND64mr : RI<0x21, MRMDestMem,
1082 (outs), (ins i64mem:$dst, GR64:$src),
1083 "and{q}\t{$src, $dst|$dst, $src}",
1084 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
1085 (implicit EFLAGS)]>;
1086 def AND64mi8 : RIi8<0x83, MRM4m,
1087 (outs), (ins i64mem:$dst, i64i8imm :$src),
1088 "and{q}\t{$src, $dst|$dst, $src}",
1089 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1090 (implicit EFLAGS)]>;
1091 def AND64mi32 : RIi32<0x81, MRM4m,
1092 (outs), (ins i64mem:$dst, i64i32imm:$src),
1093 "and{q}\t{$src, $dst|$dst, $src}",
1094 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1095 (implicit EFLAGS)]>;
1097 let isTwoAddress = 1 in {
1098 let isCommutable = 1 in
1099 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1100 (ins GR64:$src1, GR64:$src2),
1101 "or{q}\t{$src2, $dst|$dst, $src2}",
1102 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
1103 (implicit EFLAGS)]>;
1104 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1105 (ins GR64:$src1, GR64:$src2),
1106 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1107 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1108 (ins GR64:$src1, i64mem:$src2),
1109 "or{q}\t{$src2, $dst|$dst, $src2}",
1110 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
1111 (implicit EFLAGS)]>;
1112 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1113 (ins GR64:$src1, i64i8imm:$src2),
1114 "or{q}\t{$src2, $dst|$dst, $src2}",
1115 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
1116 (implicit EFLAGS)]>;
1117 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1118 (ins GR64:$src1, i64i32imm:$src2),
1119 "or{q}\t{$src2, $dst|$dst, $src2}",
1120 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
1121 (implicit EFLAGS)]>;
1124 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1125 "or{q}\t{$src, $dst|$dst, $src}",
1126 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1127 (implicit EFLAGS)]>;
1128 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1129 "or{q}\t{$src, $dst|$dst, $src}",
1130 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1131 (implicit EFLAGS)]>;
1132 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1133 "or{q}\t{$src, $dst|$dst, $src}",
1134 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1135 (implicit EFLAGS)]>;
1137 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1138 "or{q}\t{$src, %rax|%rax, $src}", []>;
1140 let isTwoAddress = 1 in {
1141 let isCommutable = 1 in
1142 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1143 (ins GR64:$src1, GR64:$src2),
1144 "xor{q}\t{$src2, $dst|$dst, $src2}",
1145 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1146 (implicit EFLAGS)]>;
1147 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1148 (ins GR64:$src1, GR64:$src2),
1149 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1150 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1151 (ins GR64:$src1, i64mem:$src2),
1152 "xor{q}\t{$src2, $dst|$dst, $src2}",
1153 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1154 (implicit EFLAGS)]>;
1155 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1156 (ins GR64:$src1, i64i8imm:$src2),
1157 "xor{q}\t{$src2, $dst|$dst, $src2}",
1158 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1159 (implicit EFLAGS)]>;
1160 def XOR64ri32 : RIi32<0x81, MRM6r,
1161 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1162 "xor{q}\t{$src2, $dst|$dst, $src2}",
1163 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1164 (implicit EFLAGS)]>;
1167 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1168 "xor{q}\t{$src, $dst|$dst, $src}",
1169 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1170 (implicit EFLAGS)]>;
1171 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1172 "xor{q}\t{$src, $dst|$dst, $src}",
1173 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1174 (implicit EFLAGS)]>;
1175 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1176 "xor{q}\t{$src, $dst|$dst, $src}",
1177 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1178 (implicit EFLAGS)]>;
1180 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1181 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1183 } // Defs = [EFLAGS]
1185 //===----------------------------------------------------------------------===//
1186 // Comparison Instructions...
1189 // Integer comparison
1190 let Defs = [EFLAGS] in {
1191 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i32imm:$src),
1192 "test{q}\t{$src, %rax|%rax, $src}", []>;
1193 let isCommutable = 1 in
1194 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1195 "test{q}\t{$src2, $src1|$src1, $src2}",
1196 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1197 (implicit EFLAGS)]>;
1198 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1199 "test{q}\t{$src2, $src1|$src1, $src2}",
1200 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1201 (implicit EFLAGS)]>;
1202 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1203 (ins GR64:$src1, i64i32imm:$src2),
1204 "test{q}\t{$src2, $src1|$src1, $src2}",
1205 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1206 (implicit EFLAGS)]>;
1207 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1208 (ins i64mem:$src1, i64i32imm:$src2),
1209 "test{q}\t{$src2, $src1|$src1, $src2}",
1210 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1211 (implicit EFLAGS)]>;
1214 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1215 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1216 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1217 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1218 [(X86cmp GR64:$src1, GR64:$src2),
1219 (implicit EFLAGS)]>;
1220 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1221 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1222 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1223 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1224 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1225 (implicit EFLAGS)]>;
1226 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1227 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1228 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1229 (implicit EFLAGS)]>;
1230 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1231 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1232 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1233 (implicit EFLAGS)]>;
1234 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1235 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1236 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1237 (implicit EFLAGS)]>;
1238 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1239 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1240 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1241 (implicit EFLAGS)]>;
1242 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1243 (ins i64mem:$src1, i64i32imm:$src2),
1244 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1245 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1246 (implicit EFLAGS)]>;
1247 } // Defs = [EFLAGS]
1250 // TODO: BTC, BTR, and BTS
1251 let Defs = [EFLAGS] in {
1252 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1253 "bt{q}\t{$src2, $src1|$src1, $src2}",
1254 [(X86bt GR64:$src1, GR64:$src2),
1255 (implicit EFLAGS)]>, TB;
1257 // Unlike with the register+register form, the memory+register form of the
1258 // bt instruction does not ignore the high bits of the index. From ISel's
1259 // perspective, this is pretty bizarre. Disable these instructions for now.
1260 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1261 "bt{q}\t{$src2, $src1|$src1, $src2}",
1262 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1263 // (implicit EFLAGS)]
1267 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1268 "bt{q}\t{$src2, $src1|$src1, $src2}",
1269 [(X86bt GR64:$src1, i64immSExt8:$src2),
1270 (implicit EFLAGS)]>, TB;
1271 // Note that these instructions don't need FastBTMem because that
1272 // only applies when the other operand is in a register. When it's
1273 // an immediate, bt is still fast.
1274 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1275 "bt{q}\t{$src2, $src1|$src1, $src2}",
1276 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1277 (implicit EFLAGS)]>, TB;
1279 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1280 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1281 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1282 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1283 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1284 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1285 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1286 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1288 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1289 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1290 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1291 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1292 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1293 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1294 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1295 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1297 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1298 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1299 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1300 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1301 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1302 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1303 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1304 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1305 } // Defs = [EFLAGS]
1307 // Conditional moves
1308 let Uses = [EFLAGS], isTwoAddress = 1 in {
1309 let isCommutable = 1 in {
1310 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1311 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1312 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1314 X86_COND_B, EFLAGS))]>, TB;
1315 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1316 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1317 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1318 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1319 X86_COND_AE, EFLAGS))]>, TB;
1320 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1321 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1322 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1324 X86_COND_E, EFLAGS))]>, TB;
1325 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1326 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1327 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1329 X86_COND_NE, EFLAGS))]>, TB;
1330 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1331 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1332 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1334 X86_COND_BE, EFLAGS))]>, TB;
1335 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1336 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1337 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1338 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1339 X86_COND_A, EFLAGS))]>, TB;
1340 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1341 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1342 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1344 X86_COND_L, EFLAGS))]>, TB;
1345 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1346 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1347 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1348 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1349 X86_COND_GE, EFLAGS))]>, TB;
1350 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1351 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1352 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1354 X86_COND_LE, EFLAGS))]>, TB;
1355 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1356 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1357 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1358 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1359 X86_COND_G, EFLAGS))]>, TB;
1360 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1361 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1362 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1363 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1364 X86_COND_S, EFLAGS))]>, TB;
1365 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1366 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1367 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1368 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1369 X86_COND_NS, EFLAGS))]>, TB;
1370 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1371 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1372 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1374 X86_COND_P, EFLAGS))]>, TB;
1375 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1376 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1377 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1378 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1379 X86_COND_NP, EFLAGS))]>, TB;
1380 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1381 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1382 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1384 X86_COND_O, EFLAGS))]>, TB;
1385 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1386 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1387 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1388 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1389 X86_COND_NO, EFLAGS))]>, TB;
1390 } // isCommutable = 1
1392 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1393 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1394 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1396 X86_COND_B, EFLAGS))]>, TB;
1397 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1398 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1399 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1401 X86_COND_AE, EFLAGS))]>, TB;
1402 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1403 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1404 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1406 X86_COND_E, EFLAGS))]>, TB;
1407 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1408 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1409 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1410 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1411 X86_COND_NE, EFLAGS))]>, TB;
1412 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1413 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1414 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1416 X86_COND_BE, EFLAGS))]>, TB;
1417 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1418 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1419 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1421 X86_COND_A, EFLAGS))]>, TB;
1422 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1423 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1424 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1426 X86_COND_L, EFLAGS))]>, TB;
1427 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1428 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1429 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1430 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1431 X86_COND_GE, EFLAGS))]>, TB;
1432 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1433 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1434 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1436 X86_COND_LE, EFLAGS))]>, TB;
1437 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1438 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1439 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1440 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1441 X86_COND_G, EFLAGS))]>, TB;
1442 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1443 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1444 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1446 X86_COND_S, EFLAGS))]>, TB;
1447 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1448 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1449 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1451 X86_COND_NS, EFLAGS))]>, TB;
1452 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1453 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1454 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1455 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1456 X86_COND_P, EFLAGS))]>, TB;
1457 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1458 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1459 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1461 X86_COND_NP, EFLAGS))]>, TB;
1462 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1463 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1464 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1465 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1466 X86_COND_O, EFLAGS))]>, TB;
1467 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1468 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1469 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1470 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1471 X86_COND_NO, EFLAGS))]>, TB;
1474 // Use sbb to materialize carry flag into a GPR.
1475 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1476 // However, Pat<> can't replicate the destination reg into the inputs of the
1478 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1480 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1481 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1482 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1484 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1487 //===----------------------------------------------------------------------===//
1488 // Conversion Instructions...
1491 // f64 -> signed i64
1492 def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1493 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1494 def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1495 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1496 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1497 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1499 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1500 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1502 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1503 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1504 (load addr:$src)))]>;
1505 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1506 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1507 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1508 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1509 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1510 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1511 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1512 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1514 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1515 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1517 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1519 (int_x86_sse2_cvttsd2si64
1520 (load addr:$src)))]>;
1522 // Signed i64 -> f64
1523 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1524 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1525 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1526 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1527 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1528 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1530 let isTwoAddress = 1 in {
1531 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1532 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1533 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1535 (int_x86_sse2_cvtsi642sd VR128:$src1,
1537 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1538 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1539 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1541 (int_x86_sse2_cvtsi642sd VR128:$src1,
1542 (loadi64 addr:$src2)))]>;
1545 // Signed i64 -> f32
1546 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1547 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1548 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1549 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1550 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1551 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1553 let isTwoAddress = 1 in {
1554 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1555 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1556 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1558 (int_x86_sse_cvtsi642ss VR128:$src1,
1560 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1562 (ins VR128:$src1, i64mem:$src2),
1563 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1565 (int_x86_sse_cvtsi642ss VR128:$src1,
1566 (loadi64 addr:$src2)))]>;
1569 // f32 -> signed i64
1570 def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1571 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1572 def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1573 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1574 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1575 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1577 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1578 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1579 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1580 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1581 (load addr:$src)))]>;
1582 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1583 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1584 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1585 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1586 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1587 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1588 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1589 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1591 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1592 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1594 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1596 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1598 // Descriptor-table support instructions
1600 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1602 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1603 "sldt{q}\t$dst", []>, TB;
1604 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1605 "sldt{q}\t$dst", []>, TB;
1607 //===----------------------------------------------------------------------===//
1608 // Alias Instructions
1609 //===----------------------------------------------------------------------===//
1611 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1612 // smaller encoding, but doing so at isel time interferes with rematerialization
1613 // in the current register allocator. For now, this is rewritten when the
1614 // instruction is lowered to an MCInst.
1615 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1616 // when we have a better way to specify isel priority.
1617 let Defs = [EFLAGS],
1618 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1619 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1620 [(set GR64:$dst, 0)]>;
1622 // Materialize i64 constant where top 32-bits are zero. This could theoretically
1623 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1624 // that would make it more difficult to rematerialize.
1625 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1626 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1627 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1629 //===----------------------------------------------------------------------===//
1630 // Thread Local Storage Instructions
1631 //===----------------------------------------------------------------------===//
1633 // All calls clobber the non-callee saved registers. RSP is marked as
1634 // a use to prevent stack-pointer assignments that appear immediately
1635 // before calls from potentially appearing dead.
1636 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1637 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1638 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1639 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1640 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1642 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1644 "leaq\t$sym(%rip), %rdi; "
1647 "call\t__tls_get_addr@PLT",
1648 [(X86tlsaddr tls64addr:$sym)]>,
1649 Requires<[In64BitMode]>;
1651 let AddedComplexity = 5, isCodeGenOnly = 1 in
1652 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1653 "movq\t%gs:$src, $dst",
1654 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1656 let AddedComplexity = 5, isCodeGenOnly = 1 in
1657 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1658 "movq\t%fs:$src, $dst",
1659 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1661 //===----------------------------------------------------------------------===//
1662 // Atomic Instructions
1663 //===----------------------------------------------------------------------===//
1665 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1666 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1668 "cmpxchgq\t$swap,$ptr",
1669 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1672 let Constraints = "$val = $dst" in {
1673 let Defs = [EFLAGS] in
1674 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1677 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1680 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1681 (ins GR64:$val,i64mem:$ptr),
1682 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1683 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1685 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1686 "xchg{q}\t{$val, $src|$src, $val}", []>;
1689 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1690 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1691 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1692 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1694 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1695 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1696 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1697 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1699 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1700 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1701 "cmpxchg16b\t$dst", []>, TB;
1703 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1704 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1706 // Optimized codegen when the non-memory output is not used.
1707 let Defs = [EFLAGS] in {
1708 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1709 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1711 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1712 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1713 (ins i64mem:$dst, i64i8imm :$src2),
1715 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1716 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1717 (ins i64mem:$dst, i64i32imm :$src2),
1719 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1720 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1722 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1723 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1724 (ins i64mem:$dst, i64i8imm :$src2),
1726 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1727 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1728 (ins i64mem:$dst, i64i32imm:$src2),
1730 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1731 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1733 "inc{q}\t$dst", []>, LOCK;
1734 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1736 "dec{q}\t$dst", []>, LOCK;
1738 // Atomic exchange, and, or, xor
1739 let Constraints = "$val = $dst", Defs = [EFLAGS],
1740 usesCustomInserter = 1 in {
1741 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1742 "#ATOMAND64 PSEUDO!",
1743 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1744 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1745 "#ATOMOR64 PSEUDO!",
1746 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1747 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1748 "#ATOMXOR64 PSEUDO!",
1749 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1750 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1751 "#ATOMNAND64 PSEUDO!",
1752 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1753 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1754 "#ATOMMIN64 PSEUDO!",
1755 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1756 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1757 "#ATOMMAX64 PSEUDO!",
1758 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1759 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1760 "#ATOMUMIN64 PSEUDO!",
1761 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1762 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1763 "#ATOMUMAX64 PSEUDO!",
1764 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1767 // Segmentation support instructions
1769 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1770 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1771 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1772 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1773 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1775 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1776 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1777 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1778 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1780 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1782 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1783 "push{q}\t%fs", []>, TB;
1784 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1785 "push{q}\t%gs", []>, TB;
1787 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1788 "pop{q}\t%fs", []>, TB;
1789 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1790 "pop{q}\t%gs", []>, TB;
1792 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1793 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1794 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1795 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1796 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1797 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1799 // Specialized register support
1801 // no m form encodable; use SMSW16m
1802 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1803 "smsw{q}\t$dst", []>, TB;
1805 // String manipulation instructions
1807 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1809 //===----------------------------------------------------------------------===//
1810 // Non-Instruction Patterns
1811 //===----------------------------------------------------------------------===//
1813 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1814 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1815 // 'movabs' predicate should handle this sort of thing.
1816 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1817 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1818 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1819 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1820 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1821 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1822 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1823 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1824 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1825 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1827 // In static codegen with small code model, we can get the address of a label
1828 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1829 // the MOV64ri64i32 should accept these.
1830 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1831 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1832 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1833 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1834 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1835 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1836 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1837 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1838 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1839 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1841 // In kernel code model, we can get the address of a label
1842 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1843 // the MOV64ri32 should accept these.
1844 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1845 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1846 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1847 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1848 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1849 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1850 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1851 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1852 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1853 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1855 // If we have small model and -static mode, it is safe to store global addresses
1856 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1857 // for MOV64mi32 should handle this sort of thing.
1858 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1859 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1860 Requires<[NearData, IsStatic]>;
1861 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1862 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1863 Requires<[NearData, IsStatic]>;
1864 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1865 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1866 Requires<[NearData, IsStatic]>;
1867 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1868 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1869 Requires<[NearData, IsStatic]>;
1870 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1871 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1872 Requires<[NearData, IsStatic]>;
1875 // Direct PC relative function call for small code model. 32-bit displacement
1876 // sign extended to 64-bit.
1877 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1878 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1879 def : Pat<(X86call (i64 texternalsym:$dst)),
1880 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1882 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1883 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1884 def : Pat<(X86call (i64 texternalsym:$dst)),
1885 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1888 def : Pat<(X86tcret GR64:$dst, imm:$off),
1889 (TCRETURNri64 GR64:$dst, imm:$off)>;
1891 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1892 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>;
1894 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1895 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1899 // TEST R,R is smaller than CMP R,0
1900 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1901 (TEST64rr GR64:$src1, GR64:$src1)>;
1903 // Conditional moves with folded loads with operands swapped and conditions
1905 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1906 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1907 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1908 (CMOVB64rm GR64:$src2, addr:$src1)>;
1909 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1910 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1911 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1912 (CMOVE64rm GR64:$src2, addr:$src1)>;
1913 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1914 (CMOVA64rm GR64:$src2, addr:$src1)>;
1915 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1916 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1917 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1918 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1919 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1920 (CMOVL64rm GR64:$src2, addr:$src1)>;
1921 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1922 (CMOVG64rm GR64:$src2, addr:$src1)>;
1923 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1924 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1925 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1926 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1927 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1928 (CMOVP64rm GR64:$src2, addr:$src1)>;
1929 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1930 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1931 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1932 (CMOVS64rm GR64:$src2, addr:$src1)>;
1933 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1934 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1935 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1936 (CMOVO64rm GR64:$src2, addr:$src1)>;
1938 // zextload bool -> zextload byte
1939 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1942 // When extloading from 16-bit and smaller memory locations into 64-bit
1943 // registers, use zero-extending loads so that the entire 64-bit register is
1944 // defined, avoiding partial-register updates.
1945 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1946 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1947 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1948 // For other extloads, use subregs, since the high contents of the register are
1949 // defined after an extload.
1950 def : Pat<(extloadi64i32 addr:$src),
1951 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1954 // anyext. Define these to do an explicit zero-extend to
1955 // avoid partial-register updates.
1956 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1957 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1958 def : Pat<(i64 (anyext GR32:$src)),
1959 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1961 //===----------------------------------------------------------------------===//
1963 //===----------------------------------------------------------------------===//
1965 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1966 // +128 doesn't, so in this special case use a sub instead of an add.
1967 def : Pat<(add GR64:$src1, 128),
1968 (SUB64ri8 GR64:$src1, -128)>;
1969 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1970 (SUB64mi8 addr:$dst, -128)>;
1972 // The same trick applies for 32-bit immediate fields in 64-bit
1974 def : Pat<(add GR64:$src1, 0x0000000080000000),
1975 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1976 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1977 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1979 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
1980 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
1981 // materialize that immediate in a register first.
1982 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1986 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit),
1987 (i32 (GetLo32XForm imm:$imm))),
1990 // r & (2^32-1) ==> movz
1991 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1992 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1993 // r & (2^16-1) ==> movz
1994 def : Pat<(and GR64:$src, 0xffff),
1995 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1996 // r & (2^8-1) ==> movz
1997 def : Pat<(and GR64:$src, 0xff),
1998 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1999 // r & (2^8-1) ==> movz
2000 def : Pat<(and GR32:$src1, 0xff),
2001 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
2002 Requires<[In64BitMode]>;
2003 // r & (2^8-1) ==> movz
2004 def : Pat<(and GR16:$src1, 0xff),
2005 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
2006 Requires<[In64BitMode]>;
2008 // sext_inreg patterns
2009 def : Pat<(sext_inreg GR64:$src, i32),
2010 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2011 def : Pat<(sext_inreg GR64:$src, i16),
2012 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2013 def : Pat<(sext_inreg GR64:$src, i8),
2014 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
2015 def : Pat<(sext_inreg GR32:$src, i8),
2016 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
2017 Requires<[In64BitMode]>;
2018 def : Pat<(sext_inreg GR16:$src, i8),
2019 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
2020 Requires<[In64BitMode]>;
2023 def : Pat<(i32 (trunc GR64:$src)),
2024 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
2025 def : Pat<(i16 (trunc GR64:$src)),
2026 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
2027 def : Pat<(i8 (trunc GR64:$src)),
2028 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
2029 def : Pat<(i8 (trunc GR32:$src)),
2030 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
2031 Requires<[In64BitMode]>;
2032 def : Pat<(i8 (trunc GR16:$src)),
2033 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
2034 Requires<[In64BitMode]>;
2036 // h-register tricks.
2037 // For now, be conservative on x86-64 and use an h-register extract only if the
2038 // value is immediately zero-extended or stored, which are somewhat common
2039 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
2040 // from being allocated in the same instruction as the h register, as there's
2041 // currently no way to describe this requirement to the register allocator.
2043 // h-register extract and zero-extend.
2044 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2048 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2049 x86_subreg_8bit_hi)),
2051 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2053 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2054 x86_subreg_8bit_hi))>,
2055 Requires<[In64BitMode]>;
2056 def : Pat<(srl GR16:$src, (i8 8)),
2059 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2060 x86_subreg_8bit_hi)),
2062 Requires<[In64BitMode]>;
2063 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2065 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2066 x86_subreg_8bit_hi))>,
2067 Requires<[In64BitMode]>;
2068 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2070 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2071 x86_subreg_8bit_hi))>,
2072 Requires<[In64BitMode]>;
2073 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2077 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2078 x86_subreg_8bit_hi)),
2080 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2084 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2085 x86_subreg_8bit_hi)),
2088 // h-register extract and store.
2089 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2092 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2093 x86_subreg_8bit_hi))>;
2094 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2097 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2098 x86_subreg_8bit_hi))>,
2099 Requires<[In64BitMode]>;
2100 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2103 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2104 x86_subreg_8bit_hi))>,
2105 Requires<[In64BitMode]>;
2107 // (shl x, 1) ==> (add x, x)
2108 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2110 // (shl x (and y, 63)) ==> (shl x, y)
2111 def : Pat<(shl GR64:$src1, (and CL, 63)),
2112 (SHL64rCL GR64:$src1)>;
2113 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2114 (SHL64mCL addr:$dst)>;
2116 def : Pat<(srl GR64:$src1, (and CL, 63)),
2117 (SHR64rCL GR64:$src1)>;
2118 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2119 (SHR64mCL addr:$dst)>;
2121 def : Pat<(sra GR64:$src1, (and CL, 63)),
2122 (SAR64rCL GR64:$src1)>;
2123 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2124 (SAR64mCL addr:$dst)>;
2126 // Double shift patterns
2127 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2128 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2130 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
2131 GR64:$src2, (i8 imm)), addr:$dst),
2132 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2134 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2135 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2137 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
2138 GR64:$src2, (i8 imm)), addr:$dst),
2139 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2141 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2142 let AddedComplexity = 5 in { // Try this before the selecting to OR
2143 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt8:$src2),
2145 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2146 def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt32:$src2),
2148 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2149 def : Pat<(parallel (or_is_add GR64:$src1, GR64:$src2),
2151 (ADD64rr GR64:$src1, GR64:$src2)>;
2152 } // AddedComplexity
2154 // X86 specific add which produces a flag.
2155 def : Pat<(addc GR64:$src1, GR64:$src2),
2156 (ADD64rr GR64:$src1, GR64:$src2)>;
2157 def : Pat<(addc GR64:$src1, (load addr:$src2)),
2158 (ADD64rm GR64:$src1, addr:$src2)>;
2159 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2160 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2161 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2162 (ADD64ri32 GR64:$src1, imm:$src2)>;
2164 def : Pat<(subc GR64:$src1, GR64:$src2),
2165 (SUB64rr GR64:$src1, GR64:$src2)>;
2166 def : Pat<(subc GR64:$src1, (load addr:$src2)),
2167 (SUB64rm GR64:$src1, addr:$src2)>;
2168 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2169 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2170 def : Pat<(subc GR64:$src1, imm:$src2),
2171 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2173 //===----------------------------------------------------------------------===//
2174 // EFLAGS-defining Patterns
2175 //===----------------------------------------------------------------------===//
2177 // Register-Register Addition with EFLAGS result
2178 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
2180 (ADD64rr GR64:$src1, GR64:$src2)>;
2182 // Register-Integer Addition with EFLAGS result
2183 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
2185 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2186 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
2188 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2190 // Register-Memory Addition with EFLAGS result
2191 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
2193 (ADD64rm GR64:$src1, addr:$src2)>;
2195 // Memory-Register Addition with EFLAGS result
2196 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
2199 (ADD64mr addr:$dst, GR64:$src2)>;
2200 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2203 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
2204 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
2205 i64immSExt32:$src2),
2208 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
2210 // Register-Register Subtraction with EFLAGS result
2211 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
2213 (SUB64rr GR64:$src1, GR64:$src2)>;
2215 // Register-Memory Subtraction with EFLAGS result
2216 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
2218 (SUB64rm GR64:$src1, addr:$src2)>;
2220 // Register-Integer Subtraction with EFLAGS result
2221 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
2223 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2224 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
2226 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2228 // Memory-Register Subtraction with EFLAGS result
2229 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
2232 (SUB64mr addr:$dst, GR64:$src2)>;
2234 // Memory-Integer Subtraction with EFLAGS result
2235 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2239 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2240 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2241 i64immSExt32:$src2),
2244 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
2246 // Register-Register Signed Integer Multiplication with EFLAGS result
2247 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
2249 (IMUL64rr GR64:$src1, GR64:$src2)>;
2251 // Register-Memory Signed Integer Multiplication with EFLAGS result
2252 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
2254 (IMUL64rm GR64:$src1, addr:$src2)>;
2256 // Register-Integer Signed Integer Multiplication with EFLAGS result
2257 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2259 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2260 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2262 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2264 // Memory-Integer Signed Integer Multiplication with EFLAGS result
2265 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2267 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2268 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2270 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2272 // INC and DEC with EFLAGS result. Note that these do not set CF.
2273 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2274 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2275 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2277 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2278 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2279 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2280 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2282 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2284 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2285 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2286 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2288 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2289 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2290 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2291 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2293 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2295 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2296 (INC64r GR64:$src)>;
2297 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2299 (INC64m addr:$dst)>;
2300 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2301 (DEC64r GR64:$src)>;
2302 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2304 (DEC64m addr:$dst)>;
2306 // Register-Register Logical Or with EFLAGS result
2307 def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2309 (OR64rr GR64:$src1, GR64:$src2)>;
2311 // Register-Integer Logical Or with EFLAGS result
2312 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2314 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2315 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2317 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2319 // Register-Memory Logical Or with EFLAGS result
2320 def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2322 (OR64rm GR64:$src1, addr:$src2)>;
2324 // Memory-Register Logical Or with EFLAGS result
2325 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2328 (OR64mr addr:$dst, GR64:$src2)>;
2329 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2332 (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2333 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2336 (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2338 // Register-Register Logical XOr with EFLAGS result
2339 def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2341 (XOR64rr GR64:$src1, GR64:$src2)>;
2343 // Register-Integer Logical XOr with EFLAGS result
2344 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2346 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2347 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2349 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2351 // Register-Memory Logical XOr with EFLAGS result
2352 def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2354 (XOR64rm GR64:$src1, addr:$src2)>;
2356 // Memory-Register Logical XOr with EFLAGS result
2357 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2360 (XOR64mr addr:$dst, GR64:$src2)>;
2361 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2364 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2365 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
2366 i64immSExt32:$src2),
2369 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2371 // Register-Register Logical And with EFLAGS result
2372 def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2374 (AND64rr GR64:$src1, GR64:$src2)>;
2376 // Register-Integer Logical And with EFLAGS result
2377 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2379 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2380 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2382 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2384 // Register-Memory Logical And with EFLAGS result
2385 def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2387 (AND64rm GR64:$src1, addr:$src2)>;
2389 // Memory-Register Logical And with EFLAGS result
2390 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2393 (AND64mr addr:$dst, GR64:$src2)>;
2394 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2397 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2398 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
2399 i64immSExt32:$src2),
2402 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2404 //===----------------------------------------------------------------------===//
2405 // X86-64 SSE Instructions
2406 //===----------------------------------------------------------------------===//
2408 // Move instructions...
2410 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2411 "mov{d|q}\t{$src, $dst|$dst, $src}",
2413 (v2i64 (scalar_to_vector GR64:$src)))]>;
2414 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2415 "mov{d|q}\t{$src, $dst|$dst, $src}",
2416 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2419 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2420 "mov{d|q}\t{$src, $dst|$dst, $src}",
2421 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2422 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2423 "movq\t{$src, $dst|$dst, $src}",
2424 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2426 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2427 "mov{d|q}\t{$src, $dst|$dst, $src}",
2428 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2429 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2430 "movq\t{$src, $dst|$dst, $src}",
2431 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2433 //===----------------------------------------------------------------------===//
2434 // X86-64 SSE4.1 Instructions
2435 //===----------------------------------------------------------------------===//
2437 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2438 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2439 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2440 (ins VR128:$src1, i32i8imm:$src2),
2441 !strconcat(OpcodeStr,
2442 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2444 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2445 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2446 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2447 !strconcat(OpcodeStr,
2448 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2449 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2450 addr:$dst)]>, OpSize, REX_W;
2453 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2455 let isTwoAddress = 1 in {
2456 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2457 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2458 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2459 !strconcat(OpcodeStr,
2460 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2462 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2464 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2465 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2466 !strconcat(OpcodeStr,
2467 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2469 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2470 imm:$src3)))]>, OpSize, REX_W;
2474 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2476 // -disable-16bit support.
2477 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
2478 (MOV16mi addr:$dst, imm:$src)>;
2479 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2480 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2481 def : Pat<(i64 (sextloadi16 addr:$dst)),
2482 (MOVSX64rm16 addr:$dst)>;
2483 def : Pat<(i64 (zextloadi16 addr:$dst)),
2484 (MOVZX64rm16 addr:$dst)>;
2485 def : Pat<(i64 (extloadi16 addr:$dst)),
2486 (MOVZX64rm16 addr:$dst)>;