1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
756 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
757 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
758 VEX_W, EVEX_CD8<64, CD8VF>;
760 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
761 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
763 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
764 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
765 VEX_W, EVEX_CD8<64, CD8VF>;
767 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
768 (COPY_TO_REGCLASS (VPCMPGTDZrr
769 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
772 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
773 (COPY_TO_REGCLASS (VPCMPEQDZrr
774 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
775 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
777 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
778 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
779 SDNode OpNode, ValueType vt, Operand CC, string asm,
781 def rri : AVX512AIi8<opc, MRMSrcReg,
782 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
784 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
785 def rmi : AVX512AIi8<opc, MRMSrcMem,
786 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
787 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
788 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
789 // Accept explicit immediate argument form instead of comparison code.
790 let isAsmParserOnly = 1, hasSideEffects = 0 in {
791 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
792 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
793 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
794 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
795 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
796 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
800 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
801 X86cmpm, v16i32, AVXCC,
802 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
803 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
804 EVEX_V512, EVEX_CD8<32, CD8VF>;
805 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
806 X86cmpmu, v16i32, AVXCC,
807 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
808 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
809 EVEX_V512, EVEX_CD8<32, CD8VF>;
811 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
812 X86cmpm, v8i64, AVXCC,
813 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
815 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
816 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
817 X86cmpmu, v8i64, AVXCC,
818 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
819 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
820 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
822 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
823 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
824 X86MemOperand x86memop, ValueType vt,
825 string suffix, Domain d> {
826 def rri : AVX512PIi8<0xC2, MRMSrcReg,
827 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
828 !strconcat("vcmp${cc}", suffix,
829 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
830 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
831 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
832 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
833 !strconcat("vcmp${cc}", suffix,
834 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
836 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
837 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
838 !strconcat("vcmp${cc}", suffix,
839 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
841 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
843 // Accept explicit immediate argument form instead of comparison code.
844 let isAsmParserOnly = 1, hasSideEffects = 0 in {
845 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
846 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
849 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
850 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
851 !strconcat("vcmp", suffix,
852 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
856 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
857 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
859 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
860 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
863 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
864 (COPY_TO_REGCLASS (VCMPPSZrri
865 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
866 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
868 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
869 (COPY_TO_REGCLASS (VPCMPDZrri
870 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
873 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
874 (COPY_TO_REGCLASS (VPCMPUDZrri
875 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
876 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
879 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
880 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
882 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
883 (I8Imm imm:$cc)), GR16)>;
885 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
886 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
888 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
889 (I8Imm imm:$cc)), GR8)>;
891 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
892 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
894 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
895 (I8Imm imm:$cc)), GR16)>;
897 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
898 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
900 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
901 (I8Imm imm:$cc)), GR8)>;
903 // Mask register copy, including
904 // - copy between mask registers
905 // - load/store mask registers
906 // - copy from GPR to mask register and vice versa
908 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
909 string OpcodeStr, RegisterClass KRC,
910 ValueType vt, X86MemOperand x86memop> {
911 let hasSideEffects = 0 in {
912 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
913 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
915 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
917 [(set KRC:$dst, (vt (load addr:$src)))]>;
919 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
920 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
924 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
926 RegisterClass KRC, RegisterClass GRC> {
927 let hasSideEffects = 0 in {
928 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
929 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
930 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
931 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
935 let Predicates = [HasAVX512] in {
936 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
938 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
942 let Predicates = [HasAVX512] in {
943 // GR16 from/to 16-bit mask
944 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
945 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
946 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
947 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
949 // Store kreg in memory
950 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
951 (KMOVWmk addr:$dst, VK16:$src)>;
953 def : Pat<(store VK8:$src, addr:$dst),
954 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
956 def : Pat<(i1 (load addr:$src)),
957 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
959 def : Pat<(v8i1 (load addr:$src)),
960 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
962 def : Pat<(i1 (trunc (i32 GR32:$src))),
963 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
965 def : Pat<(i1 (trunc (i8 GR8:$src))),
967 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
969 def : Pat<(i1 (trunc (i16 GR16:$src))),
971 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
974 def : Pat<(i32 (zext VK1:$src)),
975 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
976 def : Pat<(i8 (zext VK1:$src)),
979 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
980 def : Pat<(i64 (zext VK1:$src)),
981 (AND64ri8 (SUBREG_TO_REG (i64 0),
982 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
983 def : Pat<(i16 (zext VK1:$src)),
985 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
988 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
989 let Predicates = [HasAVX512] in {
990 // GR from/to 8-bit mask without native support
991 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
993 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
995 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
997 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1000 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1001 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1002 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1003 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1007 // Mask unary operation
1009 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1010 RegisterClass KRC, SDPatternOperator OpNode> {
1011 let Predicates = [HasAVX512] in
1012 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1013 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1014 [(set KRC:$dst, (OpNode KRC:$src))]>;
1017 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1018 SDPatternOperator OpNode> {
1019 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1023 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1025 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1026 let Predicates = [HasAVX512] in
1027 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1029 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1030 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1032 defm : avx512_mask_unop_int<"knot", "KNOT">;
1034 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1035 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1036 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1038 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1039 def : Pat<(not VK8:$src),
1041 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1043 // Mask binary operation
1044 // - KAND, KANDN, KOR, KXNOR, KXOR
1045 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1046 RegisterClass KRC, SDPatternOperator OpNode> {
1047 let Predicates = [HasAVX512] in
1048 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1049 !strconcat(OpcodeStr,
1050 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1051 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1054 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1055 SDPatternOperator OpNode> {
1056 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1060 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1061 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1063 let isCommutable = 1 in {
1064 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1065 let isCommutable = 0 in
1066 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1067 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1068 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1069 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1072 def : Pat<(xor VK1:$src1, VK1:$src2),
1073 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1074 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1076 def : Pat<(or VK1:$src1, VK1:$src2),
1077 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1078 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1080 def : Pat<(and VK1:$src1, VK1:$src2),
1081 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1082 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1084 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1085 let Predicates = [HasAVX512] in
1086 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1087 (i16 GR16:$src1), (i16 GR16:$src2)),
1088 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1089 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1090 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1093 defm : avx512_mask_binop_int<"kand", "KAND">;
1094 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1095 defm : avx512_mask_binop_int<"kor", "KOR">;
1096 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1097 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1099 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1100 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1101 let Predicates = [HasAVX512] in
1102 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1104 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1105 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1108 defm : avx512_binop_pat<and, KANDWrr>;
1109 defm : avx512_binop_pat<andn, KANDNWrr>;
1110 defm : avx512_binop_pat<or, KORWrr>;
1111 defm : avx512_binop_pat<xnor, KXNORWrr>;
1112 defm : avx512_binop_pat<xor, KXORWrr>;
1115 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1116 RegisterClass KRC> {
1117 let Predicates = [HasAVX512] in
1118 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1119 !strconcat(OpcodeStr,
1120 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1123 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1124 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1128 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1129 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1130 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1131 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1134 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1135 let Predicates = [HasAVX512] in
1136 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1137 (i16 GR16:$src1), (i16 GR16:$src2)),
1138 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1139 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1140 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1142 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1145 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1147 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1148 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1149 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1150 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1153 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1154 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1158 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1160 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1161 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1162 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1165 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1167 let Predicates = [HasAVX512] in
1168 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1169 !strconcat(OpcodeStr,
1170 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1171 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1174 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1176 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1180 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1181 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1183 // Mask setting all 0s or 1s
1184 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1185 let Predicates = [HasAVX512] in
1186 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1187 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1188 [(set KRC:$dst, (VT Val))]>;
1191 multiclass avx512_mask_setop_w<PatFrag Val> {
1192 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1193 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1196 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1197 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1199 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1200 let Predicates = [HasAVX512] in {
1201 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1202 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1203 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1204 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1205 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1207 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1208 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1210 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1211 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1213 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1214 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1216 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1217 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1219 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1220 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1221 //===----------------------------------------------------------------------===//
1222 // AVX-512 - Aligned and unaligned load and store
1225 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1226 X86MemOperand x86memop, PatFrag ld_frag,
1227 string asm, Domain d,
1228 ValueType vt, bit IsReMaterializable = 1> {
1229 let hasSideEffects = 0 in {
1230 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1231 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1233 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1235 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1236 [], d>, EVEX, EVEX_KZ;
1238 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1239 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1240 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1241 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1242 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1243 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1244 (ins RC:$src1, KRC:$mask, RC:$src2),
1246 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1249 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1250 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1252 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1253 [], d>, EVEX, EVEX_K;
1256 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1257 (ins KRC:$mask, x86memop:$src2),
1259 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1260 [], d>, EVEX, EVEX_KZ;
1263 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1264 X86MemOperand x86memop, PatFrag store_frag,
1265 string asm, Domain d, ValueType vt> {
1266 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1267 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1268 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1270 let Constraints = "$src1 = $dst" in
1271 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1272 (ins RC:$src1, KRC:$mask, RC:$src2),
1274 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1276 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1277 (ins KRC:$mask, RC:$src),
1279 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1280 [], d>, EVEX, EVEX_KZ;
1282 let mayStore = 1 in {
1283 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1284 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1285 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1286 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1287 (ins x86memop:$dst, KRC:$mask, RC:$src),
1289 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1290 [], d>, EVEX, EVEX_K;
1291 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1292 (ins x86memop:$dst, KRC:$mask, RC:$src),
1294 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1295 [], d>, EVEX, EVEX_KZ;
1299 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1300 "vmovaps", SSEPackedSingle, v16f32>,
1301 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1302 "vmovaps", SSEPackedSingle, v16f32>,
1303 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1304 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1305 "vmovapd", SSEPackedDouble, v8f64>,
1306 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1307 "vmovapd", SSEPackedDouble, v8f64>,
1308 PD, EVEX_V512, VEX_W,
1309 EVEX_CD8<64, CD8VF>;
1310 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1311 "vmovups", SSEPackedSingle, v16f32>,
1312 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1313 "vmovups", SSEPackedSingle, v16f32>,
1314 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1315 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1316 "vmovupd", SSEPackedDouble, v8f64, 0>,
1317 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1318 "vmovupd", SSEPackedDouble, v8f64>,
1319 PD, EVEX_V512, VEX_W,
1320 EVEX_CD8<64, CD8VF>;
1321 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1322 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1323 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1325 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1326 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1327 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1329 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1331 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1333 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1335 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1338 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1339 "vmovdqa32", SSEPackedInt, v16i32>,
1340 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1341 "vmovdqa32", SSEPackedInt, v16i32>,
1342 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1343 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1344 "vmovdqa64", SSEPackedInt, v8i64>,
1345 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1346 "vmovdqa64", SSEPackedInt, v8i64>,
1347 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1348 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1349 "vmovdqu32", SSEPackedInt, v16i32>,
1350 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1351 "vmovdqu32", SSEPackedInt, v16i32>,
1352 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1353 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1354 "vmovdqu64", SSEPackedInt, v8i64>,
1355 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1356 "vmovdqu64", SSEPackedInt, v8i64>,
1357 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1359 let AddedComplexity = 20 in {
1360 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1361 (bc_v8i64 (v16i32 immAllZerosV)))),
1362 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1364 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1365 (v8i64 VR512:$src))),
1366 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1369 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1370 (v16i32 immAllZerosV))),
1371 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1373 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1374 (v16i32 VR512:$src))),
1375 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1377 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1378 (v16f32 VR512:$src2))),
1379 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1380 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1381 (v8f64 VR512:$src2))),
1382 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1383 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1384 (v16i32 VR512:$src2))),
1385 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1386 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1387 (v8i64 VR512:$src2))),
1388 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1390 // Move Int Doubleword to Packed Double Int
1392 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1393 "vmovd\t{$src, $dst|$dst, $src}",
1395 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1397 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1398 "vmovd\t{$src, $dst|$dst, $src}",
1400 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1401 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1402 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1403 "vmovq\t{$src, $dst|$dst, $src}",
1405 (v2i64 (scalar_to_vector GR64:$src)))],
1406 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1407 let isCodeGenOnly = 1 in {
1408 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1409 "vmovq\t{$src, $dst|$dst, $src}",
1410 [(set FR64:$dst, (bitconvert GR64:$src))],
1411 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1412 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1413 "vmovq\t{$src, $dst|$dst, $src}",
1414 [(set GR64:$dst, (bitconvert FR64:$src))],
1415 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1417 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1418 "vmovq\t{$src, $dst|$dst, $src}",
1419 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1420 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1421 EVEX_CD8<64, CD8VT1>;
1423 // Move Int Doubleword to Single Scalar
1425 let isCodeGenOnly = 1 in {
1426 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1427 "vmovd\t{$src, $dst|$dst, $src}",
1428 [(set FR32X:$dst, (bitconvert GR32:$src))],
1429 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1431 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1432 "vmovd\t{$src, $dst|$dst, $src}",
1433 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1434 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1437 // Move doubleword from xmm register to r/m32
1439 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1440 "vmovd\t{$src, $dst|$dst, $src}",
1441 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1442 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1444 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1445 (ins i32mem:$dst, VR128X:$src),
1446 "vmovd\t{$src, $dst|$dst, $src}",
1447 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1448 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1449 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1451 // Move quadword from xmm1 register to r/m64
1453 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1454 "vmovq\t{$src, $dst|$dst, $src}",
1455 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1457 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1458 Requires<[HasAVX512, In64BitMode]>;
1460 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1461 (ins i64mem:$dst, VR128X:$src),
1462 "vmovq\t{$src, $dst|$dst, $src}",
1463 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1464 addr:$dst)], IIC_SSE_MOVDQ>,
1465 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1466 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1468 // Move Scalar Single to Double Int
1470 let isCodeGenOnly = 1 in {
1471 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1473 "vmovd\t{$src, $dst|$dst, $src}",
1474 [(set GR32:$dst, (bitconvert FR32X:$src))],
1475 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1476 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1477 (ins i32mem:$dst, FR32X:$src),
1478 "vmovd\t{$src, $dst|$dst, $src}",
1479 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1480 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1483 // Move Quadword Int to Packed Quadword Int
1485 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1487 "vmovq\t{$src, $dst|$dst, $src}",
1489 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1490 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1492 //===----------------------------------------------------------------------===//
1493 // AVX-512 MOVSS, MOVSD
1494 //===----------------------------------------------------------------------===//
1496 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1497 SDNode OpNode, ValueType vt,
1498 X86MemOperand x86memop, PatFrag mem_pat> {
1499 let hasSideEffects = 0 in {
1500 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1501 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1502 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1503 (scalar_to_vector RC:$src2))))],
1504 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1505 let Constraints = "$src1 = $dst" in
1506 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1507 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1509 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1510 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1511 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1512 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1513 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1515 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1516 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1517 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1519 } //hasSideEffects = 0
1522 let ExeDomain = SSEPackedSingle in
1523 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1524 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1526 let ExeDomain = SSEPackedDouble in
1527 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1528 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1530 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1531 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1532 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1534 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1535 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1536 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1538 // For the disassembler
1539 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1540 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1541 (ins VR128X:$src1, FR32X:$src2),
1542 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1544 XS, EVEX_4V, VEX_LIG;
1545 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1546 (ins VR128X:$src1, FR64X:$src2),
1547 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1549 XD, EVEX_4V, VEX_LIG, VEX_W;
1552 let Predicates = [HasAVX512] in {
1553 let AddedComplexity = 15 in {
1554 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1555 // MOVS{S,D} to the lower bits.
1556 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1557 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1558 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1559 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1560 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1561 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1562 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1563 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1565 // Move low f32 and clear high bits.
1566 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1567 (SUBREG_TO_REG (i32 0),
1568 (VMOVSSZrr (v4f32 (V_SET0)),
1569 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1570 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1571 (SUBREG_TO_REG (i32 0),
1572 (VMOVSSZrr (v4i32 (V_SET0)),
1573 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1576 let AddedComplexity = 20 in {
1577 // MOVSSrm zeros the high parts of the register; represent this
1578 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1579 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1580 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1581 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1582 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1583 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1584 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1586 // MOVSDrm zeros the high parts of the register; represent this
1587 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1588 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1589 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1590 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1591 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1592 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1593 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1594 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1595 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1596 def : Pat<(v2f64 (X86vzload addr:$src)),
1597 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1599 // Represent the same patterns above but in the form they appear for
1601 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1602 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1603 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1604 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1605 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1606 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1607 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1608 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1609 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1611 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1612 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1613 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1614 FR32X:$src)), sub_xmm)>;
1615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1616 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1617 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1618 FR64X:$src)), sub_xmm)>;
1619 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1620 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1621 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1623 // Move low f64 and clear high bits.
1624 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1625 (SUBREG_TO_REG (i32 0),
1626 (VMOVSDZrr (v2f64 (V_SET0)),
1627 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1629 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1630 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1631 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1633 // Extract and store.
1634 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1636 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1637 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1639 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1641 // Shuffle with VMOVSS
1642 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1643 (VMOVSSZrr (v4i32 VR128X:$src1),
1644 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1645 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1646 (VMOVSSZrr (v4f32 VR128X:$src1),
1647 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1650 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1651 (SUBREG_TO_REG (i32 0),
1652 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1653 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1655 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1656 (SUBREG_TO_REG (i32 0),
1657 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1658 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1661 // Shuffle with VMOVSD
1662 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1663 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1664 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1665 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1666 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1667 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1668 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1669 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1672 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1673 (SUBREG_TO_REG (i32 0),
1674 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1675 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1677 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1678 (SUBREG_TO_REG (i32 0),
1679 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1680 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1683 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1684 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1685 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1686 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1687 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1688 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1689 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1690 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1693 let AddedComplexity = 15 in
1694 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1696 "vmovq\t{$src, $dst|$dst, $src}",
1697 [(set VR128X:$dst, (v2i64 (X86vzmovl
1698 (v2i64 VR128X:$src))))],
1699 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1701 let AddedComplexity = 20 in
1702 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1704 "vmovq\t{$src, $dst|$dst, $src}",
1705 [(set VR128X:$dst, (v2i64 (X86vzmovl
1706 (loadv2i64 addr:$src))))],
1707 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1708 EVEX_CD8<8, CD8VT8>;
1710 let Predicates = [HasAVX512] in {
1711 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1712 let AddedComplexity = 20 in {
1713 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1714 (VMOVDI2PDIZrm addr:$src)>;
1715 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1716 (VMOV64toPQIZrr GR64:$src)>;
1717 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1718 (VMOVDI2PDIZrr GR32:$src)>;
1720 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1721 (VMOVDI2PDIZrm addr:$src)>;
1722 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1723 (VMOVDI2PDIZrm addr:$src)>;
1724 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1725 (VMOVZPQILo2PQIZrm addr:$src)>;
1726 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1727 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1728 def : Pat<(v2i64 (X86vzload addr:$src)),
1729 (VMOVZPQILo2PQIZrm addr:$src)>;
1732 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1733 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1734 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1735 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1736 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1737 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1738 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1741 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1742 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1744 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1745 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1747 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1748 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1750 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1751 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1753 //===----------------------------------------------------------------------===//
1754 // AVX-512 - Integer arithmetic
1756 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1757 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1758 X86MemOperand x86memop, PatFrag scalar_mfrag,
1759 X86MemOperand x86scalar_mop, string BrdcstStr,
1760 OpndItins itins, bit IsCommutable = 0> {
1761 let isCommutable = IsCommutable in
1762 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1763 (ins RC:$src1, RC:$src2),
1764 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1765 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1767 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1768 (ins RC:$src1, x86memop:$src2),
1769 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1770 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1772 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1773 (ins RC:$src1, x86scalar_mop:$src2),
1774 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1775 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1776 [(set RC:$dst, (OpNode RC:$src1,
1777 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1778 itins.rm>, EVEX_4V, EVEX_B;
1780 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1781 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1782 PatFrag memop_frag, X86MemOperand x86memop,
1784 bit IsCommutable = 0> {
1785 let isCommutable = IsCommutable in
1786 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1787 (ins RC:$src1, RC:$src2),
1788 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1789 []>, EVEX_4V, VEX_W;
1790 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1791 (ins RC:$src1, x86memop:$src2),
1792 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1793 []>, EVEX_4V, VEX_W;
1796 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1797 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1798 EVEX_V512, EVEX_CD8<32, CD8VF>;
1800 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1801 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1802 EVEX_V512, EVEX_CD8<32, CD8VF>;
1804 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1805 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1806 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1808 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1809 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1810 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1812 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1813 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1814 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1816 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1817 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1818 EVEX_V512, EVEX_CD8<64, CD8VF>;
1820 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1821 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1822 EVEX_CD8<64, CD8VF>;
1824 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1825 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1827 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1828 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1829 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1830 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1831 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1832 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1834 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1835 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1836 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1837 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1838 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1839 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1841 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1842 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1843 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1844 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1845 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1846 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1848 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1849 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1850 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1851 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1852 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1853 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1855 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1856 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1857 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1858 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1859 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1860 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1862 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1863 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1864 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1865 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1866 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1867 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1868 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1869 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1870 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1871 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1872 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1873 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1874 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1875 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1876 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1877 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1878 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1879 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1880 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1881 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1882 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1883 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1884 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1885 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1886 //===----------------------------------------------------------------------===//
1887 // AVX-512 - Unpack Instructions
1888 //===----------------------------------------------------------------------===//
1890 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1891 PatFrag mem_frag, RegisterClass RC,
1892 X86MemOperand x86memop, string asm,
1894 def rr : AVX512PI<opc, MRMSrcReg,
1895 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1897 (vt (OpNode RC:$src1, RC:$src2)))],
1899 def rm : AVX512PI<opc, MRMSrcMem,
1900 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1902 (vt (OpNode RC:$src1,
1903 (bitconvert (mem_frag addr:$src2)))))],
1907 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1908 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1909 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1910 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1911 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1912 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1913 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1914 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1915 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1916 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1917 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1918 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1920 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1921 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1922 X86MemOperand x86memop> {
1923 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1924 (ins RC:$src1, RC:$src2),
1925 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1926 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1927 IIC_SSE_UNPCK>, EVEX_4V;
1928 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1929 (ins RC:$src1, x86memop:$src2),
1930 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1931 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1932 (bitconvert (memop_frag addr:$src2)))))],
1933 IIC_SSE_UNPCK>, EVEX_4V;
1935 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1936 VR512, memopv16i32, i512mem>, EVEX_V512,
1937 EVEX_CD8<32, CD8VF>;
1938 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1939 VR512, memopv8i64, i512mem>, EVEX_V512,
1940 VEX_W, EVEX_CD8<64, CD8VF>;
1941 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1942 VR512, memopv16i32, i512mem>, EVEX_V512,
1943 EVEX_CD8<32, CD8VF>;
1944 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1945 VR512, memopv8i64, i512mem>, EVEX_V512,
1946 VEX_W, EVEX_CD8<64, CD8VF>;
1947 //===----------------------------------------------------------------------===//
1951 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1952 SDNode OpNode, PatFrag mem_frag,
1953 X86MemOperand x86memop, ValueType OpVT> {
1954 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1955 (ins RC:$src1, i8imm:$src2),
1956 !strconcat(OpcodeStr,
1957 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1959 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1961 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1962 (ins x86memop:$src1, i8imm:$src2),
1963 !strconcat(OpcodeStr,
1964 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1966 (OpVT (OpNode (mem_frag addr:$src1),
1967 (i8 imm:$src2))))]>, EVEX;
1970 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1971 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1973 let ExeDomain = SSEPackedSingle in
1974 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1975 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1976 EVEX_CD8<32, CD8VF>;
1977 let ExeDomain = SSEPackedDouble in
1978 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1979 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1980 VEX_W, EVEX_CD8<32, CD8VF>;
1982 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1983 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1984 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1985 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1987 //===----------------------------------------------------------------------===//
1988 // AVX-512 Logical Instructions
1989 //===----------------------------------------------------------------------===//
1991 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1992 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1993 EVEX_V512, EVEX_CD8<32, CD8VF>;
1994 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1995 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1996 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1997 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1998 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1999 EVEX_V512, EVEX_CD8<32, CD8VF>;
2000 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
2001 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2002 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2003 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
2004 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2005 EVEX_V512, EVEX_CD8<32, CD8VF>;
2006 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
2007 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2008 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2009 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
2010 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2011 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2012 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
2013 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
2014 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2016 //===----------------------------------------------------------------------===//
2017 // AVX-512 FP arithmetic
2018 //===----------------------------------------------------------------------===//
2020 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2022 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2023 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2024 EVEX_CD8<32, CD8VT1>;
2025 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2026 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2027 EVEX_CD8<64, CD8VT1>;
2030 let isCommutable = 1 in {
2031 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2032 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2033 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2034 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2036 let isCommutable = 0 in {
2037 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2038 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2041 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2043 RegisterClass RC, ValueType vt,
2044 X86MemOperand x86memop, PatFrag mem_frag,
2045 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2047 Domain d, OpndItins itins, bit commutable> {
2048 let isCommutable = commutable in {
2049 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2050 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2051 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2054 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2055 !strconcat(OpcodeStr,
2056 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2057 [], itins.rr, d>, EVEX_4V, EVEX_K;
2059 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2060 !strconcat(OpcodeStr,
2061 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2062 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2065 let mayLoad = 1 in {
2066 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2067 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2068 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2069 itins.rm, d>, EVEX_4V;
2071 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2072 (ins RC:$src1, x86scalar_mop:$src2),
2073 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2074 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2075 [(set RC:$dst, (OpNode RC:$src1,
2076 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2077 itins.rm, d>, EVEX_4V, EVEX_B;
2079 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2080 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2081 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2082 [], itins.rm, d>, EVEX_4V, EVEX_K;
2084 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2085 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2086 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2087 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2089 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2090 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2091 " \t{${src2}", BrdcstStr,
2092 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2093 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2095 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2096 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2097 " \t{${src2}", BrdcstStr,
2098 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2100 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2104 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2105 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2106 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2108 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2109 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2110 SSE_ALU_ITINS_P.d, 1>,
2111 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2113 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2114 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2115 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2116 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2117 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2118 SSE_ALU_ITINS_P.d, 1>,
2119 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2121 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2122 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2123 SSE_ALU_ITINS_P.s, 1>,
2124 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2125 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2126 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2127 SSE_ALU_ITINS_P.s, 1>,
2128 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2130 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2131 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2132 SSE_ALU_ITINS_P.d, 1>,
2133 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2134 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2135 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2136 SSE_ALU_ITINS_P.d, 1>,
2137 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2139 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2140 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2141 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2142 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2143 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2144 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2146 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2147 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2148 SSE_ALU_ITINS_P.d, 0>,
2149 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2150 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2151 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2152 SSE_ALU_ITINS_P.d, 0>,
2153 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2155 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2156 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2157 (i16 -1), FROUND_CURRENT)),
2158 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2160 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2161 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2162 (i8 -1), FROUND_CURRENT)),
2163 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2165 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2166 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2167 (i16 -1), FROUND_CURRENT)),
2168 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2170 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2171 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2172 (i8 -1), FROUND_CURRENT)),
2173 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2174 //===----------------------------------------------------------------------===//
2175 // AVX-512 VPTESTM instructions
2176 //===----------------------------------------------------------------------===//
2178 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2179 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2180 SDNode OpNode, ValueType vt> {
2181 def rr : AVX512PI<opc, MRMSrcReg,
2182 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2183 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2184 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2185 SSEPackedInt>, EVEX_4V;
2186 def rm : AVX512PI<opc, MRMSrcMem,
2187 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2188 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2189 [(set KRC:$dst, (OpNode (vt RC:$src1),
2190 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2193 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2194 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2195 EVEX_CD8<32, CD8VF>;
2196 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2197 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2198 EVEX_CD8<64, CD8VF>;
2200 let Predicates = [HasCDI] in {
2201 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2202 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2203 EVEX_CD8<32, CD8VF>;
2204 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2205 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2206 EVEX_CD8<64, CD8VF>;
2209 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2210 (v16i32 VR512:$src2), (i16 -1))),
2211 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2213 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2214 (v8i64 VR512:$src2), (i8 -1))),
2215 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2216 //===----------------------------------------------------------------------===//
2217 // AVX-512 Shift instructions
2218 //===----------------------------------------------------------------------===//
2219 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2220 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2221 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2222 RegisterClass KRC> {
2223 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2224 (ins RC:$src1, i8imm:$src2),
2225 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2226 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2227 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2228 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2229 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2230 !strconcat(OpcodeStr,
2231 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2232 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2233 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2234 (ins x86memop:$src1, i8imm:$src2),
2235 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2236 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2237 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2238 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2239 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2240 !strconcat(OpcodeStr,
2241 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2242 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2245 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2246 RegisterClass RC, ValueType vt, ValueType SrcVT,
2247 PatFrag bc_frag, RegisterClass KRC> {
2248 // src2 is always 128-bit
2249 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2250 (ins RC:$src1, VR128X:$src2),
2251 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2252 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2253 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2254 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2255 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2256 !strconcat(OpcodeStr,
2257 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2258 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2259 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2260 (ins RC:$src1, i128mem:$src2),
2261 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2262 [(set RC:$dst, (vt (OpNode RC:$src1,
2263 (bc_frag (memopv2i64 addr:$src2)))))],
2264 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2265 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2266 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2267 !strconcat(OpcodeStr,
2268 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2269 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2272 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2273 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2274 EVEX_V512, EVEX_CD8<32, CD8VF>;
2275 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2276 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2277 EVEX_CD8<32, CD8VQ>;
2279 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2280 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2281 EVEX_CD8<64, CD8VF>, VEX_W;
2282 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2283 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2284 EVEX_CD8<64, CD8VQ>, VEX_W;
2286 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2287 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2288 EVEX_CD8<32, CD8VF>;
2289 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2290 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2291 EVEX_CD8<32, CD8VQ>;
2293 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2294 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2295 EVEX_CD8<64, CD8VF>, VEX_W;
2296 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2297 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2298 EVEX_CD8<64, CD8VQ>, VEX_W;
2300 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2301 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2302 EVEX_V512, EVEX_CD8<32, CD8VF>;
2303 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2304 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2305 EVEX_CD8<32, CD8VQ>;
2307 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2308 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2309 EVEX_CD8<64, CD8VF>, VEX_W;
2310 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2311 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2312 EVEX_CD8<64, CD8VQ>, VEX_W;
2314 //===-------------------------------------------------------------------===//
2315 // Variable Bit Shifts
2316 //===-------------------------------------------------------------------===//
2317 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2318 RegisterClass RC, ValueType vt,
2319 X86MemOperand x86memop, PatFrag mem_frag> {
2320 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2321 (ins RC:$src1, RC:$src2),
2322 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2324 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2326 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2327 (ins RC:$src1, x86memop:$src2),
2328 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2330 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2334 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2335 i512mem, memopv16i32>, EVEX_V512,
2336 EVEX_CD8<32, CD8VF>;
2337 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2338 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2339 EVEX_CD8<64, CD8VF>;
2340 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2341 i512mem, memopv16i32>, EVEX_V512,
2342 EVEX_CD8<32, CD8VF>;
2343 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2344 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2345 EVEX_CD8<64, CD8VF>;
2346 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2347 i512mem, memopv16i32>, EVEX_V512,
2348 EVEX_CD8<32, CD8VF>;
2349 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2350 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2351 EVEX_CD8<64, CD8VF>;
2353 //===----------------------------------------------------------------------===//
2354 // AVX-512 - MOVDDUP
2355 //===----------------------------------------------------------------------===//
2357 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2358 X86MemOperand x86memop, PatFrag memop_frag> {
2359 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2360 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2361 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2362 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2363 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2365 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2368 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2369 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2370 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2371 (VMOVDDUPZrm addr:$src)>;
2373 //===---------------------------------------------------------------------===//
2374 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2375 //===---------------------------------------------------------------------===//
2376 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2377 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2378 X86MemOperand x86memop> {
2379 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2380 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2381 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2383 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2384 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2385 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2388 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2389 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2390 EVEX_CD8<32, CD8VF>;
2391 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2392 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2393 EVEX_CD8<32, CD8VF>;
2395 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2396 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2397 (VMOVSHDUPZrm addr:$src)>;
2398 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2399 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2400 (VMOVSLDUPZrm addr:$src)>;
2402 //===----------------------------------------------------------------------===//
2403 // Move Low to High and High to Low packed FP Instructions
2404 //===----------------------------------------------------------------------===//
2405 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2406 (ins VR128X:$src1, VR128X:$src2),
2407 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2408 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2409 IIC_SSE_MOV_LH>, EVEX_4V;
2410 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2411 (ins VR128X:$src1, VR128X:$src2),
2412 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2413 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2414 IIC_SSE_MOV_LH>, EVEX_4V;
2416 let Predicates = [HasAVX512] in {
2418 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2419 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2420 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2421 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2424 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2425 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2428 //===----------------------------------------------------------------------===//
2429 // FMA - Fused Multiply Operations
2431 let Constraints = "$src1 = $dst" in {
2432 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2433 RegisterClass RC, X86MemOperand x86memop,
2434 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2435 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2436 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2437 (ins RC:$src1, RC:$src2, RC:$src3),
2438 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2439 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2442 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2443 (ins RC:$src1, RC:$src2, x86memop:$src3),
2444 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2445 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2446 (mem_frag addr:$src3))))]>;
2447 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2448 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2449 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2450 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2451 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2452 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2454 } // Constraints = "$src1 = $dst"
2456 let ExeDomain = SSEPackedSingle in {
2457 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2458 memopv16f32, f32mem, loadf32, "{1to16}",
2459 X86Fmadd, v16f32>, EVEX_V512,
2460 EVEX_CD8<32, CD8VF>;
2461 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2462 memopv16f32, f32mem, loadf32, "{1to16}",
2463 X86Fmsub, v16f32>, EVEX_V512,
2464 EVEX_CD8<32, CD8VF>;
2465 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2466 memopv16f32, f32mem, loadf32, "{1to16}",
2467 X86Fmaddsub, v16f32>,
2468 EVEX_V512, EVEX_CD8<32, CD8VF>;
2469 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2470 memopv16f32, f32mem, loadf32, "{1to16}",
2471 X86Fmsubadd, v16f32>,
2472 EVEX_V512, EVEX_CD8<32, CD8VF>;
2473 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2474 memopv16f32, f32mem, loadf32, "{1to16}",
2475 X86Fnmadd, v16f32>, EVEX_V512,
2476 EVEX_CD8<32, CD8VF>;
2477 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2478 memopv16f32, f32mem, loadf32, "{1to16}",
2479 X86Fnmsub, v16f32>, EVEX_V512,
2480 EVEX_CD8<32, CD8VF>;
2482 let ExeDomain = SSEPackedDouble in {
2483 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2484 memopv8f64, f64mem, loadf64, "{1to8}",
2485 X86Fmadd, v8f64>, EVEX_V512,
2486 VEX_W, EVEX_CD8<64, CD8VF>;
2487 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2488 memopv8f64, f64mem, loadf64, "{1to8}",
2489 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2490 EVEX_CD8<64, CD8VF>;
2491 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2492 memopv8f64, f64mem, loadf64, "{1to8}",
2493 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2494 EVEX_CD8<64, CD8VF>;
2495 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2496 memopv8f64, f64mem, loadf64, "{1to8}",
2497 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2498 EVEX_CD8<64, CD8VF>;
2499 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2500 memopv8f64, f64mem, loadf64, "{1to8}",
2501 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2502 EVEX_CD8<64, CD8VF>;
2503 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2504 memopv8f64, f64mem, loadf64, "{1to8}",
2505 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2506 EVEX_CD8<64, CD8VF>;
2509 let Constraints = "$src1 = $dst" in {
2510 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2511 RegisterClass RC, X86MemOperand x86memop,
2512 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2513 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2515 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2516 (ins RC:$src1, RC:$src3, x86memop:$src2),
2517 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2518 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2519 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2520 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2521 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2522 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2523 [(set RC:$dst, (OpNode RC:$src1,
2524 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2526 } // Constraints = "$src1 = $dst"
2529 let ExeDomain = SSEPackedSingle in {
2530 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2531 memopv16f32, f32mem, loadf32, "{1to16}",
2532 X86Fmadd, v16f32>, EVEX_V512,
2533 EVEX_CD8<32, CD8VF>;
2534 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2535 memopv16f32, f32mem, loadf32, "{1to16}",
2536 X86Fmsub, v16f32>, EVEX_V512,
2537 EVEX_CD8<32, CD8VF>;
2538 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2539 memopv16f32, f32mem, loadf32, "{1to16}",
2540 X86Fmaddsub, v16f32>,
2541 EVEX_V512, EVEX_CD8<32, CD8VF>;
2542 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2543 memopv16f32, f32mem, loadf32, "{1to16}",
2544 X86Fmsubadd, v16f32>,
2545 EVEX_V512, EVEX_CD8<32, CD8VF>;
2546 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2547 memopv16f32, f32mem, loadf32, "{1to16}",
2548 X86Fnmadd, v16f32>, EVEX_V512,
2549 EVEX_CD8<32, CD8VF>;
2550 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2551 memopv16f32, f32mem, loadf32, "{1to16}",
2552 X86Fnmsub, v16f32>, EVEX_V512,
2553 EVEX_CD8<32, CD8VF>;
2555 let ExeDomain = SSEPackedDouble in {
2556 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2557 memopv8f64, f64mem, loadf64, "{1to8}",
2558 X86Fmadd, v8f64>, EVEX_V512,
2559 VEX_W, EVEX_CD8<64, CD8VF>;
2560 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2561 memopv8f64, f64mem, loadf64, "{1to8}",
2562 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2563 EVEX_CD8<64, CD8VF>;
2564 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2565 memopv8f64, f64mem, loadf64, "{1to8}",
2566 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2567 EVEX_CD8<64, CD8VF>;
2568 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2569 memopv8f64, f64mem, loadf64, "{1to8}",
2570 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2571 EVEX_CD8<64, CD8VF>;
2572 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2573 memopv8f64, f64mem, loadf64, "{1to8}",
2574 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2575 EVEX_CD8<64, CD8VF>;
2576 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2577 memopv8f64, f64mem, loadf64, "{1to8}",
2578 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2579 EVEX_CD8<64, CD8VF>;
2583 let Constraints = "$src1 = $dst" in {
2584 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2585 RegisterClass RC, ValueType OpVT,
2586 X86MemOperand x86memop, Operand memop,
2588 let isCommutable = 1 in
2589 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2590 (ins RC:$src1, RC:$src2, RC:$src3),
2591 !strconcat(OpcodeStr,
2592 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2594 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2596 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2597 (ins RC:$src1, RC:$src2, f128mem:$src3),
2598 !strconcat(OpcodeStr,
2599 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2601 (OpVT (OpNode RC:$src2, RC:$src1,
2602 (mem_frag addr:$src3))))]>;
2605 } // Constraints = "$src1 = $dst"
2607 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2608 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2609 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2610 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2611 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2612 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2613 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2614 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2615 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2616 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2617 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2618 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2619 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2620 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2621 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2622 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2624 //===----------------------------------------------------------------------===//
2625 // AVX-512 Scalar convert from sign integer to float/double
2626 //===----------------------------------------------------------------------===//
2628 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2629 X86MemOperand x86memop, string asm> {
2630 let hasSideEffects = 0 in {
2631 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2632 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2635 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2636 (ins DstRC:$src1, x86memop:$src),
2637 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2639 } // hasSideEffects = 0
2641 let Predicates = [HasAVX512] in {
2642 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2643 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2644 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2645 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2646 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2647 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2648 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2649 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2651 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2652 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2653 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2654 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2655 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2656 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2657 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2658 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2660 def : Pat<(f32 (sint_to_fp GR32:$src)),
2661 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2662 def : Pat<(f32 (sint_to_fp GR64:$src)),
2663 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2664 def : Pat<(f64 (sint_to_fp GR32:$src)),
2665 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2666 def : Pat<(f64 (sint_to_fp GR64:$src)),
2667 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2669 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2670 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2671 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2672 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2673 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2674 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2675 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2676 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2678 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2679 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2680 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2681 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2682 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2683 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2684 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2685 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2687 def : Pat<(f32 (uint_to_fp GR32:$src)),
2688 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2689 def : Pat<(f32 (uint_to_fp GR64:$src)),
2690 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2691 def : Pat<(f64 (uint_to_fp GR32:$src)),
2692 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2693 def : Pat<(f64 (uint_to_fp GR64:$src)),
2694 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2697 //===----------------------------------------------------------------------===//
2698 // AVX-512 Scalar convert from float/double to integer
2699 //===----------------------------------------------------------------------===//
2700 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2701 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2703 let hasSideEffects = 0 in {
2704 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2705 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2706 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2707 Requires<[HasAVX512]>;
2709 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2710 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2711 Requires<[HasAVX512]>;
2712 } // hasSideEffects = 0
2714 let Predicates = [HasAVX512] in {
2715 // Convert float/double to signed/unsigned int 32/64
2716 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2717 ssmem, sse_load_f32, "cvtss2si">,
2718 XS, EVEX_CD8<32, CD8VT1>;
2719 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2720 ssmem, sse_load_f32, "cvtss2si">,
2721 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2722 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2723 ssmem, sse_load_f32, "cvtss2usi">,
2724 XS, EVEX_CD8<32, CD8VT1>;
2725 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2726 int_x86_avx512_cvtss2usi64, ssmem,
2727 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2728 EVEX_CD8<32, CD8VT1>;
2729 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2730 sdmem, sse_load_f64, "cvtsd2si">,
2731 XD, EVEX_CD8<64, CD8VT1>;
2732 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2733 sdmem, sse_load_f64, "cvtsd2si">,
2734 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2735 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2736 sdmem, sse_load_f64, "cvtsd2usi">,
2737 XD, EVEX_CD8<64, CD8VT1>;
2738 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2739 int_x86_avx512_cvtsd2usi64, sdmem,
2740 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2741 EVEX_CD8<64, CD8VT1>;
2743 let isCodeGenOnly = 1 in {
2744 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2745 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2746 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2747 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2748 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2749 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2750 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2751 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2752 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2753 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2754 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2755 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2757 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2758 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2759 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2760 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2761 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2762 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2763 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2764 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2765 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2766 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2767 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2768 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2769 } // isCodeGenOnly = 1
2771 // Convert float/double to signed/unsigned int 32/64 with truncation
2772 let isCodeGenOnly = 1 in {
2773 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2774 ssmem, sse_load_f32, "cvttss2si">,
2775 XS, EVEX_CD8<32, CD8VT1>;
2776 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2777 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2778 "cvttss2si">, XS, VEX_W,
2779 EVEX_CD8<32, CD8VT1>;
2780 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2781 sdmem, sse_load_f64, "cvttsd2si">, XD,
2782 EVEX_CD8<64, CD8VT1>;
2783 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2784 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2785 "cvttsd2si">, XD, VEX_W,
2786 EVEX_CD8<64, CD8VT1>;
2787 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2788 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2789 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2790 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2791 int_x86_avx512_cvttss2usi64, ssmem,
2792 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2793 EVEX_CD8<32, CD8VT1>;
2794 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2795 int_x86_avx512_cvttsd2usi,
2796 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2797 EVEX_CD8<64, CD8VT1>;
2798 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2799 int_x86_avx512_cvttsd2usi64, sdmem,
2800 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2801 EVEX_CD8<64, CD8VT1>;
2802 } // isCodeGenOnly = 1
2804 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2805 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2807 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2808 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2809 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2810 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2811 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2812 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2815 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2816 loadf32, "cvttss2si">, XS,
2817 EVEX_CD8<32, CD8VT1>;
2818 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2819 loadf32, "cvttss2usi">, XS,
2820 EVEX_CD8<32, CD8VT1>;
2821 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2822 loadf32, "cvttss2si">, XS, VEX_W,
2823 EVEX_CD8<32, CD8VT1>;
2824 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2825 loadf32, "cvttss2usi">, XS, VEX_W,
2826 EVEX_CD8<32, CD8VT1>;
2827 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2828 loadf64, "cvttsd2si">, XD,
2829 EVEX_CD8<64, CD8VT1>;
2830 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2831 loadf64, "cvttsd2usi">, XD,
2832 EVEX_CD8<64, CD8VT1>;
2833 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2834 loadf64, "cvttsd2si">, XD, VEX_W,
2835 EVEX_CD8<64, CD8VT1>;
2836 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2837 loadf64, "cvttsd2usi">, XD, VEX_W,
2838 EVEX_CD8<64, CD8VT1>;
2840 //===----------------------------------------------------------------------===//
2841 // AVX-512 Convert form float to double and back
2842 //===----------------------------------------------------------------------===//
2843 let hasSideEffects = 0 in {
2844 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2845 (ins FR32X:$src1, FR32X:$src2),
2846 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2847 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2849 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2850 (ins FR32X:$src1, f32mem:$src2),
2851 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2852 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2853 EVEX_CD8<32, CD8VT1>;
2855 // Convert scalar double to scalar single
2856 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2857 (ins FR64X:$src1, FR64X:$src2),
2858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2859 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2861 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2862 (ins FR64X:$src1, f64mem:$src2),
2863 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2864 []>, EVEX_4V, VEX_LIG, VEX_W,
2865 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2868 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2869 Requires<[HasAVX512]>;
2870 def : Pat<(fextend (loadf32 addr:$src)),
2871 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2873 def : Pat<(extloadf32 addr:$src),
2874 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2875 Requires<[HasAVX512, OptForSize]>;
2877 def : Pat<(extloadf32 addr:$src),
2878 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2879 Requires<[HasAVX512, OptForSpeed]>;
2881 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2882 Requires<[HasAVX512]>;
2884 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2885 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2886 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2888 let hasSideEffects = 0 in {
2889 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2890 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2892 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2893 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2894 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2895 [], d>, EVEX, EVEX_B, EVEX_RC;
2897 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2898 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2900 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2901 } // hasSideEffects = 0
2904 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2905 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2906 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2908 let hasSideEffects = 0 in {
2909 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2910 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2912 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2914 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2915 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2917 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2918 } // hasSideEffects = 0
2921 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2922 memopv8f64, f512mem, v8f32, v8f64,
2923 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2924 EVEX_CD8<64, CD8VF>;
2926 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2927 memopv4f64, f256mem, v8f64, v8f32,
2928 SSEPackedDouble>, EVEX_V512, PS,
2929 EVEX_CD8<32, CD8VH>;
2930 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2931 (VCVTPS2PDZrm addr:$src)>;
2933 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2934 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2935 (VCVTPD2PSZrr VR512:$src)>;
2937 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2938 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2939 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2941 //===----------------------------------------------------------------------===//
2942 // AVX-512 Vector convert from sign integer to float/double
2943 //===----------------------------------------------------------------------===//
2945 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2946 memopv8i64, i512mem, v16f32, v16i32,
2947 SSEPackedSingle>, EVEX_V512, PS,
2948 EVEX_CD8<32, CD8VF>;
2950 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2951 memopv4i64, i256mem, v8f64, v8i32,
2952 SSEPackedDouble>, EVEX_V512, XS,
2953 EVEX_CD8<32, CD8VH>;
2955 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2956 memopv16f32, f512mem, v16i32, v16f32,
2957 SSEPackedSingle>, EVEX_V512, XS,
2958 EVEX_CD8<32, CD8VF>;
2960 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2961 memopv8f64, f512mem, v8i32, v8f64,
2962 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2963 EVEX_CD8<64, CD8VF>;
2965 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2966 memopv16f32, f512mem, v16i32, v16f32,
2967 SSEPackedSingle>, EVEX_V512, PS,
2968 EVEX_CD8<32, CD8VF>;
2970 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2971 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2972 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2973 (VCVTTPS2UDQZrr VR512:$src)>;
2975 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2976 memopv8f64, f512mem, v8i32, v8f64,
2977 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
2978 EVEX_CD8<64, CD8VF>;
2980 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2981 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2982 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2983 (VCVTTPD2UDQZrr VR512:$src)>;
2985 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2986 memopv4i64, f256mem, v8f64, v8i32,
2987 SSEPackedDouble>, EVEX_V512, XS,
2988 EVEX_CD8<32, CD8VH>;
2990 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2991 memopv16i32, f512mem, v16f32, v16i32,
2992 SSEPackedSingle>, EVEX_V512, XD,
2993 EVEX_CD8<32, CD8VF>;
2995 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2996 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2997 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3000 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3001 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3002 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3003 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3004 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3005 (VCVTDQ2PDZrr VR256X:$src)>;
3006 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3007 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3008 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3009 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3010 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3011 (VCVTUDQ2PDZrr VR256X:$src)>;
3013 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3014 RegisterClass DstRC, PatFrag mem_frag,
3015 X86MemOperand x86memop, Domain d> {
3016 let hasSideEffects = 0 in {
3017 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3018 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3020 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3021 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3022 [], d>, EVEX, EVEX_B, EVEX_RC;
3024 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3025 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3027 } // hasSideEffects = 0
3030 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3031 memopv16f32, f512mem, SSEPackedSingle>, PD,
3032 EVEX_V512, EVEX_CD8<32, CD8VF>;
3033 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3034 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3035 EVEX_V512, EVEX_CD8<64, CD8VF>;
3037 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3038 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3039 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3041 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3042 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3043 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3045 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3046 memopv16f32, f512mem, SSEPackedSingle>,
3047 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3048 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3049 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3050 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3052 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3053 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3054 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3056 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3057 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3058 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3060 let Predicates = [HasAVX512] in {
3061 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3062 (VCVTPD2PSZrm addr:$src)>;
3063 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3064 (VCVTPS2PDZrm addr:$src)>;
3067 //===----------------------------------------------------------------------===//
3068 // Half precision conversion instructions
3069 //===----------------------------------------------------------------------===//
3070 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3071 X86MemOperand x86memop> {
3072 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3073 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3075 let hasSideEffects = 0, mayLoad = 1 in
3076 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3077 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3080 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3081 X86MemOperand x86memop> {
3082 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3083 (ins srcRC:$src1, i32i8imm:$src2),
3084 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3086 let hasSideEffects = 0, mayStore = 1 in
3087 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3088 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3089 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3092 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3093 EVEX_CD8<32, CD8VH>;
3094 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3095 EVEX_CD8<32, CD8VH>;
3097 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3098 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3099 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3101 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3102 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3103 (VCVTPH2PSZrr VR256X:$src)>;
3105 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3106 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3107 "ucomiss">, PS, EVEX, VEX_LIG,
3108 EVEX_CD8<32, CD8VT1>;
3109 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3110 "ucomisd">, PD, EVEX,
3111 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3112 let Pattern = []<dag> in {
3113 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3114 "comiss">, PS, EVEX, VEX_LIG,
3115 EVEX_CD8<32, CD8VT1>;
3116 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3117 "comisd">, PD, EVEX,
3118 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3120 let isCodeGenOnly = 1 in {
3121 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3122 load, "ucomiss">, PS, EVEX, VEX_LIG,
3123 EVEX_CD8<32, CD8VT1>;
3124 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3125 load, "ucomisd">, PD, EVEX,
3126 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3128 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3129 load, "comiss">, PS, EVEX, VEX_LIG,
3130 EVEX_CD8<32, CD8VT1>;
3131 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3132 load, "comisd">, PD, EVEX,
3133 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3137 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3138 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3139 X86MemOperand x86memop> {
3140 let hasSideEffects = 0 in {
3141 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3142 (ins RC:$src1, RC:$src2),
3143 !strconcat(OpcodeStr,
3144 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3145 let mayLoad = 1 in {
3146 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3147 (ins RC:$src1, x86memop:$src2),
3148 !strconcat(OpcodeStr,
3149 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3154 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3155 EVEX_CD8<32, CD8VT1>;
3156 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3157 VEX_W, EVEX_CD8<64, CD8VT1>;
3158 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3159 EVEX_CD8<32, CD8VT1>;
3160 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3161 VEX_W, EVEX_CD8<64, CD8VT1>;
3163 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3164 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3165 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3166 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3168 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3169 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3170 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3171 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3173 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3174 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3175 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3176 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3178 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3179 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3180 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3181 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3183 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3184 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3185 RegisterClass RC, X86MemOperand x86memop,
3186 PatFrag mem_frag, ValueType OpVt> {
3187 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3188 !strconcat(OpcodeStr,
3189 " \t{$src, $dst|$dst, $src}"),
3190 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3192 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3193 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3194 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3197 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3198 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3199 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3200 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3201 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3202 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3203 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3204 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3206 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3207 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3208 (VRSQRT14PSZr VR512:$src)>;
3209 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3210 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3211 (VRSQRT14PDZr VR512:$src)>;
3213 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3214 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3215 (VRCP14PSZr VR512:$src)>;
3216 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3217 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3218 (VRCP14PDZr VR512:$src)>;
3220 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3221 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3222 X86MemOperand x86memop> {
3223 let hasSideEffects = 0, Predicates = [HasERI] in {
3224 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3225 (ins RC:$src1, RC:$src2),
3226 !strconcat(OpcodeStr,
3227 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3228 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3229 (ins RC:$src1, RC:$src2),
3230 !strconcat(OpcodeStr,
3231 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3232 []>, EVEX_4V, EVEX_B;
3233 let mayLoad = 1 in {
3234 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3235 (ins RC:$src1, x86memop:$src2),
3236 !strconcat(OpcodeStr,
3237 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3242 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3243 EVEX_CD8<32, CD8VT1>;
3244 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3245 VEX_W, EVEX_CD8<64, CD8VT1>;
3246 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3247 EVEX_CD8<32, CD8VT1>;
3248 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3249 VEX_W, EVEX_CD8<64, CD8VT1>;
3251 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3252 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3254 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3255 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3257 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3258 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3260 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3261 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3263 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3264 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3266 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3267 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3269 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3270 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3272 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3273 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3275 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3276 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3277 RegisterClass RC, X86MemOperand x86memop> {
3278 let hasSideEffects = 0, Predicates = [HasERI] in {
3279 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3280 !strconcat(OpcodeStr,
3281 " \t{$src, $dst|$dst, $src}"),
3283 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3284 !strconcat(OpcodeStr,
3285 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3287 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3288 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3292 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3293 EVEX_V512, EVEX_CD8<32, CD8VF>;
3294 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3295 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3296 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3297 EVEX_V512, EVEX_CD8<32, CD8VF>;
3298 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3299 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3301 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3302 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3303 (VRSQRT28PSZrb VR512:$src)>;
3304 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3305 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3306 (VRSQRT28PDZrb VR512:$src)>;
3308 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3309 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3310 (VRCP28PSZrb VR512:$src)>;
3311 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3312 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3313 (VRCP28PDZrb VR512:$src)>;
3315 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3316 Intrinsic V16F32Int, Intrinsic V8F64Int,
3317 OpndItins itins_s, OpndItins itins_d> {
3318 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3319 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3320 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3324 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3325 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3327 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3328 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3330 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3331 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3332 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3336 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3337 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3338 [(set VR512:$dst, (OpNode
3339 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3340 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3342 let isCodeGenOnly = 1 in {
3343 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3344 !strconcat(OpcodeStr,
3345 "ps\t{$src, $dst|$dst, $src}"),
3346 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3348 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3349 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3351 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3352 EVEX_V512, EVEX_CD8<32, CD8VF>;
3353 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3354 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3355 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3356 EVEX, EVEX_V512, VEX_W;
3357 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3358 !strconcat(OpcodeStr,
3359 "pd\t{$src, $dst|$dst, $src}"),
3360 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3361 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3362 } // isCodeGenOnly = 1
3365 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3366 Intrinsic F32Int, Intrinsic F64Int,
3367 OpndItins itins_s, OpndItins itins_d> {
3368 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3369 (ins FR32X:$src1, FR32X:$src2),
3370 !strconcat(OpcodeStr,
3371 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3372 [], itins_s.rr>, XS, EVEX_4V;
3373 let isCodeGenOnly = 1 in
3374 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3375 (ins VR128X:$src1, VR128X:$src2),
3376 !strconcat(OpcodeStr,
3377 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3379 (F32Int VR128X:$src1, VR128X:$src2))],
3380 itins_s.rr>, XS, EVEX_4V;
3381 let mayLoad = 1 in {
3382 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3383 (ins FR32X:$src1, f32mem:$src2),
3384 !strconcat(OpcodeStr,
3385 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3386 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3387 let isCodeGenOnly = 1 in
3388 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3389 (ins VR128X:$src1, ssmem:$src2),
3390 !strconcat(OpcodeStr,
3391 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3393 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3394 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3396 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3397 (ins FR64X:$src1, FR64X:$src2),
3398 !strconcat(OpcodeStr,
3399 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3401 let isCodeGenOnly = 1 in
3402 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3403 (ins VR128X:$src1, VR128X:$src2),
3404 !strconcat(OpcodeStr,
3405 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3407 (F64Int VR128X:$src1, VR128X:$src2))],
3408 itins_s.rr>, XD, EVEX_4V, VEX_W;
3409 let mayLoad = 1 in {
3410 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3411 (ins FR64X:$src1, f64mem:$src2),
3412 !strconcat(OpcodeStr,
3413 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3414 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3415 let isCodeGenOnly = 1 in
3416 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3417 (ins VR128X:$src1, sdmem:$src2),
3418 !strconcat(OpcodeStr,
3419 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3421 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3422 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3427 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3428 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3429 SSE_SQRTSS, SSE_SQRTSD>,
3430 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3431 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3432 SSE_SQRTPS, SSE_SQRTPD>;
3434 let Predicates = [HasAVX512] in {
3435 def : Pat<(f32 (fsqrt FR32X:$src)),
3436 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3437 def : Pat<(f32 (fsqrt (load addr:$src))),
3438 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3439 Requires<[OptForSize]>;
3440 def : Pat<(f64 (fsqrt FR64X:$src)),
3441 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3442 def : Pat<(f64 (fsqrt (load addr:$src))),
3443 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3444 Requires<[OptForSize]>;
3446 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3447 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3448 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3449 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3450 Requires<[OptForSize]>;
3452 def : Pat<(f32 (X86frcp FR32X:$src)),
3453 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3454 def : Pat<(f32 (X86frcp (load addr:$src))),
3455 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3456 Requires<[OptForSize]>;
3458 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3459 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3460 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3462 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3463 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3465 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3466 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3467 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3469 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3470 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3474 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3475 X86MemOperand x86memop, RegisterClass RC,
3476 PatFrag mem_frag32, PatFrag mem_frag64,
3477 Intrinsic V4F32Int, Intrinsic V2F64Int,
3479 let ExeDomain = SSEPackedSingle in {
3480 // Intrinsic operation, reg.
3481 // Vector intrinsic operation, reg
3482 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3483 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3484 !strconcat(OpcodeStr,
3485 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3486 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3488 // Vector intrinsic operation, mem
3489 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3490 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3491 !strconcat(OpcodeStr,
3492 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3494 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3495 EVEX_CD8<32, VForm>;
3496 } // ExeDomain = SSEPackedSingle
3498 let ExeDomain = SSEPackedDouble in {
3499 // Vector intrinsic operation, reg
3500 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3501 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3502 !strconcat(OpcodeStr,
3503 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3504 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3506 // Vector intrinsic operation, mem
3507 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3508 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3509 !strconcat(OpcodeStr,
3510 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3512 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3513 EVEX_CD8<64, VForm>;
3514 } // ExeDomain = SSEPackedDouble
3517 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3521 let ExeDomain = GenericDomain in {
3523 let hasSideEffects = 0 in
3524 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3525 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3526 !strconcat(OpcodeStr,
3527 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3530 // Intrinsic operation, reg.
3531 let isCodeGenOnly = 1 in
3532 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3533 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3534 !strconcat(OpcodeStr,
3535 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3536 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3538 // Intrinsic operation, mem.
3539 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3540 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3541 !strconcat(OpcodeStr,
3542 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3543 [(set VR128X:$dst, (F32Int VR128X:$src1,
3544 sse_load_f32:$src2, imm:$src3))]>,
3545 EVEX_CD8<32, CD8VT1>;
3548 let hasSideEffects = 0 in
3549 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3550 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3551 !strconcat(OpcodeStr,
3552 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3555 // Intrinsic operation, reg.
3556 let isCodeGenOnly = 1 in
3557 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3558 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3559 !strconcat(OpcodeStr,
3560 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3561 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3564 // Intrinsic operation, mem.
3565 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3566 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3567 !strconcat(OpcodeStr,
3568 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3570 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3571 VEX_W, EVEX_CD8<64, CD8VT1>;
3572 } // ExeDomain = GenericDomain
3575 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3576 X86MemOperand x86memop, RegisterClass RC,
3577 PatFrag mem_frag, Domain d> {
3578 let ExeDomain = d in {
3579 // Intrinsic operation, reg.
3580 // Vector intrinsic operation, reg
3581 def r : AVX512AIi8<opc, MRMSrcReg,
3582 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3583 !strconcat(OpcodeStr,
3584 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3587 // Vector intrinsic operation, mem
3588 def m : AVX512AIi8<opc, MRMSrcMem,
3589 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3590 !strconcat(OpcodeStr,
3591 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3597 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3598 memopv16f32, SSEPackedSingle>, EVEX_V512,
3599 EVEX_CD8<32, CD8VF>;
3601 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3602 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3604 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3607 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3608 memopv8f64, SSEPackedDouble>, EVEX_V512,
3609 VEX_W, EVEX_CD8<64, CD8VF>;
3611 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3612 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3614 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3616 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3617 Operand x86memop, RegisterClass RC, Domain d> {
3618 let ExeDomain = d in {
3619 def r : AVX512AIi8<opc, MRMSrcReg,
3620 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3621 !strconcat(OpcodeStr,
3622 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3625 def m : AVX512AIi8<opc, MRMSrcMem,
3626 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3627 !strconcat(OpcodeStr,
3628 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3633 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3634 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3636 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3637 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3639 def : Pat<(ffloor FR32X:$src),
3640 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3641 def : Pat<(f64 (ffloor FR64X:$src)),
3642 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3643 def : Pat<(f32 (fnearbyint FR32X:$src)),
3644 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3645 def : Pat<(f64 (fnearbyint FR64X:$src)),
3646 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3647 def : Pat<(f32 (fceil FR32X:$src)),
3648 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3649 def : Pat<(f64 (fceil FR64X:$src)),
3650 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3651 def : Pat<(f32 (frint FR32X:$src)),
3652 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3653 def : Pat<(f64 (frint FR64X:$src)),
3654 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3655 def : Pat<(f32 (ftrunc FR32X:$src)),
3656 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3657 def : Pat<(f64 (ftrunc FR64X:$src)),
3658 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3660 def : Pat<(v16f32 (ffloor VR512:$src)),
3661 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3662 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3663 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3664 def : Pat<(v16f32 (fceil VR512:$src)),
3665 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3666 def : Pat<(v16f32 (frint VR512:$src)),
3667 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3668 def : Pat<(v16f32 (ftrunc VR512:$src)),
3669 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3671 def : Pat<(v8f64 (ffloor VR512:$src)),
3672 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3673 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3674 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3675 def : Pat<(v8f64 (fceil VR512:$src)),
3676 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3677 def : Pat<(v8f64 (frint VR512:$src)),
3678 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3679 def : Pat<(v8f64 (ftrunc VR512:$src)),
3680 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3682 //-------------------------------------------------
3683 // Integer truncate and extend operations
3684 //-------------------------------------------------
3686 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3687 RegisterClass dstRC, RegisterClass srcRC,
3688 RegisterClass KRC, X86MemOperand x86memop> {
3689 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3691 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3694 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3695 (ins KRC:$mask, srcRC:$src),
3696 !strconcat(OpcodeStr,
3697 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3700 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3701 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3704 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3705 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3706 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3707 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3708 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3709 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3710 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3711 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3712 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3713 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3714 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3715 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3716 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3717 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3718 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3719 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3720 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3721 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3722 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3723 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3724 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3725 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3726 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3727 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3728 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3729 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3730 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3731 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3732 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3733 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3735 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3736 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3737 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3738 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3739 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3741 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3742 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3743 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3744 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3745 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3746 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3747 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3748 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3751 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3752 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3753 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3755 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3757 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3758 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3759 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3760 (ins x86memop:$src),
3761 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3763 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3767 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3768 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3770 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3771 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3773 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3774 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3775 EVEX_CD8<16, CD8VH>;
3776 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3777 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3778 EVEX_CD8<16, CD8VQ>;
3779 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3780 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3781 EVEX_CD8<32, CD8VH>;
3783 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3784 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3786 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3787 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3789 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3790 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3791 EVEX_CD8<16, CD8VH>;
3792 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3793 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3794 EVEX_CD8<16, CD8VQ>;
3795 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3796 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3797 EVEX_CD8<32, CD8VH>;
3799 //===----------------------------------------------------------------------===//
3800 // GATHER - SCATTER Operations
3802 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3803 RegisterClass RC, X86MemOperand memop> {
3805 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3806 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3807 (ins RC:$src1, KRC:$mask, memop:$src2),
3808 !strconcat(OpcodeStr,
3809 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3812 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3813 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3814 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3815 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3817 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3818 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3819 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3820 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3822 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3823 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3824 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3825 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3827 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3828 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3829 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3830 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3832 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3833 RegisterClass RC, X86MemOperand memop> {
3834 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3835 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3836 (ins memop:$dst, KRC:$mask, RC:$src2),
3837 !strconcat(OpcodeStr,
3838 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3842 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3843 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3844 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3845 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3847 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3848 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3849 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3850 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3852 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3853 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3854 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3855 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3857 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3858 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3859 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3860 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3862 //===----------------------------------------------------------------------===//
3863 // VSHUFPS - VSHUFPD Operations
3865 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3866 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3868 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3869 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3870 !strconcat(OpcodeStr,
3871 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3872 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3873 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3874 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3875 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3876 (ins RC:$src1, RC:$src2, i8imm:$src3),
3877 !strconcat(OpcodeStr,
3878 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3879 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3880 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3881 EVEX_4V, Sched<[WriteShuffle]>;
3884 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3885 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3886 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3887 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3889 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3890 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3891 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3892 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3893 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3895 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3896 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3897 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3898 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3899 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3901 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3902 X86MemOperand x86memop> {
3903 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3904 (ins RC:$src1, RC:$src2, i8imm:$src3),
3905 !strconcat(OpcodeStr,
3906 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3909 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3910 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3911 !strconcat(OpcodeStr,
3912 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3915 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3916 EVEX_V512, EVEX_CD8<32, CD8VF>;
3917 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3918 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3920 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3921 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3922 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3923 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3924 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3925 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3926 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3927 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3929 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3930 X86MemOperand x86memop> {
3931 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3932 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3934 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3935 (ins x86memop:$src),
3936 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3940 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3941 EVEX_CD8<32, CD8VF>;
3942 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3943 EVEX_CD8<64, CD8VF>;
3945 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3946 (v16i32 immAllZerosV), (i16 -1))),
3947 (VPABSDrr VR512:$src)>;
3948 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3949 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3950 (VPABSQrr VR512:$src)>;
3952 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3953 RegisterClass RC, RegisterClass KRC,
3954 X86MemOperand x86memop,
3955 X86MemOperand x86scalar_mop, string BrdcstStr> {
3956 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3958 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3960 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3961 (ins x86memop:$src),
3962 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3964 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3965 (ins x86scalar_mop:$src),
3966 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3967 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3969 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3970 (ins KRC:$mask, RC:$src),
3971 !strconcat(OpcodeStr,
3972 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3974 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3975 (ins KRC:$mask, x86memop:$src),
3976 !strconcat(OpcodeStr,
3977 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3979 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3980 (ins KRC:$mask, x86scalar_mop:$src),
3981 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3982 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3984 []>, EVEX, EVEX_KZ, EVEX_B;
3986 let Constraints = "$src1 = $dst" in {
3987 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3988 (ins RC:$src1, KRC:$mask, RC:$src2),
3989 !strconcat(OpcodeStr,
3990 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3992 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3993 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3994 !strconcat(OpcodeStr,
3995 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3997 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3998 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3999 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4000 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4001 []>, EVEX, EVEX_K, EVEX_B;
4005 let Predicates = [HasCDI] in {
4006 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4007 i512mem, i32mem, "{1to16}">,
4008 EVEX_V512, EVEX_CD8<32, CD8VF>;
4011 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4012 i512mem, i64mem, "{1to8}">,
4013 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4017 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4019 (VPCONFLICTDrrk VR512:$src1,
4020 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4022 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4024 (VPCONFLICTQrrk VR512:$src1,
4025 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;