1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 // Similar to AVX512_maskable_3rc but in this case the input VT for the tied
280 // operand differs from the output VT. This requires a bitconvert on
281 // the preserved vector going into the vselect.
282 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
283 X86VectorVTInfo InVT,
284 dag Outs, dag NonTiedIns, string OpcodeStr,
285 string AttSrcAsm, string IntelSrcAsm,
287 AVX512_maskable_common<O, F, OutVT, Outs,
288 !con((ins InVT.RC:$src1), NonTiedIns),
289 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
290 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
291 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
292 (vselect InVT.KRCWM:$mask, RHS,
293 (bitconvert InVT.RC:$src1))>;
295 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
296 dag Outs, dag NonTiedIns, string OpcodeStr,
297 string AttSrcAsm, string IntelSrcAsm,
299 AVX512_maskable_common<O, F, _, Outs,
300 !con((ins _.RC:$src1), NonTiedIns),
301 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
302 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
303 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
304 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
306 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
309 string AttSrcAsm, string IntelSrcAsm,
311 AVX512_maskable_custom<O, F, Outs, Ins,
312 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
313 !con((ins _.KRCWM:$mask), Ins),
314 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
318 // Instruction with mask that puts result in mask register,
319 // like "compare" and "vptest"
320 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
322 dag Ins, dag MaskingIns,
324 string AttSrcAsm, string IntelSrcAsm,
326 list<dag> MaskingPattern,
328 InstrItinClass itin = NoItinerary> {
329 def NAME: AVX512<O, F, Outs, Ins,
330 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
331 "$dst "#Round#", "#IntelSrcAsm#"}",
334 def NAME#k: AVX512<O, F, Outs, MaskingIns,
335 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
336 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
337 MaskingPattern, itin>, EVEX_K;
340 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
342 dag Ins, dag MaskingIns,
344 string AttSrcAsm, string IntelSrcAsm,
345 dag RHS, dag MaskingRHS,
347 InstrItinClass itin = NoItinerary> :
348 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
349 AttSrcAsm, IntelSrcAsm,
350 [(set _.KRC:$dst, RHS)],
351 [(set _.KRC:$dst, MaskingRHS)],
354 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
355 dag Outs, dag Ins, string OpcodeStr,
356 string AttSrcAsm, string IntelSrcAsm,
357 dag RHS, string Round = "",
358 InstrItinClass itin = NoItinerary> :
359 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
360 !con((ins _.KRCWM:$mask), Ins),
361 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
362 (and _.KRCWM:$mask, RHS),
365 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
366 dag Outs, dag Ins, string OpcodeStr,
367 string AttSrcAsm, string IntelSrcAsm> :
368 AVX512_maskable_custom_cmp<O, F, Outs,
369 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
370 AttSrcAsm, IntelSrcAsm,
371 [],[],"", NoItinerary>;
373 // Bitcasts between 512-bit vector types. Return the original type since
374 // no instruction is needed for the conversion
375 let Predicates = [HasAVX512] in {
376 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
378 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
379 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
380 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
387 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
395 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
396 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
397 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
403 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
408 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
409 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
410 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
411 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
412 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
413 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
414 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
415 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
416 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
417 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
418 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
419 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
420 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
421 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
422 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
423 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
424 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
425 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
426 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
427 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
428 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
429 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
430 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
431 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
432 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
433 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
434 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
435 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
436 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
437 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
439 // Bitcasts between 256-bit vector types. Return the original type since
440 // no instruction is needed for the conversion
441 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
442 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
443 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
444 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
445 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
446 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
447 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
448 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
449 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
450 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
451 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
452 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
453 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
454 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
455 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
456 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
457 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
458 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
459 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
460 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
461 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
462 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
463 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
464 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
465 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
466 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
467 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
468 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
469 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
470 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
474 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
477 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
478 isPseudo = 1, Predicates = [HasAVX512] in {
479 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
480 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
483 let Predicates = [HasAVX512] in {
484 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
485 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
486 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
489 //===----------------------------------------------------------------------===//
490 // AVX-512 - VECTOR INSERT
492 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
493 PatFrag vinsert_insert> {
494 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
495 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
496 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
497 "vinsert" # From.EltTypeName # "x" # From.NumElts,
498 "$src3, $src2, $src1", "$src1, $src2, $src3",
499 (vinsert_insert:$src3 (To.VT To.RC:$src1),
500 (From.VT From.RC:$src2),
501 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
504 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
505 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
506 "vinsert" # From.EltTypeName # "x" # From.NumElts,
507 "$src3, $src2, $src1", "$src1, $src2, $src3",
508 (vinsert_insert:$src3 (To.VT To.RC:$src1),
509 (From.VT (bitconvert (From.LdFrag addr:$src2))),
510 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
511 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
515 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
516 X86VectorVTInfo To, PatFrag vinsert_insert,
517 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
518 let Predicates = p in {
519 def : Pat<(vinsert_insert:$ins
520 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
521 (To.VT (!cast<Instruction>(InstrStr#"rr")
522 To.RC:$src1, From.RC:$src2,
523 (INSERT_get_vinsert_imm To.RC:$ins)))>;
525 def : Pat<(vinsert_insert:$ins
527 (From.VT (bitconvert (From.LdFrag addr:$src2))),
529 (To.VT (!cast<Instruction>(InstrStr#"rm")
530 To.RC:$src1, addr:$src2,
531 (INSERT_get_vinsert_imm To.RC:$ins)))>;
535 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
536 ValueType EltVT64, int Opcode256> {
538 let Predicates = [HasVLX] in
539 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 4, EltVT32, VR128X>,
541 X86VectorVTInfo< 8, EltVT32, VR256X>,
542 vinsert128_insert>, EVEX_V256;
544 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
545 X86VectorVTInfo< 4, EltVT32, VR128X>,
546 X86VectorVTInfo<16, EltVT32, VR512>,
547 vinsert128_insert>, EVEX_V512;
549 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
550 X86VectorVTInfo< 4, EltVT64, VR256X>,
551 X86VectorVTInfo< 8, EltVT64, VR512>,
552 vinsert256_insert>, VEX_W, EVEX_V512;
554 let Predicates = [HasVLX, HasDQI] in
555 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
556 X86VectorVTInfo< 2, EltVT64, VR128X>,
557 X86VectorVTInfo< 4, EltVT64, VR256X>,
558 vinsert128_insert>, VEX_W, EVEX_V256;
560 let Predicates = [HasDQI] in {
561 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
562 X86VectorVTInfo< 2, EltVT64, VR128X>,
563 X86VectorVTInfo< 8, EltVT64, VR512>,
564 vinsert128_insert>, VEX_W, EVEX_V512;
566 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
567 X86VectorVTInfo< 8, EltVT32, VR256X>,
568 X86VectorVTInfo<16, EltVT32, VR512>,
569 vinsert256_insert>, EVEX_V512;
573 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
574 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
576 // Codegen pattern with the alternative types,
577 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
578 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
583 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
588 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
593 // Codegen pattern with the alternative types insert VEC128 into VEC256
594 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
595 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
596 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
597 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
598 // Codegen pattern with the alternative types insert VEC128 into VEC512
599 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
600 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
601 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
602 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
603 // Codegen pattern with the alternative types insert VEC256 into VEC512
604 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
605 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
606 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
607 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
609 // vinsertps - insert f32 to XMM
610 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
611 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
612 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
613 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
615 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
616 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
617 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
618 [(set VR128X:$dst, (X86insertps VR128X:$src1,
619 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
620 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
622 //===----------------------------------------------------------------------===//
623 // AVX-512 VECTOR EXTRACT
626 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
627 X86VectorVTInfo To> {
628 // A subvector extract from the first vector position is
629 // a subregister copy that needs no instruction.
630 def NAME # To.NumElts:
631 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
632 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
635 multiclass vextract_for_size<int Opcode,
636 X86VectorVTInfo From, X86VectorVTInfo To,
637 PatFrag vextract_extract> :
638 vextract_for_size_first_position_lowering<From, To> {
640 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
641 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
642 // vextract_extract), we interesting only in patterns without mask,
643 // intrinsics pattern match generated bellow.
644 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
645 (ins From.RC:$src1, i32u8imm:$idx),
646 "vextract" # To.EltTypeName # "x" # To.NumElts,
647 "$idx, $src1", "$src1, $idx",
648 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
650 AVX512AIi8Base, EVEX;
651 let mayStore = 1 in {
652 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
653 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
654 "vextract" # To.EltTypeName # "x" # To.NumElts #
655 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
658 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
659 (ins To.MemOp:$dst, To.KRCWM:$mask,
660 From.RC:$src1, i32u8imm:$src2),
661 "vextract" # To.EltTypeName # "x" # To.NumElts #
662 "\t{$src2, $src1, $dst {${mask}}|"
663 "$dst {${mask}}, $src1, $src2}",
668 // Intrinsic call with masking.
669 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
670 "x" # To.NumElts # "_" # From.Size)
671 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
672 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
673 From.ZSuffix # "rrk")
675 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
676 From.RC:$src1, imm:$idx)>;
678 // Intrinsic call with zero-masking.
679 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
680 "x" # To.NumElts # "_" # From.Size)
681 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
682 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
683 From.ZSuffix # "rrkz")
684 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
685 From.RC:$src1, imm:$idx)>;
687 // Intrinsic call without masking.
688 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
689 "x" # To.NumElts # "_" # From.Size)
690 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
691 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
693 From.RC:$src1, imm:$idx)>;
696 // Codegen pattern for the alternative types
697 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
698 X86VectorVTInfo To, PatFrag vextract_extract,
699 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
700 vextract_for_size_first_position_lowering<From, To> {
702 let Predicates = p in
703 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
704 (To.VT (!cast<Instruction>(InstrStr#"rr")
706 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
709 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
710 ValueType EltVT64, int Opcode256> {
711 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
712 X86VectorVTInfo<16, EltVT32, VR512>,
713 X86VectorVTInfo< 4, EltVT32, VR128X>,
714 vextract128_extract>,
715 EVEX_V512, EVEX_CD8<32, CD8VT4>;
716 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
717 X86VectorVTInfo< 8, EltVT64, VR512>,
718 X86VectorVTInfo< 4, EltVT64, VR256X>,
719 vextract256_extract>,
720 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
721 let Predicates = [HasVLX] in
722 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
723 X86VectorVTInfo< 8, EltVT32, VR256X>,
724 X86VectorVTInfo< 4, EltVT32, VR128X>,
725 vextract128_extract>,
726 EVEX_V256, EVEX_CD8<32, CD8VT4>;
727 let Predicates = [HasVLX, HasDQI] in
728 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
729 X86VectorVTInfo< 4, EltVT64, VR256X>,
730 X86VectorVTInfo< 2, EltVT64, VR128X>,
731 vextract128_extract>,
732 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
733 let Predicates = [HasDQI] in {
734 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
735 X86VectorVTInfo< 8, EltVT64, VR512>,
736 X86VectorVTInfo< 2, EltVT64, VR128X>,
737 vextract128_extract>,
738 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
739 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
740 X86VectorVTInfo<16, EltVT32, VR512>,
741 X86VectorVTInfo< 8, EltVT32, VR256X>,
742 vextract256_extract>,
743 EVEX_V512, EVEX_CD8<32, CD8VT8>;
747 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
748 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
750 // extract_subvector codegen patterns with the alternative types.
751 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
752 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
757 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
762 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
763 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
764 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
765 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
767 // Codegen pattern with the alternative types extract VEC128 from VEC512
768 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
769 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
770 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
771 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
772 // Codegen pattern with the alternative types extract VEC256 from VEC512
773 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
774 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
775 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
776 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
778 // A 128-bit subvector insert to the first 512-bit vector position
779 // is a subregister copy that needs no instruction.
780 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
781 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
782 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
784 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
785 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
786 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
788 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
789 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
790 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
792 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
793 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
794 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
797 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
798 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
799 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
800 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
801 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
802 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
803 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
804 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
805 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
806 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
807 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
808 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
810 // vextractps - extract 32 bits from XMM
811 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
812 (ins VR128X:$src1, u8imm:$src2),
813 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
817 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
818 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
819 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
820 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
821 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
823 //===---------------------------------------------------------------------===//
827 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
830 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
831 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
832 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
836 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
837 (DestInfo.VT (X86VBroadcast
838 (SrcInfo.ScalarLdFrag addr:$src)))>,
839 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
842 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
843 AVX512VLVectorVTInfo _> {
844 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
847 let Predicates = [HasVLX] in {
848 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
853 let ExeDomain = SSEPackedSingle in {
854 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
856 let Predicates = [HasVLX] in {
857 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
858 v4f32x_info, v4f32x_info>, EVEX_V128;
862 let ExeDomain = SSEPackedDouble in {
863 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
864 avx512vl_f64_info>, VEX_W;
867 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
868 // Later, we can canonize broadcast instructions before ISel phase and
869 // eliminate additional patterns on ISel.
870 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
871 // representations of source
872 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
873 X86VectorVTInfo _, RegisterClass SrcRC_v,
874 RegisterClass SrcRC_s> {
875 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
876 (!cast<Instruction>(InstName##"r")
877 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
879 let AddedComplexity = 30 in {
880 def : Pat<(_.VT (vselect _.KRCWM:$mask,
881 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
882 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
883 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
885 def : Pat<(_.VT(vselect _.KRCWM:$mask,
886 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
887 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
888 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
892 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
894 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
897 let Predicates = [HasVLX] in {
898 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
899 v8f32x_info, VR128X, FR32X>;
900 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
901 v4f32x_info, VR128X, FR32X>;
902 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
903 v4f64x_info, VR128X, FR64X>;
906 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
907 (VBROADCASTSSZm addr:$src)>;
908 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
909 (VBROADCASTSDZm addr:$src)>;
911 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
912 (VBROADCASTSSZm addr:$src)>;
913 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
914 (VBROADCASTSDZm addr:$src)>;
916 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
917 RegisterClass SrcRC> {
918 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
919 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
920 "$src", "$src", []>, T8PD, EVEX;
923 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
924 RegisterClass SrcRC, Predicate prd> {
925 let Predicates = [prd] in
926 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
927 let Predicates = [prd, HasVLX] in {
928 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
929 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
933 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
935 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
937 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
939 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
942 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
943 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
945 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
946 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
948 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
949 (VPBROADCASTDrZr GR32:$src)>;
950 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
951 (VPBROADCASTQrZr GR64:$src)>;
953 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
954 (VPBROADCASTDrZr GR32:$src)>;
955 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
956 (VPBROADCASTQrZr GR64:$src)>;
958 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
959 (v16i32 immAllZerosV), (i16 GR16:$mask))),
960 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
961 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
962 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
963 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
965 // Provide aliases for broadcast from the same register class that
966 // automatically does the extract.
967 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
968 X86VectorVTInfo SrcInfo> {
969 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
970 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
971 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
974 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
975 AVX512VLVectorVTInfo _, Predicate prd> {
976 let Predicates = [prd] in {
977 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
978 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
980 // Defined separately to avoid redefinition.
981 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
983 let Predicates = [prd, HasVLX] in {
984 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
985 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
987 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
992 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
993 avx512vl_i8_info, HasBWI>;
994 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
995 avx512vl_i16_info, HasBWI>;
996 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
997 avx512vl_i32_info, HasAVX512>;
998 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
999 avx512vl_i64_info, HasAVX512>, VEX_W;
1001 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
1002 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
1003 let mayLoad = 1 in {
1004 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
1005 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1007 (_Dst.VT (X86SubVBroadcast
1008 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
1009 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1011 !strconcat(OpcodeStr,
1012 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1014 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1016 !strconcat(OpcodeStr,
1017 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1022 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1023 v16i32_info, v4i32x_info>,
1024 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1025 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1026 v16f32_info, v4f32x_info>,
1027 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1028 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1029 v8i64_info, v4i64x_info>, VEX_W,
1030 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1031 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1032 v8f64_info, v4f64x_info>, VEX_W,
1033 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1035 let Predicates = [HasVLX] in {
1036 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1037 v8i32x_info, v4i32x_info>,
1038 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1039 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1040 v8f32x_info, v4f32x_info>,
1041 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1043 let Predicates = [HasVLX, HasDQI] in {
1044 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1045 v4i64x_info, v2i64x_info>, VEX_W,
1046 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1047 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1048 v4f64x_info, v2f64x_info>, VEX_W,
1049 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1051 let Predicates = [HasDQI] in {
1052 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1053 v8i64_info, v2i64x_info>, VEX_W,
1054 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1055 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1056 v16i32_info, v8i32x_info>,
1057 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1058 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1059 v8f64_info, v2f64x_info>, VEX_W,
1060 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1061 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1062 v16f32_info, v8f32x_info>,
1063 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1066 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1067 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1068 SDNode OpNode = X86SubVBroadcast> {
1070 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1071 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1072 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1075 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1076 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1078 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1079 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1082 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1083 AVX512VLVectorVTInfo _> {
1084 let Predicates = [HasDQI] in
1085 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1087 let Predicates = [HasDQI, HasVLX] in
1088 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1092 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1093 AVX512VLVectorVTInfo _> :
1094 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1096 let Predicates = [HasDQI, HasVLX] in
1097 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1098 X86SubV32x2Broadcast>, EVEX_V128;
1101 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1103 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1106 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1107 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1108 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1109 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1111 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1112 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1113 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1114 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1116 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1117 (VBROADCASTSSZr VR128X:$src)>;
1118 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1119 (VBROADCASTSDZr VR128X:$src)>;
1121 // Provide fallback in case the load node that is used in the patterns above
1122 // is used by additional users, which prevents the pattern selection.
1123 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1124 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1125 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1126 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1129 //===----------------------------------------------------------------------===//
1130 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1132 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1133 X86VectorVTInfo _, RegisterClass KRC> {
1134 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1135 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1136 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1139 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1140 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1141 let Predicates = [HasCDI] in
1142 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1143 let Predicates = [HasCDI, HasVLX] in {
1144 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1145 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1149 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1150 avx512vl_i32_info, VK16>;
1151 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1152 avx512vl_i64_info, VK8>, VEX_W;
1154 //===----------------------------------------------------------------------===//
1155 // -- VPERMI2 - 3 source operands form --
1156 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr,
1157 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1158 let Constraints = "$src1 = $dst" in {
1159 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1160 (ins _.RC:$src2, _.RC:$src3),
1161 OpcodeStr, "$src3, $src2", "$src2, $src3",
1162 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1166 defm rm: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1167 (ins _.RC:$src2, _.MemOp:$src3),
1168 OpcodeStr, "$src3, $src2", "$src2, $src3",
1169 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2,
1170 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1171 EVEX_4V, AVX5128IBase;
1174 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1175 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1176 let mayLoad = 1, Constraints = "$src1 = $dst" in
1177 defm rmb: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1178 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1179 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1180 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1181 (_.VT (X86VPermi2X IdxVT.RC:$src1,
1182 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1183 AVX5128IBase, EVEX_4V, EVEX_B;
1186 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1187 AVX512VLVectorVTInfo VTInfo,
1188 AVX512VLVectorVTInfo ShuffleMask> {
1189 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1190 ShuffleMask.info512>,
1191 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info512,
1192 ShuffleMask.info512>, EVEX_V512;
1193 let Predicates = [HasVLX] in {
1194 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1195 ShuffleMask.info128>,
1196 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info128,
1197 ShuffleMask.info128>, EVEX_V128;
1198 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1199 ShuffleMask.info256>,
1200 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info256,
1201 ShuffleMask.info256>, EVEX_V256;
1205 multiclass avx512_perm_i_sizes_w<bits<8> opc, string OpcodeStr,
1206 AVX512VLVectorVTInfo VTInfo,
1207 AVX512VLVectorVTInfo Idx> {
1208 let Predicates = [HasBWI] in
1209 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1210 Idx.info512>, EVEX_V512;
1211 let Predicates = [HasBWI, HasVLX] in {
1212 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1213 Idx.info128>, EVEX_V128;
1214 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1215 Idx.info256>, EVEX_V256;
1219 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d",
1220 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1221 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q",
1222 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1223 defm VPERMI2W : avx512_perm_i_sizes_w<0x75, "vpermi2w",
1224 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1225 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps",
1226 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1227 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd",
1228 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1231 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1232 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1233 let Constraints = "$src1 = $dst" in {
1234 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1235 (ins IdxVT.RC:$src2, _.RC:$src3),
1236 OpcodeStr, "$src3, $src2", "$src2, $src3",
1237 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3))>, EVEX_4V,
1241 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1242 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1243 OpcodeStr, "$src3, $src2", "$src2, $src3",
1244 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1245 (bitconvert (_.LdFrag addr:$src3))))>,
1246 EVEX_4V, AVX5128IBase;
1249 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1250 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1251 let mayLoad = 1, Constraints = "$src1 = $dst" in
1252 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1253 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1254 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1255 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1256 (_.VT (X86VPermt2 _.RC:$src1,
1257 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1258 AVX5128IBase, EVEX_4V, EVEX_B;
1261 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1262 AVX512VLVectorVTInfo VTInfo,
1263 AVX512VLVectorVTInfo ShuffleMask> {
1264 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1265 ShuffleMask.info512>,
1266 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1267 ShuffleMask.info512>, EVEX_V512;
1268 let Predicates = [HasVLX] in {
1269 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1270 ShuffleMask.info128>,
1271 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1272 ShuffleMask.info128>, EVEX_V128;
1273 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1274 ShuffleMask.info256>,
1275 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1276 ShuffleMask.info256>, EVEX_V256;
1280 multiclass avx512_perm_t_sizes_w<bits<8> opc, string OpcodeStr,
1281 AVX512VLVectorVTInfo VTInfo,
1282 AVX512VLVectorVTInfo Idx> {
1283 let Predicates = [HasBWI] in
1284 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1285 Idx.info512>, EVEX_V512;
1286 let Predicates = [HasBWI, HasVLX] in {
1287 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1288 Idx.info128>, EVEX_V128;
1289 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1290 Idx.info256>, EVEX_V256;
1294 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1295 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1296 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1297 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1298 defm VPERMT2W : avx512_perm_t_sizes_w<0x7D, "vpermt2w",
1299 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1300 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1301 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1302 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1303 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1305 //===----------------------------------------------------------------------===//
1306 // AVX-512 - BLEND using mask
1308 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1309 let ExeDomain = _.ExeDomain in {
1310 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1311 (ins _.RC:$src1, _.RC:$src2),
1312 !strconcat(OpcodeStr,
1313 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1315 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1316 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1317 !strconcat(OpcodeStr,
1318 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1319 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1320 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1321 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1322 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1323 !strconcat(OpcodeStr,
1324 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1325 []>, EVEX_4V, EVEX_KZ;
1326 let mayLoad = 1 in {
1327 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1328 (ins _.RC:$src1, _.MemOp:$src2),
1329 !strconcat(OpcodeStr,
1330 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1331 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1332 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1333 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1334 !strconcat(OpcodeStr,
1335 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1336 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1337 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1338 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1339 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1340 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1341 !strconcat(OpcodeStr,
1342 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1343 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1347 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1349 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1350 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1351 !strconcat(OpcodeStr,
1352 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1353 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1354 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1355 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1356 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1358 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1359 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1360 !strconcat(OpcodeStr,
1361 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1362 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1363 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1367 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1368 AVX512VLVectorVTInfo VTInfo> {
1369 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1370 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1372 let Predicates = [HasVLX] in {
1373 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1374 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1375 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1376 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1380 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1381 AVX512VLVectorVTInfo VTInfo> {
1382 let Predicates = [HasBWI] in
1383 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1385 let Predicates = [HasBWI, HasVLX] in {
1386 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1387 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1392 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1393 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1394 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1395 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1396 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1397 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1400 let Predicates = [HasAVX512] in {
1401 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1402 (v8f32 VR256X:$src2))),
1404 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1405 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1406 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1408 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1409 (v8i32 VR256X:$src2))),
1411 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1412 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1413 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1415 //===----------------------------------------------------------------------===//
1416 // Compare Instructions
1417 //===----------------------------------------------------------------------===//
1419 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1421 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1423 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1425 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1426 "vcmp${cc}"#_.Suffix,
1427 "$src2, $src1", "$src1, $src2",
1428 (OpNode (_.VT _.RC:$src1),
1432 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1434 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1435 "vcmp${cc}"#_.Suffix,
1436 "$src2, $src1", "$src1, $src2",
1437 (OpNode (_.VT _.RC:$src1),
1438 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1439 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1441 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1443 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1444 "vcmp${cc}"#_.Suffix,
1445 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1446 (OpNodeRnd (_.VT _.RC:$src1),
1449 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1450 // Accept explicit immediate argument form instead of comparison code.
1451 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1452 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1454 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1456 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1457 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1459 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1461 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1462 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1464 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1466 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1468 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1470 }// let isAsmParserOnly = 1, hasSideEffects = 0
1472 let isCodeGenOnly = 1 in {
1473 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1474 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1475 !strconcat("vcmp${cc}", _.Suffix,
1476 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1477 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1480 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1482 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1484 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1485 !strconcat("vcmp${cc}", _.Suffix,
1486 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1487 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1488 (_.ScalarLdFrag addr:$src2),
1490 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1494 let Predicates = [HasAVX512] in {
1495 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1497 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1498 AVX512XDIi8Base, VEX_W;
1501 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1502 X86VectorVTInfo _> {
1503 def rr : AVX512BI<opc, MRMSrcReg,
1504 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1505 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1506 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1507 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1509 def rm : AVX512BI<opc, MRMSrcMem,
1510 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1511 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1512 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1513 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1514 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1515 def rrk : AVX512BI<opc, MRMSrcReg,
1516 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1518 "$dst {${mask}}, $src1, $src2}"),
1519 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1520 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1521 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1523 def rmk : AVX512BI<opc, MRMSrcMem,
1524 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1526 "$dst {${mask}}, $src1, $src2}"),
1527 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1528 (OpNode (_.VT _.RC:$src1),
1530 (_.LdFrag addr:$src2))))))],
1531 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1534 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1535 X86VectorVTInfo _> :
1536 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1537 let mayLoad = 1 in {
1538 def rmb : AVX512BI<opc, MRMSrcMem,
1539 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1540 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1541 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1542 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1543 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1544 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1545 def rmbk : AVX512BI<opc, MRMSrcMem,
1546 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1547 _.ScalarMemOp:$src2),
1548 !strconcat(OpcodeStr,
1549 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1550 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1551 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1552 (OpNode (_.VT _.RC:$src1),
1554 (_.ScalarLdFrag addr:$src2)))))],
1555 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1559 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1560 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1561 let Predicates = [prd] in
1562 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1565 let Predicates = [prd, HasVLX] in {
1566 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1568 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1573 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1574 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1576 let Predicates = [prd] in
1577 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1580 let Predicates = [prd, HasVLX] in {
1581 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1583 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1588 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1589 avx512vl_i8_info, HasBWI>,
1592 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1593 avx512vl_i16_info, HasBWI>,
1594 EVEX_CD8<16, CD8VF>;
1596 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1597 avx512vl_i32_info, HasAVX512>,
1598 EVEX_CD8<32, CD8VF>;
1600 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1601 avx512vl_i64_info, HasAVX512>,
1602 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1604 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1605 avx512vl_i8_info, HasBWI>,
1608 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1609 avx512vl_i16_info, HasBWI>,
1610 EVEX_CD8<16, CD8VF>;
1612 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1613 avx512vl_i32_info, HasAVX512>,
1614 EVEX_CD8<32, CD8VF>;
1616 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1617 avx512vl_i64_info, HasAVX512>,
1618 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1620 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1621 (COPY_TO_REGCLASS (VPCMPGTDZrr
1622 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1623 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1625 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1626 (COPY_TO_REGCLASS (VPCMPEQDZrr
1627 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1628 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1630 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1631 X86VectorVTInfo _> {
1632 def rri : AVX512AIi8<opc, MRMSrcReg,
1633 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1634 !strconcat("vpcmp${cc}", Suffix,
1635 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1636 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1638 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1640 def rmi : AVX512AIi8<opc, MRMSrcMem,
1641 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1642 !strconcat("vpcmp${cc}", Suffix,
1643 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1644 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1645 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1647 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1648 def rrik : AVX512AIi8<opc, MRMSrcReg,
1649 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1651 !strconcat("vpcmp${cc}", Suffix,
1652 "\t{$src2, $src1, $dst {${mask}}|",
1653 "$dst {${mask}}, $src1, $src2}"),
1654 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1655 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1657 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1659 def rmik : AVX512AIi8<opc, MRMSrcMem,
1660 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1662 !strconcat("vpcmp${cc}", Suffix,
1663 "\t{$src2, $src1, $dst {${mask}}|",
1664 "$dst {${mask}}, $src1, $src2}"),
1665 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1666 (OpNode (_.VT _.RC:$src1),
1667 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1669 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1671 // Accept explicit immediate argument form instead of comparison code.
1672 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1673 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1674 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1675 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1676 "$dst, $src1, $src2, $cc}"),
1677 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1679 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1680 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1681 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1682 "$dst, $src1, $src2, $cc}"),
1683 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1684 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1685 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1687 !strconcat("vpcmp", Suffix,
1688 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1689 "$dst {${mask}}, $src1, $src2, $cc}"),
1690 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1692 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1693 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1695 !strconcat("vpcmp", Suffix,
1696 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1697 "$dst {${mask}}, $src1, $src2, $cc}"),
1698 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1702 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1703 X86VectorVTInfo _> :
1704 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1705 def rmib : AVX512AIi8<opc, MRMSrcMem,
1706 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1708 !strconcat("vpcmp${cc}", Suffix,
1709 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1710 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1711 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1712 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1714 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1715 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1716 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1717 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1718 !strconcat("vpcmp${cc}", Suffix,
1719 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1720 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1721 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1722 (OpNode (_.VT _.RC:$src1),
1723 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1725 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1727 // Accept explicit immediate argument form instead of comparison code.
1728 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1729 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1730 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1732 !strconcat("vpcmp", Suffix,
1733 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1734 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1735 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1736 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1737 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1738 _.ScalarMemOp:$src2, u8imm:$cc),
1739 !strconcat("vpcmp", Suffix,
1740 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1741 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1742 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1746 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1747 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1748 let Predicates = [prd] in
1749 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1751 let Predicates = [prd, HasVLX] in {
1752 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1753 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1757 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1758 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1759 let Predicates = [prd] in
1760 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1763 let Predicates = [prd, HasVLX] in {
1764 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1766 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1771 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1772 HasBWI>, EVEX_CD8<8, CD8VF>;
1773 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1774 HasBWI>, EVEX_CD8<8, CD8VF>;
1776 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1777 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1778 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1779 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1781 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1782 HasAVX512>, EVEX_CD8<32, CD8VF>;
1783 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1784 HasAVX512>, EVEX_CD8<32, CD8VF>;
1786 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1787 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1788 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1789 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1791 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1793 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1794 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1795 "vcmp${cc}"#_.Suffix,
1796 "$src2, $src1", "$src1, $src2",
1797 (X86cmpm (_.VT _.RC:$src1),
1801 let mayLoad = 1 in {
1802 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1803 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1804 "vcmp${cc}"#_.Suffix,
1805 "$src2, $src1", "$src1, $src2",
1806 (X86cmpm (_.VT _.RC:$src1),
1807 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1810 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1812 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1813 "vcmp${cc}"#_.Suffix,
1814 "${src2}"##_.BroadcastStr##", $src1",
1815 "$src1, ${src2}"##_.BroadcastStr,
1816 (X86cmpm (_.VT _.RC:$src1),
1817 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1820 // Accept explicit immediate argument form instead of comparison code.
1821 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1822 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1824 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1826 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1828 let mayLoad = 1 in {
1829 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1831 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1833 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1835 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1837 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1839 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1840 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1845 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1846 // comparison code form (VCMP[EQ/LT/LE/...]
1847 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1848 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1849 "vcmp${cc}"#_.Suffix,
1850 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1851 (X86cmpmRnd (_.VT _.RC:$src1),
1854 (i32 FROUND_NO_EXC))>, EVEX_B;
1856 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1857 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1859 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1861 "$cc,{sae}, $src2, $src1",
1862 "$src1, $src2,{sae}, $cc">, EVEX_B;
1866 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1867 let Predicates = [HasAVX512] in {
1868 defm Z : avx512_vcmp_common<_.info512>,
1869 avx512_vcmp_sae<_.info512>, EVEX_V512;
1872 let Predicates = [HasAVX512,HasVLX] in {
1873 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1874 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1878 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1879 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1880 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1881 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1883 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1884 (COPY_TO_REGCLASS (VCMPPSZrri
1885 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1886 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1888 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1889 (COPY_TO_REGCLASS (VPCMPDZrri
1890 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1891 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1893 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1894 (COPY_TO_REGCLASS (VPCMPUDZrri
1895 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1896 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1899 // ----------------------------------------------------------------
1901 //handle fpclass instruction mask = op(reg_scalar,imm)
1902 // op(mem_scalar,imm)
1903 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1904 X86VectorVTInfo _, Predicate prd> {
1905 let Predicates = [prd] in {
1906 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1907 (ins _.RC:$src1, i32u8imm:$src2),
1908 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1909 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1910 (i32 imm:$src2)))], NoItinerary>;
1911 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1912 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1913 OpcodeStr##_.Suffix#
1914 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1915 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1916 (OpNode (_.VT _.RC:$src1),
1917 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1918 let mayLoad = 1, AddedComplexity = 20 in {
1919 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1920 (ins _.MemOp:$src1, i32u8imm:$src2),
1921 OpcodeStr##_.Suffix##
1922 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1924 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1925 (i32 imm:$src2)))], NoItinerary>;
1926 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1927 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1928 OpcodeStr##_.Suffix##
1929 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1930 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1931 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1932 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1937 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1938 // fpclass(reg_vec, mem_vec, imm)
1939 // fpclass(reg_vec, broadcast(eltVt), imm)
1940 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1941 X86VectorVTInfo _, string mem, string broadcast>{
1942 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1943 (ins _.RC:$src1, i32u8imm:$src2),
1944 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1945 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1946 (i32 imm:$src2)))], NoItinerary>;
1947 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1948 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1949 OpcodeStr##_.Suffix#
1950 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1951 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1952 (OpNode (_.VT _.RC:$src1),
1953 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1954 let mayLoad = 1 in {
1955 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1956 (ins _.MemOp:$src1, i32u8imm:$src2),
1957 OpcodeStr##_.Suffix##mem#
1958 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1959 [(set _.KRC:$dst,(OpNode
1960 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1961 (i32 imm:$src2)))], NoItinerary>;
1962 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1963 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1964 OpcodeStr##_.Suffix##mem#
1965 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1966 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1967 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1968 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1969 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1970 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1971 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1972 _.BroadcastStr##", $dst | $dst, ${src1}"
1973 ##_.BroadcastStr##", $src2}",
1974 [(set _.KRC:$dst,(OpNode
1975 (_.VT (X86VBroadcast
1976 (_.ScalarLdFrag addr:$src1))),
1977 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1978 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1979 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1980 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1981 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1982 _.BroadcastStr##", $src2}",
1983 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1984 (_.VT (X86VBroadcast
1985 (_.ScalarLdFrag addr:$src1))),
1986 (i32 imm:$src2))))], NoItinerary>,
1991 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1992 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1994 let Predicates = [prd] in {
1995 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1996 broadcast>, EVEX_V512;
1998 let Predicates = [prd, HasVLX] in {
1999 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
2000 broadcast>, EVEX_V128;
2001 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
2002 broadcast>, EVEX_V256;
2006 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
2007 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
2008 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
2009 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
2010 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
2011 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
2012 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2013 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
2014 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2015 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
2018 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
2019 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
2021 //-----------------------------------------------------------------
2022 // Mask register copy, including
2023 // - copy between mask registers
2024 // - load/store mask registers
2025 // - copy from GPR to mask register and vice versa
2027 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
2028 string OpcodeStr, RegisterClass KRC,
2029 ValueType vvt, X86MemOperand x86memop> {
2030 let hasSideEffects = 0 in {
2031 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2032 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2034 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2035 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2036 [(set KRC:$dst, (vvt (load addr:$src)))]>;
2038 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2039 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2040 [(store KRC:$src, addr:$dst)]>;
2044 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
2046 RegisterClass KRC, RegisterClass GRC> {
2047 let hasSideEffects = 0 in {
2048 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
2049 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2050 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
2051 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2055 let Predicates = [HasDQI] in
2056 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2057 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
2060 let Predicates = [HasAVX512] in
2061 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2062 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2065 let Predicates = [HasBWI] in {
2066 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2068 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2072 let Predicates = [HasBWI] in {
2073 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2075 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2079 // GR from/to mask register
2080 let Predicates = [HasDQI] in {
2081 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2082 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2083 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2084 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2086 let Predicates = [HasAVX512] in {
2087 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2088 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2089 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2090 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2092 let Predicates = [HasBWI] in {
2093 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2094 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2096 let Predicates = [HasBWI] in {
2097 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2098 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2102 let Predicates = [HasDQI] in {
2103 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2104 (KMOVBmk addr:$dst, VK8:$src)>;
2105 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2106 (KMOVBkm addr:$src)>;
2108 def : Pat<(store VK4:$src, addr:$dst),
2109 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2110 def : Pat<(store VK2:$src, addr:$dst),
2111 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2113 let Predicates = [HasAVX512, NoDQI] in {
2114 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2115 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2116 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2117 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2119 let Predicates = [HasAVX512] in {
2120 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2121 (KMOVWmk addr:$dst, VK16:$src)>;
2122 def : Pat<(i1 (load addr:$src)),
2123 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2124 (MOV8rm addr:$src), sub_8bit)),
2126 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2127 (KMOVWkm addr:$src)>;
2129 let Predicates = [HasBWI] in {
2130 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2131 (KMOVDmk addr:$dst, VK32:$src)>;
2132 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2133 (KMOVDkm addr:$src)>;
2135 let Predicates = [HasBWI] in {
2136 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2137 (KMOVQmk addr:$dst, VK64:$src)>;
2138 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2139 (KMOVQkm addr:$src)>;
2142 let Predicates = [HasAVX512] in {
2143 def : Pat<(i1 (trunc (i64 GR64:$src))),
2144 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2147 def : Pat<(i1 (trunc (i32 GR32:$src))),
2148 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2150 def : Pat<(i1 (trunc (i8 GR8:$src))),
2152 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2154 def : Pat<(i1 (trunc (i16 GR16:$src))),
2156 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2159 def : Pat<(i32 (zext VK1:$src)),
2160 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2161 def : Pat<(i32 (anyext VK1:$src)),
2162 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2164 def : Pat<(i8 (zext VK1:$src)),
2167 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2168 def : Pat<(i8 (anyext VK1:$src)),
2170 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2172 def : Pat<(i64 (zext VK1:$src)),
2173 (AND64ri8 (SUBREG_TO_REG (i64 0),
2174 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2175 def : Pat<(i16 (zext VK1:$src)),
2177 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2179 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2180 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2181 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2182 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2184 let Predicates = [HasBWI] in {
2185 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2186 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2187 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2188 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2192 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2193 let Predicates = [HasAVX512, NoDQI] in {
2194 // GR from/to 8-bit mask without native support
2195 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2197 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2198 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2200 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2204 let Predicates = [HasAVX512] in {
2205 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2206 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2207 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2208 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2210 let Predicates = [HasBWI] in {
2211 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2212 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2213 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2214 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2217 // Mask unary operation
2219 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2220 RegisterClass KRC, SDPatternOperator OpNode,
2222 let Predicates = [prd] in
2223 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2224 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2225 [(set KRC:$dst, (OpNode KRC:$src))]>;
2228 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2229 SDPatternOperator OpNode> {
2230 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2232 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2233 HasAVX512>, VEX, PS;
2234 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2235 HasBWI>, VEX, PD, VEX_W;
2236 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2237 HasBWI>, VEX, PS, VEX_W;
2240 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2242 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2243 let Predicates = [HasAVX512] in
2244 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2246 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2247 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2249 defm : avx512_mask_unop_int<"knot", "KNOT">;
2251 let Predicates = [HasDQI] in
2252 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2253 let Predicates = [HasAVX512] in
2254 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2255 let Predicates = [HasBWI] in
2256 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2257 let Predicates = [HasBWI] in
2258 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2260 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2261 let Predicates = [HasAVX512, NoDQI] in {
2262 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2263 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2264 def : Pat<(not VK8:$src),
2266 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2268 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2269 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2270 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2271 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2273 // Mask binary operation
2274 // - KAND, KANDN, KOR, KXNOR, KXOR
2275 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2276 RegisterClass KRC, SDPatternOperator OpNode,
2277 Predicate prd, bit IsCommutable> {
2278 let Predicates = [prd], isCommutable = IsCommutable in
2279 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2280 !strconcat(OpcodeStr,
2281 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2282 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2285 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2286 SDPatternOperator OpNode, bit IsCommutable,
2287 Predicate prdW = HasAVX512> {
2288 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2289 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2290 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2291 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2292 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2293 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2294 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2295 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2298 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2299 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2301 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2302 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2303 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2304 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2305 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2306 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2308 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2309 let Predicates = [HasAVX512] in
2310 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2311 (i16 GR16:$src1), (i16 GR16:$src2)),
2312 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2313 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2314 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2317 defm : avx512_mask_binop_int<"kand", "KAND">;
2318 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2319 defm : avx512_mask_binop_int<"kor", "KOR">;
2320 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2321 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2323 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2324 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2325 // for the DQI set, this type is legal and KxxxB instruction is used
2326 let Predicates = [NoDQI] in
2327 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2329 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2330 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2332 // All types smaller than 8 bits require conversion anyway
2333 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2334 (COPY_TO_REGCLASS (Inst
2335 (COPY_TO_REGCLASS VK1:$src1, VK16),
2336 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2337 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2338 (COPY_TO_REGCLASS (Inst
2339 (COPY_TO_REGCLASS VK2:$src1, VK16),
2340 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2341 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2342 (COPY_TO_REGCLASS (Inst
2343 (COPY_TO_REGCLASS VK4:$src1, VK16),
2344 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2347 defm : avx512_binop_pat<and, KANDWrr>;
2348 defm : avx512_binop_pat<andn, KANDNWrr>;
2349 defm : avx512_binop_pat<or, KORWrr>;
2350 defm : avx512_binop_pat<xnor, KXNORWrr>;
2351 defm : avx512_binop_pat<xor, KXORWrr>;
2353 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2354 (KXNORWrr VK16:$src1, VK16:$src2)>;
2355 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2356 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2357 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2358 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2359 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2360 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2362 let Predicates = [NoDQI] in
2363 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2364 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2365 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2367 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2368 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2369 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2371 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2372 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2373 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2375 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2376 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2377 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2380 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2381 RegisterClass KRCSrc, Predicate prd> {
2382 let Predicates = [prd] in {
2383 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2384 (ins KRC:$src1, KRC:$src2),
2385 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2388 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2389 (!cast<Instruction>(NAME##rr)
2390 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2391 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2395 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2396 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2397 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2399 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2400 let Predicates = [HasAVX512] in
2401 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2402 (i16 GR16:$src1), (i16 GR16:$src2)),
2403 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2404 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2405 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2407 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2410 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2411 SDNode OpNode, Predicate prd> {
2412 let Predicates = [prd], Defs = [EFLAGS] in
2413 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2414 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2415 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2418 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2419 Predicate prdW = HasAVX512> {
2420 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2422 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2424 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2426 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2430 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2431 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2434 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2436 let Predicates = [HasAVX512] in
2437 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2438 !strconcat(OpcodeStr,
2439 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2440 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2443 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2445 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2447 let Predicates = [HasDQI] in
2448 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2450 let Predicates = [HasBWI] in {
2451 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2453 let Predicates = [HasDQI] in
2454 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2459 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2460 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2462 // Mask setting all 0s or 1s
2463 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2464 let Predicates = [HasAVX512] in
2465 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2466 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2467 [(set KRC:$dst, (VT Val))]>;
2470 multiclass avx512_mask_setop_w<PatFrag Val> {
2471 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2472 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2473 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2474 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2477 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2478 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2480 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2481 let Predicates = [HasAVX512] in {
2482 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2483 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2484 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2485 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2486 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2487 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2488 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2490 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2491 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2493 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2494 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2496 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2497 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2499 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2500 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2502 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2503 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2505 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2506 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2507 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2508 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2510 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2511 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2513 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2514 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2515 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2516 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2518 def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2519 (v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
2520 def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2521 (v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
2522 def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2523 (v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
2524 def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2525 (v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
2527 def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2528 (v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
2529 def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2530 (v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
2531 def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2532 (v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
2533 def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2534 (v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
2535 def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
2536 (v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
2539 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2540 (v8i1 (COPY_TO_REGCLASS
2541 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2542 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2544 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2545 (v8i1 (COPY_TO_REGCLASS
2546 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2547 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2549 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2550 (v4i1 (COPY_TO_REGCLASS
2551 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2552 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2554 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2555 (v4i1 (COPY_TO_REGCLASS
2556 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2557 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2559 //===----------------------------------------------------------------------===//
2560 // AVX-512 - Aligned and unaligned load and store
2564 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2565 PatFrag ld_frag, PatFrag mload,
2566 bit IsReMaterializable = 1> {
2567 let hasSideEffects = 0 in {
2568 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2569 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2571 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2572 (ins _.KRCWM:$mask, _.RC:$src),
2573 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2574 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2577 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2578 SchedRW = [WriteLoad] in
2579 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2581 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2584 let Constraints = "$src0 = $dst" in {
2585 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2586 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2587 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2588 "${dst} {${mask}}, $src1}"),
2589 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2591 (_.VT _.RC:$src0))))], _.ExeDomain>,
2593 let mayLoad = 1, SchedRW = [WriteLoad] in
2594 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2595 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2596 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2597 "${dst} {${mask}}, $src1}"),
2598 [(set _.RC:$dst, (_.VT
2599 (vselect _.KRCWM:$mask,
2600 (_.VT (bitconvert (ld_frag addr:$src1))),
2601 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2603 let mayLoad = 1, SchedRW = [WriteLoad] in
2604 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2605 (ins _.KRCWM:$mask, _.MemOp:$src),
2606 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2607 "${dst} {${mask}} {z}, $src}",
2608 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2609 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2610 _.ExeDomain>, EVEX, EVEX_KZ;
2612 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2613 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2615 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2616 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2618 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2619 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2620 _.KRCWM:$mask, addr:$ptr)>;
2623 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2624 AVX512VLVectorVTInfo _,
2626 bit IsReMaterializable = 1> {
2627 let Predicates = [prd] in
2628 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2629 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2631 let Predicates = [prd, HasVLX] in {
2632 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2633 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2634 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2635 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2639 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2640 AVX512VLVectorVTInfo _,
2642 bit IsReMaterializable = 1> {
2643 let Predicates = [prd] in
2644 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2645 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2647 let Predicates = [prd, HasVLX] in {
2648 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2649 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2650 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2651 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2655 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2656 PatFrag st_frag, PatFrag mstore> {
2658 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2659 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2660 [], _.ExeDomain>, EVEX;
2661 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2662 (ins _.KRCWM:$mask, _.RC:$src),
2663 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2664 "${dst} {${mask}}, $src}",
2665 [], _.ExeDomain>, EVEX, EVEX_K;
2666 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2667 (ins _.KRCWM:$mask, _.RC:$src),
2668 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2669 "${dst} {${mask}} {z}, $src}",
2670 [], _.ExeDomain>, EVEX, EVEX_KZ;
2672 let mayStore = 1 in {
2673 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2674 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2675 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2676 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2677 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2678 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2679 [], _.ExeDomain>, EVEX, EVEX_K;
2682 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2683 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2684 _.KRCWM:$mask, _.RC:$src)>;
2688 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2689 AVX512VLVectorVTInfo _, Predicate prd> {
2690 let Predicates = [prd] in
2691 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2692 masked_store_unaligned>, EVEX_V512;
2694 let Predicates = [prd, HasVLX] in {
2695 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2696 masked_store_unaligned>, EVEX_V256;
2697 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2698 masked_store_unaligned>, EVEX_V128;
2702 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2703 AVX512VLVectorVTInfo _, Predicate prd> {
2704 let Predicates = [prd] in
2705 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2706 masked_store_aligned512>, EVEX_V512;
2708 let Predicates = [prd, HasVLX] in {
2709 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2710 masked_store_aligned256>, EVEX_V256;
2711 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2712 masked_store_aligned128>, EVEX_V128;
2716 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2718 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2719 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2721 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2723 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2724 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2726 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2727 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2728 PS, EVEX_CD8<32, CD8VF>;
2730 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2731 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2732 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2734 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2735 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2736 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2738 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2739 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2740 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2742 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2743 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2744 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2746 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2747 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2748 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2750 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2751 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2752 (VMOVAPDZrm addr:$ptr)>;
2754 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2755 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2756 (VMOVAPSZrm addr:$ptr)>;
2758 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2760 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2762 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2764 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2767 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2769 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2771 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2773 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2776 let Predicates = [HasAVX512, NoVLX] in {
2777 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2778 (VMOVUPSZmrk addr:$ptr,
2779 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2780 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2782 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2783 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2784 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2786 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2787 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2789 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2792 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2794 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2795 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2797 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2799 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2800 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2802 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2803 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2804 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2806 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2807 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2808 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2810 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2811 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2812 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2814 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2815 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2816 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2818 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2819 (v16i32 immAllZerosV), GR16:$mask)),
2820 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2822 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2823 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2824 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2826 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2828 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2830 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2832 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2835 let AddedComplexity = 20 in {
2836 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2837 (bc_v8i64 (v16i32 immAllZerosV)))),
2838 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2840 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2841 (v8i64 VR512:$src))),
2842 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2845 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2846 (v16i32 immAllZerosV))),
2847 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2849 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2850 (v16i32 VR512:$src))),
2851 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2854 let Predicates = [HasAVX512, NoVLX] in {
2855 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2856 (VMOVDQU32Zmrk addr:$ptr,
2857 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2858 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2860 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2861 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2862 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2865 // Move Int Doubleword to Packed Double Int
2867 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2868 "vmovd\t{$src, $dst|$dst, $src}",
2870 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2872 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2873 "vmovd\t{$src, $dst|$dst, $src}",
2875 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2876 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2877 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2878 "vmovq\t{$src, $dst|$dst, $src}",
2880 (v2i64 (scalar_to_vector GR64:$src)))],
2881 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2882 let isCodeGenOnly = 1 in {
2883 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2884 "vmovq\t{$src, $dst|$dst, $src}",
2885 [(set FR64:$dst, (bitconvert GR64:$src))],
2886 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2887 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2888 "vmovq\t{$src, $dst|$dst, $src}",
2889 [(set GR64:$dst, (bitconvert FR64:$src))],
2890 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2892 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2893 "vmovq\t{$src, $dst|$dst, $src}",
2894 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2895 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2896 EVEX_CD8<64, CD8VT1>;
2898 // Move Int Doubleword to Single Scalar
2900 let isCodeGenOnly = 1 in {
2901 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2902 "vmovd\t{$src, $dst|$dst, $src}",
2903 [(set FR32X:$dst, (bitconvert GR32:$src))],
2904 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2906 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2907 "vmovd\t{$src, $dst|$dst, $src}",
2908 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2909 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2912 // Move doubleword from xmm register to r/m32
2914 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2915 "vmovd\t{$src, $dst|$dst, $src}",
2916 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2917 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2919 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2920 (ins i32mem:$dst, VR128X:$src),
2921 "vmovd\t{$src, $dst|$dst, $src}",
2922 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2923 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2924 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2926 // Move quadword from xmm1 register to r/m64
2928 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2929 "vmovq\t{$src, $dst|$dst, $src}",
2930 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2932 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2933 Requires<[HasAVX512, In64BitMode]>;
2935 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2936 (ins i64mem:$dst, VR128X:$src),
2937 "vmovq\t{$src, $dst|$dst, $src}",
2938 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2939 addr:$dst)], IIC_SSE_MOVDQ>,
2940 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2941 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2943 def VMOV64toPQIZrr_REV : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
2945 "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
2946 EVEX, VEX_W, VEX_LIG;
2948 // Move Scalar Single to Double Int
2950 let isCodeGenOnly = 1 in {
2951 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2953 "vmovd\t{$src, $dst|$dst, $src}",
2954 [(set GR32:$dst, (bitconvert FR32X:$src))],
2955 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2956 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2957 (ins i32mem:$dst, FR32X:$src),
2958 "vmovd\t{$src, $dst|$dst, $src}",
2959 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2960 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2963 // Move Quadword Int to Packed Quadword Int
2965 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2967 "vmovq\t{$src, $dst|$dst, $src}",
2969 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2970 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2972 //===----------------------------------------------------------------------===//
2973 // AVX-512 MOVSS, MOVSD
2974 //===----------------------------------------------------------------------===//
2976 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2977 SDNode OpNode, ValueType vt,
2978 X86MemOperand x86memop, PatFrag mem_pat> {
2979 let hasSideEffects = 0 in {
2980 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2981 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2982 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2983 (scalar_to_vector RC:$src2))))],
2984 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2985 let Constraints = "$src1 = $dst" in
2986 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2987 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2989 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2990 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2991 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2992 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2993 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2995 let mayStore = 1 in {
2996 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2997 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2998 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
3000 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
3001 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
3002 [], IIC_SSE_MOV_S_MR>,
3003 EVEX, VEX_LIG, EVEX_K;
3005 } //hasSideEffects = 0
3008 let ExeDomain = SSEPackedSingle in
3009 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
3010 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
3012 let ExeDomain = SSEPackedDouble in
3013 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
3014 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3016 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
3017 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
3018 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
3020 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
3021 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
3022 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
3024 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
3025 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
3026 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3028 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
3029 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3030 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
3031 XS, EVEX_4V, VEX_LIG;
3033 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
3034 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3035 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
3036 XD, EVEX_4V, VEX_LIG, VEX_W;
3038 let Predicates = [HasAVX512] in {
3039 let AddedComplexity = 15 in {
3040 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3041 // MOVS{S,D} to the lower bits.
3042 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3043 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
3044 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3045 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3046 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3047 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3048 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3049 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
3051 // Move low f32 and clear high bits.
3052 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3053 (SUBREG_TO_REG (i32 0),
3054 (VMOVSSZrr (v4f32 (V_SET0)),
3055 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3056 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3057 (SUBREG_TO_REG (i32 0),
3058 (VMOVSSZrr (v4i32 (V_SET0)),
3059 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3062 let AddedComplexity = 20 in {
3063 // MOVSSrm zeros the high parts of the register; represent this
3064 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3065 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3066 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3067 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3068 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3069 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3070 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3072 // MOVSDrm zeros the high parts of the register; represent this
3073 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3074 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3075 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3076 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3077 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3078 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3079 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3080 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3081 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3082 def : Pat<(v2f64 (X86vzload addr:$src)),
3083 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3085 // Represent the same patterns above but in the form they appear for
3087 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3088 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3089 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3090 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3091 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3092 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3093 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3094 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3095 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3097 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3098 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3099 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3100 FR32X:$src)), sub_xmm)>;
3101 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3102 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3103 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3104 FR64X:$src)), sub_xmm)>;
3105 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3106 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3107 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3109 // Move low f64 and clear high bits.
3110 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3111 (SUBREG_TO_REG (i32 0),
3112 (VMOVSDZrr (v2f64 (V_SET0)),
3113 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3115 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3116 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3117 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3119 // Extract and store.
3120 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3122 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3123 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3125 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3127 // Shuffle with VMOVSS
3128 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3129 (VMOVSSZrr (v4i32 VR128X:$src1),
3130 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3131 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3132 (VMOVSSZrr (v4f32 VR128X:$src1),
3133 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3136 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3137 (SUBREG_TO_REG (i32 0),
3138 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3139 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3141 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3142 (SUBREG_TO_REG (i32 0),
3143 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3144 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3147 // Shuffle with VMOVSD
3148 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3149 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3150 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3151 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3152 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3153 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3154 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3155 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3158 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3159 (SUBREG_TO_REG (i32 0),
3160 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3161 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3163 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3164 (SUBREG_TO_REG (i32 0),
3165 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3166 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3169 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3170 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3171 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3172 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3173 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3174 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3175 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3176 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3179 let AddedComplexity = 15 in
3180 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3182 "vmovq\t{$src, $dst|$dst, $src}",
3183 [(set VR128X:$dst, (v2i64 (X86vzmovl
3184 (v2i64 VR128X:$src))))],
3185 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3187 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3188 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3190 "vmovq\t{$src, $dst|$dst, $src}",
3191 [(set VR128X:$dst, (v2i64 (X86vzmovl
3192 (loadv2i64 addr:$src))))],
3193 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3194 EVEX_CD8<8, CD8VT8>;
3196 let Predicates = [HasAVX512] in {
3197 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3198 let AddedComplexity = 20 in {
3199 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3200 (VMOVDI2PDIZrm addr:$src)>;
3201 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3202 (VMOV64toPQIZrr GR64:$src)>;
3203 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3204 (VMOVDI2PDIZrr GR32:$src)>;
3206 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3207 (VMOVDI2PDIZrm addr:$src)>;
3208 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3209 (VMOVDI2PDIZrm addr:$src)>;
3210 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3211 (VMOVZPQILo2PQIZrm addr:$src)>;
3212 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3213 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3214 def : Pat<(v2i64 (X86vzload addr:$src)),
3215 (VMOVZPQILo2PQIZrm addr:$src)>;
3218 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3219 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3220 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3221 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3222 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3223 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3224 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3227 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3228 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3230 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3231 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3233 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3234 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3236 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3237 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3239 //===----------------------------------------------------------------------===//
3240 // AVX-512 - Non-temporals
3241 //===----------------------------------------------------------------------===//
3242 let SchedRW = [WriteLoad] in {
3243 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3244 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3245 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3246 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3247 EVEX_CD8<64, CD8VF>;
3249 let Predicates = [HasAVX512, HasVLX] in {
3250 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3252 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3253 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3254 EVEX_CD8<64, CD8VF>;
3256 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3258 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3259 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3260 EVEX_CD8<64, CD8VF>;
3264 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3265 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3266 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3267 let SchedRW = [WriteStore], mayStore = 1,
3268 AddedComplexity = 400 in
3269 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3270 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3271 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3274 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3275 string elty, string elsz, string vsz512,
3276 string vsz256, string vsz128, Domain d,
3277 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3278 let Predicates = [prd] in
3279 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3280 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3281 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3284 let Predicates = [prd, HasVLX] in {
3285 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3286 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3287 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3290 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3291 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3292 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3297 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3298 "i", "64", "8", "4", "2", SSEPackedInt,
3299 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3301 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3302 "f", "64", "8", "4", "2", SSEPackedDouble,
3303 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3305 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3306 "f", "32", "16", "8", "4", SSEPackedSingle,
3307 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3309 //===----------------------------------------------------------------------===//
3310 // AVX-512 - Integer arithmetic
3312 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3313 X86VectorVTInfo _, OpndItins itins,
3314 bit IsCommutable = 0> {
3315 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3316 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3317 "$src2, $src1", "$src1, $src2",
3318 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3319 itins.rr, IsCommutable>,
3320 AVX512BIBase, EVEX_4V;
3323 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3324 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3325 "$src2, $src1", "$src1, $src2",
3326 (_.VT (OpNode _.RC:$src1,
3327 (bitconvert (_.LdFrag addr:$src2)))),
3329 AVX512BIBase, EVEX_4V;
3332 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3333 X86VectorVTInfo _, OpndItins itins,
3334 bit IsCommutable = 0> :
3335 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3337 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3338 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3339 "${src2}"##_.BroadcastStr##", $src1",
3340 "$src1, ${src2}"##_.BroadcastStr,
3341 (_.VT (OpNode _.RC:$src1,
3343 (_.ScalarLdFrag addr:$src2)))),
3345 AVX512BIBase, EVEX_4V, EVEX_B;
3348 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3349 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3350 Predicate prd, bit IsCommutable = 0> {
3351 let Predicates = [prd] in
3352 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3353 IsCommutable>, EVEX_V512;
3355 let Predicates = [prd, HasVLX] in {
3356 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3357 IsCommutable>, EVEX_V256;
3358 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3359 IsCommutable>, EVEX_V128;
3363 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3364 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3365 Predicate prd, bit IsCommutable = 0> {
3366 let Predicates = [prd] in
3367 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3368 IsCommutable>, EVEX_V512;
3370 let Predicates = [prd, HasVLX] in {
3371 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3372 IsCommutable>, EVEX_V256;
3373 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3374 IsCommutable>, EVEX_V128;
3378 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3379 OpndItins itins, Predicate prd,
3380 bit IsCommutable = 0> {
3381 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3382 itins, prd, IsCommutable>,
3383 VEX_W, EVEX_CD8<64, CD8VF>;
3386 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3387 OpndItins itins, Predicate prd,
3388 bit IsCommutable = 0> {
3389 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3390 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3393 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3394 OpndItins itins, Predicate prd,
3395 bit IsCommutable = 0> {
3396 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3397 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3400 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3401 OpndItins itins, Predicate prd,
3402 bit IsCommutable = 0> {
3403 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3404 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3407 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3408 SDNode OpNode, OpndItins itins, Predicate prd,
3409 bit IsCommutable = 0> {
3410 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3413 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3417 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3418 SDNode OpNode, OpndItins itins, Predicate prd,
3419 bit IsCommutable = 0> {
3420 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3423 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3427 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3428 bits<8> opc_d, bits<8> opc_q,
3429 string OpcodeStr, SDNode OpNode,
3430 OpndItins itins, bit IsCommutable = 0> {
3431 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3432 itins, HasAVX512, IsCommutable>,
3433 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3434 itins, HasBWI, IsCommutable>;
3437 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3438 SDNode OpNode,X86VectorVTInfo _Src,
3439 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3440 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3441 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3442 "$src2, $src1","$src1, $src2",
3444 (_Src.VT _Src.RC:$src1),
3445 (_Src.VT _Src.RC:$src2))),
3446 itins.rr, IsCommutable>,
3447 AVX512BIBase, EVEX_4V;
3448 let mayLoad = 1 in {
3449 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3450 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3451 "$src2, $src1", "$src1, $src2",
3452 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3453 (bitconvert (_Src.LdFrag addr:$src2)))),
3455 AVX512BIBase, EVEX_4V;
3457 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3458 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3460 "${src2}"##_Dst.BroadcastStr##", $src1",
3461 "$src1, ${src2}"##_Dst.BroadcastStr,
3462 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3463 (_Dst.VT (X86VBroadcast
3464 (_Dst.ScalarLdFrag addr:$src2)))))),
3466 AVX512BIBase, EVEX_4V, EVEX_B;
3470 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3471 SSE_INTALU_ITINS_P, 1>;
3472 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3473 SSE_INTALU_ITINS_P, 0>;
3474 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3475 SSE_INTALU_ITINS_P, HasBWI, 1>;
3476 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3477 SSE_INTALU_ITINS_P, HasBWI, 0>;
3478 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3479 SSE_INTALU_ITINS_P, HasBWI, 1>;
3480 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3481 SSE_INTALU_ITINS_P, HasBWI, 0>;
3482 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3483 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3484 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3485 SSE_INTALU_ITINS_P, HasBWI, 1>;
3486 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3487 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3488 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3490 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3492 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3494 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3495 SSE_INTALU_ITINS_P, HasBWI, 1>;
3497 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3498 SDNode OpNode, bit IsCommutable = 0> {
3500 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3501 v16i32_info, v8i64_info, IsCommutable>,
3502 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3503 let Predicates = [HasVLX] in {
3504 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3505 v8i32x_info, v4i64x_info, IsCommutable>,
3506 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3507 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3508 v4i32x_info, v2i64x_info, IsCommutable>,
3509 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3513 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3515 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3518 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3519 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3520 let mayLoad = 1 in {
3521 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3522 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3524 "${src2}"##_Src.BroadcastStr##", $src1",
3525 "$src1, ${src2}"##_Src.BroadcastStr,
3526 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3527 (_Src.VT (X86VBroadcast
3528 (_Src.ScalarLdFrag addr:$src2))))))>,
3529 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3533 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3534 SDNode OpNode,X86VectorVTInfo _Src,
3535 X86VectorVTInfo _Dst> {
3536 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3537 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3538 "$src2, $src1","$src1, $src2",
3540 (_Src.VT _Src.RC:$src1),
3541 (_Src.VT _Src.RC:$src2)))>,
3542 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3543 let mayLoad = 1 in {
3544 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3545 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3546 "$src2, $src1", "$src1, $src2",
3547 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3548 (bitconvert (_Src.LdFrag addr:$src2))))>,
3549 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3553 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3555 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3557 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3558 v32i16_info>, EVEX_V512;
3559 let Predicates = [HasVLX] in {
3560 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3562 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3563 v16i16x_info>, EVEX_V256;
3564 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3566 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3567 v8i16x_info>, EVEX_V128;
3570 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3572 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3573 v64i8_info>, EVEX_V512;
3574 let Predicates = [HasVLX] in {
3575 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3576 v32i8x_info>, EVEX_V256;
3577 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3578 v16i8x_info>, EVEX_V128;
3582 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3583 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3584 AVX512VLVectorVTInfo _Dst> {
3585 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3586 _Dst.info512>, EVEX_V512;
3587 let Predicates = [HasVLX] in {
3588 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3589 _Dst.info256>, EVEX_V256;
3590 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3591 _Dst.info128>, EVEX_V128;
3595 let Predicates = [HasBWI] in {
3596 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3597 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3598 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3599 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3601 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3602 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3603 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3604 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3607 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3608 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3609 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3610 SSE_INTALU_ITINS_P, HasBWI, 1>;
3611 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3612 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3614 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3615 SSE_INTALU_ITINS_P, HasBWI, 1>;
3616 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3617 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3618 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3619 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3621 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3622 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3623 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3624 SSE_INTALU_ITINS_P, HasBWI, 1>;
3625 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3626 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3628 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3629 SSE_INTALU_ITINS_P, HasBWI, 1>;
3630 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3631 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3632 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3633 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3634 //===----------------------------------------------------------------------===//
3635 // AVX-512 Logical Instructions
3636 //===----------------------------------------------------------------------===//
3638 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3639 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3640 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3641 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3642 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3643 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3644 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3645 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3647 //===----------------------------------------------------------------------===//
3648 // AVX-512 FP arithmetic
3649 //===----------------------------------------------------------------------===//
3650 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3651 SDNode OpNode, SDNode VecNode, OpndItins itins,
3654 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3655 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3656 "$src2, $src1", "$src1, $src2",
3657 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3658 (i32 FROUND_CURRENT)),
3659 itins.rr, IsCommutable>;
3661 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3662 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3663 "$src2, $src1", "$src1, $src2",
3664 (VecNode (_.VT _.RC:$src1),
3665 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3666 (i32 FROUND_CURRENT)),
3667 itins.rm, IsCommutable>;
3668 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3669 Predicates = [HasAVX512] in {
3670 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3671 (ins _.FRC:$src1, _.FRC:$src2),
3672 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3673 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3675 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3676 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3677 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3678 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3679 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3683 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3684 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3686 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3687 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3688 "$rc, $src2, $src1", "$src1, $src2, $rc",
3689 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3690 (i32 imm:$rc)), itins.rr, IsCommutable>,
3693 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3694 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3696 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3697 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3698 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3699 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3700 (i32 FROUND_NO_EXC))>, EVEX_B;
3703 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3705 SizeItins itins, bit IsCommutable> {
3706 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3707 itins.s, IsCommutable>,
3708 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3709 itins.s, IsCommutable>,
3710 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3711 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3712 itins.d, IsCommutable>,
3713 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3714 itins.d, IsCommutable>,
3715 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3718 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3720 SizeItins itins, bit IsCommutable> {
3721 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3722 itins.s, IsCommutable>,
3723 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3724 itins.s, IsCommutable>,
3725 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3726 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3727 itins.d, IsCommutable>,
3728 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3729 itins.d, IsCommutable>,
3730 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3732 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3733 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3734 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3735 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3736 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3737 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3739 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3740 X86VectorVTInfo _, bit IsCommutable> {
3741 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3742 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3743 "$src2, $src1", "$src1, $src2",
3744 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3745 let mayLoad = 1 in {
3746 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3747 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3748 "$src2, $src1", "$src1, $src2",
3749 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3750 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3751 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3752 "${src2}"##_.BroadcastStr##", $src1",
3753 "$src1, ${src2}"##_.BroadcastStr,
3754 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3755 (_.ScalarLdFrag addr:$src2))))>,
3760 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3761 X86VectorVTInfo _> {
3762 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3763 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3764 "$rc, $src2, $src1", "$src1, $src2, $rc",
3765 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3766 EVEX_4V, EVEX_B, EVEX_RC;
3770 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3771 X86VectorVTInfo _> {
3772 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3773 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3774 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3775 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3779 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3780 bit IsCommutable = 0> {
3781 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3782 IsCommutable>, EVEX_V512, PS,
3783 EVEX_CD8<32, CD8VF>;
3784 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3785 IsCommutable>, EVEX_V512, PD, VEX_W,
3786 EVEX_CD8<64, CD8VF>;
3788 // Define only if AVX512VL feature is present.
3789 let Predicates = [HasVLX] in {
3790 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3791 IsCommutable>, EVEX_V128, PS,
3792 EVEX_CD8<32, CD8VF>;
3793 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3794 IsCommutable>, EVEX_V256, PS,
3795 EVEX_CD8<32, CD8VF>;
3796 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3797 IsCommutable>, EVEX_V128, PD, VEX_W,
3798 EVEX_CD8<64, CD8VF>;
3799 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3800 IsCommutable>, EVEX_V256, PD, VEX_W,
3801 EVEX_CD8<64, CD8VF>;
3805 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3806 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3807 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3808 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3809 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3812 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3813 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3814 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3815 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3816 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3819 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3820 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3821 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3822 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3823 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3824 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3825 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3826 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3827 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3828 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3829 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3830 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3831 let Predicates = [HasDQI] in {
3832 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3833 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3834 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3835 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3838 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3839 X86VectorVTInfo _> {
3840 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3841 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3842 "$src2, $src1", "$src1, $src2",
3843 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3844 let mayLoad = 1 in {
3845 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3846 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3847 "$src2, $src1", "$src1, $src2",
3848 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3849 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3850 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3851 "${src2}"##_.BroadcastStr##", $src1",
3852 "$src1, ${src2}"##_.BroadcastStr,
3853 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3854 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3859 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3860 X86VectorVTInfo _> {
3861 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3862 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3863 "$src2, $src1", "$src1, $src2",
3864 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3865 let mayLoad = 1 in {
3866 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3867 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3868 "$src2, $src1", "$src1, $src2",
3869 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3873 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3874 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3875 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3876 EVEX_V512, EVEX_CD8<32, CD8VF>;
3877 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3878 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3879 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3880 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3881 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3882 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3883 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3884 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3885 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3887 // Define only if AVX512VL feature is present.
3888 let Predicates = [HasVLX] in {
3889 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3890 EVEX_V128, EVEX_CD8<32, CD8VF>;
3891 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3892 EVEX_V256, EVEX_CD8<32, CD8VF>;
3893 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3894 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3895 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3896 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3899 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3901 //===----------------------------------------------------------------------===//
3902 // AVX-512 VPTESTM instructions
3903 //===----------------------------------------------------------------------===//
3905 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3906 X86VectorVTInfo _> {
3907 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3908 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3909 "$src2, $src1", "$src1, $src2",
3910 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3913 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3914 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3915 "$src2, $src1", "$src1, $src2",
3916 (OpNode (_.VT _.RC:$src1),
3917 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3919 EVEX_CD8<_.EltSize, CD8VF>;
3922 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3923 X86VectorVTInfo _> {
3925 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3926 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3927 "${src2}"##_.BroadcastStr##", $src1",
3928 "$src1, ${src2}"##_.BroadcastStr,
3929 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3930 (_.ScalarLdFrag addr:$src2))))>,
3931 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3933 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3934 AVX512VLVectorVTInfo _> {
3935 let Predicates = [HasAVX512] in
3936 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3937 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3939 let Predicates = [HasAVX512, HasVLX] in {
3940 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3941 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3942 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3943 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3947 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3948 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3950 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3951 avx512vl_i64_info>, VEX_W;
3954 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3956 let Predicates = [HasBWI] in {
3957 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3959 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3962 let Predicates = [HasVLX, HasBWI] in {
3964 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3966 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3968 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3970 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3975 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3977 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3978 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3980 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3981 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3983 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3984 (v16i32 VR512:$src2), (i16 -1))),
3985 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3987 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3988 (v8i64 VR512:$src2), (i8 -1))),
3989 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3991 //===----------------------------------------------------------------------===//
3992 // AVX-512 Shift instructions
3993 //===----------------------------------------------------------------------===//
3994 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3995 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3996 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3997 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3998 "$src2, $src1", "$src1, $src2",
3999 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
4000 SSE_INTSHIFT_ITINS_P.rr>;
4002 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
4003 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
4004 "$src2, $src1", "$src1, $src2",
4005 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
4007 SSE_INTSHIFT_ITINS_P.rm>;
4010 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
4011 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
4013 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
4014 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
4015 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
4016 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
4017 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
4020 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4021 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
4022 // src2 is always 128-bit
4023 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4024 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
4025 "$src2, $src1", "$src1, $src2",
4026 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
4027 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
4028 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4029 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
4030 "$src2, $src1", "$src1, $src2",
4031 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4032 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4036 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4037 ValueType SrcVT, PatFrag bc_frag,
4038 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4039 let Predicates = [prd] in
4040 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4041 VTInfo.info512>, EVEX_V512,
4042 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4043 let Predicates = [prd, HasVLX] in {
4044 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4045 VTInfo.info256>, EVEX_V256,
4046 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4047 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4048 VTInfo.info128>, EVEX_V128,
4049 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4053 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4054 string OpcodeStr, SDNode OpNode> {
4055 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4056 avx512vl_i32_info, HasAVX512>;
4057 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4058 avx512vl_i64_info, HasAVX512>, VEX_W;
4059 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4060 avx512vl_i16_info, HasBWI>;
4063 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4064 string OpcodeStr, SDNode OpNode,
4065 AVX512VLVectorVTInfo VTInfo> {
4066 let Predicates = [HasAVX512] in
4067 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4069 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4070 VTInfo.info512>, EVEX_V512;
4071 let Predicates = [HasAVX512, HasVLX] in {
4072 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4074 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4075 VTInfo.info256>, EVEX_V256;
4076 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4078 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4079 VTInfo.info128>, EVEX_V128;
4083 multiclass avx512_shift_rmi_w<bits<8> opcw,
4084 Format ImmFormR, Format ImmFormM,
4085 string OpcodeStr, SDNode OpNode> {
4086 let Predicates = [HasBWI] in
4087 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4088 v32i16_info>, EVEX_V512;
4089 let Predicates = [HasVLX, HasBWI] in {
4090 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4091 v16i16x_info>, EVEX_V256;
4092 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4093 v8i16x_info>, EVEX_V128;
4097 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4098 Format ImmFormR, Format ImmFormM,
4099 string OpcodeStr, SDNode OpNode> {
4100 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4101 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4102 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4103 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4106 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4107 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4109 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4110 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4112 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4113 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4115 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4116 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4118 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4119 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4120 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4122 //===-------------------------------------------------------------------===//
4123 // Variable Bit Shifts
4124 //===-------------------------------------------------------------------===//
4125 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4126 X86VectorVTInfo _> {
4127 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4128 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4129 "$src2, $src1", "$src1, $src2",
4130 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4131 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4133 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4134 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4135 "$src2, $src1", "$src1, $src2",
4136 (_.VT (OpNode _.RC:$src1,
4137 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4138 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4139 EVEX_CD8<_.EltSize, CD8VF>;
4142 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4143 X86VectorVTInfo _> {
4145 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4146 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4147 "${src2}"##_.BroadcastStr##", $src1",
4148 "$src1, ${src2}"##_.BroadcastStr,
4149 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4150 (_.ScalarLdFrag addr:$src2))))),
4151 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4152 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4154 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4155 AVX512VLVectorVTInfo _> {
4156 let Predicates = [HasAVX512] in
4157 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4158 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4160 let Predicates = [HasAVX512, HasVLX] in {
4161 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4162 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4163 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4164 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4168 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4170 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4172 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4173 avx512vl_i64_info>, VEX_W;
4176 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4178 let Predicates = [HasBWI] in
4179 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4181 let Predicates = [HasVLX, HasBWI] in {
4183 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4185 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4190 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4191 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4192 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4193 avx512_var_shift_w<0x11, "vpsravw", sra>;
4194 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4195 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4196 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4197 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4199 //===-------------------------------------------------------------------===//
4200 // 1-src variable permutation VPERMW/D/Q
4201 //===-------------------------------------------------------------------===//
4202 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4203 AVX512VLVectorVTInfo _> {
4204 let Predicates = [HasAVX512] in
4205 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4206 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4208 let Predicates = [HasAVX512, HasVLX] in
4209 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4210 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4213 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4214 string OpcodeStr, SDNode OpNode,
4215 AVX512VLVectorVTInfo VTInfo> {
4216 let Predicates = [HasAVX512] in
4217 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4219 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4220 VTInfo.info512>, EVEX_V512;
4221 let Predicates = [HasAVX512, HasVLX] in
4222 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4224 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4225 VTInfo.info256>, EVEX_V256;
4229 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4231 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4233 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4234 avx512vl_i64_info>, VEX_W;
4235 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4237 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4238 avx512vl_f64_info>, VEX_W;
4240 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4241 X86VPermi, avx512vl_i64_info>,
4242 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4243 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4244 X86VPermi, avx512vl_f64_info>,
4245 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4246 //===----------------------------------------------------------------------===//
4247 // AVX-512 - VPERMIL
4248 //===----------------------------------------------------------------------===//
4250 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4251 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4252 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4253 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4254 "$src2, $src1", "$src1, $src2",
4255 (_.VT (OpNode _.RC:$src1,
4256 (Ctrl.VT Ctrl.RC:$src2)))>,
4258 let mayLoad = 1 in {
4259 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4260 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4261 "$src2, $src1", "$src1, $src2",
4264 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4265 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4266 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4267 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4268 "${src2}"##_.BroadcastStr##", $src1",
4269 "$src1, ${src2}"##_.BroadcastStr,
4272 (Ctrl.VT (X86VBroadcast
4273 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4274 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4278 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4279 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4280 let Predicates = [HasAVX512] in {
4281 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4282 Ctrl.info512>, EVEX_V512;
4284 let Predicates = [HasAVX512, HasVLX] in {
4285 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4286 Ctrl.info128>, EVEX_V128;
4287 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4288 Ctrl.info256>, EVEX_V256;
4292 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4293 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4295 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4296 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4298 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4300 let isCodeGenOnly = 1 in {
4301 // lowering implementation with the alternative types
4302 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4303 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4304 OpcodeStr, X86VPermilpi, Ctrl>,
4305 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4309 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4311 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4312 avx512vl_i64_info>, VEX_W;
4313 //===----------------------------------------------------------------------===//
4314 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4315 //===----------------------------------------------------------------------===//
4317 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4318 X86PShufd, avx512vl_i32_info>,
4319 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4320 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4321 X86PShufhw>, EVEX, AVX512XSIi8Base;
4322 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4323 X86PShuflw>, EVEX, AVX512XDIi8Base;
4325 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4326 let Predicates = [HasBWI] in
4327 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4329 let Predicates = [HasVLX, HasBWI] in {
4330 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4331 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4335 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4337 //===----------------------------------------------------------------------===//
4338 // Move Low to High and High to Low packed FP Instructions
4339 //===----------------------------------------------------------------------===//
4340 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4341 (ins VR128X:$src1, VR128X:$src2),
4342 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4343 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4344 IIC_SSE_MOV_LH>, EVEX_4V;
4345 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4346 (ins VR128X:$src1, VR128X:$src2),
4347 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4348 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4349 IIC_SSE_MOV_LH>, EVEX_4V;
4351 let Predicates = [HasAVX512] in {
4353 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4354 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4355 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4356 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4359 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4360 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4363 //===----------------------------------------------------------------------===//
4364 // VMOVHPS/PD VMOVLPS Instructions
4365 // All patterns was taken from SSS implementation.
4366 //===----------------------------------------------------------------------===//
4367 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4368 X86VectorVTInfo _> {
4370 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4371 (ins _.RC:$src1, f64mem:$src2),
4372 !strconcat(OpcodeStr,
4373 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4377 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4378 IIC_SSE_MOV_LH>, EVEX_4V;
4381 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4382 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4383 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4384 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4385 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4386 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4387 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4388 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4390 let Predicates = [HasAVX512] in {
4392 def : Pat<(X86Movlhps VR128X:$src1,
4393 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4394 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4395 def : Pat<(X86Movlhps VR128X:$src1,
4396 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4397 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4399 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4400 (scalar_to_vector (loadf64 addr:$src2)))),
4401 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4402 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4403 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4404 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4406 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4407 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4408 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4409 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4411 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4412 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4413 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4414 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4415 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4416 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4417 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4420 let mayStore = 1 in {
4421 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4422 (ins f64mem:$dst, VR128X:$src),
4423 "vmovhps\t{$src, $dst|$dst, $src}",
4424 [(store (f64 (vector_extract
4425 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4426 (bc_v2f64 (v4f32 VR128X:$src))),
4427 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4428 EVEX, EVEX_CD8<32, CD8VT2>;
4429 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4430 (ins f64mem:$dst, VR128X:$src),
4431 "vmovhpd\t{$src, $dst|$dst, $src}",
4432 [(store (f64 (vector_extract
4433 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4434 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4435 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4436 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4437 (ins f64mem:$dst, VR128X:$src),
4438 "vmovlps\t{$src, $dst|$dst, $src}",
4439 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4440 (iPTR 0))), addr:$dst)],
4442 EVEX, EVEX_CD8<32, CD8VT2>;
4443 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4444 (ins f64mem:$dst, VR128X:$src),
4445 "vmovlpd\t{$src, $dst|$dst, $src}",
4446 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4447 (iPTR 0))), addr:$dst)],
4449 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4451 let Predicates = [HasAVX512] in {
4453 def : Pat<(store (f64 (vector_extract
4454 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4455 (iPTR 0))), addr:$dst),
4456 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4458 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4460 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4461 def : Pat<(store (v4i32 (X86Movlps
4462 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4463 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4465 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4467 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4468 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4470 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4472 //===----------------------------------------------------------------------===//
4473 // FMA - Fused Multiply Operations
4476 let Constraints = "$src1 = $dst" in {
4477 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4478 X86VectorVTInfo _> {
4479 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4480 (ins _.RC:$src2, _.RC:$src3),
4481 OpcodeStr, "$src3, $src2", "$src2, $src3",
4482 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4485 let mayLoad = 1 in {
4486 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4487 (ins _.RC:$src2, _.MemOp:$src3),
4488 OpcodeStr, "$src3, $src2", "$src2, $src3",
4489 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4492 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4493 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4494 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4495 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4497 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4498 AVX512FMA3Base, EVEX_B;
4502 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4503 X86VectorVTInfo _> {
4504 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4505 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4506 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4507 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4508 AVX512FMA3Base, EVEX_B, EVEX_RC;
4510 } // Constraints = "$src1 = $dst"
4512 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4513 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4514 let Predicates = [HasAVX512] in {
4515 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4516 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4517 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4519 let Predicates = [HasVLX, HasAVX512] in {
4520 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4521 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4522 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4523 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4527 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4528 SDNode OpNodeRnd > {
4529 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4531 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4532 avx512vl_f64_info>, VEX_W;
4535 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4536 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4537 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4538 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4539 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4540 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4543 let Constraints = "$src1 = $dst" in {
4544 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4545 X86VectorVTInfo _> {
4546 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4547 (ins _.RC:$src2, _.RC:$src3),
4548 OpcodeStr, "$src3, $src2", "$src2, $src3",
4549 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4552 let mayLoad = 1 in {
4553 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4554 (ins _.RC:$src2, _.MemOp:$src3),
4555 OpcodeStr, "$src3, $src2", "$src2, $src3",
4556 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4559 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4560 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4561 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4562 "$src2, ${src3}"##_.BroadcastStr,
4563 (_.VT (OpNode _.RC:$src2,
4564 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4565 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4569 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4570 X86VectorVTInfo _> {
4571 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4572 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4573 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4574 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4575 AVX512FMA3Base, EVEX_B, EVEX_RC;
4577 } // Constraints = "$src1 = $dst"
4579 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4580 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4581 let Predicates = [HasAVX512] in {
4582 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4583 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4584 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4586 let Predicates = [HasVLX, HasAVX512] in {
4587 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4588 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4589 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4590 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4594 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4595 SDNode OpNodeRnd > {
4596 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4598 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4599 avx512vl_f64_info>, VEX_W;
4602 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4603 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4604 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4605 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4606 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4607 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4609 let Constraints = "$src1 = $dst" in {
4610 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4611 X86VectorVTInfo _> {
4612 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4613 (ins _.RC:$src3, _.RC:$src2),
4614 OpcodeStr, "$src2, $src3", "$src3, $src2",
4615 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4618 let mayLoad = 1 in {
4619 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4620 (ins _.RC:$src3, _.MemOp:$src2),
4621 OpcodeStr, "$src2, $src3", "$src3, $src2",
4622 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4625 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4626 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4627 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4628 "$src3, ${src2}"##_.BroadcastStr,
4629 (_.VT (OpNode _.RC:$src1,
4630 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4631 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4635 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4636 X86VectorVTInfo _> {
4637 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4638 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4639 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4640 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4641 AVX512FMA3Base, EVEX_B, EVEX_RC;
4643 } // Constraints = "$src1 = $dst"
4645 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4646 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4647 let Predicates = [HasAVX512] in {
4648 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4649 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4650 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4652 let Predicates = [HasVLX, HasAVX512] in {
4653 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4654 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4655 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4656 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4660 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4661 SDNode OpNodeRnd > {
4662 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4664 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4665 avx512vl_f64_info>, VEX_W;
4668 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4669 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4670 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4671 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4672 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4673 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4676 let Constraints = "$src1 = $dst" in {
4677 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4678 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4679 dag RHS_r, dag RHS_m > {
4680 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4681 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4682 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4685 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4686 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4687 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4689 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4690 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4691 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4692 AVX512FMA3Base, EVEX_B, EVEX_RC;
4694 let isCodeGenOnly = 1 in {
4695 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4696 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4697 !strconcat(OpcodeStr,
4698 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4701 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4702 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4703 !strconcat(OpcodeStr,
4704 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4706 }// isCodeGenOnly = 1
4708 }// Constraints = "$src1 = $dst"
4710 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4711 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4714 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4715 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4716 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4717 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4718 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4720 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4722 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4723 (_.ScalarLdFrag addr:$src3))))>;
4725 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4726 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4727 (_.VT (OpNode _.RC:$src2,
4728 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4730 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4732 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4734 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4735 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4737 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4738 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4739 (_.VT (OpNode _.RC:$src1,
4740 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4742 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4744 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4746 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4747 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4750 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4751 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4752 let Predicates = [HasAVX512] in {
4753 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4754 OpNodeRnd, f32x_info, "SS">,
4755 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4756 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4757 OpNodeRnd, f64x_info, "SD">,
4758 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4762 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4763 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4764 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4765 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4767 //===----------------------------------------------------------------------===//
4768 // AVX-512 Scalar convert from sign integer to float/double
4769 //===----------------------------------------------------------------------===//
4771 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4772 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4773 PatFrag ld_frag, string asm> {
4774 let hasSideEffects = 0 in {
4775 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4776 (ins DstVT.FRC:$src1, SrcRC:$src),
4777 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4780 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4781 (ins DstVT.FRC:$src1, x86memop:$src),
4782 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4784 } // hasSideEffects = 0
4785 let isCodeGenOnly = 1 in {
4786 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4787 (ins DstVT.RC:$src1, SrcRC:$src2),
4788 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4789 [(set DstVT.RC:$dst,
4790 (OpNode (DstVT.VT DstVT.RC:$src1),
4792 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4794 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4795 (ins DstVT.RC:$src1, x86memop:$src2),
4796 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4797 [(set DstVT.RC:$dst,
4798 (OpNode (DstVT.VT DstVT.RC:$src1),
4799 (ld_frag addr:$src2),
4800 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4801 }//isCodeGenOnly = 1
4804 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4805 X86VectorVTInfo DstVT, string asm> {
4806 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4807 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4809 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4810 [(set DstVT.RC:$dst,
4811 (OpNode (DstVT.VT DstVT.RC:$src1),
4813 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4816 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4817 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4818 PatFrag ld_frag, string asm> {
4819 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4820 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4824 let Predicates = [HasAVX512] in {
4825 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4826 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4827 XS, EVEX_CD8<32, CD8VT1>;
4828 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4829 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4830 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4831 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4832 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4833 XD, EVEX_CD8<32, CD8VT1>;
4834 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4835 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4836 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4838 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4839 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4840 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4841 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4842 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4843 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4844 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4845 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4847 def : Pat<(f32 (sint_to_fp GR32:$src)),
4848 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4849 def : Pat<(f32 (sint_to_fp GR64:$src)),
4850 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4851 def : Pat<(f64 (sint_to_fp GR32:$src)),
4852 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4853 def : Pat<(f64 (sint_to_fp GR64:$src)),
4854 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4856 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4857 v4f32x_info, i32mem, loadi32,
4858 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4859 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4860 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4861 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4862 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4863 i32mem, loadi32, "cvtusi2sd{l}">,
4864 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4865 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4866 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4867 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4869 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4870 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4871 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4872 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4873 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4874 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4875 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4876 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4878 def : Pat<(f32 (uint_to_fp GR32:$src)),
4879 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4880 def : Pat<(f32 (uint_to_fp GR64:$src)),
4881 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4882 def : Pat<(f64 (uint_to_fp GR32:$src)),
4883 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4884 def : Pat<(f64 (uint_to_fp GR64:$src)),
4885 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4888 //===----------------------------------------------------------------------===//
4889 // AVX-512 Scalar convert from float/double to integer
4890 //===----------------------------------------------------------------------===//
4891 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4892 RegisterClass DstRC, Intrinsic Int,
4893 Operand memop, ComplexPattern mem_cpat, string asm> {
4894 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4895 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4896 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4897 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4898 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4899 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4900 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4902 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4903 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4904 } // hasSideEffects = 0, Predicates = [HasAVX512]
4907 // Convert float/double to signed/unsigned int 32/64
4908 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4909 ssmem, sse_load_f32, "cvtss2si">,
4910 XS, EVEX_CD8<32, CD8VT1>;
4911 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4912 int_x86_sse_cvtss2si64,
4913 ssmem, sse_load_f32, "cvtss2si">,
4914 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4915 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4916 int_x86_avx512_cvtss2usi,
4917 ssmem, sse_load_f32, "cvtss2usi">,
4918 XS, EVEX_CD8<32, CD8VT1>;
4919 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4920 int_x86_avx512_cvtss2usi64, ssmem,
4921 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4922 EVEX_CD8<32, CD8VT1>;
4923 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4924 sdmem, sse_load_f64, "cvtsd2si">,
4925 XD, EVEX_CD8<64, CD8VT1>;
4926 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4927 int_x86_sse2_cvtsd2si64,
4928 sdmem, sse_load_f64, "cvtsd2si">,
4929 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4930 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4931 int_x86_avx512_cvtsd2usi,
4932 sdmem, sse_load_f64, "cvtsd2usi">,
4933 XD, EVEX_CD8<64, CD8VT1>;
4934 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4935 int_x86_avx512_cvtsd2usi64, sdmem,
4936 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4937 EVEX_CD8<64, CD8VT1>;
4939 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4940 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4941 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4942 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4943 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4944 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4945 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4946 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4947 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4948 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4949 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4950 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4951 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4953 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4954 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4955 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4956 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4958 // Convert float/double to signed/unsigned int 32/64 with truncation
4959 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4960 X86VectorVTInfo _DstRC, SDNode OpNode,
4962 let Predicates = [HasAVX512] in {
4963 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4964 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4965 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4966 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4967 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4969 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4970 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4971 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4974 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4975 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4976 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4977 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4978 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4979 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4980 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4981 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4982 (i32 FROUND_NO_EXC)))]>,
4983 EVEX,VEX_LIG , EVEX_B;
4985 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4986 (ins _SrcRC.MemOp:$src),
4987 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4990 } // isCodeGenOnly = 1, hasSideEffects = 0
4995 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4996 fp_to_sint,X86cvttss2IntRnd>,
4997 XS, EVEX_CD8<32, CD8VT1>;
4998 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4999 fp_to_sint,X86cvttss2IntRnd>,
5000 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
5001 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
5002 fp_to_sint,X86cvttsd2IntRnd>,
5003 XD, EVEX_CD8<64, CD8VT1>;
5004 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
5005 fp_to_sint,X86cvttsd2IntRnd>,
5006 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
5008 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
5009 fp_to_uint,X86cvttss2UIntRnd>,
5010 XS, EVEX_CD8<32, CD8VT1>;
5011 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
5012 fp_to_uint,X86cvttss2UIntRnd>,
5013 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
5014 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
5015 fp_to_uint,X86cvttsd2UIntRnd>,
5016 XD, EVEX_CD8<64, CD8VT1>;
5017 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
5018 fp_to_uint,X86cvttsd2UIntRnd>,
5019 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5020 let Predicates = [HasAVX512] in {
5021 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
5022 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5023 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
5024 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5025 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
5026 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5027 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
5028 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5031 //===----------------------------------------------------------------------===//
5032 // AVX-512 Convert form float to double and back
5033 //===----------------------------------------------------------------------===//
5034 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5035 X86VectorVTInfo _Src, SDNode OpNode> {
5036 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5037 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5038 "$src2, $src1", "$src1, $src2",
5039 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5040 (_Src.VT _Src.RC:$src2)))>,
5041 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
5042 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5043 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
5044 "$src2, $src1", "$src1, $src2",
5045 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5046 (_Src.VT (scalar_to_vector
5047 (_Src.ScalarLdFrag addr:$src2)))))>,
5048 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
5051 // Scalar Coversion with SAE - suppress all exceptions
5052 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5053 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5054 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5055 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5056 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5057 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5058 (_Src.VT _Src.RC:$src2),
5059 (i32 FROUND_NO_EXC)))>,
5060 EVEX_4V, VEX_LIG, EVEX_B;
5063 // Scalar Conversion with rounding control (RC)
5064 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5065 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5066 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5067 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
5068 "$rc, $src2, $src1", "$src1, $src2, $rc",
5069 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5070 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
5071 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
5074 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
5075 SDNode OpNodeRnd, X86VectorVTInfo _src,
5076 X86VectorVTInfo _dst> {
5077 let Predicates = [HasAVX512] in {
5078 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5079 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
5080 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5085 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5086 SDNode OpNodeRnd, X86VectorVTInfo _src,
5087 X86VectorVTInfo _dst> {
5088 let Predicates = [HasAVX512] in {
5089 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5090 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5091 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5094 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5095 X86froundRnd, f64x_info, f32x_info>;
5096 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5097 X86fpextRnd,f32x_info, f64x_info >;
5099 def : Pat<(f64 (fextend FR32X:$src)),
5100 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5101 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5102 Requires<[HasAVX512]>;
5103 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5104 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5105 Requires<[HasAVX512]>;
5107 def : Pat<(f64 (extloadf32 addr:$src)),
5108 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5109 Requires<[HasAVX512, OptForSize]>;
5111 def : Pat<(f64 (extloadf32 addr:$src)),
5112 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5113 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5114 Requires<[HasAVX512, OptForSpeed]>;
5116 def : Pat<(f32 (fround FR64X:$src)),
5117 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5118 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5119 Requires<[HasAVX512]>;
5120 //===----------------------------------------------------------------------===//
5121 // AVX-512 Vector convert from signed/unsigned integer to float/double
5122 // and from float/double to signed/unsigned integer
5123 //===----------------------------------------------------------------------===//
5125 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5126 X86VectorVTInfo _Src, SDNode OpNode,
5127 string Broadcast = _.BroadcastStr,
5128 string Alias = ""> {
5130 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5131 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5132 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5134 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5135 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5136 (_.VT (OpNode (_Src.VT
5137 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5139 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5140 (ins _Src.MemOp:$src), OpcodeStr,
5141 "${src}"##Broadcast, "${src}"##Broadcast,
5142 (_.VT (OpNode (_Src.VT
5143 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5146 // Coversion with SAE - suppress all exceptions
5147 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5148 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5149 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5150 (ins _Src.RC:$src), OpcodeStr,
5151 "{sae}, $src", "$src, {sae}",
5152 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5153 (i32 FROUND_NO_EXC)))>,
5157 // Conversion with rounding control (RC)
5158 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5159 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5160 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5161 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5162 "$rc, $src", "$src, $rc",
5163 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5164 EVEX, EVEX_B, EVEX_RC;
5167 // Extend Float to Double
5168 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5169 let Predicates = [HasAVX512] in {
5170 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5171 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5172 X86vfpextRnd>, EVEX_V512;
5174 let Predicates = [HasVLX] in {
5175 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5176 X86vfpext, "{1to2}">, EVEX_V128;
5177 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5182 // Truncate Double to Float
5183 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5184 let Predicates = [HasAVX512] in {
5185 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5186 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5187 X86vfproundRnd>, EVEX_V512;
5189 let Predicates = [HasVLX] in {
5190 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5191 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5192 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5193 "{1to4}", "{y}">, EVEX_V256;
5197 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5198 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5199 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5200 PS, EVEX_CD8<32, CD8VH>;
5202 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5203 (VCVTPS2PDZrm addr:$src)>;
5205 let Predicates = [HasVLX] in {
5206 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5207 (VCVTPS2PDZ256rm addr:$src)>;
5210 // Convert Signed/Unsigned Doubleword to Double
5211 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5213 // No rounding in this op
5214 let Predicates = [HasAVX512] in
5215 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5218 let Predicates = [HasVLX] in {
5219 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5220 OpNode128, "{1to2}">, EVEX_V128;
5221 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5226 // Convert Signed/Unsigned Doubleword to Float
5227 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5229 let Predicates = [HasAVX512] in
5230 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5231 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5232 OpNodeRnd>, EVEX_V512;
5234 let Predicates = [HasVLX] in {
5235 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5237 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5242 // Convert Float to Signed/Unsigned Doubleword with truncation
5243 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5244 SDNode OpNode, SDNode OpNodeRnd> {
5245 let Predicates = [HasAVX512] in {
5246 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5247 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5248 OpNodeRnd>, EVEX_V512;
5250 let Predicates = [HasVLX] in {
5251 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5253 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5258 // Convert Float to Signed/Unsigned Doubleword
5259 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5260 SDNode OpNode, SDNode OpNodeRnd> {
5261 let Predicates = [HasAVX512] in {
5262 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5263 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5264 OpNodeRnd>, EVEX_V512;
5266 let Predicates = [HasVLX] in {
5267 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5269 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5274 // Convert Double to Signed/Unsigned Doubleword with truncation
5275 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5276 SDNode OpNode, SDNode OpNodeRnd> {
5277 let Predicates = [HasAVX512] in {
5278 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5279 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5280 OpNodeRnd>, EVEX_V512;
5282 let Predicates = [HasVLX] in {
5283 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5284 // memory forms of these instructions in Asm Parcer. They have the same
5285 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5286 // due to the same reason.
5287 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5288 "{1to2}", "{x}">, EVEX_V128;
5289 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5290 "{1to4}", "{y}">, EVEX_V256;
5294 // Convert Double to Signed/Unsigned Doubleword
5295 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5296 SDNode OpNode, SDNode OpNodeRnd> {
5297 let Predicates = [HasAVX512] in {
5298 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5299 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5300 OpNodeRnd>, EVEX_V512;
5302 let Predicates = [HasVLX] in {
5303 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5304 // memory forms of these instructions in Asm Parcer. They have the same
5305 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5306 // due to the same reason.
5307 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5308 "{1to2}", "{x}">, EVEX_V128;
5309 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5310 "{1to4}", "{y}">, EVEX_V256;
5314 // Convert Double to Signed/Unsigned Quardword
5315 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5316 SDNode OpNode, SDNode OpNodeRnd> {
5317 let Predicates = [HasDQI] in {
5318 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5319 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5320 OpNodeRnd>, EVEX_V512;
5322 let Predicates = [HasDQI, HasVLX] in {
5323 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5325 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5330 // Convert Double to Signed/Unsigned Quardword with truncation
5331 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5332 SDNode OpNode, SDNode OpNodeRnd> {
5333 let Predicates = [HasDQI] in {
5334 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5335 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5336 OpNodeRnd>, EVEX_V512;
5338 let Predicates = [HasDQI, HasVLX] in {
5339 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5341 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5346 // Convert Signed/Unsigned Quardword to Double
5347 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5348 SDNode OpNode, SDNode OpNodeRnd> {
5349 let Predicates = [HasDQI] in {
5350 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5351 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5352 OpNodeRnd>, EVEX_V512;
5354 let Predicates = [HasDQI, HasVLX] in {
5355 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5357 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5362 // Convert Float to Signed/Unsigned Quardword
5363 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5364 SDNode OpNode, SDNode OpNodeRnd> {
5365 let Predicates = [HasDQI] in {
5366 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5367 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5368 OpNodeRnd>, EVEX_V512;
5370 let Predicates = [HasDQI, HasVLX] in {
5371 // Explicitly specified broadcast string, since we take only 2 elements
5372 // from v4f32x_info source
5373 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5374 "{1to2}">, EVEX_V128;
5375 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5380 // Convert Float to Signed/Unsigned Quardword with truncation
5381 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5382 SDNode OpNode, SDNode OpNodeRnd> {
5383 let Predicates = [HasDQI] in {
5384 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5385 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5386 OpNodeRnd>, EVEX_V512;
5388 let Predicates = [HasDQI, HasVLX] in {
5389 // Explicitly specified broadcast string, since we take only 2 elements
5390 // from v4f32x_info source
5391 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5392 "{1to2}">, EVEX_V128;
5393 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5398 // Convert Signed/Unsigned Quardword to Float
5399 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5400 SDNode OpNode, SDNode OpNodeRnd> {
5401 let Predicates = [HasDQI] in {
5402 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5403 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5404 OpNodeRnd>, EVEX_V512;
5406 let Predicates = [HasDQI, HasVLX] in {
5407 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5408 // memory forms of these instructions in Asm Parcer. They have the same
5409 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5410 // due to the same reason.
5411 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5412 "{1to2}", "{x}">, EVEX_V128;
5413 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5414 "{1to4}", "{y}">, EVEX_V256;
5418 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5419 EVEX_CD8<32, CD8VH>;
5421 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5423 PS, EVEX_CD8<32, CD8VF>;
5425 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5427 XS, EVEX_CD8<32, CD8VF>;
5429 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5431 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5433 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5434 X86VFpToUintRnd>, PS,
5435 EVEX_CD8<32, CD8VF>;
5437 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5438 X86VFpToUintRnd>, PS, VEX_W,
5439 EVEX_CD8<64, CD8VF>;
5441 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5442 XS, EVEX_CD8<32, CD8VH>;
5444 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5445 X86VUintToFpRnd>, XD,
5446 EVEX_CD8<32, CD8VF>;
5448 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5449 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5451 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5452 X86cvtpd2IntRnd>, XD, VEX_W,
5453 EVEX_CD8<64, CD8VF>;
5455 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5457 PS, EVEX_CD8<32, CD8VF>;
5458 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5459 X86cvtpd2UIntRnd>, VEX_W,
5460 PS, EVEX_CD8<64, CD8VF>;
5462 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5463 X86cvtpd2IntRnd>, VEX_W,
5464 PD, EVEX_CD8<64, CD8VF>;
5466 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5467 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5469 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5470 X86cvtpd2UIntRnd>, VEX_W,
5471 PD, EVEX_CD8<64, CD8VF>;
5473 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5474 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5476 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5477 X86VFpToSlongRnd>, VEX_W,
5478 PD, EVEX_CD8<64, CD8VF>;
5480 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5481 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5483 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5484 X86VFpToUlongRnd>, VEX_W,
5485 PD, EVEX_CD8<64, CD8VF>;
5487 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5488 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5490 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5491 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5493 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5494 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5496 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5497 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5499 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5500 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5502 let Predicates = [HasAVX512, NoVLX] in {
5503 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5504 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5505 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5507 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5508 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5509 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5511 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5512 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5513 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5515 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5516 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5517 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5519 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5520 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5521 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5524 let Predicates = [HasAVX512] in {
5525 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5526 (VCVTPD2PSZrm addr:$src)>;
5527 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5528 (VCVTPS2PDZrm addr:$src)>;
5531 //===----------------------------------------------------------------------===//
5532 // Half precision conversion instructions
5533 //===----------------------------------------------------------------------===//
5534 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5535 X86MemOperand x86memop, PatFrag ld_frag> {
5536 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5537 "vcvtph2ps", "$src", "$src",
5538 (X86cvtph2ps (_src.VT _src.RC:$src),
5539 (i32 FROUND_CURRENT))>, T8PD;
5540 let hasSideEffects = 0, mayLoad = 1 in {
5541 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5542 "vcvtph2ps", "$src", "$src",
5543 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5544 (i32 FROUND_CURRENT))>, T8PD;
5548 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5549 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5550 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5551 (X86cvtph2ps (_src.VT _src.RC:$src),
5552 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5556 let Predicates = [HasAVX512] in {
5557 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5558 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5559 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5560 let Predicates = [HasVLX] in {
5561 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5562 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5563 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5564 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5568 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5569 X86MemOperand x86memop> {
5570 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5571 (ins _src.RC:$src1, i32u8imm:$src2),
5572 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5573 (X86cvtps2ph (_src.VT _src.RC:$src1),
5575 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5576 let hasSideEffects = 0, mayStore = 1 in {
5577 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5578 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5579 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5580 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5581 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5583 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5584 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5585 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5589 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5590 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5591 (ins _src.RC:$src1, i32u8imm:$src2),
5592 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5593 (X86cvtps2ph (_src.VT _src.RC:$src1),
5595 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5597 let Predicates = [HasAVX512] in {
5598 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5599 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5600 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5601 let Predicates = [HasVLX] in {
5602 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5603 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5604 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5605 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5608 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5609 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5610 "ucomiss">, PS, EVEX, VEX_LIG,
5611 EVEX_CD8<32, CD8VT1>;
5612 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5613 "ucomisd">, PD, EVEX,
5614 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5615 let Pattern = []<dag> in {
5616 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5617 "comiss">, PS, EVEX, VEX_LIG,
5618 EVEX_CD8<32, CD8VT1>;
5619 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5620 "comisd">, PD, EVEX,
5621 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5623 let isCodeGenOnly = 1 in {
5624 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5625 load, "ucomiss">, PS, EVEX, VEX_LIG,
5626 EVEX_CD8<32, CD8VT1>;
5627 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5628 load, "ucomisd">, PD, EVEX,
5629 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5631 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5632 load, "comiss">, PS, EVEX, VEX_LIG,
5633 EVEX_CD8<32, CD8VT1>;
5634 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5635 load, "comisd">, PD, EVEX,
5636 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5640 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5641 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5642 X86VectorVTInfo _> {
5643 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5644 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5645 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5646 "$src2, $src1", "$src1, $src2",
5647 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5648 let mayLoad = 1 in {
5649 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5650 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5651 "$src2, $src1", "$src1, $src2",
5652 (OpNode (_.VT _.RC:$src1),
5653 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5658 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5659 EVEX_CD8<32, CD8VT1>, T8PD;
5660 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5661 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5662 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5663 EVEX_CD8<32, CD8VT1>, T8PD;
5664 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5665 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5667 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5668 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5669 X86VectorVTInfo _> {
5670 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5671 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5672 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5673 let mayLoad = 1 in {
5674 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5675 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5677 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5678 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5679 (ins _.ScalarMemOp:$src), OpcodeStr,
5680 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5682 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5687 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5688 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5689 EVEX_V512, EVEX_CD8<32, CD8VF>;
5690 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5691 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5693 // Define only if AVX512VL feature is present.
5694 let Predicates = [HasVLX] in {
5695 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5696 OpNode, v4f32x_info>,
5697 EVEX_V128, EVEX_CD8<32, CD8VF>;
5698 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5699 OpNode, v8f32x_info>,
5700 EVEX_V256, EVEX_CD8<32, CD8VF>;
5701 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5702 OpNode, v2f64x_info>,
5703 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5704 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5705 OpNode, v4f64x_info>,
5706 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5710 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5711 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5713 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5714 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5715 (VRSQRT14PSZr VR512:$src)>;
5716 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5717 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5718 (VRSQRT14PDZr VR512:$src)>;
5720 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5721 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5722 (VRCP14PSZr VR512:$src)>;
5723 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5724 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5725 (VRCP14PDZr VR512:$src)>;
5727 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5728 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5731 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5732 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5733 "$src2, $src1", "$src1, $src2",
5734 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5735 (i32 FROUND_CURRENT))>;
5737 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5738 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5739 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5740 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5741 (i32 FROUND_NO_EXC))>, EVEX_B;
5743 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5744 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5745 "$src2, $src1", "$src1, $src2",
5746 (OpNode (_.VT _.RC:$src1),
5747 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5748 (i32 FROUND_CURRENT))>;
5751 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5752 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5753 EVEX_CD8<32, CD8VT1>;
5754 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5755 EVEX_CD8<64, CD8VT1>, VEX_W;
5758 let hasSideEffects = 0, Predicates = [HasERI] in {
5759 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5760 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5763 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5764 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5766 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5769 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5770 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5771 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5773 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5774 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5776 (bitconvert (_.LdFrag addr:$src))),
5777 (i32 FROUND_CURRENT))>;
5779 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5780 (ins _.MemOp:$src), OpcodeStr,
5781 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5783 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5784 (i32 FROUND_CURRENT))>, EVEX_B;
5786 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5788 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5789 (ins _.RC:$src), OpcodeStr,
5790 "{sae}, $src", "$src, {sae}",
5791 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5794 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5795 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5796 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5797 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5798 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5799 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5800 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5803 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5805 // Define only if AVX512VL feature is present.
5806 let Predicates = [HasVLX] in {
5807 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5808 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5809 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5810 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5811 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5812 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5813 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5814 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5817 let Predicates = [HasERI], hasSideEffects = 0 in {
5819 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5820 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5821 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5823 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5824 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5826 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5827 SDNode OpNodeRnd, X86VectorVTInfo _>{
5828 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5829 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5830 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5831 EVEX, EVEX_B, EVEX_RC;
5834 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5835 SDNode OpNode, X86VectorVTInfo _>{
5836 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5837 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5838 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5839 let mayLoad = 1 in {
5840 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5841 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5843 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5845 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5846 (ins _.ScalarMemOp:$src), OpcodeStr,
5847 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5849 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5854 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5856 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5858 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5859 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5861 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5862 // Define only if AVX512VL feature is present.
5863 let Predicates = [HasVLX] in {
5864 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5865 OpNode, v4f32x_info>,
5866 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5867 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5868 OpNode, v8f32x_info>,
5869 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5870 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5871 OpNode, v2f64x_info>,
5872 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5873 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5874 OpNode, v4f64x_info>,
5875 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5879 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5881 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5882 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5883 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5884 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5887 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5888 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5890 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5891 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5892 "$src2, $src1", "$src1, $src2",
5893 (OpNodeRnd (_.VT _.RC:$src1),
5895 (i32 FROUND_CURRENT))>;
5897 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5898 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5899 "$src2, $src1", "$src1, $src2",
5900 (OpNodeRnd (_.VT _.RC:$src1),
5901 (_.VT (scalar_to_vector
5902 (_.ScalarLdFrag addr:$src2))),
5903 (i32 FROUND_CURRENT))>;
5905 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5906 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5907 "$rc, $src2, $src1", "$src1, $src2, $rc",
5908 (OpNodeRnd (_.VT _.RC:$src1),
5913 let isCodeGenOnly = 1 in {
5914 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5915 (ins _.FRC:$src1, _.FRC:$src2),
5916 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5919 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5920 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5921 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5924 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5925 (!cast<Instruction>(NAME#SUFF#Zr)
5926 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5928 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5929 (!cast<Instruction>(NAME#SUFF#Zm)
5930 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5933 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5934 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5935 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5936 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5937 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5940 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5941 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5943 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5945 let Predicates = [HasAVX512] in {
5946 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5947 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5948 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5949 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5950 Requires<[OptForSize]>;
5951 def : Pat<(f32 (X86frcp FR32X:$src)),
5952 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5953 def : Pat<(f32 (X86frcp (load addr:$src))),
5954 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5955 Requires<[OptForSize]>;
5959 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5961 let ExeDomain = _.ExeDomain in {
5962 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5963 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5964 "$src3, $src2, $src1", "$src1, $src2, $src3",
5965 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5966 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5968 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5969 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5970 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5971 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5972 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5975 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5976 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5977 "$src3, $src2, $src1", "$src1, $src2, $src3",
5978 (_.VT (X86RndScales (_.VT _.RC:$src1),
5979 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5980 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5982 let Predicates = [HasAVX512] in {
5983 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5984 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5985 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5986 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5987 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5988 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5989 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5990 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5991 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5992 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5993 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5994 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5995 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5996 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5997 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5999 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6000 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6001 addr:$src, (i32 0x1))), _.FRC)>;
6002 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6003 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6004 addr:$src, (i32 0x2))), _.FRC)>;
6005 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6006 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6007 addr:$src, (i32 0x3))), _.FRC)>;
6008 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6009 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6010 addr:$src, (i32 0x4))), _.FRC)>;
6011 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6012 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6013 addr:$src, (i32 0xc))), _.FRC)>;
6017 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
6018 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6020 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
6021 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
6023 //-------------------------------------------------
6024 // Integer truncate and extend operations
6025 //-------------------------------------------------
6027 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6028 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
6029 X86MemOperand x86memop> {
6031 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
6032 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6033 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6036 // for intrinsic patter match
6037 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6038 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6040 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6043 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6044 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6045 DestInfo.ImmAllZerosV)),
6046 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6049 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6050 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6051 DestInfo.RC:$src0)),
6052 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6053 DestInfo.KRCWM:$mask ,
6056 let mayStore = 1 in {
6057 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
6058 (ins x86memop:$dst, SrcInfo.RC:$src),
6059 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6062 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
6063 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6064 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6069 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6070 X86VectorVTInfo DestInfo,
6071 PatFrag truncFrag, PatFrag mtruncFrag > {
6073 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6074 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6075 addr:$dst, SrcInfo.RC:$src)>;
6077 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6078 (SrcInfo.VT SrcInfo.RC:$src)),
6079 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6080 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6083 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6084 X86VectorVTInfo DestInfo, string sat > {
6086 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6087 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6088 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6089 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6090 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6091 (SrcInfo.VT SrcInfo.RC:$src))>;
6093 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6094 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6095 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6096 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6097 (SrcInfo.VT SrcInfo.RC:$src))>;
6100 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6101 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6102 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6103 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6104 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6105 Predicate prd = HasAVX512>{
6107 let Predicates = [HasVLX, prd] in {
6108 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6109 DestInfoZ128, x86memopZ128>,
6110 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6111 truncFrag, mtruncFrag>, EVEX_V128;
6113 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6114 DestInfoZ256, x86memopZ256>,
6115 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6116 truncFrag, mtruncFrag>, EVEX_V256;
6118 let Predicates = [prd] in
6119 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6120 DestInfoZ, x86memopZ>,
6121 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6122 truncFrag, mtruncFrag>, EVEX_V512;
6125 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6126 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6127 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6128 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6129 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6131 let Predicates = [HasVLX, prd] in {
6132 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6133 DestInfoZ128, x86memopZ128>,
6134 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6137 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6138 DestInfoZ256, x86memopZ256>,
6139 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6142 let Predicates = [prd] in
6143 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6144 DestInfoZ, x86memopZ>,
6145 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6149 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6150 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6151 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6152 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6154 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6155 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6156 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6157 sat>, EVEX_CD8<8, CD8VO>;
6160 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6161 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6162 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6163 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6165 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6166 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6167 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6168 sat>, EVEX_CD8<16, CD8VQ>;
6171 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6172 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6173 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6174 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6176 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6177 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6178 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6179 sat>, EVEX_CD8<32, CD8VH>;
6182 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6183 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6184 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6185 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6187 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6188 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6189 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6190 sat>, EVEX_CD8<8, CD8VQ>;
6193 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6194 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6195 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6196 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6198 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6199 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6200 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6201 sat>, EVEX_CD8<16, CD8VH>;
6204 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6205 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6206 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6207 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6209 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6210 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6211 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6212 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6215 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6216 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6217 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6219 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6220 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6221 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6223 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6224 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6225 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6227 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6228 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6229 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6231 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6232 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6233 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6235 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6236 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6237 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6239 let Predicates = [HasAVX512, NoVLX] in {
6240 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6241 (v8i16 (EXTRACT_SUBREG
6242 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6243 VR256X:$src, sub_ymm)))), sub_xmm))>;
6244 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6245 (v4i32 (EXTRACT_SUBREG
6246 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6247 VR256X:$src, sub_ymm)))), sub_xmm))>;
6250 let Predicates = [HasBWI, NoVLX] in {
6251 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6252 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6253 VR256X:$src, sub_ymm))), sub_xmm))>;
6256 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6257 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6258 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6260 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6261 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6262 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6265 let mayLoad = 1 in {
6266 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6267 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6268 (DestInfo.VT (LdFrag addr:$src))>,
6273 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6274 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6275 let Predicates = [HasVLX, HasBWI] in {
6276 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6277 v16i8x_info, i64mem, LdFrag, OpNode>,
6278 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6280 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6281 v16i8x_info, i128mem, LdFrag, OpNode>,
6282 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6284 let Predicates = [HasBWI] in {
6285 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6286 v32i8x_info, i256mem, LdFrag, OpNode>,
6287 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6291 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6292 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6293 let Predicates = [HasVLX, HasAVX512] in {
6294 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6295 v16i8x_info, i32mem, LdFrag, OpNode>,
6296 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6298 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6299 v16i8x_info, i64mem, LdFrag, OpNode>,
6300 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6302 let Predicates = [HasAVX512] in {
6303 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6304 v16i8x_info, i128mem, LdFrag, OpNode>,
6305 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6309 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6310 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6311 let Predicates = [HasVLX, HasAVX512] in {
6312 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6313 v16i8x_info, i16mem, LdFrag, OpNode>,
6314 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6316 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6317 v16i8x_info, i32mem, LdFrag, OpNode>,
6318 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6320 let Predicates = [HasAVX512] in {
6321 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6322 v16i8x_info, i64mem, LdFrag, OpNode>,
6323 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6327 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6328 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6329 let Predicates = [HasVLX, HasAVX512] in {
6330 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6331 v8i16x_info, i64mem, LdFrag, OpNode>,
6332 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6334 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6335 v8i16x_info, i128mem, LdFrag, OpNode>,
6336 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6338 let Predicates = [HasAVX512] in {
6339 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6340 v16i16x_info, i256mem, LdFrag, OpNode>,
6341 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6345 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6346 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6347 let Predicates = [HasVLX, HasAVX512] in {
6348 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6349 v8i16x_info, i32mem, LdFrag, OpNode>,
6350 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6352 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6353 v8i16x_info, i64mem, LdFrag, OpNode>,
6354 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6356 let Predicates = [HasAVX512] in {
6357 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6358 v8i16x_info, i128mem, LdFrag, OpNode>,
6359 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6363 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6364 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6366 let Predicates = [HasVLX, HasAVX512] in {
6367 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6368 v4i32x_info, i64mem, LdFrag, OpNode>,
6369 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6371 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6372 v4i32x_info, i128mem, LdFrag, OpNode>,
6373 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6375 let Predicates = [HasAVX512] in {
6376 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6377 v8i32x_info, i256mem, LdFrag, OpNode>,
6378 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6382 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6383 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6384 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6385 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6386 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6387 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6390 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6391 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6392 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6393 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6394 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6395 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6397 //===----------------------------------------------------------------------===//
6398 // GATHER - SCATTER Operations
6400 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6401 X86MemOperand memop, PatFrag GatherNode> {
6402 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6403 ExeDomain = _.ExeDomain in
6404 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6405 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6406 !strconcat(OpcodeStr#_.Suffix,
6407 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6408 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6409 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6410 vectoraddr:$src2))]>, EVEX, EVEX_K,
6411 EVEX_CD8<_.EltSize, CD8VT1>;
6414 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6415 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6416 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6417 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6418 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6419 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6420 let Predicates = [HasVLX] in {
6421 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6422 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6423 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6424 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6425 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6426 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6427 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6428 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6432 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6433 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6434 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6435 mgatherv16i32>, EVEX_V512;
6436 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6437 mgatherv8i64>, EVEX_V512;
6438 let Predicates = [HasVLX] in {
6439 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6440 vy32xmem, mgatherv8i32>, EVEX_V256;
6441 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6442 vy64xmem, mgatherv4i64>, EVEX_V256;
6443 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6444 vx32xmem, mgatherv4i32>, EVEX_V128;
6445 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6446 vx64xmem, mgatherv2i64>, EVEX_V128;
6451 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6452 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6454 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6455 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6457 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6458 X86MemOperand memop, PatFrag ScatterNode> {
6460 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6462 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6463 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6464 !strconcat(OpcodeStr#_.Suffix,
6465 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6466 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6467 _.KRCWM:$mask, vectoraddr:$dst))]>,
6468 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6471 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6472 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6473 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6474 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6475 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6476 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6477 let Predicates = [HasVLX] in {
6478 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6479 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6480 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6481 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6482 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6483 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6484 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6485 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6489 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6490 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6491 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6492 mscatterv16i32>, EVEX_V512;
6493 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6494 mscatterv8i64>, EVEX_V512;
6495 let Predicates = [HasVLX] in {
6496 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6497 vy32xmem, mscatterv8i32>, EVEX_V256;
6498 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6499 vy64xmem, mscatterv4i64>, EVEX_V256;
6500 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6501 vx32xmem, mscatterv4i32>, EVEX_V128;
6502 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6503 vx64xmem, mscatterv2i64>, EVEX_V128;
6507 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6508 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6510 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6511 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6514 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6515 RegisterClass KRC, X86MemOperand memop> {
6516 let Predicates = [HasPFI], hasSideEffects = 1 in
6517 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6518 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6522 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6523 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6525 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6526 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6528 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6529 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6531 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6532 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6534 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6535 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6537 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6538 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6540 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6541 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6543 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6544 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6546 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6547 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6549 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6550 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6552 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6553 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6555 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6556 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6558 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6559 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6561 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6562 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6564 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6565 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6567 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6568 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6570 // Helper fragments to match sext vXi1 to vXiY.
6571 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6572 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6574 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6575 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6576 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6578 def : Pat<(store VK1:$src, addr:$dst),
6580 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6581 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6583 def : Pat<(store VK8:$src, addr:$dst),
6585 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6586 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6588 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6589 (truncstore node:$val, node:$ptr), [{
6590 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6593 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6594 (MOV8mr addr:$dst, GR8:$src)>;
6596 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6597 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6598 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6599 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6602 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6603 string OpcodeStr, Predicate prd> {
6604 let Predicates = [prd] in
6605 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6607 let Predicates = [prd, HasVLX] in {
6608 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6609 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6613 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6614 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6616 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6618 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6620 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6624 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6626 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6627 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6629 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6632 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6633 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6634 let Predicates = [prd] in
6635 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6638 let Predicates = [prd, HasVLX] in {
6639 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6641 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6646 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6647 avx512vl_i8_info, HasBWI>;
6648 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6649 avx512vl_i16_info, HasBWI>, VEX_W;
6650 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6651 avx512vl_i32_info, HasDQI>;
6652 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6653 avx512vl_i64_info, HasDQI>, VEX_W;
6655 //===----------------------------------------------------------------------===//
6656 // AVX-512 - COMPRESS and EXPAND
6659 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6661 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6662 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6663 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6665 let mayStore = 1 in {
6666 def mr : AVX5128I<opc, MRMDestMem, (outs),
6667 (ins _.MemOp:$dst, _.RC:$src),
6668 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6669 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6671 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6672 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6673 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6674 [(store (_.VT (vselect _.KRCWM:$mask,
6675 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6677 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6681 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6682 AVX512VLVectorVTInfo VTInfo> {
6683 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6685 let Predicates = [HasVLX] in {
6686 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6687 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6691 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6693 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6695 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6697 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6701 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6703 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6704 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6705 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6708 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6709 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6710 (_.VT (X86expand (_.VT (bitconvert
6711 (_.LdFrag addr:$src1)))))>,
6712 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6715 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6716 AVX512VLVectorVTInfo VTInfo> {
6717 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6719 let Predicates = [HasVLX] in {
6720 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6721 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6725 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6727 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6729 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6731 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6734 //handle instruction reg_vec1 = op(reg_vec,imm)
6736 // op(broadcast(eltVt),imm)
6737 //all instruction created with FROUND_CURRENT
6738 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6740 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6741 (ins _.RC:$src1, i32u8imm:$src2),
6742 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6743 (OpNode (_.VT _.RC:$src1),
6745 (i32 FROUND_CURRENT))>;
6746 let mayLoad = 1 in {
6747 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6748 (ins _.MemOp:$src1, i32u8imm:$src2),
6749 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6750 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6752 (i32 FROUND_CURRENT))>;
6753 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6754 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6755 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6756 "${src1}"##_.BroadcastStr##", $src2",
6757 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6759 (i32 FROUND_CURRENT))>, EVEX_B;
6763 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6764 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6765 SDNode OpNode, X86VectorVTInfo _>{
6766 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6767 (ins _.RC:$src1, i32u8imm:$src2),
6768 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6769 "$src1, {sae}, $src2",
6770 (OpNode (_.VT _.RC:$src1),
6772 (i32 FROUND_NO_EXC))>, EVEX_B;
6775 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6776 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6777 let Predicates = [prd] in {
6778 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6779 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6782 let Predicates = [prd, HasVLX] in {
6783 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6785 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6790 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6791 // op(reg_vec2,mem_vec,imm)
6792 // op(reg_vec2,broadcast(eltVt),imm)
6793 //all instruction created with FROUND_CURRENT
6794 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6796 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6797 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6798 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6799 (OpNode (_.VT _.RC:$src1),
6802 (i32 FROUND_CURRENT))>;
6803 let mayLoad = 1 in {
6804 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6805 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6806 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6807 (OpNode (_.VT _.RC:$src1),
6808 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6810 (i32 FROUND_CURRENT))>;
6811 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6812 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6813 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6814 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6815 (OpNode (_.VT _.RC:$src1),
6816 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6818 (i32 FROUND_CURRENT))>, EVEX_B;
6822 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6823 // op(reg_vec2,mem_vec,imm)
6824 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6825 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6827 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6828 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6829 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6830 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6831 (SrcInfo.VT SrcInfo.RC:$src2),
6834 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6835 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6836 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6837 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6838 (SrcInfo.VT (bitconvert
6839 (SrcInfo.LdFrag addr:$src2))),
6843 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6844 // op(reg_vec2,mem_vec,imm)
6845 // op(reg_vec2,broadcast(eltVt),imm)
6846 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6848 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6851 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6852 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6853 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6854 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6855 (OpNode (_.VT _.RC:$src1),
6856 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6857 (i8 imm:$src3))>, EVEX_B;
6860 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6861 // op(reg_vec2,mem_scalar,imm)
6862 //all instruction created with FROUND_CURRENT
6863 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6864 X86VectorVTInfo _> {
6866 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6867 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6868 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6869 (OpNode (_.VT _.RC:$src1),
6872 (i32 FROUND_CURRENT))>;
6873 let mayLoad = 1 in {
6874 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6875 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6876 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6877 (OpNode (_.VT _.RC:$src1),
6878 (_.VT (scalar_to_vector
6879 (_.ScalarLdFrag addr:$src2))),
6881 (i32 FROUND_CURRENT))>;
6883 let isAsmParserOnly = 1 in {
6884 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6885 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6886 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6892 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6893 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6894 SDNode OpNode, X86VectorVTInfo _>{
6895 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6896 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6897 OpcodeStr, "$src3,{sae}, $src2, $src1",
6898 "$src1, $src2,{sae}, $src3",
6899 (OpNode (_.VT _.RC:$src1),
6902 (i32 FROUND_NO_EXC))>, EVEX_B;
6904 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6905 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6906 SDNode OpNode, X86VectorVTInfo _> {
6907 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6908 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6909 OpcodeStr, "$src3,{sae}, $src2, $src1",
6910 "$src1, $src2,{sae}, $src3",
6911 (OpNode (_.VT _.RC:$src1),
6914 (i32 FROUND_NO_EXC))>, EVEX_B;
6917 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6918 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6919 let Predicates = [prd] in {
6920 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6921 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6925 let Predicates = [prd, HasVLX] in {
6926 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6928 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6933 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6934 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6935 let Predicates = [HasBWI] in {
6936 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6937 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6939 let Predicates = [HasBWI, HasVLX] in {
6940 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6941 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6942 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6943 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6947 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6948 bits<8> opc, SDNode OpNode>{
6949 let Predicates = [HasAVX512] in {
6950 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6952 let Predicates = [HasAVX512, HasVLX] in {
6953 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6954 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6958 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6959 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6960 let Predicates = [prd] in {
6961 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6962 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6966 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6967 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6968 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6969 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6970 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6971 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6974 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6975 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6976 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6977 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6978 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6979 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6981 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6982 0x55, X86VFixupimm, HasAVX512>,
6983 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6984 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6985 0x55, X86VFixupimm, HasAVX512>,
6986 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6988 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6989 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6990 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6991 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6992 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6993 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6996 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6997 0x50, X86VRange, HasDQI>,
6998 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6999 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
7000 0x50, X86VRange, HasDQI>,
7001 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7003 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
7004 0x51, X86VRange, HasDQI>,
7005 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7006 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
7007 0x51, X86VRange, HasDQI>,
7008 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7010 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
7011 0x57, X86Reduces, HasDQI>,
7012 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7013 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
7014 0x57, X86Reduces, HasDQI>,
7015 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7017 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
7018 0x27, X86GetMants, HasAVX512>,
7019 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7020 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
7021 0x27, X86GetMants, HasAVX512>,
7022 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7024 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
7025 bits<8> opc, SDNode OpNode = X86Shuf128>{
7026 let Predicates = [HasAVX512] in {
7027 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
7030 let Predicates = [HasAVX512, HasVLX] in {
7031 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7034 let Predicates = [HasAVX512] in {
7035 def : Pat<(v16f32 (ffloor VR512:$src)),
7036 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
7037 def : Pat<(v16f32 (fnearbyint VR512:$src)),
7038 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
7039 def : Pat<(v16f32 (fceil VR512:$src)),
7040 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
7041 def : Pat<(v16f32 (frint VR512:$src)),
7042 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
7043 def : Pat<(v16f32 (ftrunc VR512:$src)),
7044 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
7046 def : Pat<(v8f64 (ffloor VR512:$src)),
7047 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
7048 def : Pat<(v8f64 (fnearbyint VR512:$src)),
7049 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
7050 def : Pat<(v8f64 (fceil VR512:$src)),
7051 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
7052 def : Pat<(v8f64 (frint VR512:$src)),
7053 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
7054 def : Pat<(v8f64 (ftrunc VR512:$src)),
7055 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
7058 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
7059 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7060 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
7061 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7062 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
7063 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7064 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
7065 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7067 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7068 AVX512VLVectorVTInfo VTInfo_FP>{
7069 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
7070 AVX512AIi8Base, EVEX_4V;
7071 let isCodeGenOnly = 1 in {
7072 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
7073 AVX512AIi8Base, EVEX_4V;
7077 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
7078 EVEX_CD8<32, CD8VF>;
7079 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
7080 EVEX_CD8<64, CD8VF>, VEX_W;
7082 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7083 let Predicates = p in
7084 def NAME#_.VTName#rri:
7085 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7086 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7087 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7090 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7091 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7092 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7093 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7095 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7096 avx512vl_i8_info, avx512vl_i8_info>,
7097 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7098 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7099 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7100 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7101 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7104 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7105 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7107 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7108 X86VectorVTInfo _> {
7109 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7110 (ins _.RC:$src1), OpcodeStr,
7112 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7115 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7116 (ins _.MemOp:$src1), OpcodeStr,
7118 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7119 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7122 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7123 X86VectorVTInfo _> :
7124 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7126 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7127 (ins _.ScalarMemOp:$src1), OpcodeStr,
7128 "${src1}"##_.BroadcastStr,
7129 "${src1}"##_.BroadcastStr,
7130 (_.VT (OpNode (X86VBroadcast
7131 (_.ScalarLdFrag addr:$src1))))>,
7132 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7135 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7136 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7137 let Predicates = [prd] in
7138 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7140 let Predicates = [prd, HasVLX] in {
7141 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7143 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7148 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7149 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7150 let Predicates = [prd] in
7151 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7154 let Predicates = [prd, HasVLX] in {
7155 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7157 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7162 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7163 SDNode OpNode, Predicate prd> {
7164 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7166 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7170 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7171 SDNode OpNode, Predicate prd> {
7172 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7173 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7176 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7177 bits<8> opc_d, bits<8> opc_q,
7178 string OpcodeStr, SDNode OpNode> {
7179 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7181 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7185 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7188 (bc_v16i32 (v16i1sextv16i32)),
7189 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7190 (VPABSDZrr VR512:$src)>;
7192 (bc_v8i64 (v8i1sextv8i64)),
7193 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7194 (VPABSQZrr VR512:$src)>;
7196 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7198 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7199 let isCodeGenOnly = 1 in
7200 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
7201 ctlz_zero_undef, prd>;
7204 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7205 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7207 //===---------------------------------------------------------------------===//
7208 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7209 //===---------------------------------------------------------------------===//
7210 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7211 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7213 let isCodeGenOnly = 1 in
7214 defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7218 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7219 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7221 //===----------------------------------------------------------------------===//
7222 // AVX-512 - MOVDDUP
7223 //===----------------------------------------------------------------------===//
7225 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7226 X86VectorVTInfo _> {
7227 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7228 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7229 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7231 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7232 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7233 (_.VT (OpNode (_.VT (scalar_to_vector
7234 (_.ScalarLdFrag addr:$src)))))>,
7235 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7238 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7239 AVX512VLVectorVTInfo VTInfo> {
7241 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7243 let Predicates = [HasAVX512, HasVLX] in {
7244 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7246 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7251 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7252 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7253 avx512vl_f64_info>, XD, VEX_W;
7254 let isCodeGenOnly = 1 in
7255 defm NAME#_I: avx512_movddup_common<opc, OpcodeStr, OpNode,
7259 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7261 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7262 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7263 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7264 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7266 //===----------------------------------------------------------------------===//
7267 // AVX-512 - Unpack Instructions
7268 //===----------------------------------------------------------------------===//
7269 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7270 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7272 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7273 SSE_INTALU_ITINS_P, HasBWI>;
7274 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7275 SSE_INTALU_ITINS_P, HasBWI>;
7276 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7277 SSE_INTALU_ITINS_P, HasBWI>;
7278 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7279 SSE_INTALU_ITINS_P, HasBWI>;
7281 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7282 SSE_INTALU_ITINS_P, HasAVX512>;
7283 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7284 SSE_INTALU_ITINS_P, HasAVX512>;
7285 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7286 SSE_INTALU_ITINS_P, HasAVX512>;
7287 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7288 SSE_INTALU_ITINS_P, HasAVX512>;
7290 //===----------------------------------------------------------------------===//
7291 // AVX-512 - Extract & Insert Integer Instructions
7292 //===----------------------------------------------------------------------===//
7294 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7295 X86VectorVTInfo _> {
7297 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7298 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7299 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7300 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7303 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7306 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7307 let Predicates = [HasBWI] in {
7308 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7309 (ins _.RC:$src1, u8imm:$src2),
7310 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7311 [(set GR32orGR64:$dst,
7312 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7315 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7319 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7320 let Predicates = [HasBWI] in {
7321 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7322 (ins _.RC:$src1, u8imm:$src2),
7323 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7324 [(set GR32orGR64:$dst,
7325 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7328 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7329 (ins _.RC:$src1, u8imm:$src2),
7330 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7333 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7337 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7338 RegisterClass GRC> {
7339 let Predicates = [HasDQI] in {
7340 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7341 (ins _.RC:$src1, u8imm:$src2),
7342 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7344 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7348 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7349 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7350 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7351 [(store (extractelt (_.VT _.RC:$src1),
7352 imm:$src2),addr:$dst)]>,
7353 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7357 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7358 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7359 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7360 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7362 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7363 X86VectorVTInfo _, PatFrag LdFrag> {
7364 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7365 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7366 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7368 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7369 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7372 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7373 X86VectorVTInfo _, PatFrag LdFrag> {
7374 let Predicates = [HasBWI] in {
7375 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7376 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7377 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7379 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7381 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7385 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7386 X86VectorVTInfo _, RegisterClass GRC> {
7387 let Predicates = [HasDQI] in {
7388 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7389 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7390 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7392 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7395 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7396 _.ScalarLdFrag>, TAPD;
7400 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7402 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7404 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7405 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7406 //===----------------------------------------------------------------------===//
7407 // VSHUFPS - VSHUFPD Operations
7408 //===----------------------------------------------------------------------===//
7409 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7410 AVX512VLVectorVTInfo VTInfo_FP>{
7411 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7412 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7413 AVX512AIi8Base, EVEX_4V;
7414 let isCodeGenOnly = 1 in {
7415 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7416 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7417 AVX512AIi8Base, EVEX_4V;
7421 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7422 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7423 //===----------------------------------------------------------------------===//
7424 // AVX-512 - Byte shift Left/Right
7425 //===----------------------------------------------------------------------===//
7427 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7428 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7429 def rr : AVX512<opc, MRMr,
7430 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7431 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7432 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7434 def rm : AVX512<opc, MRMm,
7435 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7436 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7437 [(set _.RC:$dst,(_.VT (OpNode
7438 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7441 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7442 Format MRMm, string OpcodeStr, Predicate prd>{
7443 let Predicates = [prd] in
7444 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7445 OpcodeStr, v8i64_info>, EVEX_V512;
7446 let Predicates = [prd, HasVLX] in {
7447 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7448 OpcodeStr, v4i64x_info>, EVEX_V256;
7449 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7450 OpcodeStr, v2i64x_info>, EVEX_V128;
7453 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7454 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7455 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7456 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7459 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7460 string OpcodeStr, X86VectorVTInfo _dst,
7461 X86VectorVTInfo _src>{
7462 def rr : AVX512BI<opc, MRMSrcReg,
7463 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7464 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7465 [(set _dst.RC:$dst,(_dst.VT
7466 (OpNode (_src.VT _src.RC:$src1),
7467 (_src.VT _src.RC:$src2))))]>;
7469 def rm : AVX512BI<opc, MRMSrcMem,
7470 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7471 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7472 [(set _dst.RC:$dst,(_dst.VT
7473 (OpNode (_src.VT _src.RC:$src1),
7474 (_src.VT (bitconvert
7475 (_src.LdFrag addr:$src2))))))]>;
7478 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7479 string OpcodeStr, Predicate prd> {
7480 let Predicates = [prd] in
7481 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7482 v64i8_info>, EVEX_V512;
7483 let Predicates = [prd, HasVLX] in {
7484 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7485 v32i8x_info>, EVEX_V256;
7486 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7487 v16i8x_info>, EVEX_V128;
7491 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7494 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7496 let Constraints = "$src1 = $dst" in {
7497 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7498 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7499 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7500 (OpNode (_.VT _.RC:$src1),
7503 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7504 let mayLoad = 1 in {
7505 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7506 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7507 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7508 (OpNode (_.VT _.RC:$src1),
7510 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7512 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7513 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7514 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7515 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7516 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7517 (OpNode (_.VT _.RC:$src1),
7519 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7520 (i8 imm:$src4))>, EVEX_B,
7521 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7523 }// Constraints = "$src1 = $dst"
7526 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7527 let Predicates = [HasAVX512] in
7528 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7529 let Predicates = [HasAVX512, HasVLX] in {
7530 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7531 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7535 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7536 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;