1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
278 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_custom<O, F, Outs, Ins,
284 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
285 !con((ins _.KRCWM:$mask), Ins),
286 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
290 // Instruction with mask that puts result in mask register,
291 // like "compare" and "vptest"
292 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
294 dag Ins, dag MaskingIns,
296 string AttSrcAsm, string IntelSrcAsm,
298 list<dag> MaskingPattern,
300 InstrItinClass itin = NoItinerary> {
301 def NAME: AVX512<O, F, Outs, Ins,
302 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
303 "$dst "#Round#", "#IntelSrcAsm#"}",
306 def NAME#k: AVX512<O, F, Outs, MaskingIns,
307 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
308 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
309 MaskingPattern, itin>, EVEX_K;
312 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
314 dag Ins, dag MaskingIns,
316 string AttSrcAsm, string IntelSrcAsm,
317 dag RHS, dag MaskingRHS,
319 InstrItinClass itin = NoItinerary> :
320 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
321 AttSrcAsm, IntelSrcAsm,
322 [(set _.KRC:$dst, RHS)],
323 [(set _.KRC:$dst, MaskingRHS)],
326 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
327 dag Outs, dag Ins, string OpcodeStr,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, string Round = "",
330 InstrItinClass itin = NoItinerary> :
331 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
332 !con((ins _.KRCWM:$mask), Ins),
333 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
334 (and _.KRCWM:$mask, RHS),
337 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
338 dag Outs, dag Ins, string OpcodeStr,
339 string AttSrcAsm, string IntelSrcAsm> :
340 AVX512_maskable_custom_cmp<O, F, Outs,
341 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
342 AttSrcAsm, IntelSrcAsm,
343 [],[],"", NoItinerary>;
345 // Bitcasts between 512-bit vector types. Return the original type since
346 // no instruction is needed for the conversion
347 let Predicates = [HasAVX512] in {
348 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
349 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
350 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
351 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
352 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
353 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
354 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
355 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
356 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
357 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
358 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
359 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
360 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
361 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
362 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
363 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
364 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
365 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
366 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
367 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
368 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
369 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
370 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
371 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
372 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
373 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
374 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
375 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
376 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
377 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
378 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
380 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
381 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
382 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
383 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
384 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
385 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
386 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
387 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
388 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
389 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
390 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
391 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
392 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
393 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
394 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
395 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
396 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
397 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
398 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
399 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
400 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
401 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
402 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
403 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
404 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
405 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
406 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
407 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
408 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
409 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
411 // Bitcasts between 256-bit vector types. Return the original type since
412 // no instruction is needed for the conversion
413 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
414 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
415 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
416 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
417 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
418 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
420 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
421 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
422 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
424 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
425 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
426 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
427 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
429 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
431 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
432 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
433 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
434 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
435 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
436 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
437 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
439 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
440 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
441 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
442 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
446 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
449 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
450 isPseudo = 1, Predicates = [HasAVX512] in {
451 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
452 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
455 let Predicates = [HasAVX512] in {
456 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
457 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
458 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
461 //===----------------------------------------------------------------------===//
462 // AVX-512 - VECTOR INSERT
465 multiclass vinsert_for_size_no_alt<int Opcode,
466 X86VectorVTInfo From, X86VectorVTInfo To,
467 PatFrag vinsert_insert,
468 SDNodeXForm INSERT_get_vinsert_imm> {
469 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
470 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
471 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
472 "vinsert" # From.EltTypeName # "x" # From.NumElts #
473 "\t{$src3, $src2, $src1, $dst|"
474 "$dst, $src1, $src2, $src3}",
475 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
476 (From.VT From.RC:$src2),
481 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
482 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
483 "vinsert" # From.EltTypeName # "x" # From.NumElts #
484 "\t{$src3, $src2, $src1, $dst|"
485 "$dst, $src1, $src2, $src3}",
487 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
491 multiclass vinsert_for_size<int Opcode,
492 X86VectorVTInfo From, X86VectorVTInfo To,
493 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
494 PatFrag vinsert_insert,
495 SDNodeXForm INSERT_get_vinsert_imm> :
496 vinsert_for_size_no_alt<Opcode, From, To,
497 vinsert_insert, INSERT_get_vinsert_imm> {
498 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
499 // vinserti32x4. Only add this if 64x2 and friends are not supported
500 // natively via AVX512DQ.
501 let Predicates = [NoDQI] in
502 def : Pat<(vinsert_insert:$ins
503 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
505 VR512:$src1, From.RC:$src2,
506 (INSERT_get_vinsert_imm VR512:$ins)))>;
509 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
510 ValueType EltVT64, int Opcode256> {
511 defm NAME # "32x4" : vinsert_for_size<Opcode128,
512 X86VectorVTInfo< 4, EltVT32, VR128X>,
513 X86VectorVTInfo<16, EltVT32, VR512>,
514 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 X86VectorVTInfo< 8, EltVT64, VR512>,
517 INSERT_get_vinsert128_imm>;
518 let Predicates = [HasDQI] in
519 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
520 X86VectorVTInfo< 2, EltVT64, VR128X>,
521 X86VectorVTInfo< 8, EltVT64, VR512>,
523 INSERT_get_vinsert128_imm>, VEX_W;
524 defm NAME # "64x4" : vinsert_for_size<Opcode256,
525 X86VectorVTInfo< 4, EltVT64, VR256X>,
526 X86VectorVTInfo< 8, EltVT64, VR512>,
527 X86VectorVTInfo< 8, EltVT32, VR256>,
528 X86VectorVTInfo<16, EltVT32, VR512>,
530 INSERT_get_vinsert256_imm>, VEX_W;
531 let Predicates = [HasDQI] in
532 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
533 X86VectorVTInfo< 8, EltVT32, VR256X>,
534 X86VectorVTInfo<16, EltVT32, VR512>,
536 INSERT_get_vinsert256_imm>;
539 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
540 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
542 // vinsertps - insert f32 to XMM
543 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
544 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
545 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
546 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
548 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
549 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
550 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
551 [(set VR128X:$dst, (X86insertps VR128X:$src1,
552 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
553 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
555 //===----------------------------------------------------------------------===//
556 // AVX-512 VECTOR EXTRACT
559 multiclass vextract_for_size<int Opcode,
560 X86VectorVTInfo From, X86VectorVTInfo To,
561 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
562 PatFrag vextract_extract,
563 SDNodeXForm EXTRACT_get_vextract_imm> {
564 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
565 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
566 (ins VR512:$src1, u8imm:$idx),
567 "vextract" # To.EltTypeName # "x4",
568 "$idx, $src1", "$src1, $idx",
569 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
571 AVX512AIi8Base, EVEX, EVEX_V512;
573 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
574 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
575 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
576 "$dst, $src1, $src2}",
577 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
580 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
582 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
583 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
585 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
587 // A 128/256-bit subvector extract from the first 512-bit vector position is
588 // a subregister copy that needs no instruction.
589 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
591 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
593 // And for the alternative types.
594 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
596 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
598 // Intrinsic call with masking.
599 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
601 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
602 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
603 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
604 VR512:$src1, imm:$idx)>;
606 // Intrinsic call with zero-masking.
607 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
609 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
610 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
611 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
612 VR512:$src1, imm:$idx)>;
614 // Intrinsic call without masking.
615 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
617 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
618 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
619 VR512:$src1, imm:$idx)>;
622 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
623 ValueType EltVT64, int Opcode64> {
624 defm NAME # "32x4" : vextract_for_size<Opcode32,
625 X86VectorVTInfo<16, EltVT32, VR512>,
626 X86VectorVTInfo< 4, EltVT32, VR128X>,
627 X86VectorVTInfo< 8, EltVT64, VR512>,
628 X86VectorVTInfo< 2, EltVT64, VR128X>,
630 EXTRACT_get_vextract128_imm>;
631 defm NAME # "64x4" : vextract_for_size<Opcode64,
632 X86VectorVTInfo< 8, EltVT64, VR512>,
633 X86VectorVTInfo< 4, EltVT64, VR256X>,
634 X86VectorVTInfo<16, EltVT32, VR512>,
635 X86VectorVTInfo< 8, EltVT32, VR256>,
637 EXTRACT_get_vextract256_imm>, VEX_W;
640 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
641 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
643 // A 128-bit subvector insert to the first 512-bit vector position
644 // is a subregister copy that needs no instruction.
645 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
646 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
647 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
649 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
650 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
651 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
653 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
654 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
655 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
657 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
658 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
659 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
662 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
663 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
664 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
665 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
666 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
667 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
668 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
669 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
671 // vextractps - extract 32 bits from XMM
672 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
673 (ins VR128X:$src1, u8imm:$src2),
674 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
675 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
678 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
679 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
680 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
681 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
682 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
684 //===---------------------------------------------------------------------===//
687 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
688 ValueType svt, X86VectorVTInfo _> {
689 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
690 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
691 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
695 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
696 (ins _.ScalarMemOp:$src),
697 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
698 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
703 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
704 AVX512VLVectorVTInfo _> {
705 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
708 let Predicates = [HasVLX] in {
709 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
714 let ExeDomain = SSEPackedSingle in {
715 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
716 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
717 let Predicates = [HasVLX] in {
718 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
719 v4f32, v4f32x_info>, EVEX_V128,
720 EVEX_CD8<32, CD8VT1>;
724 let ExeDomain = SSEPackedDouble in {
725 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
726 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
729 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
730 // Later, we can canonize broadcast instructions before ISel phase and
731 // eliminate additional patterns on ISel.
732 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
733 // representations of source
734 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
735 X86VectorVTInfo _, RegisterClass SrcRC_v,
736 RegisterClass SrcRC_s> {
737 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
738 (!cast<Instruction>(InstName##"r")
739 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
741 let AddedComplexity = 30 in {
742 def : Pat<(_.VT (vselect _.KRCWM:$mask,
743 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
744 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
745 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
747 def : Pat<(_.VT(vselect _.KRCWM:$mask,
748 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
749 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
750 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
754 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
756 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
759 let Predicates = [HasVLX] in {
760 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
761 v8f32x_info, VR128X, FR32X>;
762 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
763 v4f32x_info, VR128X, FR32X>;
764 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
765 v4f64x_info, VR128X, FR64X>;
768 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
769 (VBROADCASTSSZm addr:$src)>;
770 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
771 (VBROADCASTSDZm addr:$src)>;
773 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
774 (VBROADCASTSSZm addr:$src)>;
775 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
776 (VBROADCASTSDZm addr:$src)>;
778 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
779 RegisterClass SrcRC> {
780 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
781 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
782 "$src", "$src", []>, T8PD, EVEX;
785 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
786 RegisterClass SrcRC, Predicate prd> {
787 let Predicates = [prd] in
788 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
789 let Predicates = [prd, HasVLX] in {
790 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
791 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
795 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
797 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
799 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
801 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
804 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
805 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
807 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
808 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
810 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
811 (VPBROADCASTDrZr GR32:$src)>;
812 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
813 (VPBROADCASTQrZr GR64:$src)>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
816 (VPBROADCASTDrZr GR32:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
818 (VPBROADCASTQrZr GR64:$src)>;
820 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
821 (v16i32 immAllZerosV), (i16 GR16:$mask))),
822 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
823 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
824 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
825 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
827 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86MemOperand x86memop, PatFrag ld_frag,
829 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
831 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
834 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
835 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
837 !strconcat(OpcodeStr,
838 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
840 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
842 !strconcat(OpcodeStr,
843 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
846 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
849 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
850 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
855 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
857 !strconcat(OpcodeStr,
858 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
859 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
860 (X86VBroadcast (ld_frag addr:$src)),
861 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
865 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
866 loadi32, VR512, v16i32, v4i32, VK16WM>,
867 EVEX_V512, EVEX_CD8<32, CD8VT1>;
868 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
869 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
870 EVEX_CD8<64, CD8VT1>;
872 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
873 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
875 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
878 (_Dst.VT (X86SubVBroadcast
879 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
880 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
882 !strconcat(OpcodeStr,
883 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
885 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
887 !strconcat(OpcodeStr,
888 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
893 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
894 v16i32_info, v4i32x_info>,
895 EVEX_V512, EVEX_CD8<32, CD8VT4>;
896 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
897 v16f32_info, v4f32x_info>,
898 EVEX_V512, EVEX_CD8<32, CD8VT4>;
899 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
900 v8i64_info, v4i64x_info>, VEX_W,
901 EVEX_V512, EVEX_CD8<64, CD8VT4>;
902 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
903 v8f64_info, v4f64x_info>, VEX_W,
904 EVEX_V512, EVEX_CD8<64, CD8VT4>;
906 let Predicates = [HasVLX] in {
907 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
908 v8i32x_info, v4i32x_info>,
909 EVEX_V256, EVEX_CD8<32, CD8VT4>;
910 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
911 v8f32x_info, v4f32x_info>,
912 EVEX_V256, EVEX_CD8<32, CD8VT4>;
914 let Predicates = [HasVLX, HasDQI] in {
915 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
916 v4i64x_info, v2i64x_info>, VEX_W,
917 EVEX_V256, EVEX_CD8<64, CD8VT2>;
918 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
919 v4f64x_info, v2f64x_info>, VEX_W,
920 EVEX_V256, EVEX_CD8<64, CD8VT2>;
922 let Predicates = [HasDQI] in {
923 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
924 v8i64_info, v2i64x_info>, VEX_W,
925 EVEX_V512, EVEX_CD8<64, CD8VT2>;
926 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
927 v16i32_info, v8i32x_info>,
928 EVEX_V512, EVEX_CD8<32, CD8VT8>;
929 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
930 v8f64_info, v2f64x_info>, VEX_W,
931 EVEX_V512, EVEX_CD8<64, CD8VT2>;
932 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
933 v16f32_info, v8f32x_info>,
934 EVEX_V512, EVEX_CD8<32, CD8VT8>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
938 (VPBROADCASTDZrr VR128X:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
940 (VPBROADCASTQZrr VR128X:$src)>;
942 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
943 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
944 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
945 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
947 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
948 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
949 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
950 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
952 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
953 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
954 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
955 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
957 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
958 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
959 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
960 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
962 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
963 (VBROADCASTSSZr VR128X:$src)>;
964 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
965 (VBROADCASTSDZr VR128X:$src)>;
967 // Provide fallback in case the load node that is used in the patterns above
968 // is used by additional users, which prevents the pattern selection.
969 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
970 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
971 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
972 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
975 //===----------------------------------------------------------------------===//
976 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
979 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
981 let Predicates = [HasCDI] in
982 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
984 []>, EVEX, EVEX_V512;
986 let Predicates = [HasCDI, HasVLX] in {
987 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
988 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
989 []>, EVEX, EVEX_V128;
990 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
991 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
992 []>, EVEX, EVEX_V256;
996 let Predicates = [HasCDI] in {
997 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
999 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1003 //===----------------------------------------------------------------------===//
1006 // -- immediate form --
1007 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1008 X86VectorVTInfo _> {
1009 let ExeDomain = _.ExeDomain in {
1010 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1011 (ins _.RC:$src1, u8imm:$src2),
1012 !strconcat(OpcodeStr,
1013 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1015 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1017 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1018 (ins _.MemOp:$src1, u8imm:$src2),
1019 !strconcat(OpcodeStr,
1020 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1022 (_.VT (OpNode (_.LdFrag addr:$src1),
1023 (i8 imm:$src2))))]>,
1024 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1028 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1029 X86VectorVTInfo Ctrl> :
1030 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1031 let ExeDomain = _.ExeDomain in {
1032 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1033 (ins _.RC:$src1, _.RC:$src2),
1034 !strconcat("vpermil" # _.Suffix,
1035 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 (_.VT (X86VPermilpv _.RC:$src1,
1038 (Ctrl.VT Ctrl.RC:$src2))))]>,
1040 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1041 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1042 !strconcat("vpermil" # _.Suffix,
1043 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1045 (_.VT (X86VPermilpv _.RC:$src1,
1046 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1051 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
1053 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
1056 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1058 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1061 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1062 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1063 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1064 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1066 // -- VPERM - register form --
1067 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1068 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
1070 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1071 (ins RC:$src1, RC:$src2),
1072 !strconcat(OpcodeStr,
1073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1075 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
1077 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1078 (ins RC:$src1, x86memop:$src2),
1079 !strconcat(OpcodeStr,
1080 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1082 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
1086 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
1087 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1088 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
1089 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1090 let ExeDomain = SSEPackedSingle in
1091 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
1092 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1093 let ExeDomain = SSEPackedDouble in
1094 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
1095 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1097 // -- VPERM2I - 3 source operands form --
1098 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
1099 PatFrag mem_frag, X86MemOperand x86memop,
1100 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
1101 let Constraints = "$src1 = $dst" in {
1102 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1103 (ins RC:$src1, RC:$src2, RC:$src3),
1104 !strconcat(OpcodeStr,
1105 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1107 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
1110 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1111 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1112 !strconcat(OpcodeStr,
1113 "\t{$src3, $src2, $dst {${mask}}|"
1114 "$dst {${mask}}, $src2, $src3}"),
1115 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1116 (OpNode RC:$src1, RC:$src2,
1121 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1122 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1123 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1124 !strconcat(OpcodeStr,
1125 "\t{$src3, $src2, $dst {${mask}} {z} |",
1126 "$dst {${mask}} {z}, $src2, $src3}"),
1127 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1128 (OpNode RC:$src1, RC:$src2,
1131 (v16i32 immAllZerosV))))))]>,
1134 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1135 (ins RC:$src1, RC:$src2, x86memop:$src3),
1136 !strconcat(OpcodeStr,
1137 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1139 (OpVT (OpNode RC:$src1, RC:$src2,
1140 (mem_frag addr:$src3))))]>, EVEX_4V;
1142 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1143 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1144 !strconcat(OpcodeStr,
1145 "\t{$src3, $src2, $dst {${mask}}|"
1146 "$dst {${mask}}, $src2, $src3}"),
1148 (OpVT (vselect KRC:$mask,
1149 (OpNode RC:$src1, RC:$src2,
1150 (mem_frag addr:$src3)),
1154 let AddedComplexity = 10 in // Prefer over the rrkz variant
1155 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1156 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1157 !strconcat(OpcodeStr,
1158 "\t{$src3, $src2, $dst {${mask}} {z}|"
1159 "$dst {${mask}} {z}, $src2, $src3}"),
1161 (OpVT (vselect KRC:$mask,
1162 (OpNode RC:$src1, RC:$src2,
1163 (mem_frag addr:$src3)),
1165 (v16i32 immAllZerosV))))))]>,
1169 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1170 i512mem, X86VPermiv3, v16i32, VK16WM>,
1171 EVEX_V512, EVEX_CD8<32, CD8VF>;
1172 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1173 i512mem, X86VPermiv3, v8i64, VK8WM>,
1174 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1175 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1176 i512mem, X86VPermiv3, v16f32, VK16WM>,
1177 EVEX_V512, EVEX_CD8<32, CD8VF>;
1178 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1179 i512mem, X86VPermiv3, v8f64, VK8WM>,
1180 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1182 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1183 PatFrag mem_frag, X86MemOperand x86memop,
1184 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1185 ValueType MaskVT, RegisterClass MRC> :
1186 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1188 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1189 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1190 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1192 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1193 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1194 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1195 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1198 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1199 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1200 EVEX_V512, EVEX_CD8<32, CD8VF>;
1201 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1202 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1203 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1204 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1205 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1206 EVEX_V512, EVEX_CD8<32, CD8VF>;
1207 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1208 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1209 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1211 //===----------------------------------------------------------------------===//
1212 // AVX-512 - BLEND using mask
1214 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1215 let ExeDomain = _.ExeDomain in {
1216 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1217 (ins _.RC:$src1, _.RC:$src2),
1218 !strconcat(OpcodeStr,
1219 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1221 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1222 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1223 !strconcat(OpcodeStr,
1224 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1225 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1226 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1227 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1228 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1229 !strconcat(OpcodeStr,
1230 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1231 []>, EVEX_4V, EVEX_KZ;
1232 let mayLoad = 1 in {
1233 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1234 (ins _.RC:$src1, _.MemOp:$src2),
1235 !strconcat(OpcodeStr,
1236 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1237 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1238 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1239 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1240 !strconcat(OpcodeStr,
1241 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1242 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1243 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1244 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1245 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1246 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1247 !strconcat(OpcodeStr,
1248 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1249 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1253 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1255 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1256 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1257 !strconcat(OpcodeStr,
1258 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1259 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1260 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1261 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1262 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1264 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1265 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1266 !strconcat(OpcodeStr,
1267 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1268 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1269 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1273 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1274 AVX512VLVectorVTInfo VTInfo> {
1275 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1276 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1278 let Predicates = [HasVLX] in {
1279 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1280 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1281 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1282 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1286 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1287 AVX512VLVectorVTInfo VTInfo> {
1288 let Predicates = [HasBWI] in
1289 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1291 let Predicates = [HasBWI, HasVLX] in {
1292 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1293 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1298 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1299 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1300 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1301 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1302 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1303 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1306 let Predicates = [HasAVX512] in {
1307 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1308 (v8f32 VR256X:$src2))),
1310 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1311 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1312 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1314 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1315 (v8i32 VR256X:$src2))),
1317 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1319 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1321 //===----------------------------------------------------------------------===//
1322 // Compare Instructions
1323 //===----------------------------------------------------------------------===//
1325 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1326 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1327 SDNode OpNode, ValueType VT,
1328 PatFrag ld_frag, string Suffix> {
1329 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1330 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1331 !strconcat("vcmp${cc}", Suffix,
1332 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1333 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1334 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1335 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1336 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1337 !strconcat("vcmp${cc}", Suffix,
1338 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1339 [(set VK1:$dst, (OpNode (VT RC:$src1),
1340 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1341 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1342 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1343 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1344 !strconcat("vcmp", Suffix,
1345 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1346 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1348 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1349 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1350 !strconcat("vcmp", Suffix,
1351 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1352 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1356 let Predicates = [HasAVX512] in {
1357 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1359 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1363 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1364 X86VectorVTInfo _> {
1365 def rr : AVX512BI<opc, MRMSrcReg,
1366 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1368 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1369 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1371 def rm : AVX512BI<opc, MRMSrcMem,
1372 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1374 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1375 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1376 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1377 def rrk : AVX512BI<opc, MRMSrcReg,
1378 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1379 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1380 "$dst {${mask}}, $src1, $src2}"),
1381 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1382 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1383 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1385 def rmk : AVX512BI<opc, MRMSrcMem,
1386 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1387 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1388 "$dst {${mask}}, $src1, $src2}"),
1389 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1390 (OpNode (_.VT _.RC:$src1),
1392 (_.LdFrag addr:$src2))))))],
1393 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1396 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1397 X86VectorVTInfo _> :
1398 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1399 let mayLoad = 1 in {
1400 def rmb : AVX512BI<opc, MRMSrcMem,
1401 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1402 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1403 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1404 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1405 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1406 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1407 def rmbk : AVX512BI<opc, MRMSrcMem,
1408 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1409 _.ScalarMemOp:$src2),
1410 !strconcat(OpcodeStr,
1411 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1412 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1413 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1414 (OpNode (_.VT _.RC:$src1),
1416 (_.ScalarLdFrag addr:$src2)))))],
1417 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1421 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1422 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1423 let Predicates = [prd] in
1424 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1427 let Predicates = [prd, HasVLX] in {
1428 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1430 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1435 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1436 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1438 let Predicates = [prd] in
1439 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1442 let Predicates = [prd, HasVLX] in {
1443 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1445 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1450 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1451 avx512vl_i8_info, HasBWI>,
1454 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1455 avx512vl_i16_info, HasBWI>,
1456 EVEX_CD8<16, CD8VF>;
1458 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1459 avx512vl_i32_info, HasAVX512>,
1460 EVEX_CD8<32, CD8VF>;
1462 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1463 avx512vl_i64_info, HasAVX512>,
1464 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1466 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1467 avx512vl_i8_info, HasBWI>,
1470 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1471 avx512vl_i16_info, HasBWI>,
1472 EVEX_CD8<16, CD8VF>;
1474 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1475 avx512vl_i32_info, HasAVX512>,
1476 EVEX_CD8<32, CD8VF>;
1478 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1479 avx512vl_i64_info, HasAVX512>,
1480 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1482 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1483 (COPY_TO_REGCLASS (VPCMPGTDZrr
1484 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1485 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1487 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1488 (COPY_TO_REGCLASS (VPCMPEQDZrr
1489 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1490 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1492 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1493 X86VectorVTInfo _> {
1494 def rri : AVX512AIi8<opc, MRMSrcReg,
1495 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1496 !strconcat("vpcmp${cc}", Suffix,
1497 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1498 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1500 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1502 def rmi : AVX512AIi8<opc, MRMSrcMem,
1503 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1504 !strconcat("vpcmp${cc}", Suffix,
1505 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1506 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1507 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1509 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1510 def rrik : AVX512AIi8<opc, MRMSrcReg,
1511 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1513 !strconcat("vpcmp${cc}", Suffix,
1514 "\t{$src2, $src1, $dst {${mask}}|",
1515 "$dst {${mask}}, $src1, $src2}"),
1516 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1517 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1519 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1521 def rmik : AVX512AIi8<opc, MRMSrcMem,
1522 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1524 !strconcat("vpcmp${cc}", Suffix,
1525 "\t{$src2, $src1, $dst {${mask}}|",
1526 "$dst {${mask}}, $src1, $src2}"),
1527 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1528 (OpNode (_.VT _.RC:$src1),
1529 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1531 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1533 // Accept explicit immediate argument form instead of comparison code.
1534 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1535 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1536 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1537 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1538 "$dst, $src1, $src2, $cc}"),
1539 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1541 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1542 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1543 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1544 "$dst, $src1, $src2, $cc}"),
1545 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1546 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1547 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1549 !strconcat("vpcmp", Suffix,
1550 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1551 "$dst {${mask}}, $src1, $src2, $cc}"),
1552 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1554 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1555 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1557 !strconcat("vpcmp", Suffix,
1558 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1559 "$dst {${mask}}, $src1, $src2, $cc}"),
1560 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1564 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1565 X86VectorVTInfo _> :
1566 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1567 def rmib : AVX512AIi8<opc, MRMSrcMem,
1568 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1570 !strconcat("vpcmp${cc}", Suffix,
1571 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1572 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1573 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1574 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1576 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1577 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1578 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1579 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1580 !strconcat("vpcmp${cc}", Suffix,
1581 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1582 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1583 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1584 (OpNode (_.VT _.RC:$src1),
1585 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1587 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1589 // Accept explicit immediate argument form instead of comparison code.
1590 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1591 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1592 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1594 !strconcat("vpcmp", Suffix,
1595 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1596 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1597 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1598 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1599 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1600 _.ScalarMemOp:$src2, u8imm:$cc),
1601 !strconcat("vpcmp", Suffix,
1602 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1603 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1604 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1608 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1609 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1610 let Predicates = [prd] in
1611 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1613 let Predicates = [prd, HasVLX] in {
1614 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1615 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1619 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1620 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1621 let Predicates = [prd] in
1622 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1625 let Predicates = [prd, HasVLX] in {
1626 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1628 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1633 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1634 HasBWI>, EVEX_CD8<8, CD8VF>;
1635 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1636 HasBWI>, EVEX_CD8<8, CD8VF>;
1638 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1639 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1640 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1641 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1643 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1644 HasAVX512>, EVEX_CD8<32, CD8VF>;
1645 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1646 HasAVX512>, EVEX_CD8<32, CD8VF>;
1648 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1649 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1650 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1651 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1653 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1655 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1656 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1657 "vcmp${cc}"#_.Suffix,
1658 "$src2, $src1", "$src1, $src2",
1659 (X86cmpm (_.VT _.RC:$src1),
1663 let mayLoad = 1 in {
1664 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1665 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1666 "vcmp${cc}"#_.Suffix,
1667 "$src2, $src1", "$src1, $src2",
1668 (X86cmpm (_.VT _.RC:$src1),
1669 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1672 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1674 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1675 "vcmp${cc}"#_.Suffix,
1676 "${src2}"##_.BroadcastStr##", $src1",
1677 "$src1, ${src2}"##_.BroadcastStr,
1678 (X86cmpm (_.VT _.RC:$src1),
1679 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1682 // Accept explicit immediate argument form instead of comparison code.
1683 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1684 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1686 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1688 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1690 let mayLoad = 1 in {
1691 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1693 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1695 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1697 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1699 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1701 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1702 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1707 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1708 // comparison code form (VCMP[EQ/LT/LE/...]
1709 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1710 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1711 "vcmp${cc}"#_.Suffix,
1712 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1713 (X86cmpmRnd (_.VT _.RC:$src1),
1716 (i32 FROUND_NO_EXC))>, EVEX_B;
1718 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1719 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1721 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1723 "$cc,{sae}, $src2, $src1",
1724 "$src1, $src2,{sae}, $cc">, EVEX_B;
1728 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1729 let Predicates = [HasAVX512] in {
1730 defm Z : avx512_vcmp_common<_.info512>,
1731 avx512_vcmp_sae<_.info512>, EVEX_V512;
1734 let Predicates = [HasAVX512,HasVLX] in {
1735 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1736 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1740 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1741 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1742 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1743 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1745 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1746 (COPY_TO_REGCLASS (VCMPPSZrri
1747 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1748 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1750 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1751 (COPY_TO_REGCLASS (VPCMPDZrri
1752 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1753 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1755 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1756 (COPY_TO_REGCLASS (VPCMPUDZrri
1757 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1758 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1761 //-----------------------------------------------------------------
1762 // Mask register copy, including
1763 // - copy between mask registers
1764 // - load/store mask registers
1765 // - copy from GPR to mask register and vice versa
1767 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1768 string OpcodeStr, RegisterClass KRC,
1769 ValueType vvt, X86MemOperand x86memop> {
1770 let hasSideEffects = 0 in {
1771 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1772 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1774 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1775 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1776 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1778 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1779 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1780 [(store KRC:$src, addr:$dst)]>;
1784 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1786 RegisterClass KRC, RegisterClass GRC> {
1787 let hasSideEffects = 0 in {
1788 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1789 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1790 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1795 let Predicates = [HasDQI] in
1796 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1797 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1800 let Predicates = [HasAVX512] in
1801 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1802 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1805 let Predicates = [HasBWI] in {
1806 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1808 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1812 let Predicates = [HasBWI] in {
1813 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1815 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1819 // GR from/to mask register
1820 let Predicates = [HasDQI] in {
1821 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1822 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1823 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1824 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1826 let Predicates = [HasAVX512] in {
1827 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1828 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1829 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1830 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1832 let Predicates = [HasBWI] in {
1833 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1834 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1836 let Predicates = [HasBWI] in {
1837 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1838 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1842 let Predicates = [HasDQI] in {
1843 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1844 (KMOVBmk addr:$dst, VK8:$src)>;
1845 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1846 (KMOVBkm addr:$src)>;
1848 let Predicates = [HasAVX512, NoDQI] in {
1849 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1850 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1851 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1852 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1854 let Predicates = [HasAVX512] in {
1855 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1856 (KMOVWmk addr:$dst, VK16:$src)>;
1857 def : Pat<(i1 (load addr:$src)),
1858 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1859 (MOV8rm addr:$src), sub_8bit)),
1861 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1862 (KMOVWkm addr:$src)>;
1864 let Predicates = [HasBWI] in {
1865 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1866 (KMOVDmk addr:$dst, VK32:$src)>;
1867 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1868 (KMOVDkm addr:$src)>;
1870 let Predicates = [HasBWI] in {
1871 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1872 (KMOVQmk addr:$dst, VK64:$src)>;
1873 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1874 (KMOVQkm addr:$src)>;
1877 let Predicates = [HasAVX512] in {
1878 def : Pat<(i1 (trunc (i64 GR64:$src))),
1879 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1882 def : Pat<(i1 (trunc (i32 GR32:$src))),
1883 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1885 def : Pat<(i1 (trunc (i8 GR8:$src))),
1887 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1889 def : Pat<(i1 (trunc (i16 GR16:$src))),
1891 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1894 def : Pat<(i32 (zext VK1:$src)),
1895 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1896 def : Pat<(i32 (anyext VK1:$src)),
1897 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
1898 def : Pat<(i8 (zext VK1:$src)),
1901 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1902 def : Pat<(i64 (zext VK1:$src)),
1903 (AND64ri8 (SUBREG_TO_REG (i64 0),
1904 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1905 def : Pat<(i16 (zext VK1:$src)),
1907 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1909 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1910 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1911 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1912 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1914 let Predicates = [HasBWI] in {
1915 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1916 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1917 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1918 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1922 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1923 let Predicates = [HasAVX512, NoDQI] in {
1924 // GR from/to 8-bit mask without native support
1925 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1927 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1928 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1930 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1934 let Predicates = [HasAVX512] in {
1935 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1936 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1937 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1938 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1940 let Predicates = [HasBWI] in {
1941 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1942 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1943 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1944 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1947 // Mask unary operation
1949 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1950 RegisterClass KRC, SDPatternOperator OpNode,
1952 let Predicates = [prd] in
1953 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1954 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1955 [(set KRC:$dst, (OpNode KRC:$src))]>;
1958 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1959 SDPatternOperator OpNode> {
1960 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1962 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1963 HasAVX512>, VEX, PS;
1964 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1965 HasBWI>, VEX, PD, VEX_W;
1966 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1967 HasBWI>, VEX, PS, VEX_W;
1970 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1972 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1973 let Predicates = [HasAVX512] in
1974 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1976 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1977 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1979 defm : avx512_mask_unop_int<"knot", "KNOT">;
1981 let Predicates = [HasDQI] in
1982 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1983 let Predicates = [HasAVX512] in
1984 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1985 let Predicates = [HasBWI] in
1986 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1987 let Predicates = [HasBWI] in
1988 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1990 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1991 let Predicates = [HasAVX512, NoDQI] in {
1992 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1993 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1994 def : Pat<(not VK8:$src),
1996 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1998 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1999 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2000 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2001 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2003 // Mask binary operation
2004 // - KAND, KANDN, KOR, KXNOR, KXOR
2005 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2006 RegisterClass KRC, SDPatternOperator OpNode,
2007 Predicate prd, bit IsCommutable> {
2008 let Predicates = [prd], isCommutable = IsCommutable in
2009 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2010 !strconcat(OpcodeStr,
2011 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2012 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2015 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2016 SDPatternOperator OpNode, bit IsCommutable> {
2017 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2018 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2019 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2020 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
2021 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2022 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2023 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2024 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2027 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2028 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2030 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2031 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2032 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2033 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2034 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2036 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2037 let Predicates = [HasAVX512] in
2038 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2039 (i16 GR16:$src1), (i16 GR16:$src2)),
2040 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2041 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2042 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2045 defm : avx512_mask_binop_int<"kand", "KAND">;
2046 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2047 defm : avx512_mask_binop_int<"kor", "KOR">;
2048 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2049 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2051 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2052 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2053 // for the DQI set, this type is legal and KxxxB instruction is used
2054 let Predicates = [NoDQI] in
2055 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2057 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2058 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2060 // All types smaller than 8 bits require conversion anyway
2061 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2062 (COPY_TO_REGCLASS (Inst
2063 (COPY_TO_REGCLASS VK1:$src1, VK16),
2064 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2065 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2066 (COPY_TO_REGCLASS (Inst
2067 (COPY_TO_REGCLASS VK2:$src1, VK16),
2068 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2069 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2070 (COPY_TO_REGCLASS (Inst
2071 (COPY_TO_REGCLASS VK4:$src1, VK16),
2072 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2075 defm : avx512_binop_pat<and, KANDWrr>;
2076 defm : avx512_binop_pat<andn, KANDNWrr>;
2077 defm : avx512_binop_pat<or, KORWrr>;
2078 defm : avx512_binop_pat<xnor, KXNORWrr>;
2079 defm : avx512_binop_pat<xor, KXORWrr>;
2081 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2082 (KXNORWrr VK16:$src1, VK16:$src2)>;
2083 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2084 (KXNORBrr VK8:$src1, VK8:$src2)>;
2085 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2086 (KXNORDrr VK32:$src1, VK32:$src2)>;
2087 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2088 (KXNORQrr VK64:$src1, VK64:$src2)>;
2090 let Predicates = [NoDQI] in
2091 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2092 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2093 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2095 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2096 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2097 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2099 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2100 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2101 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2103 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2104 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2105 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2108 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2109 RegisterClass KRC> {
2110 let Predicates = [HasAVX512] in
2111 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2112 !strconcat(OpcodeStr,
2113 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2116 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2117 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2121 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2122 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2123 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2124 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2127 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2128 let Predicates = [HasAVX512] in
2129 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2130 (i16 GR16:$src1), (i16 GR16:$src2)),
2131 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2132 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2133 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2135 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2138 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2140 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2141 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2142 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2143 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2146 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2147 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2149 let Predicates = [HasDQI] in
2150 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2152 let Predicates = [HasBWI] in {
2153 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2155 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2160 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2163 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2165 let Predicates = [HasAVX512] in
2166 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2167 !strconcat(OpcodeStr,
2168 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2169 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2172 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2174 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2176 let Predicates = [HasDQI] in
2177 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2179 let Predicates = [HasBWI] in {
2180 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2182 let Predicates = [HasDQI] in
2183 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2188 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2189 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2191 // Mask setting all 0s or 1s
2192 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2193 let Predicates = [HasAVX512] in
2194 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2195 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2196 [(set KRC:$dst, (VT Val))]>;
2199 multiclass avx512_mask_setop_w<PatFrag Val> {
2200 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2201 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2202 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2203 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2206 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2207 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2209 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2210 let Predicates = [HasAVX512] in {
2211 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2212 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2213 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2214 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2215 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2216 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2217 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2219 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2220 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2222 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2223 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2225 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2226 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2228 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2229 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2231 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2232 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2234 let Predicates = [HasVLX] in {
2235 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2236 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2237 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2238 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2239 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2240 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2241 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2242 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2243 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2244 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2247 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2248 (v8i1 (COPY_TO_REGCLASS
2249 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2250 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2252 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2253 (v8i1 (COPY_TO_REGCLASS
2254 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2255 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2257 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2258 (v4i1 (COPY_TO_REGCLASS
2259 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2260 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2262 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2263 (v4i1 (COPY_TO_REGCLASS
2264 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2265 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2267 //===----------------------------------------------------------------------===//
2268 // AVX-512 - Aligned and unaligned load and store
2272 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2273 PatFrag ld_frag, PatFrag mload,
2274 bit IsReMaterializable = 1> {
2275 let hasSideEffects = 0 in {
2276 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2277 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2279 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2280 (ins _.KRCWM:$mask, _.RC:$src),
2281 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2282 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2285 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2286 SchedRW = [WriteLoad] in
2287 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2288 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2289 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2292 let Constraints = "$src0 = $dst" in {
2293 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2294 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2295 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2296 "${dst} {${mask}}, $src1}"),
2297 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2299 (_.VT _.RC:$src0))))], _.ExeDomain>,
2301 let mayLoad = 1, SchedRW = [WriteLoad] in
2302 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2303 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2304 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2305 "${dst} {${mask}}, $src1}"),
2306 [(set _.RC:$dst, (_.VT
2307 (vselect _.KRCWM:$mask,
2308 (_.VT (bitconvert (ld_frag addr:$src1))),
2309 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2311 let mayLoad = 1, SchedRW = [WriteLoad] in
2312 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2313 (ins _.KRCWM:$mask, _.MemOp:$src),
2314 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2315 "${dst} {${mask}} {z}, $src}",
2316 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2317 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2318 _.ExeDomain>, EVEX, EVEX_KZ;
2320 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2321 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2323 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2324 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2326 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2327 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2328 _.KRCWM:$mask, addr:$ptr)>;
2331 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2332 AVX512VLVectorVTInfo _,
2334 bit IsReMaterializable = 1> {
2335 let Predicates = [prd] in
2336 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2337 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2339 let Predicates = [prd, HasVLX] in {
2340 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2341 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2342 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2343 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2347 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2348 AVX512VLVectorVTInfo _,
2350 bit IsReMaterializable = 1> {
2351 let Predicates = [prd] in
2352 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2353 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2355 let Predicates = [prd, HasVLX] in {
2356 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2357 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2358 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2359 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2363 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2364 PatFrag st_frag, PatFrag mstore> {
2365 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2366 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2367 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2369 let Constraints = "$src1 = $dst" in
2370 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2371 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2373 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2374 [], _.ExeDomain>, EVEX, EVEX_K;
2375 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2376 (ins _.KRCWM:$mask, _.RC:$src),
2378 "\t{$src, ${dst} {${mask}} {z}|" #
2379 "${dst} {${mask}} {z}, $src}",
2380 [], _.ExeDomain>, EVEX, EVEX_KZ;
2382 let mayStore = 1 in {
2383 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2384 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2385 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2386 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2387 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2388 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2389 [], _.ExeDomain>, EVEX, EVEX_K;
2392 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2393 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2394 _.KRCWM:$mask, _.RC:$src)>;
2398 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2399 AVX512VLVectorVTInfo _, Predicate prd> {
2400 let Predicates = [prd] in
2401 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2402 masked_store_unaligned>, EVEX_V512;
2404 let Predicates = [prd, HasVLX] in {
2405 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2406 masked_store_unaligned>, EVEX_V256;
2407 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2408 masked_store_unaligned>, EVEX_V128;
2412 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2413 AVX512VLVectorVTInfo _, Predicate prd> {
2414 let Predicates = [prd] in
2415 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2416 masked_store_aligned512>, EVEX_V512;
2418 let Predicates = [prd, HasVLX] in {
2419 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2420 masked_store_aligned256>, EVEX_V256;
2421 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2422 masked_store_aligned128>, EVEX_V128;
2426 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2428 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2429 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2431 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2433 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2434 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2436 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2437 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2438 PS, EVEX_CD8<32, CD8VF>;
2440 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2441 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2442 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2444 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2445 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2446 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2448 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2449 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2450 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2452 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2453 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2454 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2456 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2457 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2458 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2460 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2461 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2462 (VMOVAPDZrm addr:$ptr)>;
2464 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2465 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2466 (VMOVAPSZrm addr:$ptr)>;
2468 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2470 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2472 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2474 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2477 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2479 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2481 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2483 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2486 let Predicates = [HasAVX512, NoVLX] in {
2487 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2488 (VMOVUPSZmrk addr:$ptr,
2489 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2490 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2492 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2493 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2494 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2496 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2497 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2498 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2499 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2502 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2504 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2505 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2507 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2509 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2510 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2512 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2513 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2514 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2516 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2517 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2518 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2520 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2521 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2522 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2524 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2525 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2526 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2528 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2529 (v16i32 immAllZerosV), GR16:$mask)),
2530 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2532 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2533 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2534 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2536 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2538 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2540 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2542 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2545 let AddedComplexity = 20 in {
2546 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2547 (bc_v8i64 (v16i32 immAllZerosV)))),
2548 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2550 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2551 (v8i64 VR512:$src))),
2552 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2555 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2556 (v16i32 immAllZerosV))),
2557 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2559 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2560 (v16i32 VR512:$src))),
2561 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2564 let Predicates = [HasAVX512, NoVLX] in {
2565 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2566 (VMOVDQU32Zmrk addr:$ptr,
2567 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2568 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2570 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2571 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2572 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2575 // Move Int Doubleword to Packed Double Int
2577 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2578 "vmovd\t{$src, $dst|$dst, $src}",
2580 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2582 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2583 "vmovd\t{$src, $dst|$dst, $src}",
2585 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2586 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2587 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2588 "vmovq\t{$src, $dst|$dst, $src}",
2590 (v2i64 (scalar_to_vector GR64:$src)))],
2591 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2592 let isCodeGenOnly = 1 in {
2593 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2594 "vmovq\t{$src, $dst|$dst, $src}",
2595 [(set FR64:$dst, (bitconvert GR64:$src))],
2596 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2597 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2598 "vmovq\t{$src, $dst|$dst, $src}",
2599 [(set GR64:$dst, (bitconvert FR64:$src))],
2600 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2602 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2603 "vmovq\t{$src, $dst|$dst, $src}",
2604 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2605 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2606 EVEX_CD8<64, CD8VT1>;
2608 // Move Int Doubleword to Single Scalar
2610 let isCodeGenOnly = 1 in {
2611 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2612 "vmovd\t{$src, $dst|$dst, $src}",
2613 [(set FR32X:$dst, (bitconvert GR32:$src))],
2614 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2616 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2617 "vmovd\t{$src, $dst|$dst, $src}",
2618 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2619 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2622 // Move doubleword from xmm register to r/m32
2624 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2625 "vmovd\t{$src, $dst|$dst, $src}",
2626 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2627 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2629 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2630 (ins i32mem:$dst, VR128X:$src),
2631 "vmovd\t{$src, $dst|$dst, $src}",
2632 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2633 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2634 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2636 // Move quadword from xmm1 register to r/m64
2638 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2639 "vmovq\t{$src, $dst|$dst, $src}",
2640 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2642 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2643 Requires<[HasAVX512, In64BitMode]>;
2645 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2646 (ins i64mem:$dst, VR128X:$src),
2647 "vmovq\t{$src, $dst|$dst, $src}",
2648 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2649 addr:$dst)], IIC_SSE_MOVDQ>,
2650 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2651 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2653 // Move Scalar Single to Double Int
2655 let isCodeGenOnly = 1 in {
2656 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2658 "vmovd\t{$src, $dst|$dst, $src}",
2659 [(set GR32:$dst, (bitconvert FR32X:$src))],
2660 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2661 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2662 (ins i32mem:$dst, FR32X:$src),
2663 "vmovd\t{$src, $dst|$dst, $src}",
2664 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2665 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2668 // Move Quadword Int to Packed Quadword Int
2670 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2672 "vmovq\t{$src, $dst|$dst, $src}",
2674 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2675 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2677 //===----------------------------------------------------------------------===//
2678 // AVX-512 MOVSS, MOVSD
2679 //===----------------------------------------------------------------------===//
2681 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2682 SDNode OpNode, ValueType vt,
2683 X86MemOperand x86memop, PatFrag mem_pat> {
2684 let hasSideEffects = 0 in {
2685 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2686 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2687 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2688 (scalar_to_vector RC:$src2))))],
2689 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2690 let Constraints = "$src1 = $dst" in
2691 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2692 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2694 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2695 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2696 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2697 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2698 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2700 let mayStore = 1 in {
2701 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2702 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2703 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2705 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2706 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2707 [], IIC_SSE_MOV_S_MR>,
2708 EVEX, VEX_LIG, EVEX_K;
2710 } //hasSideEffects = 0
2713 let ExeDomain = SSEPackedSingle in
2714 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2715 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2717 let ExeDomain = SSEPackedDouble in
2718 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2719 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2721 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2722 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2723 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2725 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2726 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2727 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2729 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2730 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2731 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2733 // For the disassembler
2734 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2735 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2736 (ins VR128X:$src1, FR32X:$src2),
2737 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2739 XS, EVEX_4V, VEX_LIG;
2740 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2741 (ins VR128X:$src1, FR64X:$src2),
2742 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2744 XD, EVEX_4V, VEX_LIG, VEX_W;
2747 let Predicates = [HasAVX512] in {
2748 let AddedComplexity = 15 in {
2749 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2750 // MOVS{S,D} to the lower bits.
2751 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2752 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2753 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2754 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2755 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2756 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2757 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2758 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2760 // Move low f32 and clear high bits.
2761 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2762 (SUBREG_TO_REG (i32 0),
2763 (VMOVSSZrr (v4f32 (V_SET0)),
2764 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2765 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2766 (SUBREG_TO_REG (i32 0),
2767 (VMOVSSZrr (v4i32 (V_SET0)),
2768 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2771 let AddedComplexity = 20 in {
2772 // MOVSSrm zeros the high parts of the register; represent this
2773 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2774 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2775 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2776 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2777 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2778 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2779 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2781 // MOVSDrm zeros the high parts of the register; represent this
2782 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2783 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2784 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2785 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2786 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2787 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2788 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2789 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2790 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2791 def : Pat<(v2f64 (X86vzload addr:$src)),
2792 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2794 // Represent the same patterns above but in the form they appear for
2796 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2797 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2798 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2799 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2800 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2801 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2802 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2803 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2804 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2806 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2807 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2808 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2809 FR32X:$src)), sub_xmm)>;
2810 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2811 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2812 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2813 FR64X:$src)), sub_xmm)>;
2814 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2815 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2816 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2818 // Move low f64 and clear high bits.
2819 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2820 (SUBREG_TO_REG (i32 0),
2821 (VMOVSDZrr (v2f64 (V_SET0)),
2822 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2824 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2825 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2826 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2828 // Extract and store.
2829 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2831 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2832 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2834 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2836 // Shuffle with VMOVSS
2837 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2838 (VMOVSSZrr (v4i32 VR128X:$src1),
2839 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2840 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2841 (VMOVSSZrr (v4f32 VR128X:$src1),
2842 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2845 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2846 (SUBREG_TO_REG (i32 0),
2847 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2848 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2850 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2851 (SUBREG_TO_REG (i32 0),
2852 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2853 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2856 // Shuffle with VMOVSD
2857 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2858 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2859 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2860 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2861 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2862 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2863 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2864 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2867 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2868 (SUBREG_TO_REG (i32 0),
2869 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2870 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2872 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2873 (SUBREG_TO_REG (i32 0),
2874 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2875 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2878 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2879 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2880 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2881 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2882 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2883 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2884 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2885 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2888 let AddedComplexity = 15 in
2889 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2891 "vmovq\t{$src, $dst|$dst, $src}",
2892 [(set VR128X:$dst, (v2i64 (X86vzmovl
2893 (v2i64 VR128X:$src))))],
2894 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2896 let AddedComplexity = 20 in
2897 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2899 "vmovq\t{$src, $dst|$dst, $src}",
2900 [(set VR128X:$dst, (v2i64 (X86vzmovl
2901 (loadv2i64 addr:$src))))],
2902 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2903 EVEX_CD8<8, CD8VT8>;
2905 let Predicates = [HasAVX512] in {
2906 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2907 let AddedComplexity = 20 in {
2908 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2909 (VMOVDI2PDIZrm addr:$src)>;
2910 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2911 (VMOV64toPQIZrr GR64:$src)>;
2912 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2913 (VMOVDI2PDIZrr GR32:$src)>;
2915 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2916 (VMOVDI2PDIZrm addr:$src)>;
2917 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2918 (VMOVDI2PDIZrm addr:$src)>;
2919 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2920 (VMOVZPQILo2PQIZrm addr:$src)>;
2921 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2922 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2923 def : Pat<(v2i64 (X86vzload addr:$src)),
2924 (VMOVZPQILo2PQIZrm addr:$src)>;
2927 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2928 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2929 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2930 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2931 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2932 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2933 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2936 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2937 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2939 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2940 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2942 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2943 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2945 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2946 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2948 //===----------------------------------------------------------------------===//
2949 // AVX-512 - Non-temporals
2950 //===----------------------------------------------------------------------===//
2951 let SchedRW = [WriteLoad] in {
2952 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2953 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2954 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2955 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2956 EVEX_CD8<64, CD8VF>;
2958 let Predicates = [HasAVX512, HasVLX] in {
2959 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2961 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2962 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2963 EVEX_CD8<64, CD8VF>;
2965 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2967 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2968 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2969 EVEX_CD8<64, CD8VF>;
2973 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2974 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2975 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2976 let SchedRW = [WriteStore], mayStore = 1,
2977 AddedComplexity = 400 in
2978 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2980 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2983 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2984 string elty, string elsz, string vsz512,
2985 string vsz256, string vsz128, Domain d,
2986 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2987 let Predicates = [prd] in
2988 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2989 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2990 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2993 let Predicates = [prd, HasVLX] in {
2994 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2995 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2996 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2999 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3000 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3001 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3006 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3007 "i", "64", "8", "4", "2", SSEPackedInt,
3008 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3010 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3011 "f", "64", "8", "4", "2", SSEPackedDouble,
3012 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3014 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3015 "f", "32", "16", "8", "4", SSEPackedSingle,
3016 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3018 //===----------------------------------------------------------------------===//
3019 // AVX-512 - Integer arithmetic
3021 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3022 X86VectorVTInfo _, OpndItins itins,
3023 bit IsCommutable = 0> {
3024 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3025 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3026 "$src2, $src1", "$src1, $src2",
3027 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3028 itins.rr, IsCommutable>,
3029 AVX512BIBase, EVEX_4V;
3032 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3033 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3034 "$src2, $src1", "$src1, $src2",
3035 (_.VT (OpNode _.RC:$src1,
3036 (bitconvert (_.LdFrag addr:$src2)))),
3038 AVX512BIBase, EVEX_4V;
3041 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3042 X86VectorVTInfo _, OpndItins itins,
3043 bit IsCommutable = 0> :
3044 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3046 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3047 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3048 "${src2}"##_.BroadcastStr##", $src1",
3049 "$src1, ${src2}"##_.BroadcastStr,
3050 (_.VT (OpNode _.RC:$src1,
3052 (_.ScalarLdFrag addr:$src2)))),
3054 AVX512BIBase, EVEX_4V, EVEX_B;
3057 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3058 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3059 Predicate prd, bit IsCommutable = 0> {
3060 let Predicates = [prd] in
3061 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3062 IsCommutable>, EVEX_V512;
3064 let Predicates = [prd, HasVLX] in {
3065 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3066 IsCommutable>, EVEX_V256;
3067 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3068 IsCommutable>, EVEX_V128;
3072 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3073 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3074 Predicate prd, bit IsCommutable = 0> {
3075 let Predicates = [prd] in
3076 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3077 IsCommutable>, EVEX_V512;
3079 let Predicates = [prd, HasVLX] in {
3080 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3081 IsCommutable>, EVEX_V256;
3082 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3083 IsCommutable>, EVEX_V128;
3087 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3088 OpndItins itins, Predicate prd,
3089 bit IsCommutable = 0> {
3090 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3091 itins, prd, IsCommutable>,
3092 VEX_W, EVEX_CD8<64, CD8VF>;
3095 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3096 OpndItins itins, Predicate prd,
3097 bit IsCommutable = 0> {
3098 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3099 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3102 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3103 OpndItins itins, Predicate prd,
3104 bit IsCommutable = 0> {
3105 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3106 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3109 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3110 OpndItins itins, Predicate prd,
3111 bit IsCommutable = 0> {
3112 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3113 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3116 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3117 SDNode OpNode, OpndItins itins, Predicate prd,
3118 bit IsCommutable = 0> {
3119 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
3122 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
3126 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3127 SDNode OpNode, OpndItins itins, Predicate prd,
3128 bit IsCommutable = 0> {
3129 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
3132 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
3136 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3137 bits<8> opc_d, bits<8> opc_q,
3138 string OpcodeStr, SDNode OpNode,
3139 OpndItins itins, bit IsCommutable = 0> {
3140 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3141 itins, HasAVX512, IsCommutable>,
3142 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3143 itins, HasBWI, IsCommutable>;
3146 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3147 SDNode OpNode,X86VectorVTInfo _Src,
3148 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3149 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3150 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3151 "$src2, $src1","$src1, $src2",
3153 (_Src.VT _Src.RC:$src1),
3154 (_Src.VT _Src.RC:$src2))),
3155 itins.rr, IsCommutable>,
3156 AVX512BIBase, EVEX_4V;
3157 let mayLoad = 1 in {
3158 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3159 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3160 "$src2, $src1", "$src1, $src2",
3161 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3162 (bitconvert (_Src.LdFrag addr:$src2)))),
3164 AVX512BIBase, EVEX_4V;
3166 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3167 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3169 "${src2}"##_Dst.BroadcastStr##", $src1",
3170 "$src1, ${src2}"##_Dst.BroadcastStr,
3171 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3172 (_Dst.VT (X86VBroadcast
3173 (_Dst.ScalarLdFrag addr:$src2)))))),
3175 AVX512BIBase, EVEX_4V, EVEX_B;
3179 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3180 SSE_INTALU_ITINS_P, 1>;
3181 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3182 SSE_INTALU_ITINS_P, 0>;
3183 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3184 SSE_INTALU_ITINS_P, HasBWI, 1>;
3185 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3186 SSE_INTALU_ITINS_P, HasBWI, 0>;
3187 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3188 SSE_INTALU_ITINS_P, HasBWI, 1>;
3189 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3190 SSE_INTALU_ITINS_P, HasBWI, 0>;
3191 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3192 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3193 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3194 SSE_INTALU_ITINS_P, HasBWI, 1>;
3195 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3196 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3199 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3200 SDNode OpNode, bit IsCommutable = 0> {
3202 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3203 v16i32_info, v8i64_info, IsCommutable>,
3204 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3205 let Predicates = [HasVLX] in {
3206 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3207 v8i32x_info, v4i64x_info, IsCommutable>,
3208 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3209 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3210 v4i32x_info, v2i64x_info, IsCommutable>,
3211 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3215 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3217 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3220 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3221 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3222 let mayLoad = 1 in {
3223 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3224 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3226 "${src2}"##_Src.BroadcastStr##", $src1",
3227 "$src1, ${src2}"##_Src.BroadcastStr,
3228 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3229 (_Src.VT (X86VBroadcast
3230 (_Src.ScalarLdFrag addr:$src2))))))>,
3231 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3235 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3236 SDNode OpNode,X86VectorVTInfo _Src,
3237 X86VectorVTInfo _Dst> {
3238 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3239 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3240 "$src2, $src1","$src1, $src2",
3242 (_Src.VT _Src.RC:$src1),
3243 (_Src.VT _Src.RC:$src2)))>,
3244 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3245 let mayLoad = 1 in {
3246 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3247 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3248 "$src2, $src1", "$src1, $src2",
3249 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3250 (bitconvert (_Src.LdFrag addr:$src2))))>,
3251 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3255 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3257 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3259 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3260 v32i16_info>, EVEX_V512;
3261 let Predicates = [HasVLX] in {
3262 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3264 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3265 v16i16x_info>, EVEX_V256;
3266 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3268 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3269 v8i16x_info>, EVEX_V128;
3272 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3274 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3275 v64i8_info>, EVEX_V512;
3276 let Predicates = [HasVLX] in {
3277 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3278 v32i8x_info>, EVEX_V256;
3279 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3280 v16i8x_info>, EVEX_V128;
3283 let Predicates = [HasBWI] in {
3284 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3285 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3286 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3287 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3290 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3291 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3292 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3293 SSE_INTALU_ITINS_P, HasBWI, 1>;
3294 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3295 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3297 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3298 SSE_INTALU_ITINS_P, HasBWI, 1>;
3299 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3300 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3301 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3302 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3304 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3305 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3306 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3307 SSE_INTALU_ITINS_P, HasBWI, 1>;
3308 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3309 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3311 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3312 SSE_INTALU_ITINS_P, HasBWI, 1>;
3313 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3314 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3315 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3316 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3318 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3319 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3320 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3321 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3322 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3323 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3324 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3325 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3326 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3327 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3328 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3329 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3330 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3331 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3332 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3333 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3334 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3335 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3336 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3337 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3338 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3339 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3340 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3341 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3342 //===----------------------------------------------------------------------===//
3343 // AVX-512 - Unpack Instructions
3344 //===----------------------------------------------------------------------===//
3346 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3347 PatFrag mem_frag, RegisterClass RC,
3348 X86MemOperand x86memop, string asm,
3350 def rr : AVX512PI<opc, MRMSrcReg,
3351 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3353 (vt (OpNode RC:$src1, RC:$src2)))],
3355 def rm : AVX512PI<opc, MRMSrcMem,
3356 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3358 (vt (OpNode RC:$src1,
3359 (bitconvert (mem_frag addr:$src2)))))],
3363 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3364 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3365 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3366 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3367 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3368 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3369 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3370 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3371 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3372 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3373 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3374 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3376 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3377 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3378 X86MemOperand x86memop> {
3379 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3380 (ins RC:$src1, RC:$src2),
3381 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3382 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3383 IIC_SSE_UNPCK>, EVEX_4V;
3384 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3385 (ins RC:$src1, x86memop:$src2),
3386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3387 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3388 (bitconvert (memop_frag addr:$src2)))))],
3389 IIC_SSE_UNPCK>, EVEX_4V;
3391 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3392 VR512, loadv16i32, i512mem>, EVEX_V512,
3393 EVEX_CD8<32, CD8VF>;
3394 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3395 VR512, loadv8i64, i512mem>, EVEX_V512,
3396 VEX_W, EVEX_CD8<64, CD8VF>;
3397 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3398 VR512, loadv16i32, i512mem>, EVEX_V512,
3399 EVEX_CD8<32, CD8VF>;
3400 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3401 VR512, loadv8i64, i512mem>, EVEX_V512,
3402 VEX_W, EVEX_CD8<64, CD8VF>;
3403 //===----------------------------------------------------------------------===//
3404 // AVX-512 Logical Instructions
3405 //===----------------------------------------------------------------------===//
3407 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3408 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3409 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3410 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3411 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3412 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3413 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3414 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3416 //===----------------------------------------------------------------------===//
3417 // AVX-512 FP arithmetic
3418 //===----------------------------------------------------------------------===//
3419 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3420 SDNode OpNode, SDNode VecNode, OpndItins itins,
3423 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3424 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3425 "$src2, $src1", "$src1, $src2",
3426 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3427 (i32 FROUND_CURRENT)),
3428 itins.rr, IsCommutable>;
3430 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3431 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3432 "$src2, $src1", "$src1, $src2",
3433 (VecNode (_.VT _.RC:$src1),
3434 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3435 (i32 FROUND_CURRENT)),
3436 itins.rm, IsCommutable>;
3437 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3438 Predicates = [HasAVX512] in {
3439 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3440 (ins _.FRC:$src1, _.FRC:$src2),
3441 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3442 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3444 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3445 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3446 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3447 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3448 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3452 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3453 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3455 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3456 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3457 "$rc, $src2, $src1", "$src1, $src2, $rc",
3458 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3459 (i32 imm:$rc)), itins.rr, IsCommutable>,
3462 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3463 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3465 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3466 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3467 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3468 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3469 (i32 FROUND_NO_EXC))>, EVEX_B;
3472 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3474 SizeItins itins, bit IsCommutable> {
3475 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3476 itins.s, IsCommutable>,
3477 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3478 itins.s, IsCommutable>,
3479 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3480 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3481 itins.d, IsCommutable>,
3482 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3483 itins.d, IsCommutable>,
3484 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3487 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3489 SizeItins itins, bit IsCommutable> {
3490 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3491 itins.s, IsCommutable>,
3492 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3493 itins.s, IsCommutable>,
3494 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3495 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3496 itins.d, IsCommutable>,
3497 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3498 itins.d, IsCommutable>,
3499 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3501 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3502 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3503 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3504 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3505 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3506 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3508 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3509 X86VectorVTInfo _, bit IsCommutable> {
3510 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3511 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3512 "$src2, $src1", "$src1, $src2",
3513 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3514 let mayLoad = 1 in {
3515 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3516 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3517 "$src2, $src1", "$src1, $src2",
3518 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3519 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3520 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3521 "${src2}"##_.BroadcastStr##", $src1",
3522 "$src1, ${src2}"##_.BroadcastStr,
3523 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3524 (_.ScalarLdFrag addr:$src2))))>,
3529 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3530 X86VectorVTInfo _, bit IsCommutable> {
3531 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3532 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3533 "$rc, $src2, $src1", "$src1, $src2, $rc",
3534 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3535 EVEX_4V, EVEX_B, EVEX_RC;
3539 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3540 X86VectorVTInfo _, bit IsCommutable> {
3541 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3542 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3543 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3544 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3548 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3549 bit IsCommutable = 0> {
3550 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3551 IsCommutable>, EVEX_V512, PS,
3552 EVEX_CD8<32, CD8VF>;
3553 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3554 IsCommutable>, EVEX_V512, PD, VEX_W,
3555 EVEX_CD8<64, CD8VF>;
3557 // Define only if AVX512VL feature is present.
3558 let Predicates = [HasVLX] in {
3559 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3560 IsCommutable>, EVEX_V128, PS,
3561 EVEX_CD8<32, CD8VF>;
3562 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3563 IsCommutable>, EVEX_V256, PS,
3564 EVEX_CD8<32, CD8VF>;
3565 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3566 IsCommutable>, EVEX_V128, PD, VEX_W,
3567 EVEX_CD8<64, CD8VF>;
3568 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3569 IsCommutable>, EVEX_V256, PD, VEX_W,
3570 EVEX_CD8<64, CD8VF>;
3574 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3575 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3576 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3577 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3578 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3581 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3582 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3583 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3584 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3585 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3588 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3589 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3590 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3591 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3592 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3593 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3594 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3595 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3596 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3597 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3598 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3599 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3600 let Predicates = [HasDQI] in {
3601 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3602 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3603 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3604 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3607 //===----------------------------------------------------------------------===//
3608 // AVX-512 VPTESTM instructions
3609 //===----------------------------------------------------------------------===//
3611 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3612 X86VectorVTInfo _> {
3613 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3614 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3615 "$src2, $src1", "$src1, $src2",
3616 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3619 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3620 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3621 "$src2, $src1", "$src1, $src2",
3622 (OpNode (_.VT _.RC:$src1),
3623 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3625 EVEX_CD8<_.EltSize, CD8VF>;
3628 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3629 X86VectorVTInfo _> {
3631 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3632 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3633 "${src2}"##_.BroadcastStr##", $src1",
3634 "$src1, ${src2}"##_.BroadcastStr,
3635 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3636 (_.ScalarLdFrag addr:$src2))))>,
3637 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3639 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3640 AVX512VLVectorVTInfo _> {
3641 let Predicates = [HasAVX512] in
3642 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3643 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3645 let Predicates = [HasAVX512, HasVLX] in {
3646 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3647 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3648 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3649 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3653 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3654 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3656 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3657 avx512vl_i64_info>, VEX_W;
3660 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3662 let Predicates = [HasBWI] in {
3663 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3665 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3668 let Predicates = [HasVLX, HasBWI] in {
3670 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3672 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3674 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3676 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3681 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3683 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3684 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3686 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3687 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3689 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3690 (v16i32 VR512:$src2), (i16 -1))),
3691 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3693 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3694 (v8i64 VR512:$src2), (i8 -1))),
3695 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3697 //===----------------------------------------------------------------------===//
3698 // AVX-512 Shift instructions
3699 //===----------------------------------------------------------------------===//
3700 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3701 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3702 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3703 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3704 "$src2, $src1", "$src1, $src2",
3705 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3706 SSE_INTSHIFT_ITINS_P.rr>;
3708 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3709 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3710 "$src2, $src1", "$src1, $src2",
3711 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3713 SSE_INTSHIFT_ITINS_P.rm>;
3716 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3717 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3719 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3720 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3721 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3722 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3723 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3726 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3727 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3728 // src2 is always 128-bit
3729 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3730 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3731 "$src2, $src1", "$src1, $src2",
3732 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3733 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3734 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3735 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3736 "$src2, $src1", "$src1, $src2",
3737 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3738 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3742 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3743 ValueType SrcVT, PatFrag bc_frag,
3744 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3745 let Predicates = [prd] in
3746 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3747 VTInfo.info512>, EVEX_V512,
3748 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3749 let Predicates = [prd, HasVLX] in {
3750 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3751 VTInfo.info256>, EVEX_V256,
3752 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3753 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3754 VTInfo.info128>, EVEX_V128,
3755 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3759 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3760 string OpcodeStr, SDNode OpNode> {
3761 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3762 avx512vl_i32_info, HasAVX512>;
3763 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3764 avx512vl_i64_info, HasAVX512>, VEX_W;
3765 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3766 avx512vl_i16_info, HasBWI>;
3769 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3770 string OpcodeStr, SDNode OpNode,
3771 AVX512VLVectorVTInfo VTInfo> {
3772 let Predicates = [HasAVX512] in
3773 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3775 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3776 VTInfo.info512>, EVEX_V512;
3777 let Predicates = [HasAVX512, HasVLX] in {
3778 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3780 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3781 VTInfo.info256>, EVEX_V256;
3782 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3784 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3785 VTInfo.info128>, EVEX_V128;
3789 multiclass avx512_shift_rmi_w<bits<8> opcw,
3790 Format ImmFormR, Format ImmFormM,
3791 string OpcodeStr, SDNode OpNode> {
3792 let Predicates = [HasBWI] in
3793 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3794 v32i16_info>, EVEX_V512;
3795 let Predicates = [HasVLX, HasBWI] in {
3796 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3797 v16i16x_info>, EVEX_V256;
3798 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3799 v8i16x_info>, EVEX_V128;
3803 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3804 Format ImmFormR, Format ImmFormM,
3805 string OpcodeStr, SDNode OpNode> {
3806 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3807 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3808 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3809 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3812 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3813 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3815 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3816 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3818 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3819 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3821 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3822 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3824 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3825 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3826 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3828 //===-------------------------------------------------------------------===//
3829 // Variable Bit Shifts
3830 //===-------------------------------------------------------------------===//
3831 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3832 X86VectorVTInfo _> {
3833 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3834 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3835 "$src2, $src1", "$src1, $src2",
3836 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3837 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3839 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3840 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3841 "$src2, $src1", "$src1, $src2",
3842 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3843 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3844 EVEX_CD8<_.EltSize, CD8VF>;
3847 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3848 X86VectorVTInfo _> {
3850 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3851 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3852 "${src2}"##_.BroadcastStr##", $src1",
3853 "$src1, ${src2}"##_.BroadcastStr,
3854 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3855 (_.ScalarLdFrag addr:$src2))))),
3856 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3857 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3859 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3860 AVX512VLVectorVTInfo _> {
3861 let Predicates = [HasAVX512] in
3862 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3863 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3865 let Predicates = [HasAVX512, HasVLX] in {
3866 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3867 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3868 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3869 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3873 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3875 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3877 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3878 avx512vl_i64_info>, VEX_W;
3881 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3883 let Predicates = [HasBWI] in
3884 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3886 let Predicates = [HasVLX, HasBWI] in {
3888 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3890 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3895 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3896 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3897 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3898 avx512_var_shift_w<0x11, "vpsravw", sra>;
3899 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3900 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3901 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3902 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3904 //===----------------------------------------------------------------------===//
3905 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
3906 //===----------------------------------------------------------------------===//
3908 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
3909 X86PShufd, avx512vl_i32_info>,
3910 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
3911 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
3912 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
3913 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
3914 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
3915 //===----------------------------------------------------------------------===//
3916 // AVX-512 - MOVDDUP
3917 //===----------------------------------------------------------------------===//
3919 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3920 X86MemOperand x86memop, PatFrag memop_frag> {
3921 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3922 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3923 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3924 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3925 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3927 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3930 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3931 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3932 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3933 (VMOVDDUPZrm addr:$src)>;
3935 //===---------------------------------------------------------------------===//
3936 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3937 //===---------------------------------------------------------------------===//
3938 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3939 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3940 X86MemOperand x86memop> {
3941 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3942 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3943 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3945 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3946 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3947 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3950 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3951 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3952 EVEX_CD8<32, CD8VF>;
3953 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3954 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3955 EVEX_CD8<32, CD8VF>;
3957 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3958 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3959 (VMOVSHDUPZrm addr:$src)>;
3960 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3961 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3962 (VMOVSLDUPZrm addr:$src)>;
3964 //===----------------------------------------------------------------------===//
3965 // Move Low to High and High to Low packed FP Instructions
3966 //===----------------------------------------------------------------------===//
3967 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3968 (ins VR128X:$src1, VR128X:$src2),
3969 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3970 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3971 IIC_SSE_MOV_LH>, EVEX_4V;
3972 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3973 (ins VR128X:$src1, VR128X:$src2),
3974 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3975 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3976 IIC_SSE_MOV_LH>, EVEX_4V;
3978 let Predicates = [HasAVX512] in {
3980 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3981 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3982 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3983 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3986 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3987 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3990 //===----------------------------------------------------------------------===//
3991 // FMA - Fused Multiply Operations
3994 let Constraints = "$src1 = $dst" in {
3995 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3996 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3997 SDPatternOperator OpNode = null_frag> {
3998 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3999 (ins _.RC:$src2, _.RC:$src3),
4000 OpcodeStr, "$src3, $src2", "$src2, $src3",
4001 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4005 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4006 (ins _.RC:$src2, _.MemOp:$src3),
4007 OpcodeStr, "$src3, $src2", "$src2, $src3",
4008 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4011 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4012 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4013 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4014 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4016 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4017 AVX512FMA3Base, EVEX_B;
4019 } // Constraints = "$src1 = $dst"
4021 let Constraints = "$src1 = $dst" in {
4022 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
4023 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
4025 SDPatternOperator OpNode> {
4026 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4027 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4028 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4029 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4030 AVX512FMA3Base, EVEX_B, EVEX_RC;
4032 } // Constraints = "$src1 = $dst"
4034 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
4035 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
4036 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4037 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4040 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
4041 string OpcodeStr, X86VectorVTInfo VTI,
4042 SDPatternOperator OpNode> {
4043 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4044 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4045 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
4046 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
4049 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
4051 SDPatternOperator OpNode,
4052 SDPatternOperator OpNodeRnd> {
4053 let ExeDomain = SSEPackedSingle in {
4054 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4055 v16f32_info, OpNode>,
4056 avx512_fma3_round_forms<opc213, OpcodeStr,
4057 v16f32_info, OpNodeRnd>, EVEX_V512;
4058 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4059 v8f32x_info, OpNode>, EVEX_V256;
4060 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4061 v4f32x_info, OpNode>, EVEX_V128;
4063 let ExeDomain = SSEPackedDouble in {
4064 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4065 v8f64_info, OpNode>,
4066 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
4067 OpNodeRnd>, EVEX_V512, VEX_W;
4068 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4069 v4f64x_info, OpNode>,
4071 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4072 v2f64x_info, OpNode>,
4077 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
4078 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
4079 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
4080 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
4081 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4082 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4084 let Constraints = "$src1 = $dst" in {
4085 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
4086 X86VectorVTInfo _> {
4088 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4089 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
4090 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
4091 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
4093 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4094 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
4095 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
4096 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
4098 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4099 (_.ScalarLdFrag addr:$src2))),
4100 _.RC:$src3))]>, EVEX_B;
4102 } // Constraints = "$src1 = $dst"
4104 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4106 let ExeDomain = SSEPackedSingle in {
4107 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
4108 OpNode,v16f32_info>, EVEX_V512,
4109 EVEX_CD8<32, CD8VF>;
4110 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4111 OpNode, v8f32x_info>, EVEX_V256,
4112 EVEX_CD8<32, CD8VF>;
4113 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4114 OpNode, v4f32x_info>, EVEX_V128,
4115 EVEX_CD8<32, CD8VF>;
4117 let ExeDomain = SSEPackedDouble in {
4118 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
4119 OpNode, v8f64_info>, EVEX_V512,
4120 VEX_W, EVEX_CD8<32, CD8VF>;
4121 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4122 OpNode, v4f64x_info>, EVEX_V256,
4123 VEX_W, EVEX_CD8<32, CD8VF>;
4124 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4125 OpNode, v2f64x_info>, EVEX_V128,
4126 VEX_W, EVEX_CD8<32, CD8VF>;
4130 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
4131 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
4132 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
4133 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
4134 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
4135 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
4138 let Constraints = "$src1 = $dst" in {
4139 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4140 RegisterClass RC, ValueType OpVT,
4141 X86MemOperand x86memop, Operand memop,
4143 let isCommutable = 1 in
4144 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
4145 (ins RC:$src1, RC:$src2, RC:$src3),
4146 !strconcat(OpcodeStr,
4147 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4149 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
4151 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
4152 (ins RC:$src1, RC:$src2, f128mem:$src3),
4153 !strconcat(OpcodeStr,
4154 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4156 (OpVT (OpNode RC:$src2, RC:$src1,
4157 (mem_frag addr:$src3))))]>;
4159 } // Constraints = "$src1 = $dst"
4161 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
4162 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4163 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
4164 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4165 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
4166 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4167 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
4168 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4169 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
4170 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4171 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
4172 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4173 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
4174 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4175 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
4176 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4178 //===----------------------------------------------------------------------===//
4179 // AVX-512 Scalar convert from sign integer to float/double
4180 //===----------------------------------------------------------------------===//
4182 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4183 X86MemOperand x86memop, string asm> {
4184 let hasSideEffects = 0 in {
4185 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
4186 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4189 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
4190 (ins DstRC:$src1, x86memop:$src),
4191 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4193 } // hasSideEffects = 0
4196 let Predicates = [HasAVX512] in {
4197 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
4198 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4199 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
4200 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4201 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
4202 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4203 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
4204 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4206 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4207 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4208 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4209 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4210 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4211 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4212 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4213 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4215 def : Pat<(f32 (sint_to_fp GR32:$src)),
4216 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4217 def : Pat<(f32 (sint_to_fp GR64:$src)),
4218 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4219 def : Pat<(f64 (sint_to_fp GR32:$src)),
4220 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4221 def : Pat<(f64 (sint_to_fp GR64:$src)),
4222 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4224 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
4225 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4226 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
4227 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4228 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
4229 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4230 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
4231 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4233 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4234 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4235 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4236 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4237 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4238 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4239 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4240 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4242 def : Pat<(f32 (uint_to_fp GR32:$src)),
4243 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4244 def : Pat<(f32 (uint_to_fp GR64:$src)),
4245 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4246 def : Pat<(f64 (uint_to_fp GR32:$src)),
4247 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4248 def : Pat<(f64 (uint_to_fp GR64:$src)),
4249 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4252 //===----------------------------------------------------------------------===//
4253 // AVX-512 Scalar convert from float/double to integer
4254 //===----------------------------------------------------------------------===//
4255 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4256 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4258 let hasSideEffects = 0 in {
4259 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4260 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4261 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4262 Requires<[HasAVX512]>;
4264 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4265 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4266 Requires<[HasAVX512]>;
4267 } // hasSideEffects = 0
4269 let Predicates = [HasAVX512] in {
4270 // Convert float/double to signed/unsigned int 32/64
4271 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4272 ssmem, sse_load_f32, "cvtss2si">,
4273 XS, EVEX_CD8<32, CD8VT1>;
4274 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4275 ssmem, sse_load_f32, "cvtss2si">,
4276 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4277 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4278 ssmem, sse_load_f32, "cvtss2usi">,
4279 XS, EVEX_CD8<32, CD8VT1>;
4280 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4281 int_x86_avx512_cvtss2usi64, ssmem,
4282 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4283 EVEX_CD8<32, CD8VT1>;
4284 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4285 sdmem, sse_load_f64, "cvtsd2si">,
4286 XD, EVEX_CD8<64, CD8VT1>;
4287 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4288 sdmem, sse_load_f64, "cvtsd2si">,
4289 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4290 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4291 sdmem, sse_load_f64, "cvtsd2usi">,
4292 XD, EVEX_CD8<64, CD8VT1>;
4293 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4294 int_x86_avx512_cvtsd2usi64, sdmem,
4295 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4296 EVEX_CD8<64, CD8VT1>;
4298 let isCodeGenOnly = 1 in {
4299 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4300 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4301 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4302 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4303 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4304 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4305 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4306 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4307 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4308 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4309 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4310 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4312 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4313 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
4314 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4315 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4316 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
4317 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4318 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4319 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4320 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4321 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4322 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
4323 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4324 } // isCodeGenOnly = 1
4326 // Convert float/double to signed/unsigned int 32/64 with truncation
4327 let isCodeGenOnly = 1 in {
4328 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4329 ssmem, sse_load_f32, "cvttss2si">,
4330 XS, EVEX_CD8<32, CD8VT1>;
4331 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4332 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4333 "cvttss2si">, XS, VEX_W,
4334 EVEX_CD8<32, CD8VT1>;
4335 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4336 sdmem, sse_load_f64, "cvttsd2si">, XD,
4337 EVEX_CD8<64, CD8VT1>;
4338 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4339 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4340 "cvttsd2si">, XD, VEX_W,
4341 EVEX_CD8<64, CD8VT1>;
4342 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4343 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4344 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4345 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4346 int_x86_avx512_cvttss2usi64, ssmem,
4347 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4348 EVEX_CD8<32, CD8VT1>;
4349 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4350 int_x86_avx512_cvttsd2usi,
4351 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4352 EVEX_CD8<64, CD8VT1>;
4353 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4354 int_x86_avx512_cvttsd2usi64, sdmem,
4355 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4356 EVEX_CD8<64, CD8VT1>;
4357 } // isCodeGenOnly = 1
4359 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4360 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4362 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4363 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4364 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4365 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4366 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4367 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4370 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4371 loadf32, "cvttss2si">, XS,
4372 EVEX_CD8<32, CD8VT1>;
4373 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4374 loadf32, "cvttss2usi">, XS,
4375 EVEX_CD8<32, CD8VT1>;
4376 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4377 loadf32, "cvttss2si">, XS, VEX_W,
4378 EVEX_CD8<32, CD8VT1>;
4379 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4380 loadf32, "cvttss2usi">, XS, VEX_W,
4381 EVEX_CD8<32, CD8VT1>;
4382 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4383 loadf64, "cvttsd2si">, XD,
4384 EVEX_CD8<64, CD8VT1>;
4385 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4386 loadf64, "cvttsd2usi">, XD,
4387 EVEX_CD8<64, CD8VT1>;
4388 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4389 loadf64, "cvttsd2si">, XD, VEX_W,
4390 EVEX_CD8<64, CD8VT1>;
4391 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4392 loadf64, "cvttsd2usi">, XD, VEX_W,
4393 EVEX_CD8<64, CD8VT1>;
4395 //===----------------------------------------------------------------------===//
4396 // AVX-512 Convert form float to double and back
4397 //===----------------------------------------------------------------------===//
4398 let hasSideEffects = 0 in {
4399 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4400 (ins FR32X:$src1, FR32X:$src2),
4401 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4402 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4404 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4405 (ins FR32X:$src1, f32mem:$src2),
4406 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4407 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4408 EVEX_CD8<32, CD8VT1>;
4410 // Convert scalar double to scalar single
4411 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4412 (ins FR64X:$src1, FR64X:$src2),
4413 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4414 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4416 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4417 (ins FR64X:$src1, f64mem:$src2),
4418 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4419 []>, EVEX_4V, VEX_LIG, VEX_W,
4420 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4423 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4424 Requires<[HasAVX512]>;
4425 def : Pat<(fextend (loadf32 addr:$src)),
4426 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4428 def : Pat<(extloadf32 addr:$src),
4429 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4430 Requires<[HasAVX512, OptForSize]>;
4432 def : Pat<(extloadf32 addr:$src),
4433 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4434 Requires<[HasAVX512, OptForSpeed]>;
4436 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4437 Requires<[HasAVX512]>;
4439 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4440 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4441 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4443 let hasSideEffects = 0 in {
4444 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4445 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4447 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4448 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4449 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4450 [], d>, EVEX, EVEX_B, EVEX_RC;
4452 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4453 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4455 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4456 } // hasSideEffects = 0
4459 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4460 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4461 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4463 let hasSideEffects = 0 in {
4464 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4465 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4467 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4469 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4470 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4472 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4473 } // hasSideEffects = 0
4476 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4477 loadv8f64, f512mem, v8f32, v8f64,
4478 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4479 EVEX_CD8<64, CD8VF>;
4481 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4482 loadv4f64, f256mem, v8f64, v8f32,
4483 SSEPackedDouble>, EVEX_V512, PS,
4484 EVEX_CD8<32, CD8VH>;
4485 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4486 (VCVTPS2PDZrm addr:$src)>;
4488 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4489 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4490 (VCVTPD2PSZrr VR512:$src)>;
4492 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4493 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4494 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4496 //===----------------------------------------------------------------------===//
4497 // AVX-512 Vector convert from sign integer to float/double
4498 //===----------------------------------------------------------------------===//
4500 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4501 loadv8i64, i512mem, v16f32, v16i32,
4502 SSEPackedSingle>, EVEX_V512, PS,
4503 EVEX_CD8<32, CD8VF>;
4505 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4506 loadv4i64, i256mem, v8f64, v8i32,
4507 SSEPackedDouble>, EVEX_V512, XS,
4508 EVEX_CD8<32, CD8VH>;
4510 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4511 loadv16f32, f512mem, v16i32, v16f32,
4512 SSEPackedSingle>, EVEX_V512, XS,
4513 EVEX_CD8<32, CD8VF>;
4515 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4516 loadv8f64, f512mem, v8i32, v8f64,
4517 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4518 EVEX_CD8<64, CD8VF>;
4520 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4521 loadv16f32, f512mem, v16i32, v16f32,
4522 SSEPackedSingle>, EVEX_V512, PS,
4523 EVEX_CD8<32, CD8VF>;
4525 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4526 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4527 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4528 (VCVTTPS2UDQZrr VR512:$src)>;
4530 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4531 loadv8f64, f512mem, v8i32, v8f64,
4532 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4533 EVEX_CD8<64, CD8VF>;
4535 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4536 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4537 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4538 (VCVTTPD2UDQZrr VR512:$src)>;
4540 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4541 loadv4i64, f256mem, v8f64, v8i32,
4542 SSEPackedDouble>, EVEX_V512, XS,
4543 EVEX_CD8<32, CD8VH>;
4545 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4546 loadv16i32, f512mem, v16f32, v16i32,
4547 SSEPackedSingle>, EVEX_V512, XD,
4548 EVEX_CD8<32, CD8VF>;
4550 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4551 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4552 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4554 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4555 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4556 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4558 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4559 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4560 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4562 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4563 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4564 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4566 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4567 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4568 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4570 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4571 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4572 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4573 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4574 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4575 (VCVTDQ2PDZrr VR256X:$src)>;
4576 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4577 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4578 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4579 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4580 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4581 (VCVTUDQ2PDZrr VR256X:$src)>;
4583 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4584 RegisterClass DstRC, PatFrag mem_frag,
4585 X86MemOperand x86memop, Domain d> {
4586 let hasSideEffects = 0 in {
4587 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4588 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4590 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4591 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4592 [], d>, EVEX, EVEX_B, EVEX_RC;
4594 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4595 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4597 } // hasSideEffects = 0
4600 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4601 loadv16f32, f512mem, SSEPackedSingle>, PD,
4602 EVEX_V512, EVEX_CD8<32, CD8VF>;
4603 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4604 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4605 EVEX_V512, EVEX_CD8<64, CD8VF>;
4607 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4608 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4609 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4611 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4612 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4613 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4615 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4616 loadv16f32, f512mem, SSEPackedSingle>,
4617 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4618 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4619 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4620 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4622 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4623 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4624 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4626 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4627 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4628 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4630 let Predicates = [HasAVX512] in {
4631 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4632 (VCVTPD2PSZrm addr:$src)>;
4633 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4634 (VCVTPS2PDZrm addr:$src)>;
4637 //===----------------------------------------------------------------------===//
4638 // Half precision conversion instructions
4639 //===----------------------------------------------------------------------===//
4640 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4641 X86MemOperand x86memop> {
4642 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4643 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4645 let hasSideEffects = 0, mayLoad = 1 in
4646 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4647 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4650 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4651 X86MemOperand x86memop> {
4652 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4653 (ins srcRC:$src1, i32u8imm:$src2),
4654 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4656 let hasSideEffects = 0, mayStore = 1 in
4657 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4658 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4659 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4662 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4663 EVEX_CD8<32, CD8VH>;
4664 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4665 EVEX_CD8<32, CD8VH>;
4667 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4668 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4669 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4671 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4672 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4673 (VCVTPH2PSZrr VR256X:$src)>;
4675 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4676 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4677 "ucomiss">, PS, EVEX, VEX_LIG,
4678 EVEX_CD8<32, CD8VT1>;
4679 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4680 "ucomisd">, PD, EVEX,
4681 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4682 let Pattern = []<dag> in {
4683 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4684 "comiss">, PS, EVEX, VEX_LIG,
4685 EVEX_CD8<32, CD8VT1>;
4686 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4687 "comisd">, PD, EVEX,
4688 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4690 let isCodeGenOnly = 1 in {
4691 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4692 load, "ucomiss">, PS, EVEX, VEX_LIG,
4693 EVEX_CD8<32, CD8VT1>;
4694 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4695 load, "ucomisd">, PD, EVEX,
4696 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4698 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4699 load, "comiss">, PS, EVEX, VEX_LIG,
4700 EVEX_CD8<32, CD8VT1>;
4701 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4702 load, "comisd">, PD, EVEX,
4703 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4707 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4708 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4709 X86MemOperand x86memop> {
4710 let hasSideEffects = 0 in {
4711 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4712 (ins RC:$src1, RC:$src2),
4713 !strconcat(OpcodeStr,
4714 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4715 let mayLoad = 1 in {
4716 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4717 (ins RC:$src1, x86memop:$src2),
4718 !strconcat(OpcodeStr,
4719 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4724 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4725 EVEX_CD8<32, CD8VT1>;
4726 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4727 VEX_W, EVEX_CD8<64, CD8VT1>;
4728 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4729 EVEX_CD8<32, CD8VT1>;
4730 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4731 VEX_W, EVEX_CD8<64, CD8VT1>;
4733 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4734 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4735 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4736 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4738 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4739 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4740 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4741 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4743 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4744 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4745 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4746 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4748 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4749 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4750 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4751 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4753 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4754 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4755 X86VectorVTInfo _> {
4756 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4757 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4758 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4759 let mayLoad = 1 in {
4760 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4761 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4763 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4764 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4765 (ins _.ScalarMemOp:$src), OpcodeStr,
4766 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4768 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4773 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4774 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4775 EVEX_V512, EVEX_CD8<32, CD8VF>;
4776 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4777 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4779 // Define only if AVX512VL feature is present.
4780 let Predicates = [HasVLX] in {
4781 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4782 OpNode, v4f32x_info>,
4783 EVEX_V128, EVEX_CD8<32, CD8VF>;
4784 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4785 OpNode, v8f32x_info>,
4786 EVEX_V256, EVEX_CD8<32, CD8VF>;
4787 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4788 OpNode, v2f64x_info>,
4789 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4790 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4791 OpNode, v4f64x_info>,
4792 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4796 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4797 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4799 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4800 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4801 (VRSQRT14PSZr VR512:$src)>;
4802 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4803 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4804 (VRSQRT14PDZr VR512:$src)>;
4806 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4807 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4808 (VRCP14PSZr VR512:$src)>;
4809 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4810 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4811 (VRCP14PDZr VR512:$src)>;
4813 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4814 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4817 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4818 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4819 "$src2, $src1", "$src1, $src2",
4820 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4821 (i32 FROUND_CURRENT))>;
4823 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4824 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4825 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4826 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4827 (i32 FROUND_NO_EXC))>, EVEX_B;
4829 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4830 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4831 "$src2, $src1", "$src1, $src2",
4832 (OpNode (_.VT _.RC:$src1),
4833 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4834 (i32 FROUND_CURRENT))>;
4837 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4838 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4839 EVEX_CD8<32, CD8VT1>;
4840 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4841 EVEX_CD8<64, CD8VT1>, VEX_W;
4844 let hasSideEffects = 0, Predicates = [HasERI] in {
4845 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4846 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4848 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4850 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4853 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4854 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4855 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4857 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4858 (ins _.RC:$src), OpcodeStr,
4859 "{sae}, $src", "$src, {sae}",
4860 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
4862 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4863 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4865 (bitconvert (_.LdFrag addr:$src))),
4866 (i32 FROUND_CURRENT))>;
4868 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4869 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4871 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4872 (i32 FROUND_CURRENT))>, EVEX_B;
4875 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4876 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4877 EVEX_CD8<32, CD8VF>;
4878 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4879 VEX_W, EVEX_CD8<32, CD8VF>;
4882 let Predicates = [HasERI], hasSideEffects = 0 in {
4884 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4885 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4886 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4889 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4890 SDNode OpNode, X86VectorVTInfo _>{
4891 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4892 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4893 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4894 let mayLoad = 1 in {
4895 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4896 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4898 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4900 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4901 (ins _.ScalarMemOp:$src), OpcodeStr,
4902 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4904 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4909 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4910 Intrinsic F32Int, Intrinsic F64Int,
4911 OpndItins itins_s, OpndItins itins_d> {
4912 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4913 (ins FR32X:$src1, FR32X:$src2),
4914 !strconcat(OpcodeStr,
4915 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4916 [], itins_s.rr>, XS, EVEX_4V;
4917 let isCodeGenOnly = 1 in
4918 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4919 (ins VR128X:$src1, VR128X:$src2),
4920 !strconcat(OpcodeStr,
4921 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4923 (F32Int VR128X:$src1, VR128X:$src2))],
4924 itins_s.rr>, XS, EVEX_4V;
4925 let mayLoad = 1 in {
4926 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4927 (ins FR32X:$src1, f32mem:$src2),
4928 !strconcat(OpcodeStr,
4929 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4930 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4931 let isCodeGenOnly = 1 in
4932 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4933 (ins VR128X:$src1, ssmem:$src2),
4934 !strconcat(OpcodeStr,
4935 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4937 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4938 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4940 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4941 (ins FR64X:$src1, FR64X:$src2),
4942 !strconcat(OpcodeStr,
4943 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4945 let isCodeGenOnly = 1 in
4946 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4947 (ins VR128X:$src1, VR128X:$src2),
4948 !strconcat(OpcodeStr,
4949 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4951 (F64Int VR128X:$src1, VR128X:$src2))],
4952 itins_s.rr>, XD, EVEX_4V, VEX_W;
4953 let mayLoad = 1 in {
4954 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4955 (ins FR64X:$src1, f64mem:$src2),
4956 !strconcat(OpcodeStr,
4957 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4958 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4959 let isCodeGenOnly = 1 in
4960 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4961 (ins VR128X:$src1, sdmem:$src2),
4962 !strconcat(OpcodeStr,
4963 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4965 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4966 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4970 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4972 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4974 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4975 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4977 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4978 // Define only if AVX512VL feature is present.
4979 let Predicates = [HasVLX] in {
4980 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4981 OpNode, v4f32x_info>,
4982 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4983 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4984 OpNode, v8f32x_info>,
4985 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4986 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4987 OpNode, v2f64x_info>,
4988 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4989 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4990 OpNode, v4f64x_info>,
4991 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4995 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4997 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4998 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4999 SSE_SQRTSS, SSE_SQRTSD>;
5001 let Predicates = [HasAVX512] in {
5002 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
5003 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
5004 (VSQRTPSZr VR512:$src1)>;
5005 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
5006 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
5007 (VSQRTPDZr VR512:$src1)>;
5009 def : Pat<(f32 (fsqrt FR32X:$src)),
5010 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5011 def : Pat<(f32 (fsqrt (load addr:$src))),
5012 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5013 Requires<[OptForSize]>;
5014 def : Pat<(f64 (fsqrt FR64X:$src)),
5015 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5016 def : Pat<(f64 (fsqrt (load addr:$src))),
5017 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5018 Requires<[OptForSize]>;
5020 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5021 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5022 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5023 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5024 Requires<[OptForSize]>;
5026 def : Pat<(f32 (X86frcp FR32X:$src)),
5027 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5028 def : Pat<(f32 (X86frcp (load addr:$src))),
5029 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5030 Requires<[OptForSize]>;
5032 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5033 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5034 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5036 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5037 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5039 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5040 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5041 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5043 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5044 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5048 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
5049 X86MemOperand x86memop, RegisterClass RC,
5050 PatFrag mem_frag, Domain d> {
5051 let ExeDomain = d in {
5052 // Intrinsic operation, reg.
5053 // Vector intrinsic operation, reg
5054 def r : AVX512AIi8<opc, MRMSrcReg,
5055 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
5056 !strconcat(OpcodeStr,
5057 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5060 // Vector intrinsic operation, mem
5061 def m : AVX512AIi8<opc, MRMSrcMem,
5062 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
5063 !strconcat(OpcodeStr,
5064 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5069 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
5070 loadv16f32, SSEPackedSingle>, EVEX_V512,
5071 EVEX_CD8<32, CD8VF>;
5073 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
5074 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
5076 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
5079 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
5080 loadv8f64, SSEPackedDouble>, EVEX_V512,
5081 VEX_W, EVEX_CD8<64, CD8VF>;
5083 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
5084 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
5086 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
5089 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5091 let ExeDomain = _.ExeDomain in {
5092 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5093 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5094 "$src3, $src2, $src1", "$src1, $src2, $src3",
5095 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5096 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5098 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5099 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5100 "{sae}, $src3, $src2, $src1", "$src1, $src2, $src3, {sae}",
5101 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5102 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5105 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5106 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5107 "$src3, $src2, $src1", "$src1, $src2, $src3",
5108 (_.VT (X86RndScale (_.VT _.RC:$src1),
5109 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5110 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5112 let Predicates = [HasAVX512] in {
5113 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5114 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5115 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5116 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5117 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5118 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5119 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5120 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5121 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5122 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5123 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5124 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5125 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5126 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5127 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5129 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5130 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5131 addr:$src, (i32 0x1))), _.FRC)>;
5132 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5133 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5134 addr:$src, (i32 0x2))), _.FRC)>;
5135 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5136 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5137 addr:$src, (i32 0x3))), _.FRC)>;
5138 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5139 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5140 addr:$src, (i32 0x4))), _.FRC)>;
5141 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5142 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5143 addr:$src, (i32 0xc))), _.FRC)>;
5147 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5148 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5150 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5151 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5153 let Predicates = [HasAVX512] in {
5154 def : Pat<(v16f32 (ffloor VR512:$src)),
5155 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
5156 def : Pat<(v16f32 (fnearbyint VR512:$src)),
5157 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
5158 def : Pat<(v16f32 (fceil VR512:$src)),
5159 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
5160 def : Pat<(v16f32 (frint VR512:$src)),
5161 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
5162 def : Pat<(v16f32 (ftrunc VR512:$src)),
5163 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
5165 def : Pat<(v8f64 (ffloor VR512:$src)),
5166 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
5167 def : Pat<(v8f64 (fnearbyint VR512:$src)),
5168 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
5169 def : Pat<(v8f64 (fceil VR512:$src)),
5170 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
5171 def : Pat<(v8f64 (frint VR512:$src)),
5172 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
5173 def : Pat<(v8f64 (ftrunc VR512:$src)),
5174 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
5176 //-------------------------------------------------
5177 // Integer truncate and extend operations
5178 //-------------------------------------------------
5180 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
5181 RegisterClass dstRC, RegisterClass srcRC,
5182 RegisterClass KRC, X86MemOperand x86memop> {
5183 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5185 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5188 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5189 (ins KRC:$mask, srcRC:$src),
5190 !strconcat(OpcodeStr,
5191 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5194 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5195 (ins KRC:$mask, srcRC:$src),
5196 !strconcat(OpcodeStr,
5197 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5200 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
5201 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5204 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5205 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
5206 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
5210 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
5211 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5212 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
5213 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5214 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
5215 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5216 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
5217 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5218 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
5219 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5220 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
5221 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5222 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
5223 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5224 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
5225 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5226 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
5227 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5228 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
5229 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5230 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
5231 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5232 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
5233 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5234 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
5235 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5236 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
5237 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5238 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
5239 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5241 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
5242 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
5243 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
5244 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
5245 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
5247 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5248 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
5249 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5250 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
5251 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5252 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
5253 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5254 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
5257 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5258 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5259 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5261 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5262 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5263 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5266 let mayLoad = 1 in {
5267 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5268 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5269 (DestInfo.VT (LdFrag addr:$src))>,
5274 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5275 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5276 let Predicates = [HasVLX, HasBWI] in {
5277 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5278 v16i8x_info, i64mem, LdFrag, OpNode>,
5279 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5281 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5282 v16i8x_info, i128mem, LdFrag, OpNode>,
5283 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5285 let Predicates = [HasBWI] in {
5286 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
5287 v32i8x_info, i256mem, LdFrag, OpNode>,
5288 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
5292 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5293 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5294 let Predicates = [HasVLX, HasAVX512] in {
5295 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5296 v16i8x_info, i32mem, LdFrag, OpNode>,
5297 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
5299 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5300 v16i8x_info, i64mem, LdFrag, OpNode>,
5301 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
5303 let Predicates = [HasAVX512] in {
5304 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5305 v16i8x_info, i128mem, LdFrag, OpNode>,
5306 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
5310 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5311 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5312 let Predicates = [HasVLX, HasAVX512] in {
5313 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5314 v16i8x_info, i16mem, LdFrag, OpNode>,
5315 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
5317 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5318 v16i8x_info, i32mem, LdFrag, OpNode>,
5319 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
5321 let Predicates = [HasAVX512] in {
5322 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5323 v16i8x_info, i64mem, LdFrag, OpNode>,
5324 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
5328 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5329 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5330 let Predicates = [HasVLX, HasAVX512] in {
5331 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5332 v8i16x_info, i64mem, LdFrag, OpNode>,
5333 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
5335 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5336 v8i16x_info, i128mem, LdFrag, OpNode>,
5337 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
5339 let Predicates = [HasAVX512] in {
5340 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5341 v16i16x_info, i256mem, LdFrag, OpNode>,
5342 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
5346 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5347 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5348 let Predicates = [HasVLX, HasAVX512] in {
5349 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5350 v8i16x_info, i32mem, LdFrag, OpNode>,
5351 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
5353 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5354 v8i16x_info, i64mem, LdFrag, OpNode>,
5355 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
5357 let Predicates = [HasAVX512] in {
5358 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5359 v8i16x_info, i128mem, LdFrag, OpNode>,
5360 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
5364 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5365 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
5367 let Predicates = [HasVLX, HasAVX512] in {
5368 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5369 v4i32x_info, i64mem, LdFrag, OpNode>,
5370 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
5372 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5373 v4i32x_info, i128mem, LdFrag, OpNode>,
5374 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
5376 let Predicates = [HasAVX512] in {
5377 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5378 v8i32x_info, i256mem, LdFrag, OpNode>,
5379 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
5383 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
5384 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
5385 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
5386 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
5387 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
5388 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
5391 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
5392 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
5393 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
5394 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
5395 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
5396 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
5398 //===----------------------------------------------------------------------===//
5399 // GATHER - SCATTER Operations
5401 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5402 X86MemOperand memop, PatFrag GatherNode> {
5403 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5404 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5405 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5406 !strconcat(OpcodeStr,
5407 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5408 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5409 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5410 vectoraddr:$src2))]>, EVEX, EVEX_K,
5411 EVEX_CD8<_.EltSize, CD8VT1>;
5414 let ExeDomain = SSEPackedDouble in {
5415 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", v8f64_info, vy64xmem,
5416 mgatherv8i32>, EVEX_V512, VEX_W;
5417 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", v8f64_info, vz64mem,
5418 mgatherv8i64>, EVEX_V512, VEX_W;
5421 let ExeDomain = SSEPackedSingle in {
5422 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", v16f32_info, vz32mem,
5423 mgatherv16i32>, EVEX_V512;
5424 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", v8f32x_info, vz64mem,
5425 mgatherv8i64>, EVEX_V512;
5428 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", v8i64_info, vy64xmem,
5429 mgatherv8i32>, EVEX_V512, VEX_W;
5430 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", v16i32_info, vz32mem,
5431 mgatherv16i32>, EVEX_V512;
5433 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", v8i64_info, vz64mem,
5434 mgatherv8i64>, EVEX_V512, VEX_W;
5435 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", v8i32x_info, vz64mem,
5436 mgatherv8i64>, EVEX_V512;
5438 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5439 X86MemOperand memop, PatFrag ScatterNode> {
5441 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5443 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5444 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5445 !strconcat(OpcodeStr,
5446 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5447 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5448 _.KRCWM:$mask, vectoraddr:$dst))]>,
5449 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5452 let ExeDomain = SSEPackedDouble in {
5453 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", v8f64_info, vy64xmem,
5454 mscatterv8i32>, EVEX_V512, VEX_W;
5455 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", v8f64_info, vz64mem,
5456 mscatterv8i64>, EVEX_V512, VEX_W;
5459 let ExeDomain = SSEPackedSingle in {
5460 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", v16f32_info, vz32mem,
5461 mscatterv16i32>, EVEX_V512;
5462 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", v8f32x_info, vz64mem,
5463 mscatterv8i64>, EVEX_V512;
5466 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", v8i64_info, vy64xmem,
5467 mscatterv8i32>, EVEX_V512, VEX_W;
5468 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", v16i32_info, vz32mem,
5469 mscatterv16i32>, EVEX_V512;
5471 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", v8i64_info, vz64mem,
5472 mscatterv8i64>, EVEX_V512, VEX_W;
5473 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", v8i32x_info, vz64mem,
5474 mscatterv8i64>, EVEX_V512;
5477 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5478 RegisterClass KRC, X86MemOperand memop> {
5479 let Predicates = [HasPFI], hasSideEffects = 1 in
5480 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5481 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5485 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5486 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5488 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5489 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5491 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5492 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5494 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5495 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5497 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5498 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5500 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5501 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5503 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5504 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5506 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5507 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5509 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5510 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5512 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5513 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5515 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5516 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5518 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5519 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5521 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5522 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5524 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5525 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5527 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5528 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5530 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5531 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5532 //===----------------------------------------------------------------------===//
5533 // VSHUFPS - VSHUFPD Operations
5535 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5536 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5538 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5539 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5540 !strconcat(OpcodeStr,
5541 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5542 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5543 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5544 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5545 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5546 (ins RC:$src1, RC:$src2, u8imm:$src3),
5547 !strconcat(OpcodeStr,
5548 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5549 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5550 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5551 EVEX_4V, Sched<[WriteShuffle]>;
5554 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5555 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5556 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5557 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5559 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5560 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5561 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5562 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5563 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5565 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5566 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5567 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5568 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5569 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5571 multiclass avx512_valign<X86VectorVTInfo _> {
5572 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5573 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5575 "$src3, $src2, $src1", "$src1, $src2, $src3",
5576 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5578 AVX512AIi8Base, EVEX_4V;
5580 // Also match valign of packed floats.
5581 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5582 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5585 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5586 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5587 !strconcat("valign"##_.Suffix,
5588 "\t{$src3, $src2, $src1, $dst|"
5589 "$dst, $src1, $src2, $src3}"),
5592 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5593 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5595 // Helper fragments to match sext vXi1 to vXiY.
5596 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5597 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5599 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5600 RegisterClass KRC, RegisterClass RC,
5601 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5603 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5604 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5606 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5607 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5609 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5610 !strconcat(OpcodeStr,
5611 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5613 let mayLoad = 1 in {
5614 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5615 (ins x86memop:$src),
5616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5618 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5619 (ins KRC:$mask, x86memop:$src),
5620 !strconcat(OpcodeStr,
5621 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5623 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5624 (ins KRC:$mask, x86memop:$src),
5625 !strconcat(OpcodeStr,
5626 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5628 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5629 (ins x86scalar_mop:$src),
5630 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5631 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5633 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5634 (ins KRC:$mask, x86scalar_mop:$src),
5635 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5636 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5637 []>, EVEX, EVEX_B, EVEX_K;
5638 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5639 (ins KRC:$mask, x86scalar_mop:$src),
5640 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5641 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5643 []>, EVEX, EVEX_B, EVEX_KZ;
5647 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5648 i512mem, i32mem, "{1to16}">, EVEX_V512,
5649 EVEX_CD8<32, CD8VF>;
5650 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5651 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5652 EVEX_CD8<64, CD8VF>;
5655 (bc_v16i32 (v16i1sextv16i32)),
5656 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5657 (VPABSDZrr VR512:$src)>;
5659 (bc_v8i64 (v8i1sextv8i64)),
5660 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5661 (VPABSQZrr VR512:$src)>;
5663 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5664 (v16i32 immAllZerosV), (i16 -1))),
5665 (VPABSDZrr VR512:$src)>;
5666 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5667 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5668 (VPABSQZrr VR512:$src)>;
5670 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5671 RegisterClass RC, RegisterClass KRC,
5672 X86MemOperand x86memop,
5673 X86MemOperand x86scalar_mop, string BrdcstStr> {
5674 let hasSideEffects = 0 in {
5675 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5677 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5680 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5681 (ins x86memop:$src),
5682 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5685 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5686 (ins x86scalar_mop:$src),
5687 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5688 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5690 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5691 (ins KRC:$mask, RC:$src),
5692 !strconcat(OpcodeStr,
5693 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5696 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5697 (ins KRC:$mask, x86memop:$src),
5698 !strconcat(OpcodeStr,
5699 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5702 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5703 (ins KRC:$mask, x86scalar_mop:$src),
5704 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5705 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5707 []>, EVEX, EVEX_KZ, EVEX_B;
5709 let Constraints = "$src1 = $dst" in {
5710 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5711 (ins RC:$src1, KRC:$mask, RC:$src2),
5712 !strconcat(OpcodeStr,
5713 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5716 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5717 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5718 !strconcat(OpcodeStr,
5719 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5722 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5723 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5724 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5725 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5726 []>, EVEX, EVEX_K, EVEX_B;
5731 let Predicates = [HasCDI] in {
5732 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5733 i512mem, i32mem, "{1to16}">,
5734 EVEX_V512, EVEX_CD8<32, CD8VF>;
5737 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5738 i512mem, i64mem, "{1to8}">,
5739 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5743 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5745 (VPCONFLICTDrrk VR512:$src1,
5746 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5748 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5750 (VPCONFLICTQrrk VR512:$src1,
5751 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5753 let Predicates = [HasCDI] in {
5754 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5755 i512mem, i32mem, "{1to16}">,
5756 EVEX_V512, EVEX_CD8<32, CD8VF>;
5759 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5760 i512mem, i64mem, "{1to8}">,
5761 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5765 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5767 (VPLZCNTDrrk VR512:$src1,
5768 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5770 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5772 (VPLZCNTQrrk VR512:$src1,
5773 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5775 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5776 (VPLZCNTDrm addr:$src)>;
5777 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5778 (VPLZCNTDrr VR512:$src)>;
5779 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5780 (VPLZCNTQrm addr:$src)>;
5781 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5782 (VPLZCNTQrr VR512:$src)>;
5784 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5785 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5786 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5788 def : Pat<(store VK1:$src, addr:$dst),
5790 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5791 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5793 def : Pat<(store VK8:$src, addr:$dst),
5795 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5796 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5798 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5799 (truncstore node:$val, node:$ptr), [{
5800 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5803 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5804 (MOV8mr addr:$dst, GR8:$src)>;
5806 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5807 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5808 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5809 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5812 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5813 string OpcodeStr, Predicate prd> {
5814 let Predicates = [prd] in
5815 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5817 let Predicates = [prd, HasVLX] in {
5818 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5819 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5823 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5824 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5826 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5828 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5830 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5834 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5836 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
5837 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
5838 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5839 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
5842 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
5843 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
5844 let Predicates = [prd] in
5845 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
5848 let Predicates = [prd, HasVLX] in {
5849 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
5851 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
5856 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
5857 avx512vl_i8_info, HasBWI>;
5858 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
5859 avx512vl_i16_info, HasBWI>, VEX_W;
5860 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
5861 avx512vl_i32_info, HasDQI>;
5862 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
5863 avx512vl_i64_info, HasDQI>, VEX_W;
5865 //===----------------------------------------------------------------------===//
5866 // AVX-512 - COMPRESS and EXPAND
5868 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5870 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5871 (ins _.KRCWM:$mask, _.RC:$src),
5872 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5873 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5874 _.ImmAllZerosV)))]>, EVEX_KZ;
5876 let Constraints = "$src0 = $dst" in
5877 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5878 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5879 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5880 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5881 _.RC:$src0)))]>, EVEX_K;
5883 let mayStore = 1 in {
5884 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5885 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5886 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5887 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5889 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5893 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5894 AVX512VLVectorVTInfo VTInfo> {
5895 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5897 let Predicates = [HasVLX] in {
5898 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5899 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5903 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5905 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5907 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5909 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5913 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5915 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5916 (ins _.KRCWM:$mask, _.RC:$src),
5917 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5918 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5919 _.ImmAllZerosV)))]>, EVEX_KZ;
5921 let Constraints = "$src0 = $dst" in
5922 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5923 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5924 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5925 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5926 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5928 let mayLoad = 1, Constraints = "$src0 = $dst" in
5929 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5930 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5931 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5932 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5934 (_.LdFrag addr:$src))),
5936 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5939 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5940 (ins _.KRCWM:$mask, _.MemOp:$src),
5941 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5942 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5943 (_.VT (bitconvert (_.LdFrag addr:$src))),
5944 _.ImmAllZerosV)))]>,
5945 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5948 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5949 AVX512VLVectorVTInfo VTInfo> {
5950 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5952 let Predicates = [HasVLX] in {
5953 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5954 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5958 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5960 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5962 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5964 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
5967 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
5968 // op(reg_vec2,mem_vec,imm)
5969 // op(reg_vec2,broadcast(eltVt),imm)
5970 //all instruction created with FROUND_CURRENT
5971 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5973 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5974 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5975 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5976 (OpNode (_.VT _.RC:$src1),
5979 (i32 FROUND_CURRENT))>;
5980 let mayLoad = 1 in {
5981 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5982 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5983 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5984 (OpNode (_.VT _.RC:$src1),
5985 (_.VT (bitconvert (_.LdFrag addr:$src2))),
5987 (i32 FROUND_CURRENT))>;
5988 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5989 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
5990 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
5991 "$src1, ${src2}"##_.BroadcastStr##", $src3",
5992 (OpNode (_.VT _.RC:$src1),
5993 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
5995 (i32 FROUND_CURRENT))>, EVEX_B;
5999 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6000 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6001 SDNode OpNode, X86VectorVTInfo _>{
6002 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6003 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6004 OpcodeStr, "$src3,{sae}, $src2, $src1",
6005 "$src1, $src2,{sae}, $src3",
6006 (OpNode (_.VT _.RC:$src1),
6009 (i32 FROUND_NO_EXC))>, EVEX_B;
6012 multiclass avx512_vfixupimm_float<string OpcodeStr, AVX512VLVectorVTInfo _,
6013 bits<8> opc = 0x54, SDNode OpNode = X86VFixupimm>{
6014 let Predicates = [HasAVX512] in {
6015 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6016 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6020 let Predicates = [HasAVX512, HasVLX] in {
6021 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6023 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6028 defm VFIXUPIMMPD : avx512_vfixupimm_float<"vfixupimmpd", avx512vl_f64_info>,
6029 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6030 defm VFIXUPIMMPS : avx512_vfixupimm_float<"vfixupimmps", avx512vl_f32_info>,
6031 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;