1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
756 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
757 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
758 VEX_W, EVEX_CD8<64, CD8VF>;
760 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
761 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
763 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
764 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
765 VEX_W, EVEX_CD8<64, CD8VF>;
767 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
768 (COPY_TO_REGCLASS (VPCMPGTDZrr
769 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
772 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
773 (COPY_TO_REGCLASS (VPCMPEQDZrr
774 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
775 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
777 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
778 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
779 SDNode OpNode, ValueType vt, Operand CC, string asm,
781 def rri : AVX512AIi8<opc, MRMSrcReg,
782 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
784 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
785 def rmi : AVX512AIi8<opc, MRMSrcMem,
786 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
787 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
788 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
789 // Accept explicit immediate argument form instead of comparison code.
790 let isAsmParserOnly = 1, hasSideEffects = 0 in {
791 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
792 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
793 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
794 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
795 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
796 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
800 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
801 X86cmpm, v16i32, AVXCC,
802 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
803 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
804 EVEX_V512, EVEX_CD8<32, CD8VF>;
805 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
806 X86cmpmu, v16i32, AVXCC,
807 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
808 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
809 EVEX_V512, EVEX_CD8<32, CD8VF>;
811 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
812 X86cmpm, v8i64, AVXCC,
813 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
815 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
816 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
817 X86cmpmu, v8i64, AVXCC,
818 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
819 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
820 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
822 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
823 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
824 X86MemOperand x86memop, ValueType vt,
825 string suffix, Domain d> {
826 def rri : AVX512PIi8<0xC2, MRMSrcReg,
827 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
828 !strconcat("vcmp${cc}", suffix,
829 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
830 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
831 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
832 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
833 !strconcat("vcmp${cc}", suffix,
834 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
836 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
837 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
838 !strconcat("vcmp${cc}", suffix,
839 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
841 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
843 // Accept explicit immediate argument form instead of comparison code.
844 let isAsmParserOnly = 1, hasSideEffects = 0 in {
845 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
846 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
849 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
850 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
851 !strconcat("vcmp", suffix,
852 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
856 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
857 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
859 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
860 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
863 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
864 (COPY_TO_REGCLASS (VCMPPSZrri
865 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
866 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
868 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
869 (COPY_TO_REGCLASS (VPCMPDZrri
870 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
873 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
874 (COPY_TO_REGCLASS (VPCMPUDZrri
875 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
876 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
879 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
880 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
882 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
883 (I8Imm imm:$cc)), GR16)>;
885 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
886 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
888 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
889 (I8Imm imm:$cc)), GR8)>;
891 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
892 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
894 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
895 (I8Imm imm:$cc)), GR16)>;
897 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
898 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
900 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
901 (I8Imm imm:$cc)), GR8)>;
903 // Mask register copy, including
904 // - copy between mask registers
905 // - load/store mask registers
906 // - copy from GPR to mask register and vice versa
908 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
909 string OpcodeStr, RegisterClass KRC,
910 ValueType vt, X86MemOperand x86memop> {
911 let hasSideEffects = 0 in {
912 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
913 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
915 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
917 [(set KRC:$dst, (vt (load addr:$src)))]>;
919 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
920 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
924 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
926 RegisterClass KRC, RegisterClass GRC> {
927 let hasSideEffects = 0 in {
928 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
929 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
930 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
931 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
935 let Predicates = [HasAVX512] in {
936 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
938 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
942 let Predicates = [HasAVX512] in {
943 // GR16 from/to 16-bit mask
944 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
945 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
946 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
947 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
949 // Store kreg in memory
950 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
951 (KMOVWmk addr:$dst, VK16:$src)>;
953 def : Pat<(store VK8:$src, addr:$dst),
954 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
956 def : Pat<(i1 (load addr:$src)),
957 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
959 def : Pat<(v8i1 (load addr:$src)),
960 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
962 def : Pat<(i1 (trunc (i32 GR32:$src))),
963 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
965 def : Pat<(i1 (trunc (i8 GR8:$src))),
967 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
969 def : Pat<(i1 (trunc (i16 GR16:$src))),
971 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
974 def : Pat<(i32 (zext VK1:$src)),
975 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
976 def : Pat<(i8 (zext VK1:$src)),
979 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
980 def : Pat<(i64 (zext VK1:$src)),
981 (AND64ri8 (SUBREG_TO_REG (i64 0),
982 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
983 def : Pat<(i16 (zext VK1:$src)),
985 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
988 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
989 let Predicates = [HasAVX512] in {
990 // GR from/to 8-bit mask without native support
991 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
993 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
995 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
997 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1000 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1001 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1002 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1003 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1007 // Mask unary operation
1009 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1010 RegisterClass KRC, SDPatternOperator OpNode> {
1011 let Predicates = [HasAVX512] in
1012 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1013 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1014 [(set KRC:$dst, (OpNode KRC:$src))]>;
1017 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1018 SDPatternOperator OpNode> {
1019 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1023 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1025 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1026 let Predicates = [HasAVX512] in
1027 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1029 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1030 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1032 defm : avx512_mask_unop_int<"knot", "KNOT">;
1034 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1035 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1036 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1038 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1039 def : Pat<(not VK8:$src),
1041 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1043 // Mask binary operation
1044 // - KAND, KANDN, KOR, KXNOR, KXOR
1045 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1046 RegisterClass KRC, SDPatternOperator OpNode> {
1047 let Predicates = [HasAVX512] in
1048 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1049 !strconcat(OpcodeStr,
1050 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1051 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1054 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1055 SDPatternOperator OpNode> {
1056 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1060 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1061 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1063 let isCommutable = 1 in {
1064 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1065 let isCommutable = 0 in
1066 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1067 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1068 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1069 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1072 def : Pat<(xor VK1:$src1, VK1:$src2),
1073 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1074 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1076 def : Pat<(or VK1:$src1, VK1:$src2),
1077 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1078 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1080 def : Pat<(and VK1:$src1, VK1:$src2),
1081 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1082 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1084 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1085 let Predicates = [HasAVX512] in
1086 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1087 (i16 GR16:$src1), (i16 GR16:$src2)),
1088 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1089 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1090 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1093 defm : avx512_mask_binop_int<"kand", "KAND">;
1094 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1095 defm : avx512_mask_binop_int<"kor", "KOR">;
1096 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1097 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1099 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1100 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1101 let Predicates = [HasAVX512] in
1102 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1104 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1105 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1108 defm : avx512_binop_pat<and, KANDWrr>;
1109 defm : avx512_binop_pat<andn, KANDNWrr>;
1110 defm : avx512_binop_pat<or, KORWrr>;
1111 defm : avx512_binop_pat<xnor, KXNORWrr>;
1112 defm : avx512_binop_pat<xor, KXORWrr>;
1115 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1116 RegisterClass KRC> {
1117 let Predicates = [HasAVX512] in
1118 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1119 !strconcat(OpcodeStr,
1120 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1123 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1124 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1128 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1129 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1130 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1131 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1134 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1135 let Predicates = [HasAVX512] in
1136 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1137 (i16 GR16:$src1), (i16 GR16:$src2)),
1138 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1139 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1140 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1142 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1145 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1147 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1148 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1149 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1150 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1153 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1154 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1158 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1160 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1161 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1162 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1165 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1167 let Predicates = [HasAVX512] in
1168 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1169 !strconcat(OpcodeStr,
1170 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1171 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1174 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1176 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1180 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1181 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1183 // Mask setting all 0s or 1s
1184 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1185 let Predicates = [HasAVX512] in
1186 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1187 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1188 [(set KRC:$dst, (VT Val))]>;
1191 multiclass avx512_mask_setop_w<PatFrag Val> {
1192 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1193 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1196 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1197 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1199 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1200 let Predicates = [HasAVX512] in {
1201 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1202 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1203 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1204 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1205 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1207 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1208 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1210 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1211 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1213 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1214 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1216 //===----------------------------------------------------------------------===//
1217 // AVX-512 - Aligned and unaligned load and store
1220 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1221 X86MemOperand x86memop, PatFrag ld_frag,
1222 string asm, Domain d, bit IsReMaterializable = 1> {
1223 let hasSideEffects = 0 in
1224 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1225 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1227 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1228 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1229 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1230 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1231 let Constraints = "$src1 = $dst" in {
1232 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1233 (ins RC:$src1, KRC:$mask, RC:$src2),
1235 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1237 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1238 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1240 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1241 [], d>, EVEX, EVEX_K;
1245 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1246 "vmovaps", SSEPackedSingle>,
1247 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1248 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1249 "vmovapd", SSEPackedDouble>,
1250 PD, EVEX_V512, VEX_W,
1251 EVEX_CD8<64, CD8VF>;
1252 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1253 "vmovups", SSEPackedSingle>,
1254 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1255 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1256 "vmovupd", SSEPackedDouble, 0>,
1257 PD, EVEX_V512, VEX_W,
1258 EVEX_CD8<64, CD8VF>;
1259 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1260 "vmovaps\t{$src, $dst|$dst, $src}",
1261 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1262 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
1263 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1264 "vmovapd\t{$src, $dst|$dst, $src}",
1265 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1266 SSEPackedDouble>, EVEX, EVEX_V512,
1267 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1268 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1269 "vmovups\t{$src, $dst|$dst, $src}",
1270 [(store (v16f32 VR512:$src), addr:$dst)],
1271 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
1272 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1273 "vmovupd\t{$src, $dst|$dst, $src}",
1274 [(store (v8f64 VR512:$src), addr:$dst)],
1275 SSEPackedDouble>, EVEX, EVEX_V512,
1276 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1278 let hasSideEffects = 0 in {
1279 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1281 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1283 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1285 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1286 EVEX, EVEX_V512, VEX_W;
1287 let mayStore = 1 in {
1288 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1289 (ins i512mem:$dst, VR512:$src),
1290 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1291 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1292 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1293 (ins i512mem:$dst, VR512:$src),
1294 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1295 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1297 let mayLoad = 1 in {
1298 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1300 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1301 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1302 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1304 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1305 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1309 // 512-bit aligned load/store
1310 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1311 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1313 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1314 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1315 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1316 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1318 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1319 RegisterClass RC, RegisterClass KRC,
1320 PatFrag ld_frag, X86MemOperand x86memop> {
1321 let hasSideEffects = 0 in
1322 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1323 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1324 let canFoldAsLoad = 1 in
1325 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1326 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1327 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1329 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1330 (ins x86memop:$dst, VR512:$src),
1331 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1332 let Constraints = "$src1 = $dst" in {
1333 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1334 (ins RC:$src1, KRC:$mask, RC:$src2),
1336 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1338 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1339 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1341 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1344 def rrkz : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1345 (ins KRC:$mask, RC:$src),
1347 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), []>,
1351 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1352 memopv16i32, i512mem>,
1353 EVEX_V512, EVEX_CD8<32, CD8VF>;
1354 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1355 memopv8i64, i512mem>,
1356 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1358 // 512-bit unaligned load/store
1359 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1360 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1362 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1363 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1364 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1365 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1367 let AddedComplexity = 20 in {
1368 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1369 (bc_v8i64 (v16i32 immAllZerosV)))),
1370 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1372 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1373 (v8i64 VR512:$src))),
1374 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1377 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1378 (v16i32 immAllZerosV))),
1379 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1381 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1382 (v16i32 VR512:$src))),
1383 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1385 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1386 (v16f32 VR512:$src2))),
1387 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1388 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1389 (v8f64 VR512:$src2))),
1390 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1391 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1392 (v16i32 VR512:$src2))),
1393 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1394 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1395 (v8i64 VR512:$src2))),
1396 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1398 // Move Int Doubleword to Packed Double Int
1400 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1401 "vmovd\t{$src, $dst|$dst, $src}",
1403 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1405 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1406 "vmovd\t{$src, $dst|$dst, $src}",
1408 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1409 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1410 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1411 "vmovq\t{$src, $dst|$dst, $src}",
1413 (v2i64 (scalar_to_vector GR64:$src)))],
1414 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1415 let isCodeGenOnly = 1 in {
1416 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1417 "vmovq\t{$src, $dst|$dst, $src}",
1418 [(set FR64:$dst, (bitconvert GR64:$src))],
1419 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1420 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1421 "vmovq\t{$src, $dst|$dst, $src}",
1422 [(set GR64:$dst, (bitconvert FR64:$src))],
1423 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1425 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1426 "vmovq\t{$src, $dst|$dst, $src}",
1427 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1428 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1429 EVEX_CD8<64, CD8VT1>;
1431 // Move Int Doubleword to Single Scalar
1433 let isCodeGenOnly = 1 in {
1434 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1435 "vmovd\t{$src, $dst|$dst, $src}",
1436 [(set FR32X:$dst, (bitconvert GR32:$src))],
1437 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1439 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1440 "vmovd\t{$src, $dst|$dst, $src}",
1441 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1442 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1445 // Move doubleword from xmm register to r/m32
1447 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1448 "vmovd\t{$src, $dst|$dst, $src}",
1449 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1450 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1452 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1453 (ins i32mem:$dst, VR128X:$src),
1454 "vmovd\t{$src, $dst|$dst, $src}",
1455 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1456 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1457 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1459 // Move quadword from xmm1 register to r/m64
1461 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1462 "vmovq\t{$src, $dst|$dst, $src}",
1463 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1465 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1466 Requires<[HasAVX512, In64BitMode]>;
1468 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1469 (ins i64mem:$dst, VR128X:$src),
1470 "vmovq\t{$src, $dst|$dst, $src}",
1471 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1472 addr:$dst)], IIC_SSE_MOVDQ>,
1473 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1474 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1476 // Move Scalar Single to Double Int
1478 let isCodeGenOnly = 1 in {
1479 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1481 "vmovd\t{$src, $dst|$dst, $src}",
1482 [(set GR32:$dst, (bitconvert FR32X:$src))],
1483 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1484 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1485 (ins i32mem:$dst, FR32X:$src),
1486 "vmovd\t{$src, $dst|$dst, $src}",
1487 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1488 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1491 // Move Quadword Int to Packed Quadword Int
1493 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1495 "vmovq\t{$src, $dst|$dst, $src}",
1497 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1498 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1500 //===----------------------------------------------------------------------===//
1501 // AVX-512 MOVSS, MOVSD
1502 //===----------------------------------------------------------------------===//
1504 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1505 SDNode OpNode, ValueType vt,
1506 X86MemOperand x86memop, PatFrag mem_pat> {
1507 let hasSideEffects = 0 in {
1508 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1509 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1510 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1511 (scalar_to_vector RC:$src2))))],
1512 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1513 let Constraints = "$src1 = $dst" in
1514 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1515 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1517 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1518 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1519 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1520 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1521 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1523 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1524 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1525 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1527 } //hasSideEffects = 0
1530 let ExeDomain = SSEPackedSingle in
1531 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1532 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1534 let ExeDomain = SSEPackedDouble in
1535 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1536 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1538 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1539 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1540 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1542 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1543 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1544 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1546 // For the disassembler
1547 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1548 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1549 (ins VR128X:$src1, FR32X:$src2),
1550 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1552 XS, EVEX_4V, VEX_LIG;
1553 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1554 (ins VR128X:$src1, FR64X:$src2),
1555 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1557 XD, EVEX_4V, VEX_LIG, VEX_W;
1560 let Predicates = [HasAVX512] in {
1561 let AddedComplexity = 15 in {
1562 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1563 // MOVS{S,D} to the lower bits.
1564 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1565 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1566 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1567 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1568 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1569 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1571 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1573 // Move low f32 and clear high bits.
1574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1575 (SUBREG_TO_REG (i32 0),
1576 (VMOVSSZrr (v4f32 (V_SET0)),
1577 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1579 (SUBREG_TO_REG (i32 0),
1580 (VMOVSSZrr (v4i32 (V_SET0)),
1581 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1584 let AddedComplexity = 20 in {
1585 // MOVSSrm zeros the high parts of the register; represent this
1586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1588 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1590 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1592 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1594 // MOVSDrm zeros the high parts of the register; represent this
1595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1597 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1599 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1601 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1603 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1604 def : Pat<(v2f64 (X86vzload addr:$src)),
1605 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1607 // Represent the same patterns above but in the form they appear for
1609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1611 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1614 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1617 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1620 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1621 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1622 FR32X:$src)), sub_xmm)>;
1623 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1624 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1625 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1626 FR64X:$src)), sub_xmm)>;
1627 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1628 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1629 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1631 // Move low f64 and clear high bits.
1632 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1633 (SUBREG_TO_REG (i32 0),
1634 (VMOVSDZrr (v2f64 (V_SET0)),
1635 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1637 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1638 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1639 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1641 // Extract and store.
1642 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1644 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1645 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1647 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1649 // Shuffle with VMOVSS
1650 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1651 (VMOVSSZrr (v4i32 VR128X:$src1),
1652 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1653 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1654 (VMOVSSZrr (v4f32 VR128X:$src1),
1655 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1658 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1659 (SUBREG_TO_REG (i32 0),
1660 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1661 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1663 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1664 (SUBREG_TO_REG (i32 0),
1665 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1666 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1669 // Shuffle with VMOVSD
1670 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1671 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1672 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1673 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1674 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1675 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1676 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1677 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1680 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1681 (SUBREG_TO_REG (i32 0),
1682 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1683 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1685 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1686 (SUBREG_TO_REG (i32 0),
1687 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1688 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1691 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1692 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1693 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1694 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1695 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1696 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1697 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1698 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1701 let AddedComplexity = 15 in
1702 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1704 "vmovq\t{$src, $dst|$dst, $src}",
1705 [(set VR128X:$dst, (v2i64 (X86vzmovl
1706 (v2i64 VR128X:$src))))],
1707 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1709 let AddedComplexity = 20 in
1710 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1712 "vmovq\t{$src, $dst|$dst, $src}",
1713 [(set VR128X:$dst, (v2i64 (X86vzmovl
1714 (loadv2i64 addr:$src))))],
1715 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1716 EVEX_CD8<8, CD8VT8>;
1718 let Predicates = [HasAVX512] in {
1719 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1720 let AddedComplexity = 20 in {
1721 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1722 (VMOVDI2PDIZrm addr:$src)>;
1723 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1724 (VMOV64toPQIZrr GR64:$src)>;
1725 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1726 (VMOVDI2PDIZrr GR32:$src)>;
1728 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1729 (VMOVDI2PDIZrm addr:$src)>;
1730 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1731 (VMOVDI2PDIZrm addr:$src)>;
1732 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1733 (VMOVZPQILo2PQIZrm addr:$src)>;
1734 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1735 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1736 def : Pat<(v2i64 (X86vzload addr:$src)),
1737 (VMOVZPQILo2PQIZrm addr:$src)>;
1740 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1741 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1742 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1743 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1744 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1745 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1746 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1749 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1750 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1752 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1753 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1755 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1756 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1758 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1759 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1761 //===----------------------------------------------------------------------===//
1762 // AVX-512 - Integer arithmetic
1764 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1765 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1766 X86MemOperand x86memop, PatFrag scalar_mfrag,
1767 X86MemOperand x86scalar_mop, string BrdcstStr,
1768 OpndItins itins, bit IsCommutable = 0> {
1769 let isCommutable = IsCommutable in
1770 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1771 (ins RC:$src1, RC:$src2),
1772 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1773 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1775 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1776 (ins RC:$src1, x86memop:$src2),
1777 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1778 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1780 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1781 (ins RC:$src1, x86scalar_mop:$src2),
1782 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1783 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1784 [(set RC:$dst, (OpNode RC:$src1,
1785 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1786 itins.rm>, EVEX_4V, EVEX_B;
1788 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1789 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1790 PatFrag memop_frag, X86MemOperand x86memop,
1792 bit IsCommutable = 0> {
1793 let isCommutable = IsCommutable in
1794 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1795 (ins RC:$src1, RC:$src2),
1796 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1797 []>, EVEX_4V, VEX_W;
1798 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1799 (ins RC:$src1, x86memop:$src2),
1800 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1801 []>, EVEX_4V, VEX_W;
1804 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1805 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1806 EVEX_V512, EVEX_CD8<32, CD8VF>;
1808 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1809 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1810 EVEX_V512, EVEX_CD8<32, CD8VF>;
1812 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1813 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1814 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1816 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1817 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1818 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1820 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1821 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1822 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1824 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1825 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1826 EVEX_V512, EVEX_CD8<64, CD8VF>;
1828 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1829 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1830 EVEX_CD8<64, CD8VF>;
1832 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1833 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1835 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1836 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1837 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1838 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1839 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1840 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1842 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1843 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1844 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1845 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1846 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1847 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1849 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1850 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1851 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1852 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1853 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1854 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1856 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1857 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1858 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1859 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1860 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1861 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1863 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1864 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1865 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1866 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1867 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1868 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1870 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1871 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1872 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1873 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1874 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1875 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1876 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1877 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1878 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1879 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1880 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1881 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1882 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1883 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1884 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1885 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1886 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1887 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1888 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1889 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1890 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1891 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1892 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1893 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1894 //===----------------------------------------------------------------------===//
1895 // AVX-512 - Unpack Instructions
1896 //===----------------------------------------------------------------------===//
1898 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1899 PatFrag mem_frag, RegisterClass RC,
1900 X86MemOperand x86memop, string asm,
1902 def rr : AVX512PI<opc, MRMSrcReg,
1903 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1905 (vt (OpNode RC:$src1, RC:$src2)))],
1907 def rm : AVX512PI<opc, MRMSrcMem,
1908 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1910 (vt (OpNode RC:$src1,
1911 (bitconvert (mem_frag addr:$src2)))))],
1915 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1916 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1917 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1918 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1919 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1920 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1921 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1922 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1923 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1924 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1925 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1926 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1928 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1929 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1930 X86MemOperand x86memop> {
1931 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1932 (ins RC:$src1, RC:$src2),
1933 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1934 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1935 IIC_SSE_UNPCK>, EVEX_4V;
1936 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1937 (ins RC:$src1, x86memop:$src2),
1938 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1939 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1940 (bitconvert (memop_frag addr:$src2)))))],
1941 IIC_SSE_UNPCK>, EVEX_4V;
1943 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1944 VR512, memopv16i32, i512mem>, EVEX_V512,
1945 EVEX_CD8<32, CD8VF>;
1946 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1947 VR512, memopv8i64, i512mem>, EVEX_V512,
1948 VEX_W, EVEX_CD8<64, CD8VF>;
1949 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1950 VR512, memopv16i32, i512mem>, EVEX_V512,
1951 EVEX_CD8<32, CD8VF>;
1952 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1953 VR512, memopv8i64, i512mem>, EVEX_V512,
1954 VEX_W, EVEX_CD8<64, CD8VF>;
1955 //===----------------------------------------------------------------------===//
1959 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1960 SDNode OpNode, PatFrag mem_frag,
1961 X86MemOperand x86memop, ValueType OpVT> {
1962 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1963 (ins RC:$src1, i8imm:$src2),
1964 !strconcat(OpcodeStr,
1965 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1967 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1969 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1970 (ins x86memop:$src1, i8imm:$src2),
1971 !strconcat(OpcodeStr,
1972 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1974 (OpVT (OpNode (mem_frag addr:$src1),
1975 (i8 imm:$src2))))]>, EVEX;
1978 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1979 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1981 let ExeDomain = SSEPackedSingle in
1982 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1983 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1984 EVEX_CD8<32, CD8VF>;
1985 let ExeDomain = SSEPackedDouble in
1986 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1987 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1988 VEX_W, EVEX_CD8<32, CD8VF>;
1990 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1991 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1992 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1993 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1995 //===----------------------------------------------------------------------===//
1996 // AVX-512 Logical Instructions
1997 //===----------------------------------------------------------------------===//
1999 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
2000 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2001 EVEX_V512, EVEX_CD8<32, CD8VF>;
2002 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
2003 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2004 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2005 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
2006 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2007 EVEX_V512, EVEX_CD8<32, CD8VF>;
2008 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
2009 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2010 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2011 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
2012 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2013 EVEX_V512, EVEX_CD8<32, CD8VF>;
2014 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
2015 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2016 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2017 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
2018 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2019 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2020 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
2021 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
2022 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2024 //===----------------------------------------------------------------------===//
2025 // AVX-512 FP arithmetic
2026 //===----------------------------------------------------------------------===//
2028 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2030 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2031 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2032 EVEX_CD8<32, CD8VT1>;
2033 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2034 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2035 EVEX_CD8<64, CD8VT1>;
2038 let isCommutable = 1 in {
2039 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2040 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2041 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2042 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2044 let isCommutable = 0 in {
2045 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2046 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2049 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2050 RegisterClass RC, ValueType vt,
2051 X86MemOperand x86memop, PatFrag mem_frag,
2052 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2054 Domain d, OpndItins itins, bit commutable> {
2055 let isCommutable = commutable in
2056 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2057 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2058 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2060 let mayLoad = 1 in {
2061 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2062 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2063 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2064 itins.rm, d>, EVEX_4V;
2065 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2066 (ins RC:$src1, x86scalar_mop:$src2),
2067 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2068 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2069 [(set RC:$dst, (OpNode RC:$src1,
2070 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2071 itins.rm, d>, EVEX_4V, EVEX_B;
2075 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2076 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2077 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2079 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2080 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2081 SSE_ALU_ITINS_P.d, 1>,
2082 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2084 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2085 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2086 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2087 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2088 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2089 SSE_ALU_ITINS_P.d, 1>,
2090 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2092 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2093 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2094 SSE_ALU_ITINS_P.s, 1>,
2095 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2096 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2097 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2098 SSE_ALU_ITINS_P.s, 1>,
2099 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2101 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2102 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2103 SSE_ALU_ITINS_P.d, 1>,
2104 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2105 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2106 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2107 SSE_ALU_ITINS_P.d, 1>,
2108 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2110 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2111 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2112 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2113 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2114 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2115 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2117 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2118 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2119 SSE_ALU_ITINS_P.d, 0>,
2120 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2121 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2122 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2123 SSE_ALU_ITINS_P.d, 0>,
2124 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2126 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2127 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2128 (i16 -1), FROUND_CURRENT)),
2129 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2131 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2132 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2133 (i8 -1), FROUND_CURRENT)),
2134 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2136 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2137 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2138 (i16 -1), FROUND_CURRENT)),
2139 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2141 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2142 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2143 (i8 -1), FROUND_CURRENT)),
2144 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2145 //===----------------------------------------------------------------------===//
2146 // AVX-512 VPTESTM instructions
2147 //===----------------------------------------------------------------------===//
2149 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2150 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2151 SDNode OpNode, ValueType vt> {
2152 def rr : AVX512PI<opc, MRMSrcReg,
2153 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2154 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2155 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2156 SSEPackedInt>, EVEX_4V;
2157 def rm : AVX512PI<opc, MRMSrcMem,
2158 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2159 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2160 [(set KRC:$dst, (OpNode (vt RC:$src1),
2161 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2164 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2165 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2166 EVEX_CD8<32, CD8VF>;
2167 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2168 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2169 EVEX_CD8<64, CD8VF>;
2171 let Predicates = [HasCDI] in {
2172 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2173 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2174 EVEX_CD8<32, CD8VF>;
2175 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2176 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2177 EVEX_CD8<64, CD8VF>;
2180 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2181 (v16i32 VR512:$src2), (i16 -1))),
2182 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2184 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2185 (v8i64 VR512:$src2), (i8 -1))),
2186 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2187 //===----------------------------------------------------------------------===//
2188 // AVX-512 Shift instructions
2189 //===----------------------------------------------------------------------===//
2190 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2191 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2192 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2193 RegisterClass KRC> {
2194 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2195 (ins RC:$src1, i8imm:$src2),
2196 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2197 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2198 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2199 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2200 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2201 !strconcat(OpcodeStr,
2202 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2203 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2204 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2205 (ins x86memop:$src1, i8imm:$src2),
2206 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2207 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2208 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2209 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2210 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2211 !strconcat(OpcodeStr,
2212 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2213 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2216 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2217 RegisterClass RC, ValueType vt, ValueType SrcVT,
2218 PatFrag bc_frag, RegisterClass KRC> {
2219 // src2 is always 128-bit
2220 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2221 (ins RC:$src1, VR128X:$src2),
2222 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2223 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2224 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2225 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2226 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2227 !strconcat(OpcodeStr,
2228 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2229 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2230 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2231 (ins RC:$src1, i128mem:$src2),
2232 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2233 [(set RC:$dst, (vt (OpNode RC:$src1,
2234 (bc_frag (memopv2i64 addr:$src2)))))],
2235 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2236 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2237 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2238 !strconcat(OpcodeStr,
2239 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2240 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2243 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2244 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2245 EVEX_V512, EVEX_CD8<32, CD8VF>;
2246 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2247 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2248 EVEX_CD8<32, CD8VQ>;
2250 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2251 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2252 EVEX_CD8<64, CD8VF>, VEX_W;
2253 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2254 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2255 EVEX_CD8<64, CD8VQ>, VEX_W;
2257 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2258 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2259 EVEX_CD8<32, CD8VF>;
2260 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2261 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2262 EVEX_CD8<32, CD8VQ>;
2264 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2265 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2266 EVEX_CD8<64, CD8VF>, VEX_W;
2267 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2268 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2269 EVEX_CD8<64, CD8VQ>, VEX_W;
2271 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2272 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2273 EVEX_V512, EVEX_CD8<32, CD8VF>;
2274 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2275 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2276 EVEX_CD8<32, CD8VQ>;
2278 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2279 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2280 EVEX_CD8<64, CD8VF>, VEX_W;
2281 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2282 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2283 EVEX_CD8<64, CD8VQ>, VEX_W;
2285 //===-------------------------------------------------------------------===//
2286 // Variable Bit Shifts
2287 //===-------------------------------------------------------------------===//
2288 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2289 RegisterClass RC, ValueType vt,
2290 X86MemOperand x86memop, PatFrag mem_frag> {
2291 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2292 (ins RC:$src1, RC:$src2),
2293 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2295 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2297 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2298 (ins RC:$src1, x86memop:$src2),
2299 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2301 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2305 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2306 i512mem, memopv16i32>, EVEX_V512,
2307 EVEX_CD8<32, CD8VF>;
2308 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2309 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2310 EVEX_CD8<64, CD8VF>;
2311 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2312 i512mem, memopv16i32>, EVEX_V512,
2313 EVEX_CD8<32, CD8VF>;
2314 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2315 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2316 EVEX_CD8<64, CD8VF>;
2317 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2318 i512mem, memopv16i32>, EVEX_V512,
2319 EVEX_CD8<32, CD8VF>;
2320 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2321 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2322 EVEX_CD8<64, CD8VF>;
2324 //===----------------------------------------------------------------------===//
2325 // AVX-512 - MOVDDUP
2326 //===----------------------------------------------------------------------===//
2328 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2329 X86MemOperand x86memop, PatFrag memop_frag> {
2330 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2331 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2332 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2333 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2334 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2336 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2339 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2340 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2341 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2342 (VMOVDDUPZrm addr:$src)>;
2344 //===---------------------------------------------------------------------===//
2345 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2346 //===---------------------------------------------------------------------===//
2347 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2348 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2349 X86MemOperand x86memop> {
2350 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2351 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2352 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2354 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2355 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2356 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2359 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2360 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2361 EVEX_CD8<32, CD8VF>;
2362 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2363 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2364 EVEX_CD8<32, CD8VF>;
2366 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2367 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2368 (VMOVSHDUPZrm addr:$src)>;
2369 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2370 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2371 (VMOVSLDUPZrm addr:$src)>;
2373 //===----------------------------------------------------------------------===//
2374 // Move Low to High and High to Low packed FP Instructions
2375 //===----------------------------------------------------------------------===//
2376 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2377 (ins VR128X:$src1, VR128X:$src2),
2378 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2379 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2380 IIC_SSE_MOV_LH>, EVEX_4V;
2381 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2382 (ins VR128X:$src1, VR128X:$src2),
2383 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2384 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2385 IIC_SSE_MOV_LH>, EVEX_4V;
2387 let Predicates = [HasAVX512] in {
2389 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2390 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2391 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2392 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2395 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2396 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2399 //===----------------------------------------------------------------------===//
2400 // FMA - Fused Multiply Operations
2402 let Constraints = "$src1 = $dst" in {
2403 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2404 RegisterClass RC, X86MemOperand x86memop,
2405 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2406 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2407 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2408 (ins RC:$src1, RC:$src2, RC:$src3),
2409 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2410 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2413 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2414 (ins RC:$src1, RC:$src2, x86memop:$src3),
2415 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2416 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2417 (mem_frag addr:$src3))))]>;
2418 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2419 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2420 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2421 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2422 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2423 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2425 } // Constraints = "$src1 = $dst"
2427 let ExeDomain = SSEPackedSingle in {
2428 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2429 memopv16f32, f32mem, loadf32, "{1to16}",
2430 X86Fmadd, v16f32>, EVEX_V512,
2431 EVEX_CD8<32, CD8VF>;
2432 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2433 memopv16f32, f32mem, loadf32, "{1to16}",
2434 X86Fmsub, v16f32>, EVEX_V512,
2435 EVEX_CD8<32, CD8VF>;
2436 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2437 memopv16f32, f32mem, loadf32, "{1to16}",
2438 X86Fmaddsub, v16f32>,
2439 EVEX_V512, EVEX_CD8<32, CD8VF>;
2440 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2441 memopv16f32, f32mem, loadf32, "{1to16}",
2442 X86Fmsubadd, v16f32>,
2443 EVEX_V512, EVEX_CD8<32, CD8VF>;
2444 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2445 memopv16f32, f32mem, loadf32, "{1to16}",
2446 X86Fnmadd, v16f32>, EVEX_V512,
2447 EVEX_CD8<32, CD8VF>;
2448 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2449 memopv16f32, f32mem, loadf32, "{1to16}",
2450 X86Fnmsub, v16f32>, EVEX_V512,
2451 EVEX_CD8<32, CD8VF>;
2453 let ExeDomain = SSEPackedDouble in {
2454 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2455 memopv8f64, f64mem, loadf64, "{1to8}",
2456 X86Fmadd, v8f64>, EVEX_V512,
2457 VEX_W, EVEX_CD8<64, CD8VF>;
2458 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2459 memopv8f64, f64mem, loadf64, "{1to8}",
2460 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2461 EVEX_CD8<64, CD8VF>;
2462 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2463 memopv8f64, f64mem, loadf64, "{1to8}",
2464 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2465 EVEX_CD8<64, CD8VF>;
2466 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2467 memopv8f64, f64mem, loadf64, "{1to8}",
2468 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2469 EVEX_CD8<64, CD8VF>;
2470 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2471 memopv8f64, f64mem, loadf64, "{1to8}",
2472 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2473 EVEX_CD8<64, CD8VF>;
2474 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2475 memopv8f64, f64mem, loadf64, "{1to8}",
2476 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2477 EVEX_CD8<64, CD8VF>;
2480 let Constraints = "$src1 = $dst" in {
2481 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2482 RegisterClass RC, X86MemOperand x86memop,
2483 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2484 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2486 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2487 (ins RC:$src1, RC:$src3, x86memop:$src2),
2488 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2489 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2490 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2491 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2492 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2493 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2494 [(set RC:$dst, (OpNode RC:$src1,
2495 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2497 } // Constraints = "$src1 = $dst"
2500 let ExeDomain = SSEPackedSingle in {
2501 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2502 memopv16f32, f32mem, loadf32, "{1to16}",
2503 X86Fmadd, v16f32>, EVEX_V512,
2504 EVEX_CD8<32, CD8VF>;
2505 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2506 memopv16f32, f32mem, loadf32, "{1to16}",
2507 X86Fmsub, v16f32>, EVEX_V512,
2508 EVEX_CD8<32, CD8VF>;
2509 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2510 memopv16f32, f32mem, loadf32, "{1to16}",
2511 X86Fmaddsub, v16f32>,
2512 EVEX_V512, EVEX_CD8<32, CD8VF>;
2513 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2514 memopv16f32, f32mem, loadf32, "{1to16}",
2515 X86Fmsubadd, v16f32>,
2516 EVEX_V512, EVEX_CD8<32, CD8VF>;
2517 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2518 memopv16f32, f32mem, loadf32, "{1to16}",
2519 X86Fnmadd, v16f32>, EVEX_V512,
2520 EVEX_CD8<32, CD8VF>;
2521 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2522 memopv16f32, f32mem, loadf32, "{1to16}",
2523 X86Fnmsub, v16f32>, EVEX_V512,
2524 EVEX_CD8<32, CD8VF>;
2526 let ExeDomain = SSEPackedDouble in {
2527 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2528 memopv8f64, f64mem, loadf64, "{1to8}",
2529 X86Fmadd, v8f64>, EVEX_V512,
2530 VEX_W, EVEX_CD8<64, CD8VF>;
2531 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2532 memopv8f64, f64mem, loadf64, "{1to8}",
2533 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2534 EVEX_CD8<64, CD8VF>;
2535 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2536 memopv8f64, f64mem, loadf64, "{1to8}",
2537 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2538 EVEX_CD8<64, CD8VF>;
2539 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2540 memopv8f64, f64mem, loadf64, "{1to8}",
2541 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2542 EVEX_CD8<64, CD8VF>;
2543 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2544 memopv8f64, f64mem, loadf64, "{1to8}",
2545 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2546 EVEX_CD8<64, CD8VF>;
2547 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2548 memopv8f64, f64mem, loadf64, "{1to8}",
2549 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2550 EVEX_CD8<64, CD8VF>;
2554 let Constraints = "$src1 = $dst" in {
2555 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2556 RegisterClass RC, ValueType OpVT,
2557 X86MemOperand x86memop, Operand memop,
2559 let isCommutable = 1 in
2560 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2561 (ins RC:$src1, RC:$src2, RC:$src3),
2562 !strconcat(OpcodeStr,
2563 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2565 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2567 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2568 (ins RC:$src1, RC:$src2, f128mem:$src3),
2569 !strconcat(OpcodeStr,
2570 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2572 (OpVT (OpNode RC:$src2, RC:$src1,
2573 (mem_frag addr:$src3))))]>;
2576 } // Constraints = "$src1 = $dst"
2578 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2579 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2580 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2581 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2582 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2583 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2584 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2585 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2586 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2587 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2588 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2589 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2590 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2591 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2592 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2593 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2595 //===----------------------------------------------------------------------===//
2596 // AVX-512 Scalar convert from sign integer to float/double
2597 //===----------------------------------------------------------------------===//
2599 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2600 X86MemOperand x86memop, string asm> {
2601 let hasSideEffects = 0 in {
2602 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2603 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2606 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2607 (ins DstRC:$src1, x86memop:$src),
2608 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2610 } // hasSideEffects = 0
2612 let Predicates = [HasAVX512] in {
2613 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2614 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2615 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2616 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2617 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2618 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2619 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2620 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2622 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2623 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2624 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2625 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2626 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2627 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2628 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2629 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2631 def : Pat<(f32 (sint_to_fp GR32:$src)),
2632 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2633 def : Pat<(f32 (sint_to_fp GR64:$src)),
2634 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2635 def : Pat<(f64 (sint_to_fp GR32:$src)),
2636 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2637 def : Pat<(f64 (sint_to_fp GR64:$src)),
2638 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2640 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2641 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2642 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2643 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2644 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2645 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2646 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2647 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2649 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2650 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2651 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2652 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2653 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2654 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2655 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2656 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2658 def : Pat<(f32 (uint_to_fp GR32:$src)),
2659 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2660 def : Pat<(f32 (uint_to_fp GR64:$src)),
2661 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2662 def : Pat<(f64 (uint_to_fp GR32:$src)),
2663 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2664 def : Pat<(f64 (uint_to_fp GR64:$src)),
2665 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2668 //===----------------------------------------------------------------------===//
2669 // AVX-512 Scalar convert from float/double to integer
2670 //===----------------------------------------------------------------------===//
2671 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2672 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2674 let hasSideEffects = 0 in {
2675 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2676 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2677 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2678 Requires<[HasAVX512]>;
2680 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2681 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2682 Requires<[HasAVX512]>;
2683 } // hasSideEffects = 0
2685 let Predicates = [HasAVX512] in {
2686 // Convert float/double to signed/unsigned int 32/64
2687 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2688 ssmem, sse_load_f32, "cvtss2si">,
2689 XS, EVEX_CD8<32, CD8VT1>;
2690 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2691 ssmem, sse_load_f32, "cvtss2si">,
2692 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2693 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2694 ssmem, sse_load_f32, "cvtss2usi">,
2695 XS, EVEX_CD8<32, CD8VT1>;
2696 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2697 int_x86_avx512_cvtss2usi64, ssmem,
2698 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2699 EVEX_CD8<32, CD8VT1>;
2700 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2701 sdmem, sse_load_f64, "cvtsd2si">,
2702 XD, EVEX_CD8<64, CD8VT1>;
2703 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2704 sdmem, sse_load_f64, "cvtsd2si">,
2705 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2706 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2707 sdmem, sse_load_f64, "cvtsd2usi">,
2708 XD, EVEX_CD8<64, CD8VT1>;
2709 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2710 int_x86_avx512_cvtsd2usi64, sdmem,
2711 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2712 EVEX_CD8<64, CD8VT1>;
2714 let isCodeGenOnly = 1 in {
2715 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2716 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2717 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2718 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2719 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2720 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2721 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2722 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2723 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2724 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2725 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2726 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2728 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2729 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2730 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2731 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2732 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2733 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2734 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2735 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2736 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2737 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2738 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2739 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2740 } // isCodeGenOnly = 1
2742 // Convert float/double to signed/unsigned int 32/64 with truncation
2743 let isCodeGenOnly = 1 in {
2744 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2745 ssmem, sse_load_f32, "cvttss2si">,
2746 XS, EVEX_CD8<32, CD8VT1>;
2747 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2748 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2749 "cvttss2si">, XS, VEX_W,
2750 EVEX_CD8<32, CD8VT1>;
2751 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2752 sdmem, sse_load_f64, "cvttsd2si">, XD,
2753 EVEX_CD8<64, CD8VT1>;
2754 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2755 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2756 "cvttsd2si">, XD, VEX_W,
2757 EVEX_CD8<64, CD8VT1>;
2758 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2759 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2760 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2761 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2762 int_x86_avx512_cvttss2usi64, ssmem,
2763 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2764 EVEX_CD8<32, CD8VT1>;
2765 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2766 int_x86_avx512_cvttsd2usi,
2767 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2768 EVEX_CD8<64, CD8VT1>;
2769 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2770 int_x86_avx512_cvttsd2usi64, sdmem,
2771 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2772 EVEX_CD8<64, CD8VT1>;
2773 } // isCodeGenOnly = 1
2775 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2776 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2778 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2779 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2780 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2781 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2782 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2783 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2786 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2787 loadf32, "cvttss2si">, XS,
2788 EVEX_CD8<32, CD8VT1>;
2789 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2790 loadf32, "cvttss2usi">, XS,
2791 EVEX_CD8<32, CD8VT1>;
2792 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2793 loadf32, "cvttss2si">, XS, VEX_W,
2794 EVEX_CD8<32, CD8VT1>;
2795 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2796 loadf32, "cvttss2usi">, XS, VEX_W,
2797 EVEX_CD8<32, CD8VT1>;
2798 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2799 loadf64, "cvttsd2si">, XD,
2800 EVEX_CD8<64, CD8VT1>;
2801 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2802 loadf64, "cvttsd2usi">, XD,
2803 EVEX_CD8<64, CD8VT1>;
2804 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2805 loadf64, "cvttsd2si">, XD, VEX_W,
2806 EVEX_CD8<64, CD8VT1>;
2807 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2808 loadf64, "cvttsd2usi">, XD, VEX_W,
2809 EVEX_CD8<64, CD8VT1>;
2811 //===----------------------------------------------------------------------===//
2812 // AVX-512 Convert form float to double and back
2813 //===----------------------------------------------------------------------===//
2814 let hasSideEffects = 0 in {
2815 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2816 (ins FR32X:$src1, FR32X:$src2),
2817 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2818 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2820 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2821 (ins FR32X:$src1, f32mem:$src2),
2822 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2823 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2824 EVEX_CD8<32, CD8VT1>;
2826 // Convert scalar double to scalar single
2827 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2828 (ins FR64X:$src1, FR64X:$src2),
2829 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2830 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2832 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2833 (ins FR64X:$src1, f64mem:$src2),
2834 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2835 []>, EVEX_4V, VEX_LIG, VEX_W,
2836 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2839 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2840 Requires<[HasAVX512]>;
2841 def : Pat<(fextend (loadf32 addr:$src)),
2842 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2844 def : Pat<(extloadf32 addr:$src),
2845 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2846 Requires<[HasAVX512, OptForSize]>;
2848 def : Pat<(extloadf32 addr:$src),
2849 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2850 Requires<[HasAVX512, OptForSpeed]>;
2852 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2853 Requires<[HasAVX512]>;
2855 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2856 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2857 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2859 let hasSideEffects = 0 in {
2860 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2861 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2863 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2864 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2865 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2866 [], d>, EVEX, EVEX_B, EVEX_RC;
2868 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2869 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2871 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2872 } // hasSideEffects = 0
2875 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2876 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2877 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2879 let hasSideEffects = 0 in {
2880 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2881 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2883 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2885 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2886 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2888 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2889 } // hasSideEffects = 0
2892 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2893 memopv8f64, f512mem, v8f32, v8f64,
2894 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2895 EVEX_CD8<64, CD8VF>;
2897 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2898 memopv4f64, f256mem, v8f64, v8f32,
2899 SSEPackedDouble>, EVEX_V512, PS,
2900 EVEX_CD8<32, CD8VH>;
2901 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2902 (VCVTPS2PDZrm addr:$src)>;
2904 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2905 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2906 (VCVTPD2PSZrr VR512:$src)>;
2908 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2909 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2910 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2912 //===----------------------------------------------------------------------===//
2913 // AVX-512 Vector convert from sign integer to float/double
2914 //===----------------------------------------------------------------------===//
2916 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2917 memopv8i64, i512mem, v16f32, v16i32,
2918 SSEPackedSingle>, EVEX_V512, PS,
2919 EVEX_CD8<32, CD8VF>;
2921 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2922 memopv4i64, i256mem, v8f64, v8i32,
2923 SSEPackedDouble>, EVEX_V512, XS,
2924 EVEX_CD8<32, CD8VH>;
2926 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2927 memopv16f32, f512mem, v16i32, v16f32,
2928 SSEPackedSingle>, EVEX_V512, XS,
2929 EVEX_CD8<32, CD8VF>;
2931 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2932 memopv8f64, f512mem, v8i32, v8f64,
2933 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2934 EVEX_CD8<64, CD8VF>;
2936 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2937 memopv16f32, f512mem, v16i32, v16f32,
2938 SSEPackedSingle>, EVEX_V512, PS,
2939 EVEX_CD8<32, CD8VF>;
2941 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2942 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2943 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2944 (VCVTTPS2UDQZrr VR512:$src)>;
2946 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2947 memopv8f64, f512mem, v8i32, v8f64,
2948 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
2949 EVEX_CD8<64, CD8VF>;
2951 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2952 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2953 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2954 (VCVTTPD2UDQZrr VR512:$src)>;
2956 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2957 memopv4i64, f256mem, v8f64, v8i32,
2958 SSEPackedDouble>, EVEX_V512, XS,
2959 EVEX_CD8<32, CD8VH>;
2961 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2962 memopv16i32, f512mem, v16f32, v16i32,
2963 SSEPackedSingle>, EVEX_V512, XD,
2964 EVEX_CD8<32, CD8VF>;
2966 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2967 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2968 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2971 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2972 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2973 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2974 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2975 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2976 (VCVTDQ2PDZrr VR256X:$src)>;
2977 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2978 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2979 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2980 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2981 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2982 (VCVTUDQ2PDZrr VR256X:$src)>;
2984 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2985 RegisterClass DstRC, PatFrag mem_frag,
2986 X86MemOperand x86memop, Domain d> {
2987 let hasSideEffects = 0 in {
2988 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2989 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2991 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2992 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2993 [], d>, EVEX, EVEX_B, EVEX_RC;
2995 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2996 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2998 } // hasSideEffects = 0
3001 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3002 memopv16f32, f512mem, SSEPackedSingle>, PD,
3003 EVEX_V512, EVEX_CD8<32, CD8VF>;
3004 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3005 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3006 EVEX_V512, EVEX_CD8<64, CD8VF>;
3008 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3009 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3010 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3012 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3013 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3014 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3016 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3017 memopv16f32, f512mem, SSEPackedSingle>,
3018 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3019 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3020 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3021 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3023 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3024 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3025 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3027 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3028 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3029 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3031 let Predicates = [HasAVX512] in {
3032 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3033 (VCVTPD2PSZrm addr:$src)>;
3034 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3035 (VCVTPS2PDZrm addr:$src)>;
3038 //===----------------------------------------------------------------------===//
3039 // Half precision conversion instructions
3040 //===----------------------------------------------------------------------===//
3041 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3042 X86MemOperand x86memop> {
3043 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3044 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3046 let hasSideEffects = 0, mayLoad = 1 in
3047 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3048 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3051 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3052 X86MemOperand x86memop> {
3053 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3054 (ins srcRC:$src1, i32i8imm:$src2),
3055 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3057 let hasSideEffects = 0, mayStore = 1 in
3058 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3059 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3060 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3063 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3064 EVEX_CD8<32, CD8VH>;
3065 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3066 EVEX_CD8<32, CD8VH>;
3068 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3069 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3070 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3072 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3073 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3074 (VCVTPH2PSZrr VR256X:$src)>;
3076 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3077 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3078 "ucomiss">, PS, EVEX, VEX_LIG,
3079 EVEX_CD8<32, CD8VT1>;
3080 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3081 "ucomisd">, PD, EVEX,
3082 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3083 let Pattern = []<dag> in {
3084 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3085 "comiss">, PS, EVEX, VEX_LIG,
3086 EVEX_CD8<32, CD8VT1>;
3087 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3088 "comisd">, PD, EVEX,
3089 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3091 let isCodeGenOnly = 1 in {
3092 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3093 load, "ucomiss">, PS, EVEX, VEX_LIG,
3094 EVEX_CD8<32, CD8VT1>;
3095 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3096 load, "ucomisd">, PD, EVEX,
3097 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3099 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3100 load, "comiss">, PS, EVEX, VEX_LIG,
3101 EVEX_CD8<32, CD8VT1>;
3102 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3103 load, "comisd">, PD, EVEX,
3104 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3108 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3109 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3110 X86MemOperand x86memop> {
3111 let hasSideEffects = 0 in {
3112 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3113 (ins RC:$src1, RC:$src2),
3114 !strconcat(OpcodeStr,
3115 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3116 let mayLoad = 1 in {
3117 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3118 (ins RC:$src1, x86memop:$src2),
3119 !strconcat(OpcodeStr,
3120 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3125 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3126 EVEX_CD8<32, CD8VT1>;
3127 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3128 VEX_W, EVEX_CD8<64, CD8VT1>;
3129 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3130 EVEX_CD8<32, CD8VT1>;
3131 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3132 VEX_W, EVEX_CD8<64, CD8VT1>;
3134 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3135 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3136 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3137 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3139 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3140 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3141 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3142 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3144 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3145 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3146 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3147 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3149 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3150 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3151 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3152 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3154 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3155 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3156 RegisterClass RC, X86MemOperand x86memop,
3157 PatFrag mem_frag, ValueType OpVt> {
3158 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3159 !strconcat(OpcodeStr,
3160 " \t{$src, $dst|$dst, $src}"),
3161 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3163 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3164 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3165 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3168 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3169 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3170 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3171 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3172 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3173 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3174 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3175 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3177 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3178 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3179 (VRSQRT14PSZr VR512:$src)>;
3180 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3181 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3182 (VRSQRT14PDZr VR512:$src)>;
3184 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3185 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3186 (VRCP14PSZr VR512:$src)>;
3187 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3188 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3189 (VRCP14PDZr VR512:$src)>;
3191 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3192 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3193 X86MemOperand x86memop> {
3194 let hasSideEffects = 0, Predicates = [HasERI] in {
3195 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3196 (ins RC:$src1, RC:$src2),
3197 !strconcat(OpcodeStr,
3198 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3199 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3200 (ins RC:$src1, RC:$src2),
3201 !strconcat(OpcodeStr,
3202 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3203 []>, EVEX_4V, EVEX_B;
3204 let mayLoad = 1 in {
3205 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3206 (ins RC:$src1, x86memop:$src2),
3207 !strconcat(OpcodeStr,
3208 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3213 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3214 EVEX_CD8<32, CD8VT1>;
3215 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3216 VEX_W, EVEX_CD8<64, CD8VT1>;
3217 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3218 EVEX_CD8<32, CD8VT1>;
3219 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3220 VEX_W, EVEX_CD8<64, CD8VT1>;
3222 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3223 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3225 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3226 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3228 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3229 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3231 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3232 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3234 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3235 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3237 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3238 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3240 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3241 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3243 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3244 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3246 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3247 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3248 RegisterClass RC, X86MemOperand x86memop> {
3249 let hasSideEffects = 0, Predicates = [HasERI] in {
3250 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3251 !strconcat(OpcodeStr,
3252 " \t{$src, $dst|$dst, $src}"),
3254 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3255 !strconcat(OpcodeStr,
3256 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3258 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3259 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3263 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3264 EVEX_V512, EVEX_CD8<32, CD8VF>;
3265 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3266 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3267 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3268 EVEX_V512, EVEX_CD8<32, CD8VF>;
3269 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3270 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3272 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3273 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3274 (VRSQRT28PSZrb VR512:$src)>;
3275 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3276 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3277 (VRSQRT28PDZrb VR512:$src)>;
3279 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3280 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3281 (VRCP28PSZrb VR512:$src)>;
3282 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3283 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3284 (VRCP28PDZrb VR512:$src)>;
3286 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3287 Intrinsic V16F32Int, Intrinsic V8F64Int,
3288 OpndItins itins_s, OpndItins itins_d> {
3289 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3290 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3291 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3295 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3296 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3298 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3299 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3301 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3302 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3303 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3307 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3308 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3309 [(set VR512:$dst, (OpNode
3310 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3311 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3313 let isCodeGenOnly = 1 in {
3314 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3315 !strconcat(OpcodeStr,
3316 "ps\t{$src, $dst|$dst, $src}"),
3317 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3319 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3320 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3322 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3323 EVEX_V512, EVEX_CD8<32, CD8VF>;
3324 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3325 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3326 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3327 EVEX, EVEX_V512, VEX_W;
3328 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3329 !strconcat(OpcodeStr,
3330 "pd\t{$src, $dst|$dst, $src}"),
3331 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3332 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3333 } // isCodeGenOnly = 1
3336 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3337 Intrinsic F32Int, Intrinsic F64Int,
3338 OpndItins itins_s, OpndItins itins_d> {
3339 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3340 (ins FR32X:$src1, FR32X:$src2),
3341 !strconcat(OpcodeStr,
3342 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3343 [], itins_s.rr>, XS, EVEX_4V;
3344 let isCodeGenOnly = 1 in
3345 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3346 (ins VR128X:$src1, VR128X:$src2),
3347 !strconcat(OpcodeStr,
3348 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3350 (F32Int VR128X:$src1, VR128X:$src2))],
3351 itins_s.rr>, XS, EVEX_4V;
3352 let mayLoad = 1 in {
3353 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3354 (ins FR32X:$src1, f32mem:$src2),
3355 !strconcat(OpcodeStr,
3356 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3357 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3358 let isCodeGenOnly = 1 in
3359 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3360 (ins VR128X:$src1, ssmem:$src2),
3361 !strconcat(OpcodeStr,
3362 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3364 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3365 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3367 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3368 (ins FR64X:$src1, FR64X:$src2),
3369 !strconcat(OpcodeStr,
3370 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3372 let isCodeGenOnly = 1 in
3373 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3374 (ins VR128X:$src1, VR128X:$src2),
3375 !strconcat(OpcodeStr,
3376 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3378 (F64Int VR128X:$src1, VR128X:$src2))],
3379 itins_s.rr>, XD, EVEX_4V, VEX_W;
3380 let mayLoad = 1 in {
3381 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3382 (ins FR64X:$src1, f64mem:$src2),
3383 !strconcat(OpcodeStr,
3384 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3385 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3386 let isCodeGenOnly = 1 in
3387 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3388 (ins VR128X:$src1, sdmem:$src2),
3389 !strconcat(OpcodeStr,
3390 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3392 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3393 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3398 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3399 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3400 SSE_SQRTSS, SSE_SQRTSD>,
3401 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3402 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3403 SSE_SQRTPS, SSE_SQRTPD>;
3405 let Predicates = [HasAVX512] in {
3406 def : Pat<(f32 (fsqrt FR32X:$src)),
3407 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3408 def : Pat<(f32 (fsqrt (load addr:$src))),
3409 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3410 Requires<[OptForSize]>;
3411 def : Pat<(f64 (fsqrt FR64X:$src)),
3412 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3413 def : Pat<(f64 (fsqrt (load addr:$src))),
3414 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3415 Requires<[OptForSize]>;
3417 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3418 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3419 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3420 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3421 Requires<[OptForSize]>;
3423 def : Pat<(f32 (X86frcp FR32X:$src)),
3424 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3425 def : Pat<(f32 (X86frcp (load addr:$src))),
3426 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3427 Requires<[OptForSize]>;
3429 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3430 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3431 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3433 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3434 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3436 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3437 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3438 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3440 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3441 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3445 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3446 X86MemOperand x86memop, RegisterClass RC,
3447 PatFrag mem_frag32, PatFrag mem_frag64,
3448 Intrinsic V4F32Int, Intrinsic V2F64Int,
3450 let ExeDomain = SSEPackedSingle in {
3451 // Intrinsic operation, reg.
3452 // Vector intrinsic operation, reg
3453 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3454 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3455 !strconcat(OpcodeStr,
3456 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3457 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3459 // Vector intrinsic operation, mem
3460 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3461 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3462 !strconcat(OpcodeStr,
3463 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3465 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3466 EVEX_CD8<32, VForm>;
3467 } // ExeDomain = SSEPackedSingle
3469 let ExeDomain = SSEPackedDouble in {
3470 // Vector intrinsic operation, reg
3471 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3472 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3473 !strconcat(OpcodeStr,
3474 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3475 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3477 // Vector intrinsic operation, mem
3478 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3479 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3480 !strconcat(OpcodeStr,
3481 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3483 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3484 EVEX_CD8<64, VForm>;
3485 } // ExeDomain = SSEPackedDouble
3488 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3492 let ExeDomain = GenericDomain in {
3494 let hasSideEffects = 0 in
3495 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3496 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3497 !strconcat(OpcodeStr,
3498 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3501 // Intrinsic operation, reg.
3502 let isCodeGenOnly = 1 in
3503 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3504 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3505 !strconcat(OpcodeStr,
3506 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3507 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3509 // Intrinsic operation, mem.
3510 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3511 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3512 !strconcat(OpcodeStr,
3513 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3514 [(set VR128X:$dst, (F32Int VR128X:$src1,
3515 sse_load_f32:$src2, imm:$src3))]>,
3516 EVEX_CD8<32, CD8VT1>;
3519 let hasSideEffects = 0 in
3520 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3521 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3522 !strconcat(OpcodeStr,
3523 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3526 // Intrinsic operation, reg.
3527 let isCodeGenOnly = 1 in
3528 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3529 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3530 !strconcat(OpcodeStr,
3531 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3532 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3535 // Intrinsic operation, mem.
3536 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3537 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3538 !strconcat(OpcodeStr,
3539 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3541 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3542 VEX_W, EVEX_CD8<64, CD8VT1>;
3543 } // ExeDomain = GenericDomain
3546 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3547 X86MemOperand x86memop, RegisterClass RC,
3548 PatFrag mem_frag, Domain d> {
3549 let ExeDomain = d in {
3550 // Intrinsic operation, reg.
3551 // Vector intrinsic operation, reg
3552 def r : AVX512AIi8<opc, MRMSrcReg,
3553 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3554 !strconcat(OpcodeStr,
3555 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3558 // Vector intrinsic operation, mem
3559 def m : AVX512AIi8<opc, MRMSrcMem,
3560 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3561 !strconcat(OpcodeStr,
3562 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3568 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3569 memopv16f32, SSEPackedSingle>, EVEX_V512,
3570 EVEX_CD8<32, CD8VF>;
3572 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3573 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3575 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3578 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3579 memopv8f64, SSEPackedDouble>, EVEX_V512,
3580 VEX_W, EVEX_CD8<64, CD8VF>;
3582 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3583 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3585 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3587 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3588 Operand x86memop, RegisterClass RC, Domain d> {
3589 let ExeDomain = d in {
3590 def r : AVX512AIi8<opc, MRMSrcReg,
3591 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3592 !strconcat(OpcodeStr,
3593 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3596 def m : AVX512AIi8<opc, MRMSrcMem,
3597 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3598 !strconcat(OpcodeStr,
3599 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3604 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3605 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3607 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3608 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3610 def : Pat<(ffloor FR32X:$src),
3611 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3612 def : Pat<(f64 (ffloor FR64X:$src)),
3613 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3614 def : Pat<(f32 (fnearbyint FR32X:$src)),
3615 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3616 def : Pat<(f64 (fnearbyint FR64X:$src)),
3617 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3618 def : Pat<(f32 (fceil FR32X:$src)),
3619 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3620 def : Pat<(f64 (fceil FR64X:$src)),
3621 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3622 def : Pat<(f32 (frint FR32X:$src)),
3623 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3624 def : Pat<(f64 (frint FR64X:$src)),
3625 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3626 def : Pat<(f32 (ftrunc FR32X:$src)),
3627 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3628 def : Pat<(f64 (ftrunc FR64X:$src)),
3629 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3631 def : Pat<(v16f32 (ffloor VR512:$src)),
3632 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3633 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3634 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3635 def : Pat<(v16f32 (fceil VR512:$src)),
3636 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3637 def : Pat<(v16f32 (frint VR512:$src)),
3638 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3639 def : Pat<(v16f32 (ftrunc VR512:$src)),
3640 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3642 def : Pat<(v8f64 (ffloor VR512:$src)),
3643 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3644 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3645 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3646 def : Pat<(v8f64 (fceil VR512:$src)),
3647 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3648 def : Pat<(v8f64 (frint VR512:$src)),
3649 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3650 def : Pat<(v8f64 (ftrunc VR512:$src)),
3651 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3653 //-------------------------------------------------
3654 // Integer truncate and extend operations
3655 //-------------------------------------------------
3657 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3658 RegisterClass dstRC, RegisterClass srcRC,
3659 RegisterClass KRC, X86MemOperand x86memop> {
3660 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3662 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3665 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3666 (ins KRC:$mask, srcRC:$src),
3667 !strconcat(OpcodeStr,
3668 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3671 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3672 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3675 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3676 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3677 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3678 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3679 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3680 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3681 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3682 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3683 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3684 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3685 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3686 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3687 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3688 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3689 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3690 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3691 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3692 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3693 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3694 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3695 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3696 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3697 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3698 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3699 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3700 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3701 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3702 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3703 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3704 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3706 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3707 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3708 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3709 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3710 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3712 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3713 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3714 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3715 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3716 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3717 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3718 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3719 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3722 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3723 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3724 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3726 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3728 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3729 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3730 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3731 (ins x86memop:$src),
3732 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3734 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3738 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3739 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3741 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3742 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3744 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3745 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3746 EVEX_CD8<16, CD8VH>;
3747 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3748 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3749 EVEX_CD8<16, CD8VQ>;
3750 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3751 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3752 EVEX_CD8<32, CD8VH>;
3754 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3755 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3757 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3758 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3760 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3761 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3762 EVEX_CD8<16, CD8VH>;
3763 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3764 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3765 EVEX_CD8<16, CD8VQ>;
3766 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3767 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3768 EVEX_CD8<32, CD8VH>;
3770 //===----------------------------------------------------------------------===//
3771 // GATHER - SCATTER Operations
3773 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3774 RegisterClass RC, X86MemOperand memop> {
3776 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3777 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3778 (ins RC:$src1, KRC:$mask, memop:$src2),
3779 !strconcat(OpcodeStr,
3780 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3783 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3784 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3785 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3786 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3788 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3789 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3790 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3791 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3793 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3794 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3795 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3796 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3798 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3799 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3800 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3801 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3803 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3804 RegisterClass RC, X86MemOperand memop> {
3805 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3806 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3807 (ins memop:$dst, KRC:$mask, RC:$src2),
3808 !strconcat(OpcodeStr,
3809 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3813 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3814 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3815 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3816 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3818 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3819 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3820 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3821 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3823 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3824 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3825 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3826 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3828 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3829 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3830 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3831 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3833 //===----------------------------------------------------------------------===//
3834 // VSHUFPS - VSHUFPD Operations
3836 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3837 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3839 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3840 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3841 !strconcat(OpcodeStr,
3842 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3843 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3844 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3845 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3846 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3847 (ins RC:$src1, RC:$src2, i8imm:$src3),
3848 !strconcat(OpcodeStr,
3849 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3850 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3851 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3852 EVEX_4V, Sched<[WriteShuffle]>;
3855 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3856 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3857 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3858 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3860 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3861 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3862 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3863 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3864 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3866 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3867 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3868 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3869 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3870 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3872 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3873 X86MemOperand x86memop> {
3874 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3875 (ins RC:$src1, RC:$src2, i8imm:$src3),
3876 !strconcat(OpcodeStr,
3877 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3880 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3881 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3882 !strconcat(OpcodeStr,
3883 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3886 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3887 EVEX_V512, EVEX_CD8<32, CD8VF>;
3888 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3889 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3891 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3892 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3893 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3894 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3895 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3896 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3897 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3898 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3900 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3901 X86MemOperand x86memop> {
3902 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3903 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3905 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3906 (ins x86memop:$src),
3907 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3911 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3912 EVEX_CD8<32, CD8VF>;
3913 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3914 EVEX_CD8<64, CD8VF>;
3916 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3917 (v16i32 immAllZerosV), (i16 -1))),
3918 (VPABSDrr VR512:$src)>;
3919 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3920 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3921 (VPABSQrr VR512:$src)>;
3923 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3924 RegisterClass RC, RegisterClass KRC,
3925 X86MemOperand x86memop,
3926 X86MemOperand x86scalar_mop, string BrdcstStr> {
3927 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3929 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3931 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3932 (ins x86memop:$src),
3933 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3935 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3936 (ins x86scalar_mop:$src),
3937 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3938 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3940 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3941 (ins KRC:$mask, RC:$src),
3942 !strconcat(OpcodeStr,
3943 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3945 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3946 (ins KRC:$mask, x86memop:$src),
3947 !strconcat(OpcodeStr,
3948 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3950 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3951 (ins KRC:$mask, x86scalar_mop:$src),
3952 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3953 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3955 []>, EVEX, EVEX_KZ, EVEX_B;
3957 let Constraints = "$src1 = $dst" in {
3958 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3959 (ins RC:$src1, KRC:$mask, RC:$src2),
3960 !strconcat(OpcodeStr,
3961 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3963 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3964 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3965 !strconcat(OpcodeStr,
3966 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3968 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3969 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3970 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3971 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3972 []>, EVEX, EVEX_K, EVEX_B;
3976 let Predicates = [HasCDI] in {
3977 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3978 i512mem, i32mem, "{1to16}">,
3979 EVEX_V512, EVEX_CD8<32, CD8VF>;
3982 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3983 i512mem, i64mem, "{1to8}">,
3984 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3988 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3990 (VPCONFLICTDrrk VR512:$src1,
3991 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3993 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3995 (VPCONFLICTQrrk VR512:$src1,
3996 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;