1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
406 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
410 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
413 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
416 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
421 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
422 X86MemOperand x86memop, PatFrag ld_frag,
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
431 !strconcat(OpcodeStr,
432 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
442 !strconcat(OpcodeStr,
443 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
448 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
451 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
453 EVEX_CD8<64, CD8VT1>;
455 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
456 (VBROADCASTSSZrr VR128X:$src)>;
457 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
458 (VBROADCASTSDZrr VR128X:$src)>;
460 // Provide fallback in case the load node that is used in the patterns above
461 // is used by additional users, which prevents the pattern selection.
462 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
464 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
468 let Predicates = [HasAVX512] in {
469 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
472 addr:$src)), sub_ymm)>;
474 //===----------------------------------------------------------------------===//
475 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
478 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
479 RegisterClass DstRC, RegisterClass KRC,
480 ValueType OpVT, ValueType SrcVT> {
481 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
486 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
487 VK16, v16i32, v16i1>, EVEX_V512;
488 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
491 //===----------------------------------------------------------------------===//
494 // -- immediate form --
495 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
496 SDNode OpNode, PatFrag mem_frag,
497 X86MemOperand x86memop, ValueType OpVT> {
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
499 (ins RC:$src1, i8imm:$src2),
500 !strconcat(OpcodeStr,
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
506 (ins x86memop:$src1, i8imm:$src2),
507 !strconcat(OpcodeStr,
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
510 (OpVT (OpNode (mem_frag addr:$src1),
511 (i8 imm:$src2))))]>, EVEX;
514 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
516 let ExeDomain = SSEPackedDouble in
517 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
520 // -- VPERM - register form --
521 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, RC:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
532 (ins RC:$src1, x86memop:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
540 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
542 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
544 let ExeDomain = SSEPackedSingle in
545 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
547 let ExeDomain = SSEPackedDouble in
548 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
551 // -- VPERM2I - 3 source operands form --
552 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
553 PatFrag mem_frag, X86MemOperand x86memop,
555 let Constraints = "$src1 = $dst" in {
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, RC:$src2, RC:$src3),
558 !strconcat(OpcodeStr,
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
566 !strconcat(OpcodeStr,
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
570 (mem_frag addr:$src3))))]>, EVEX_4V;
573 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
582 //===----------------------------------------------------------------------===//
583 // AVX-512 - BLEND using mask
585 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
586 RegisterClass KRC, RegisterClass RC,
587 X86MemOperand x86memop, PatFrag mem_frag,
588 SDNode OpNode, ValueType vt> {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins KRC:$mask, RC:$src1, RC:$src2),
591 !strconcat(OpcodeStr,
592 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
598 !strconcat(OpcodeStr,
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
604 let ExeDomain = SSEPackedSingle in
605 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
606 memopv16f32, vselect, v16f32>,
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
608 let ExeDomain = SSEPackedDouble in
609 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
610 memopv8f64, vselect, v8f64>,
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
613 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
614 memopv8i64, vselect, v16i32>,
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
617 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
618 memopv8i64, vselect, v8i64>, VEX_W,
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
622 let Predicates = [HasAVX512] in {
623 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
624 (v8f32 VR256X:$src2))),
626 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
628 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
630 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
631 (v8i32 VR256X:$src2))),
633 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
635 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
638 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
639 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
640 SDNode OpNode, ValueType vt> {
641 def rr : AVX512BI<opc, MRMSrcReg,
642 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
644 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
645 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
646 def rm : AVX512BI<opc, MRMSrcMem,
647 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
649 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
650 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
653 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
654 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
655 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
656 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
658 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
659 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
660 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
661 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
663 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
664 (COPY_TO_REGCLASS (VPCMPGTDZrr
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
666 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
668 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
669 (COPY_TO_REGCLASS (VPCMPEQDZrr
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
671 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
673 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
674 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
675 SDNode OpNode, ValueType vt, Operand CC, string asm,
677 def rri : AVX512AIi8<opc, MRMSrcReg,
678 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
679 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
680 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
681 def rmi : AVX512AIi8<opc, MRMSrcMem,
682 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
683 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
684 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
685 // Accept explicit immediate argument form instead of comparison code.
686 let neverHasSideEffects = 1 in {
687 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
688 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
689 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
690 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
691 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
692 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
696 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
697 X86cmpm, v16i32, AVXCC,
698 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
699 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
700 EVEX_V512, EVEX_CD8<32, CD8VF>;
701 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
702 X86cmpmu, v16i32, AVXCC,
703 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
704 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
707 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
708 X86cmpm, v8i64, AVXCC,
709 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
710 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
711 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
712 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
713 X86cmpmu, v8i64, AVXCC,
714 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
716 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
718 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
719 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
720 X86MemOperand x86memop, Operand CC,
721 SDNode OpNode, ValueType vt, string asm,
722 string asm_alt, Domain d> {
723 def rri : AVX512PIi8<0xC2, MRMSrcReg,
724 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
725 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
726 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
727 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
729 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
731 // Accept explicit immediate argument form instead of comparison code.
732 let neverHasSideEffects = 1 in {
733 def rri_alt : PIi8<0xC2, MRMSrcReg,
734 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
735 asm_alt, [], IIC_SSE_ALU_F32P_RR, d>;
736 def rmi_alt : PIi8<0xC2, MRMSrcMem,
737 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_ALU_F32P_RM, d>;
742 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
743 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
744 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
745 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
746 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
747 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
749 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
752 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
753 (COPY_TO_REGCLASS (VCMPPSZrri
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
755 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
757 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
758 (COPY_TO_REGCLASS (VPCMPDZrri
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
760 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
762 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
763 (COPY_TO_REGCLASS (VPCMPUDZrri
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
768 // Mask register copy, including
769 // - copy between mask registers
770 // - load/store mask registers
771 // - copy from GPR to mask register and vice versa
773 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
774 string OpcodeStr, RegisterClass KRC,
775 ValueType vt, X86MemOperand x86memop> {
776 let neverHasSideEffects = 1 in {
777 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
780 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
782 [(set KRC:$dst, (vt (load addr:$src)))]>;
784 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
789 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
791 RegisterClass KRC, RegisterClass GRC> {
792 let neverHasSideEffects = 1 in {
793 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
795 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
800 let Predicates = [HasAVX512] in {
801 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
803 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
807 let Predicates = [HasAVX512] in {
808 // GR16 from/to 16-bit mask
809 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
810 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
811 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
812 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
814 // Store kreg in memory
815 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
816 (KMOVWmk addr:$dst, VK16:$src)>;
818 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
819 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
821 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
822 let Predicates = [HasAVX512] in {
823 // GR from/to 8-bit mask without native support
824 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
826 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
828 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
830 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
834 // Mask unary operation
836 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
837 RegisterClass KRC, SDPatternOperator OpNode> {
838 let Predicates = [HasAVX512] in
839 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
840 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
841 [(set KRC:$dst, (OpNode KRC:$src))]>;
844 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
845 SDPatternOperator OpNode> {
846 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
850 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
852 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
853 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
854 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
856 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
857 def : Pat<(not VK8:$src),
859 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
861 // Mask binary operation
862 // - KADD, KAND, KANDN, KOR, KXNOR, KXOR
863 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
864 RegisterClass KRC, SDPatternOperator OpNode> {
865 let Predicates = [HasAVX512] in
866 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
867 !strconcat(OpcodeStr,
868 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
869 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
872 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
873 SDPatternOperator OpNode> {
874 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
878 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
879 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
881 let isCommutable = 1 in {
882 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
883 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
884 let isCommutable = 0 in
885 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
886 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
887 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
888 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
891 multiclass avx512_mask_binop_int<string IntName, string InstName> {
892 let Predicates = [HasAVX512] in
893 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
894 VK16:$src1, VK16:$src2),
895 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
898 defm : avx512_mask_binop_int<"kadd", "KADD">;
899 defm : avx512_mask_binop_int<"kand", "KAND">;
900 defm : avx512_mask_binop_int<"kandn", "KANDN">;
901 defm : avx512_mask_binop_int<"kor", "KOR">;
902 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
903 defm : avx512_mask_binop_int<"kxor", "KXOR">;
904 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
905 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
906 let Predicates = [HasAVX512] in
907 def : Pat<(OpNode VK8:$src1, VK8:$src2),
909 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
910 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
913 defm : avx512_binop_pat<and, KANDWrr>;
914 defm : avx512_binop_pat<andn, KANDNWrr>;
915 defm : avx512_binop_pat<or, KORWrr>;
916 defm : avx512_binop_pat<xnor, KXNORWrr>;
917 defm : avx512_binop_pat<xor, KXORWrr>;
920 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
921 RegisterClass KRC1, RegisterClass KRC2> {
922 let Predicates = [HasAVX512] in
923 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
924 !strconcat(OpcodeStr,
925 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
928 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
929 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
930 VEX_4V, VEX_L, OpSize, TB;
933 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
935 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
936 let Predicates = [HasAVX512] in
937 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
938 VK8:$src1, VK8:$src2),
939 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
942 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
944 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
946 let Predicates = [HasAVX512], Defs = [EFLAGS] in
947 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
949 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
952 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
953 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
957 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
958 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
961 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
963 let Predicates = [HasAVX512] in
964 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
965 !strconcat(OpcodeStr,
966 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
967 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
970 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
972 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
973 VEX, OpSize, TA, VEX_W;
976 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
977 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
979 // Mask setting all 0s or 1s
980 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
981 let Predicates = [HasAVX512] in
982 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
983 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
984 [(set KRC:$dst, (VT Val))]>;
987 multiclass avx512_mask_setop_w<PatFrag Val> {
988 defm B : avx512_mask_setop<VK8, v8i1, Val>;
989 defm W : avx512_mask_setop<VK16, v16i1, Val>;
992 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
993 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
995 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
996 let Predicates = [HasAVX512] in {
997 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
998 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1000 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1001 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1003 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1004 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1006 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1007 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1009 //===----------------------------------------------------------------------===//
1010 // AVX-512 - Aligned and unaligned load and store
1013 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1014 X86MemOperand x86memop, PatFrag ld_frag,
1015 string asm, Domain d> {
1016 let neverHasSideEffects = 1 in
1017 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1018 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1020 let canFoldAsLoad = 1 in
1021 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1022 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1023 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1024 let Constraints = "$src1 = $dst" in {
1025 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1026 (ins RC:$src1, KRC:$mask, RC:$src2),
1028 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1030 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1031 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1033 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1034 [], d>, EVEX, EVEX_K;
1038 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1039 "vmovaps", SSEPackedSingle>,
1040 EVEX_V512, EVEX_CD8<32, CD8VF>;
1041 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1042 "vmovapd", SSEPackedDouble>,
1043 OpSize, EVEX_V512, VEX_W,
1044 EVEX_CD8<64, CD8VF>;
1045 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1046 "vmovups", SSEPackedSingle>,
1047 EVEX_V512, EVEX_CD8<32, CD8VF>;
1048 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1049 "vmovupd", SSEPackedDouble>,
1050 OpSize, EVEX_V512, VEX_W,
1051 EVEX_CD8<64, CD8VF>;
1052 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1053 "vmovaps\t{$src, $dst|$dst, $src}",
1054 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1055 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1056 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1057 "vmovapd\t{$src, $dst|$dst, $src}",
1058 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1059 SSEPackedDouble>, EVEX, EVEX_V512,
1060 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1061 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1062 "vmovups\t{$src, $dst|$dst, $src}",
1063 [(store (v16f32 VR512:$src), addr:$dst)],
1064 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1065 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1066 "vmovupd\t{$src, $dst|$dst, $src}",
1067 [(store (v8f64 VR512:$src), addr:$dst)],
1068 SSEPackedDouble>, EVEX, EVEX_V512,
1069 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1071 // Use vmovaps/vmovups for AVX-512 integer load/store.
1072 // 512-bit load/store
1073 def : Pat<(alignedloadv8i64 addr:$src),
1074 (VMOVAPSZrm addr:$src)>;
1075 def : Pat<(loadv8i64 addr:$src),
1076 (VMOVUPSZrm addr:$src)>;
1078 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1079 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1080 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1081 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1083 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1084 (VMOVUPDZmr addr:$dst, VR512:$src)>;
1085 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1086 (VMOVUPSZmr addr:$dst, VR512:$src)>;
1088 let neverHasSideEffects = 1 in {
1089 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1091 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1093 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1095 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1096 EVEX, EVEX_V512, VEX_W;
1097 let mayStore = 1 in {
1098 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1099 (ins i512mem:$dst, VR512:$src),
1100 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1101 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1102 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1103 (ins i512mem:$dst, VR512:$src),
1104 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1105 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1107 let mayLoad = 1 in {
1108 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1110 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1111 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1112 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1114 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1115 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1119 multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
1121 PatFrag ld_frag, X86MemOperand x86memop> {
1122 let neverHasSideEffects = 1 in
1123 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1124 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
1126 let canFoldAsLoad = 1 in
1127 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1128 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1129 [(set RC:$dst, (ld_frag addr:$src))]>,
1131 let Constraints = "$src1 = $dst" in {
1132 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
1133 (ins RC:$src1, KRC:$mask, RC:$src2),
1135 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1137 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
1138 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1140 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1145 defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
1146 EVEX_V512, EVEX_CD8<32, CD8VF>;
1147 defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
1148 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1150 let AddedComplexity = 20 in {
1151 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1152 (v16f32 VR512:$src2))),
1153 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1154 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1155 (v8f64 VR512:$src2))),
1156 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1157 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1158 (v16i32 VR512:$src2))),
1159 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1160 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1161 (v8i64 VR512:$src2))),
1162 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1164 // Move Int Doubleword to Packed Double Int
1166 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1167 "vmovd{z}\t{$src, $dst|$dst, $src}",
1169 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1171 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1172 "vmovd{z}\t{$src, $dst|$dst, $src}",
1174 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1175 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1176 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1177 "vmovq{z}\t{$src, $dst|$dst, $src}",
1179 (v2i64 (scalar_to_vector GR64:$src)))],
1180 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1181 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1182 "vmovq{z}\t{$src, $dst|$dst, $src}",
1183 [(set FR64:$dst, (bitconvert GR64:$src))],
1184 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1185 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1186 "vmovq{z}\t{$src, $dst|$dst, $src}",
1187 [(set GR64:$dst, (bitconvert FR64:$src))],
1188 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1189 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1190 "vmovq{z}\t{$src, $dst|$dst, $src}",
1191 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1192 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1193 EVEX_CD8<64, CD8VT1>;
1195 // Move Int Doubleword to Single Scalar
1197 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1198 "vmovd{z}\t{$src, $dst|$dst, $src}",
1199 [(set FR32X:$dst, (bitconvert GR32:$src))],
1200 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1202 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1203 "vmovd{z}\t{$src, $dst|$dst, $src}",
1204 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1205 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1207 // Move Packed Doubleword Int to Packed Double Int
1209 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1210 "vmovd{z}\t{$src, $dst|$dst, $src}",
1211 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1212 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1214 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1215 (ins i32mem:$dst, VR128X:$src),
1216 "vmovd{z}\t{$src, $dst|$dst, $src}",
1217 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1218 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1219 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1221 // Move Packed Doubleword Int first element to Doubleword Int
1223 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1224 "vmovq{z}\t{$src, $dst|$dst, $src}",
1225 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1227 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1228 Requires<[HasAVX512, In64BitMode]>;
1230 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1231 (ins i64mem:$dst, VR128X:$src),
1232 "vmovq{z}\t{$src, $dst|$dst, $src}",
1233 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1234 addr:$dst)], IIC_SSE_MOVDQ>,
1235 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1236 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1238 // Move Scalar Single to Double Int
1240 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1242 "vmovd{z}\t{$src, $dst|$dst, $src}",
1243 [(set GR32:$dst, (bitconvert FR32X:$src))],
1244 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1245 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1246 (ins i32mem:$dst, FR32X:$src),
1247 "vmovd{z}\t{$src, $dst|$dst, $src}",
1248 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1249 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1251 // Move Quadword Int to Packed Quadword Int
1253 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1255 "vmovq{z}\t{$src, $dst|$dst, $src}",
1257 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1258 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1260 //===----------------------------------------------------------------------===//
1261 // AVX-512 MOVSS, MOVSD
1262 //===----------------------------------------------------------------------===//
1264 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1265 SDNode OpNode, ValueType vt,
1266 X86MemOperand x86memop, PatFrag mem_pat> {
1267 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1268 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1269 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1270 (scalar_to_vector RC:$src2))))],
1271 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1272 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1273 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1274 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1276 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1277 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1278 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1282 let ExeDomain = SSEPackedSingle in
1283 defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1284 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1286 let ExeDomain = SSEPackedDouble in
1287 defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1288 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1291 // For the disassembler
1292 let isCodeGenOnly = 1 in {
1293 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1294 (ins VR128X:$src1, FR32X:$src2),
1295 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1297 XS, EVEX_4V, VEX_LIG;
1298 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1299 (ins VR128X:$src1, FR64X:$src2),
1300 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1302 XD, EVEX_4V, VEX_LIG, VEX_W;
1305 let Predicates = [HasAVX512] in {
1306 let AddedComplexity = 15 in {
1307 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1308 // MOVS{S,D} to the lower bits.
1309 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1310 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1311 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1312 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1313 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1314 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1315 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1316 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1318 // Move low f32 and clear high bits.
1319 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1320 (SUBREG_TO_REG (i32 0),
1321 (VMOVSSZrr (v4f32 (V_SET0)),
1322 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1323 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1324 (SUBREG_TO_REG (i32 0),
1325 (VMOVSSZrr (v4i32 (V_SET0)),
1326 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1329 let AddedComplexity = 20 in {
1330 // MOVSSrm zeros the high parts of the register; represent this
1331 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1332 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1333 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1334 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1335 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1336 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1337 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1339 // MOVSDrm zeros the high parts of the register; represent this
1340 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1341 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1342 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1343 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1344 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1345 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1346 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1347 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1348 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1349 def : Pat<(v2f64 (X86vzload addr:$src)),
1350 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1352 // Represent the same patterns above but in the form they appear for
1354 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1355 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1356 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1357 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1358 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1359 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1360 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1361 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1362 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1364 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1365 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1366 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1367 FR32X:$src)), sub_xmm)>;
1368 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1369 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1370 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1371 FR64X:$src)), sub_xmm)>;
1372 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1373 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1374 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1376 // Move low f64 and clear high bits.
1377 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1378 (SUBREG_TO_REG (i32 0),
1379 (VMOVSDZrr (v2f64 (V_SET0)),
1380 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1382 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1383 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1384 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1386 // Extract and store.
1387 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1389 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1390 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1392 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1394 // Shuffle with VMOVSS
1395 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1396 (VMOVSSZrr (v4i32 VR128X:$src1),
1397 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1398 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1399 (VMOVSSZrr (v4f32 VR128X:$src1),
1400 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1403 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1404 (SUBREG_TO_REG (i32 0),
1405 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1406 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1408 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1409 (SUBREG_TO_REG (i32 0),
1410 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1411 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1414 // Shuffle with VMOVSD
1415 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1416 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1417 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1418 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1419 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1420 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1421 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1422 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1425 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1426 (SUBREG_TO_REG (i32 0),
1427 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1428 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1430 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1431 (SUBREG_TO_REG (i32 0),
1432 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1433 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1436 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1437 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1438 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1439 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1440 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1441 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1442 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1443 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1446 let AddedComplexity = 15 in
1447 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1449 "vmovq{z}\t{$src, $dst|$dst, $src}",
1450 [(set VR128X:$dst, (v2i64 (X86vzmovl
1451 (v2i64 VR128X:$src))))],
1452 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1454 let AddedComplexity = 20 in
1455 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1457 "vmovq{z}\t{$src, $dst|$dst, $src}",
1458 [(set VR128X:$dst, (v2i64 (X86vzmovl
1459 (loadv2i64 addr:$src))))],
1460 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1461 EVEX_CD8<8, CD8VT8>;
1463 let Predicates = [HasAVX512] in {
1464 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1465 let AddedComplexity = 20 in {
1466 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1467 (VMOVDI2PDIZrm addr:$src)>;
1468 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1469 (VMOV64toPQIZrr GR64:$src)>;
1470 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1471 (VMOVDI2PDIZrr GR32:$src)>;
1473 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1474 (VMOVDI2PDIZrm addr:$src)>;
1475 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1476 (VMOVDI2PDIZrm addr:$src)>;
1477 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1478 (VMOVZPQILo2PQIZrm addr:$src)>;
1479 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1480 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1483 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1484 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1485 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1486 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1487 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1488 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1489 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1492 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1493 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1495 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1496 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1498 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1499 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1501 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1502 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1504 //===----------------------------------------------------------------------===//
1505 // AVX-512 - Integer arithmetic
1507 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1508 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1509 X86MemOperand x86memop, PatFrag scalar_mfrag,
1510 X86MemOperand x86scalar_mop, string BrdcstStr,
1511 OpndItins itins, bit IsCommutable = 0> {
1512 let isCommutable = IsCommutable in
1513 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1514 (ins RC:$src1, RC:$src2),
1515 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1516 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1518 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1519 (ins RC:$src1, x86memop:$src2),
1520 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1521 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1523 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1524 (ins RC:$src1, x86scalar_mop:$src2),
1525 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1526 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1527 [(set RC:$dst, (OpNode RC:$src1,
1528 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1529 itins.rm>, EVEX_4V, EVEX_B;
1531 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1532 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1533 PatFrag memop_frag, X86MemOperand x86memop,
1535 bit IsCommutable = 0> {
1536 let isCommutable = IsCommutable in
1537 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1538 (ins RC:$src1, RC:$src2),
1539 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1540 []>, EVEX_4V, VEX_W;
1541 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1542 (ins RC:$src1, x86memop:$src2),
1543 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1544 []>, EVEX_4V, VEX_W;
1547 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1548 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1549 EVEX_V512, EVEX_CD8<32, CD8VF>;
1551 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1552 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1553 EVEX_V512, EVEX_CD8<32, CD8VF>;
1555 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1556 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1557 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1559 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1560 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1561 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1563 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1564 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1565 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1567 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1568 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1569 EVEX_V512, EVEX_CD8<64, CD8VF>;
1571 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1572 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1573 EVEX_CD8<64, CD8VF>;
1575 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1576 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1578 //===----------------------------------------------------------------------===//
1579 // AVX-512 - Unpack Instructions
1580 //===----------------------------------------------------------------------===//
1582 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1583 PatFrag mem_frag, RegisterClass RC,
1584 X86MemOperand x86memop, string asm,
1586 def rr : AVX512PI<opc, MRMSrcReg,
1587 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1589 (vt (OpNode RC:$src1, RC:$src2)))],
1591 def rm : AVX512PI<opc, MRMSrcMem,
1592 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1594 (vt (OpNode RC:$src1,
1595 (bitconvert (mem_frag addr:$src2)))))],
1599 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1600 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1601 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1602 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1603 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1604 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1605 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1606 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1607 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1608 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1609 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1610 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1612 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1613 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1614 X86MemOperand x86memop> {
1615 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1616 (ins RC:$src1, RC:$src2),
1617 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1618 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1619 IIC_SSE_UNPCK>, EVEX_4V;
1620 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1621 (ins RC:$src1, x86memop:$src2),
1622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1623 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1624 (bitconvert (memop_frag addr:$src2)))))],
1625 IIC_SSE_UNPCK>, EVEX_4V;
1627 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1628 VR512, memopv16i32, i512mem>, EVEX_V512,
1629 EVEX_CD8<32, CD8VF>;
1630 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1631 VR512, memopv8i64, i512mem>, EVEX_V512,
1632 VEX_W, EVEX_CD8<64, CD8VF>;
1633 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1634 VR512, memopv16i32, i512mem>, EVEX_V512,
1635 EVEX_CD8<32, CD8VF>;
1636 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1637 VR512, memopv8i64, i512mem>, EVEX_V512,
1638 VEX_W, EVEX_CD8<64, CD8VF>;
1639 //===----------------------------------------------------------------------===//
1643 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1644 SDNode OpNode, PatFrag mem_frag,
1645 X86MemOperand x86memop, ValueType OpVT> {
1646 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1647 (ins RC:$src1, i8imm:$src2),
1648 !strconcat(OpcodeStr,
1649 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1651 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1653 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1654 (ins x86memop:$src1, i8imm:$src2),
1655 !strconcat(OpcodeStr,
1656 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1658 (OpVT (OpNode (mem_frag addr:$src1),
1659 (i8 imm:$src2))))]>, EVEX;
1662 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1663 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1665 let ExeDomain = SSEPackedSingle in
1666 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1667 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1668 EVEX_CD8<32, CD8VF>;
1669 let ExeDomain = SSEPackedDouble in
1670 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1671 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1672 VEX_W, EVEX_CD8<32, CD8VF>;
1674 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1675 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1676 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1677 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1679 //===----------------------------------------------------------------------===//
1680 // AVX-512 Logical Instructions
1681 //===----------------------------------------------------------------------===//
1683 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1684 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1685 EVEX_V512, EVEX_CD8<32, CD8VF>;
1686 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1687 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1688 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1689 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1690 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1691 EVEX_V512, EVEX_CD8<32, CD8VF>;
1692 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1693 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1694 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1695 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1696 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1697 EVEX_V512, EVEX_CD8<32, CD8VF>;
1698 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1699 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1700 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1701 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1702 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1703 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1704 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1705 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1706 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1708 //===----------------------------------------------------------------------===//
1709 // AVX-512 FP arithmetic
1710 //===----------------------------------------------------------------------===//
1712 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1714 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1715 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1716 EVEX_CD8<32, CD8VT1>;
1717 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1718 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1719 EVEX_CD8<64, CD8VT1>;
1722 let isCommutable = 1 in {
1723 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1724 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1725 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1726 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1728 let isCommutable = 0 in {
1729 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1730 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1733 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1734 RegisterClass RC, ValueType vt,
1735 X86MemOperand x86memop, PatFrag mem_frag,
1736 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1738 Domain d, OpndItins itins, bit commutable> {
1739 let isCommutable = commutable in
1740 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1741 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1742 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1744 let mayLoad = 1 in {
1745 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1747 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1748 itins.rm, d>, EVEX_4V, TB;
1749 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1750 (ins RC:$src1, x86scalar_mop:$src2),
1751 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1752 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1753 [(set RC:$dst, (OpNode RC:$src1,
1754 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1755 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1759 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1760 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1761 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1763 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1764 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1765 SSE_ALU_ITINS_P.d, 1>,
1766 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1768 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1769 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1770 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1771 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1772 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1773 SSE_ALU_ITINS_P.d, 1>,
1774 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1776 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1777 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1778 SSE_ALU_ITINS_P.s, 1>,
1779 EVEX_V512, EVEX_CD8<32, CD8VF>;
1780 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1781 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1782 SSE_ALU_ITINS_P.s, 1>,
1783 EVEX_V512, EVEX_CD8<32, CD8VF>;
1785 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1786 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1787 SSE_ALU_ITINS_P.d, 1>,
1788 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1789 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1790 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1791 SSE_ALU_ITINS_P.d, 1>,
1792 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1794 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1795 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1796 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1797 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1798 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1799 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1801 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1802 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1803 SSE_ALU_ITINS_P.d, 0>,
1804 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1805 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1806 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1807 SSE_ALU_ITINS_P.d, 0>,
1808 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1810 //===----------------------------------------------------------------------===//
1811 // AVX-512 VPTESTM instructions
1812 //===----------------------------------------------------------------------===//
1814 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1815 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1816 SDNode OpNode, ValueType vt> {
1817 def rr : AVX5128I<opc, MRMSrcReg,
1818 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1820 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1821 def rm : AVX5128I<opc, MRMSrcMem,
1822 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1823 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1824 [(set KRC:$dst, (OpNode (vt RC:$src1),
1825 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1828 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1829 memopv16i32, X86testm, v16i32>, EVEX_V512,
1830 EVEX_CD8<32, CD8VF>;
1831 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1832 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1833 EVEX_CD8<64, CD8VF>;
1835 //===----------------------------------------------------------------------===//
1836 // AVX-512 Shift instructions
1837 //===----------------------------------------------------------------------===//
1838 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1839 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1840 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1841 RegisterClass KRC> {
1842 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1843 (ins RC:$src1, i32i8imm:$src2),
1844 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1845 [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
1846 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1847 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1848 (ins KRC:$mask, RC:$src1, i32i8imm:$src2),
1849 !strconcat(OpcodeStr,
1850 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1851 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1852 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1853 (ins x86memop:$src1, i32i8imm:$src2),
1854 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1855 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1856 (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1857 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1858 (ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
1859 !strconcat(OpcodeStr,
1860 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1861 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1864 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1865 RegisterClass RC, ValueType vt, ValueType SrcVT,
1866 PatFrag bc_frag, RegisterClass KRC> {
1867 // src2 is always 128-bit
1868 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1869 (ins RC:$src1, VR128X:$src2),
1870 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1871 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1872 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1873 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1874 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1875 !strconcat(OpcodeStr,
1876 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1877 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1878 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1879 (ins RC:$src1, i128mem:$src2),
1880 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1881 [(set RC:$dst, (vt (OpNode RC:$src1,
1882 (bc_frag (memopv2i64 addr:$src2)))))],
1883 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1884 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1885 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1886 !strconcat(OpcodeStr,
1887 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1888 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1891 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1892 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1893 EVEX_V512, EVEX_CD8<32, CD8VF>;
1894 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1895 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1896 EVEX_CD8<32, CD8VQ>;
1898 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1899 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1900 EVEX_CD8<64, CD8VF>, VEX_W;
1901 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1902 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1903 EVEX_CD8<64, CD8VQ>, VEX_W;
1905 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1906 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1907 EVEX_CD8<32, CD8VF>;
1908 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1909 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1910 EVEX_CD8<32, CD8VQ>;
1912 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1913 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1914 EVEX_CD8<64, CD8VF>, VEX_W;
1915 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1916 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1917 EVEX_CD8<64, CD8VQ>, VEX_W;
1919 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1920 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1921 EVEX_V512, EVEX_CD8<32, CD8VF>;
1922 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1923 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1924 EVEX_CD8<32, CD8VQ>;
1926 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1927 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1928 EVEX_CD8<64, CD8VF>, VEX_W;
1929 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1930 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1931 EVEX_CD8<64, CD8VQ>, VEX_W;
1933 //===-------------------------------------------------------------------===//
1934 // Variable Bit Shifts
1935 //===-------------------------------------------------------------------===//
1936 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1937 RegisterClass RC, ValueType vt,
1938 X86MemOperand x86memop, PatFrag mem_frag> {
1939 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1940 (ins RC:$src1, RC:$src2),
1941 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1943 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1945 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1946 (ins RC:$src1, x86memop:$src2),
1947 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1949 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1953 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1954 i512mem, memopv16i32>, EVEX_V512,
1955 EVEX_CD8<32, CD8VF>;
1956 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1957 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1958 EVEX_CD8<64, CD8VF>;
1959 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1960 i512mem, memopv16i32>, EVEX_V512,
1961 EVEX_CD8<32, CD8VF>;
1962 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1963 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1964 EVEX_CD8<64, CD8VF>;
1965 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1966 i512mem, memopv16i32>, EVEX_V512,
1967 EVEX_CD8<32, CD8VF>;
1968 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1969 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1970 EVEX_CD8<64, CD8VF>;
1972 //===----------------------------------------------------------------------===//
1973 // AVX-512 - MOVDDUP
1974 //===----------------------------------------------------------------------===//
1976 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1977 X86MemOperand x86memop, PatFrag memop_frag> {
1978 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1980 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
1981 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1982 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1984 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
1987 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
1988 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1989 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
1990 (VMOVDDUPZrm addr:$src)>;
1992 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
1993 (ins VR128X:$src1, VR128X:$src2),
1994 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1995 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
1996 IIC_SSE_MOV_LH>, EVEX_4V;
1997 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
1998 (ins VR128X:$src1, VR128X:$src2),
1999 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2000 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2001 IIC_SSE_MOV_LH>, EVEX_4V;
2003 let Predicates = [HasAVX512] in {
2005 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2006 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2007 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2008 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2011 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2012 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2015 //===----------------------------------------------------------------------===//
2016 // FMA - Fused Multiply Operations
2018 let Constraints = "$src1 = $dst" in {
2019 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2020 RegisterClass RC, X86MemOperand x86memop,
2021 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2022 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2023 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2024 (ins RC:$src1, RC:$src2, RC:$src3),
2025 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2026 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2029 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2030 (ins RC:$src1, RC:$src2, x86memop:$src3),
2031 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2032 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2033 (mem_frag addr:$src3))))]>;
2034 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2035 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2036 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2037 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2038 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2039 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2041 } // Constraints = "$src1 = $dst"
2043 let ExeDomain = SSEPackedSingle in {
2044 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2045 memopv16f32, f32mem, loadf32, "{1to16}",
2046 X86Fmadd, v16f32>, EVEX_V512,
2047 EVEX_CD8<32, CD8VF>;
2048 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2049 memopv16f32, f32mem, loadf32, "{1to16}",
2050 X86Fmsub, v16f32>, EVEX_V512,
2051 EVEX_CD8<32, CD8VF>;
2052 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2053 memopv16f32, f32mem, loadf32, "{1to16}",
2054 X86Fmaddsub, v16f32>,
2055 EVEX_V512, EVEX_CD8<32, CD8VF>;
2056 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2057 memopv16f32, f32mem, loadf32, "{1to16}",
2058 X86Fmsubadd, v16f32>,
2059 EVEX_V512, EVEX_CD8<32, CD8VF>;
2060 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2061 memopv16f32, f32mem, loadf32, "{1to16}",
2062 X86Fnmadd, v16f32>, EVEX_V512,
2063 EVEX_CD8<32, CD8VF>;
2064 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2065 memopv16f32, f32mem, loadf32, "{1to16}",
2066 X86Fnmsub, v16f32>, EVEX_V512,
2067 EVEX_CD8<32, CD8VF>;
2069 let ExeDomain = SSEPackedDouble in {
2070 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2071 memopv8f64, f64mem, loadf64, "{1to8}",
2072 X86Fmadd, v8f64>, EVEX_V512,
2073 VEX_W, EVEX_CD8<64, CD8VF>;
2074 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2075 memopv8f64, f64mem, loadf64, "{1to8}",
2076 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2077 EVEX_CD8<64, CD8VF>;
2078 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2079 memopv8f64, f64mem, loadf64, "{1to8}",
2080 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2081 EVEX_CD8<64, CD8VF>;
2082 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2083 memopv8f64, f64mem, loadf64, "{1to8}",
2084 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2085 EVEX_CD8<64, CD8VF>;
2086 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2087 memopv8f64, f64mem, loadf64, "{1to8}",
2088 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2089 EVEX_CD8<64, CD8VF>;
2090 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2091 memopv8f64, f64mem, loadf64, "{1to8}",
2092 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2093 EVEX_CD8<64, CD8VF>;
2096 let Constraints = "$src1 = $dst" in {
2097 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2098 RegisterClass RC, X86MemOperand x86memop,
2099 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2100 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2102 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2103 (ins RC:$src1, RC:$src3, x86memop:$src2),
2104 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2105 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2106 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2107 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2108 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2109 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2110 [(set RC:$dst, (OpNode RC:$src1,
2111 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2113 } // Constraints = "$src1 = $dst"
2116 let ExeDomain = SSEPackedSingle in {
2117 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2118 memopv16f32, f32mem, loadf32, "{1to16}",
2119 X86Fmadd, v16f32>, EVEX_V512,
2120 EVEX_CD8<32, CD8VF>;
2121 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2122 memopv16f32, f32mem, loadf32, "{1to16}",
2123 X86Fmsub, v16f32>, EVEX_V512,
2124 EVEX_CD8<32, CD8VF>;
2125 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2126 memopv16f32, f32mem, loadf32, "{1to16}",
2127 X86Fmaddsub, v16f32>,
2128 EVEX_V512, EVEX_CD8<32, CD8VF>;
2129 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2130 memopv16f32, f32mem, loadf32, "{1to16}",
2131 X86Fmsubadd, v16f32>,
2132 EVEX_V512, EVEX_CD8<32, CD8VF>;
2133 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2134 memopv16f32, f32mem, loadf32, "{1to16}",
2135 X86Fnmadd, v16f32>, EVEX_V512,
2136 EVEX_CD8<32, CD8VF>;
2137 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2138 memopv16f32, f32mem, loadf32, "{1to16}",
2139 X86Fnmsub, v16f32>, EVEX_V512,
2140 EVEX_CD8<32, CD8VF>;
2142 let ExeDomain = SSEPackedDouble in {
2143 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2144 memopv8f64, f64mem, loadf64, "{1to8}",
2145 X86Fmadd, v8f64>, EVEX_V512,
2146 VEX_W, EVEX_CD8<64, CD8VF>;
2147 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2148 memopv8f64, f64mem, loadf64, "{1to8}",
2149 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2150 EVEX_CD8<64, CD8VF>;
2151 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2152 memopv8f64, f64mem, loadf64, "{1to8}",
2153 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2154 EVEX_CD8<64, CD8VF>;
2155 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2156 memopv8f64, f64mem, loadf64, "{1to8}",
2157 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2158 EVEX_CD8<64, CD8VF>;
2159 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2160 memopv8f64, f64mem, loadf64, "{1to8}",
2161 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2162 EVEX_CD8<64, CD8VF>;
2163 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2164 memopv8f64, f64mem, loadf64, "{1to8}",
2165 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2166 EVEX_CD8<64, CD8VF>;
2170 let Constraints = "$src1 = $dst" in {
2171 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2172 RegisterClass RC, ValueType OpVT,
2173 X86MemOperand x86memop, Operand memop,
2175 let isCommutable = 1 in
2176 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2177 (ins RC:$src1, RC:$src2, RC:$src3),
2178 !strconcat(OpcodeStr,
2179 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2181 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2183 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2184 (ins RC:$src1, RC:$src2, f128mem:$src3),
2185 !strconcat(OpcodeStr,
2186 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2188 (OpVT (OpNode RC:$src2, RC:$src1,
2189 (mem_frag addr:$src3))))]>;
2192 } // Constraints = "$src1 = $dst"
2194 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2195 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2196 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2197 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2198 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2199 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2200 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2201 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2202 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2203 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2204 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2205 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2206 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2207 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2208 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2209 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2211 //===----------------------------------------------------------------------===//
2212 // AVX-512 Scalar convert from sign integer to float/double
2213 //===----------------------------------------------------------------------===//
2215 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2216 X86MemOperand x86memop, string asm> {
2217 let neverHasSideEffects = 1 in {
2218 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2219 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
2221 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2222 (ins DstRC:$src1, x86memop:$src),
2223 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
2224 } // neverHasSideEffects = 1
2227 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2228 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2229 defm VCVTSI2SS64Z : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
2230 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2231 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2232 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2233 defm VCVTSI2SD64Z : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
2234 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2236 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2237 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2238 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2239 (VCVTSI2SS64Zrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2240 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2241 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2242 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2243 (VCVTSI2SD64Zrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2245 def : Pat<(f32 (sint_to_fp GR32:$src)),
2246 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2247 def : Pat<(f32 (sint_to_fp GR64:$src)),
2248 (VCVTSI2SS64Zrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2249 def : Pat<(f64 (sint_to_fp GR32:$src)),
2250 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2251 def : Pat<(f64 (sint_to_fp GR64:$src)),
2252 (VCVTSI2SD64Zrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2255 //===----------------------------------------------------------------------===//
2256 // AVX-512 Convert form float to double and back
2257 //===----------------------------------------------------------------------===//
2258 let neverHasSideEffects = 1 in {
2259 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2260 (ins FR32X:$src1, FR32X:$src2),
2261 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2262 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2264 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2265 (ins FR32X:$src1, f32mem:$src2),
2266 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2267 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2268 EVEX_CD8<32, CD8VT1>;
2270 // Convert scalar double to scalar single
2271 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2272 (ins FR64X:$src1, FR64X:$src2),
2273 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2274 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2276 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2277 (ins FR64X:$src1, f64mem:$src2),
2278 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2279 []>, EVEX_4V, VEX_LIG, VEX_W,
2280 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2283 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2284 Requires<[HasAVX512]>;
2285 def : Pat<(fextend (loadf32 addr:$src)),
2286 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2288 def : Pat<(extloadf32 addr:$src),
2289 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2290 Requires<[HasAVX512, OptForSize]>;
2292 def : Pat<(extloadf32 addr:$src),
2293 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2294 Requires<[HasAVX512, OptForSpeed]>;
2296 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2297 Requires<[HasAVX512]>;
2299 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2300 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2301 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2303 let neverHasSideEffects = 1 in {
2304 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2305 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2307 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2309 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2310 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2312 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2313 } // neverHasSideEffects = 1
2316 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2317 memopv8f64, f512mem, v8f32, v8f64,
2318 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2319 EVEX_CD8<64, CD8VF>;
2321 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2322 memopv4f64, f256mem, v8f64, v8f32,
2323 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2324 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2325 (VCVTPS2PDZrm addr:$src)>;
2327 //===----------------------------------------------------------------------===//
2328 // AVX-512 Vector convert from sign integer to float/double
2329 //===----------------------------------------------------------------------===//
2331 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2332 memopv8i64, i512mem, v16f32, v16i32,
2333 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2335 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2336 memopv4i64, i256mem, v8f64, v8i32,
2337 SSEPackedDouble>, EVEX_V512, XS,
2338 EVEX_CD8<32, CD8VH>;
2340 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2341 memopv16f32, f512mem, v16i32, v16f32,
2342 SSEPackedSingle>, EVEX_V512, XS,
2343 EVEX_CD8<32, CD8VF>;
2345 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2346 memopv8f64, f512mem, v8i32, v8f64,
2347 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2348 EVEX_CD8<64, CD8VF>;
2350 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2351 memopv16f32, f512mem, v16i32, v16f32,
2352 SSEPackedSingle>, EVEX_V512,
2353 EVEX_CD8<32, CD8VF>;
2355 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2356 memopv8f64, f512mem, v8i32, v8f64,
2357 SSEPackedDouble>, EVEX_V512, VEX_W,
2358 EVEX_CD8<64, CD8VF>;
2360 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2361 memopv4i64, f256mem, v8f64, v8i32,
2362 SSEPackedDouble>, EVEX_V512, XS,
2363 EVEX_CD8<32, CD8VH>;
2365 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2366 memopv16i32, f512mem, v16f32, v16i32,
2367 SSEPackedSingle>, EVEX_V512, XD,
2368 EVEX_CD8<32, CD8VF>;
2370 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2371 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2372 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2375 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2376 (VCVTDQ2PSZrr VR512:$src)>;
2377 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2378 (VCVTDQ2PSZrm addr:$src)>;
2380 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2381 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2383 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2384 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2385 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2386 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2388 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2389 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2392 let Predicates = [HasAVX512] in {
2393 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2394 (VCVTPD2PSZrm addr:$src)>;
2395 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2396 (VCVTPS2PDZrm addr:$src)>;
2399 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2400 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2401 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2402 EVEX_CD8<32, CD8VT1>;
2403 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2404 "ucomisd{z}">, TB, OpSize, EVEX,
2405 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2406 let Pattern = []<dag> in {
2407 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2408 "comiss{z}">, TB, EVEX, VEX_LIG,
2409 EVEX_CD8<32, CD8VT1>;
2410 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2411 "comisd{z}">, TB, OpSize, EVEX,
2412 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2414 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2415 load, "ucomiss">, TB, EVEX, VEX_LIG,
2416 EVEX_CD8<32, CD8VT1>;
2417 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2418 load, "ucomisd">, TB, OpSize, EVEX,
2419 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2421 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2422 load, "comiss">, TB, EVEX, VEX_LIG,
2423 EVEX_CD8<32, CD8VT1>;
2424 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2425 load, "comisd">, TB, OpSize, EVEX,
2426 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2429 /// avx512_unop_p - AVX-512 unops in packed form.
2430 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2431 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2432 !strconcat(OpcodeStr,
2433 "ps\t{$src, $dst|$dst, $src}"),
2434 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2436 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2437 !strconcat(OpcodeStr,
2438 "ps\t{$src, $dst|$dst, $src}"),
2439 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2440 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2441 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2442 !strconcat(OpcodeStr,
2443 "pd\t{$src, $dst|$dst, $src}"),
2444 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2445 EVEX, EVEX_V512, VEX_W;
2446 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2447 !strconcat(OpcodeStr,
2448 "pd\t{$src, $dst|$dst, $src}"),
2449 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2450 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2453 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2454 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2455 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2456 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2457 !strconcat(OpcodeStr,
2458 "ps\t{$src, $dst|$dst, $src}"),
2459 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2461 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2462 !strconcat(OpcodeStr,
2463 "ps\t{$src, $dst|$dst, $src}"),
2465 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2466 EVEX_V512, EVEX_CD8<32, CD8VF>;
2467 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2468 !strconcat(OpcodeStr,
2469 "pd\t{$src, $dst|$dst, $src}"),
2470 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2471 EVEX, EVEX_V512, VEX_W;
2472 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2473 !strconcat(OpcodeStr,
2474 "pd\t{$src, $dst|$dst, $src}"),
2476 (V8F64Int (memopv8f64 addr:$src)))]>,
2477 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2480 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2481 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
2482 Intrinsic F32Int, Intrinsic F64Int> {
2483 let hasSideEffects = 0 in {
2484 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2485 (ins FR32X:$src1, FR32X:$src2),
2486 !strconcat(OpcodeStr,
2487 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2489 let mayLoad = 1 in {
2490 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2491 (ins FR32X:$src1, f32mem:$src2),
2492 !strconcat(OpcodeStr,
2493 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2494 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2495 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2496 (ins VR128X:$src1, ssmem:$src2),
2497 !strconcat(OpcodeStr,
2498 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2499 [(set VR128X:$dst, (F32Int VR128X:$src1, sse_load_f32:$src2))]>,
2500 EVEX_4V, EVEX_CD8<32, CD8VT1>;
2502 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2503 (ins FR64X:$src1, FR64X:$src2),
2504 !strconcat(OpcodeStr,
2505 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2507 let mayLoad = 1 in {
2508 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2509 (ins FR64X:$src1, f64mem:$src2),
2510 !strconcat(OpcodeStr,
2511 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2512 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2513 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2514 (ins VR128X:$src1, sdmem:$src2),
2515 !strconcat(OpcodeStr,
2516 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2517 [(set VR128X:$dst, (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2518 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2523 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14", int_x86_avx512_rcp14_ss,
2524 int_x86_avx512_rcp14_sd>,
2525 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2526 avx512_fp_unop_p_int<0x4C, "vrcp14",
2527 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2529 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14", int_x86_avx512_rsqrt14_ss,
2530 int_x86_avx512_rsqrt14_sd>,
2531 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2532 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2533 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2535 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2536 Intrinsic V16F32Int, Intrinsic V8F64Int,
2537 OpndItins itins_s, OpndItins itins_d> {
2538 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2540 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2544 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2545 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2547 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2548 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2550 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2551 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2552 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2556 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2558 [(set VR512:$dst, (OpNode
2559 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2560 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2562 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2563 !strconcat(OpcodeStr,
2564 "ps\t{$src, $dst|$dst, $src}"),
2565 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2567 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2568 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2570 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2571 EVEX_V512, EVEX_CD8<32, CD8VF>;
2572 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2573 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2574 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2575 EVEX, EVEX_V512, VEX_W;
2576 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2577 !strconcat(OpcodeStr,
2578 "pd\t{$src, $dst|$dst, $src}"),
2579 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2580 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2583 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2584 Intrinsic F32Int, Intrinsic F64Int,
2585 OpndItins itins_s, OpndItins itins_d> {
2586 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2587 (ins FR32X:$src1, FR32X:$src2),
2588 !strconcat(OpcodeStr,
2589 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2590 [], itins_s.rr>, XS, EVEX_4V;
2591 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2592 (ins VR128X:$src1, VR128X:$src2),
2593 !strconcat(OpcodeStr,
2594 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2596 (F32Int VR128X:$src1, VR128X:$src2))],
2597 itins_s.rr>, XS, EVEX_4V;
2598 let mayLoad = 1 in {
2599 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2600 (ins FR32X:$src1, f32mem:$src2),
2601 !strconcat(OpcodeStr,
2602 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2603 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2604 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2605 (ins VR128X:$src1, ssmem:$src2),
2606 !strconcat(OpcodeStr,
2607 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2609 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2610 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2612 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2613 (ins FR64X:$src1, FR64X:$src2),
2614 !strconcat(OpcodeStr,
2615 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2617 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2618 (ins VR128X:$src1, VR128X:$src2),
2619 !strconcat(OpcodeStr,
2620 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2622 (F64Int VR128X:$src1, VR128X:$src2))],
2623 itins_s.rr>, XD, EVEX_4V, VEX_W;
2624 let mayLoad = 1 in {
2625 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2626 (ins FR64X:$src1, f64mem:$src2),
2627 !strconcat(OpcodeStr,
2628 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2629 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2630 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2631 (ins VR128X:$src1, sdmem:$src2),
2632 !strconcat(OpcodeStr,
2633 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2635 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2636 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2641 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2642 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2643 SSE_SQRTSS, SSE_SQRTSD>,
2644 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2645 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2646 SSE_SQRTPS, SSE_SQRTPD>;
2648 def : Pat<(f32 (fsqrt FR32X:$src)),
2649 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2650 def : Pat<(f32 (fsqrt (load addr:$src))),
2651 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2652 Requires<[OptForSize]>;
2653 def : Pat<(f64 (fsqrt FR64X:$src)),
2654 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2655 def : Pat<(f64 (fsqrt (load addr:$src))),
2656 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2657 Requires<[OptForSize]>;
2659 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2660 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2661 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2662 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2663 Requires<[OptForSize]>;
2665 def : Pat<(f32 (X86frcp FR32X:$src)),
2666 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2667 def : Pat<(f32 (X86frcp (load addr:$src))),
2668 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2669 Requires<[OptForSize]>;
2671 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2672 X86MemOperand x86memop, RegisterClass RC,
2673 PatFrag mem_frag32, PatFrag mem_frag64,
2674 Intrinsic V4F32Int, Intrinsic V2F64Int,
2676 let ExeDomain = SSEPackedSingle in {
2677 // Intrinsic operation, reg.
2678 // Vector intrinsic operation, reg
2679 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2680 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2681 !strconcat(OpcodeStr,
2682 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2683 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2685 // Vector intrinsic operation, mem
2686 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2687 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2688 !strconcat(OpcodeStr,
2689 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2691 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2692 EVEX_CD8<32, VForm>;
2693 } // ExeDomain = SSEPackedSingle
2695 let ExeDomain = SSEPackedDouble in {
2696 // Vector intrinsic operation, reg
2697 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2698 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2699 !strconcat(OpcodeStr,
2700 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2701 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2703 // Vector intrinsic operation, mem
2704 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2705 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2706 !strconcat(OpcodeStr,
2707 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2709 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2710 EVEX_CD8<64, VForm>;
2711 } // ExeDomain = SSEPackedDouble
2714 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2718 let ExeDomain = GenericDomain in {
2720 let hasSideEffects = 0 in
2721 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2722 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2723 !strconcat(OpcodeStr,
2724 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2727 // Intrinsic operation, reg.
2728 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2729 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2730 !strconcat(OpcodeStr,
2731 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2732 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
2734 // Intrinsic operation, mem.
2735 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
2736 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
2737 !strconcat(OpcodeStr,
2738 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2739 [(set VR128X:$dst, (F32Int VR128X:$src1,
2740 sse_load_f32:$src2, imm:$src3))]>,
2741 EVEX_CD8<32, CD8VT1>;
2744 let hasSideEffects = 0 in
2745 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
2746 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
2747 !strconcat(OpcodeStr,
2748 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2751 // Intrinsic operation, reg.
2752 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
2753 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2754 !strconcat(OpcodeStr,
2755 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2756 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
2759 // Intrinsic operation, mem.
2760 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
2761 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
2762 !strconcat(OpcodeStr,
2763 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2765 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
2766 VEX_W, EVEX_CD8<64, CD8VT1>;
2767 } // ExeDomain = GenericDomain
2770 let Predicates = [HasAVX512] in {
2771 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
2772 int_x86_avx512_rndscale_ss,
2773 int_x86_avx512_rndscale_sd>, EVEX_4V;
2775 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
2776 memopv16f32, memopv8f64,
2777 int_x86_avx512_rndscale_ps_512,
2778 int_x86_avx512_rndscale_pd_512, CD8VF>,
2782 def : Pat<(ffloor FR32X:$src),
2783 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
2784 def : Pat<(f64 (ffloor FR64X:$src)),
2785 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
2786 def : Pat<(f32 (fnearbyint FR32X:$src)),
2787 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
2788 def : Pat<(f64 (fnearbyint FR64X:$src)),
2789 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
2790 def : Pat<(f32 (fceil FR32X:$src)),
2791 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
2792 def : Pat<(f64 (fceil FR64X:$src)),
2793 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
2794 def : Pat<(f32 (frint FR32X:$src)),
2795 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
2796 def : Pat<(f64 (frint FR64X:$src)),
2797 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
2798 def : Pat<(f32 (ftrunc FR32X:$src)),
2799 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
2800 def : Pat<(f64 (ftrunc FR64X:$src)),
2801 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
2803 def : Pat<(v16f32 (ffloor VR512:$src)),
2804 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
2805 def : Pat<(v16f32 (fnearbyint VR512:$src)),
2806 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
2807 def : Pat<(v16f32 (fceil VR512:$src)),
2808 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
2809 def : Pat<(v16f32 (frint VR512:$src)),
2810 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
2811 def : Pat<(v16f32 (ftrunc VR512:$src)),
2812 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
2814 def : Pat<(v8f64 (ffloor VR512:$src)),
2815 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
2816 def : Pat<(v8f64 (fnearbyint VR512:$src)),
2817 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
2818 def : Pat<(v8f64 (fceil VR512:$src)),
2819 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
2820 def : Pat<(v8f64 (frint VR512:$src)),
2821 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
2822 def : Pat<(v8f64 (ftrunc VR512:$src)),
2823 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
2825 //-------------------------------------------------
2826 // Integer truncate and extend operations
2827 //-------------------------------------------------
2829 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
2830 RegisterClass dstRC, RegisterClass srcRC,
2831 RegisterClass KRC, X86MemOperand x86memop> {
2832 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
2834 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2837 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
2838 (ins KRC:$mask, srcRC:$src),
2839 !strconcat(OpcodeStr,
2840 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2843 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
2844 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2847 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
2848 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2849 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
2850 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2851 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
2852 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2853 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
2854 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2855 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
2856 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2857 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
2858 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2859 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
2860 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2861 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
2862 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2863 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
2864 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2865 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
2866 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2867 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
2868 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2869 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
2870 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2871 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
2872 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2873 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
2874 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2875 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
2876 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2878 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
2879 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
2880 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
2881 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
2882 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
2884 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
2885 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
2886 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
2887 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
2888 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
2889 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
2890 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
2891 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
2894 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
2895 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
2896 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
2898 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
2900 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2901 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
2902 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
2903 (ins x86memop:$src),
2904 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2906 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
2910 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
2911 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
2913 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
2914 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
2916 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
2917 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
2918 EVEX_CD8<16, CD8VH>;
2919 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
2920 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
2921 EVEX_CD8<16, CD8VQ>;
2922 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
2923 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
2924 EVEX_CD8<32, CD8VH>;
2926 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
2927 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
2929 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
2930 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
2932 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
2933 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
2934 EVEX_CD8<16, CD8VH>;
2935 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
2936 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
2937 EVEX_CD8<16, CD8VQ>;
2938 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
2939 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
2940 EVEX_CD8<32, CD8VH>;
2942 //===----------------------------------------------------------------------===//
2943 // GATHER - SCATTER Operations
2945 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2946 RegisterClass RC, X86MemOperand memop> {
2948 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
2949 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
2950 (ins RC:$src1, KRC:$mask, memop:$src2),
2951 !strconcat(OpcodeStr,
2952 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
2955 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
2956 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2957 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
2958 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2960 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
2961 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2962 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
2963 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2965 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
2966 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2967 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
2968 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2970 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
2971 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2972 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
2973 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2975 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2976 RegisterClass RC, X86MemOperand memop> {
2977 let mayStore = 1, Constraints = "$mask = $mask_wb" in
2978 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
2979 (ins memop:$dst, KRC:$mask, RC:$src2),
2980 !strconcat(OpcodeStr,
2981 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
2985 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
2986 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2987 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
2988 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2990 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
2991 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2992 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
2993 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2995 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
2996 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2997 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
2998 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3000 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3001 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3002 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3003 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3005 //===----------------------------------------------------------------------===//
3006 // VSHUFPS - VSHUFPD Operations
3008 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3009 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3011 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3012 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3013 !strconcat(OpcodeStr,
3014 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3015 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3016 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3017 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3018 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3019 (ins RC:$src1, RC:$src2, i8imm:$src3),
3020 !strconcat(OpcodeStr,
3021 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3022 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3023 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3024 EVEX_4V, Sched<[WriteShuffle]>;
3027 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3028 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3029 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3030 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3033 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3034 X86MemOperand x86memop> {
3035 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3036 (ins RC:$src1, RC:$src2, i8imm:$src3),
3037 !strconcat(OpcodeStr,
3038 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3040 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3041 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3042 !strconcat(OpcodeStr,
3043 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3046 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3047 EVEX_V512, EVEX_CD8<32, CD8VF>;
3048 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3049 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3051 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3052 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3053 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3054 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3055 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3056 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3057 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3058 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3060 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3061 X86MemOperand x86memop> {
3062 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3063 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3065 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3066 (ins x86memop:$src),
3067 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3071 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3072 EVEX_CD8<32, CD8VF>;
3073 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3074 EVEX_CD8<64, CD8VF>;