1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
278 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_custom<O, F, Outs, Ins,
284 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
285 !con((ins _.KRCWM:$mask), Ins),
286 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
290 // Instruction with mask that puts result in mask register,
291 // like "compare" and "vptest"
292 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
294 dag Ins, dag MaskingIns,
296 string AttSrcAsm, string IntelSrcAsm,
298 list<dag> MaskingPattern,
300 InstrItinClass itin = NoItinerary> {
301 def NAME: AVX512<O, F, Outs, Ins,
302 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
303 "$dst "#Round#", "#IntelSrcAsm#"}",
306 def NAME#k: AVX512<O, F, Outs, MaskingIns,
307 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
308 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
309 MaskingPattern, itin>, EVEX_K;
312 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
314 dag Ins, dag MaskingIns,
316 string AttSrcAsm, string IntelSrcAsm,
317 dag RHS, dag MaskingRHS,
319 InstrItinClass itin = NoItinerary> :
320 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
321 AttSrcAsm, IntelSrcAsm,
322 [(set _.KRC:$dst, RHS)],
323 [(set _.KRC:$dst, MaskingRHS)],
326 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
327 dag Outs, dag Ins, string OpcodeStr,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, string Round = "",
330 InstrItinClass itin = NoItinerary> :
331 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
332 !con((ins _.KRCWM:$mask), Ins),
333 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
334 (and _.KRCWM:$mask, RHS),
337 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
338 dag Outs, dag Ins, string OpcodeStr,
339 string AttSrcAsm, string IntelSrcAsm> :
340 AVX512_maskable_custom_cmp<O, F, Outs,
341 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
342 AttSrcAsm, IntelSrcAsm,
343 [],[],"", NoItinerary>;
345 // Bitcasts between 512-bit vector types. Return the original type since
346 // no instruction is needed for the conversion
347 let Predicates = [HasAVX512] in {
348 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
349 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
350 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
351 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
352 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
353 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
354 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
355 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
356 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
357 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
358 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
359 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
360 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
361 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
362 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
363 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
364 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
365 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
366 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
367 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
368 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
369 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
370 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
371 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
372 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
373 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
374 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
375 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
376 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
377 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
378 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
380 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
381 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
382 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
383 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
384 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
385 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
386 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
387 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
388 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
389 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
390 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
391 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
392 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
393 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
394 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
395 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
396 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
397 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
398 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
399 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
400 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
401 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
402 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
403 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
404 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
405 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
406 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
407 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
408 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
409 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
411 // Bitcasts between 256-bit vector types. Return the original type since
412 // no instruction is needed for the conversion
413 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
414 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
415 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
416 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
417 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
418 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
420 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
421 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
422 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
424 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
425 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
426 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
427 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
429 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
431 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
432 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
433 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
434 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
435 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
436 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
437 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
439 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
440 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
441 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
442 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
446 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
449 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
450 isPseudo = 1, Predicates = [HasAVX512] in {
451 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
452 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
455 let Predicates = [HasAVX512] in {
456 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
457 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
458 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
461 //===----------------------------------------------------------------------===//
462 // AVX-512 - VECTOR INSERT
465 multiclass vinsert_for_size_no_alt<int Opcode,
466 X86VectorVTInfo From, X86VectorVTInfo To,
467 PatFrag vinsert_insert,
468 SDNodeXForm INSERT_get_vinsert_imm> {
469 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
470 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
471 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
472 "vinsert" # From.EltTypeName # "x" # From.NumElts #
473 "\t{$src3, $src2, $src1, $dst|"
474 "$dst, $src1, $src2, $src3}",
475 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
476 (From.VT From.RC:$src2),
481 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
482 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
483 "vinsert" # From.EltTypeName # "x" # From.NumElts #
484 "\t{$src3, $src2, $src1, $dst|"
485 "$dst, $src1, $src2, $src3}",
487 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
491 multiclass vinsert_for_size<int Opcode,
492 X86VectorVTInfo From, X86VectorVTInfo To,
493 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
494 PatFrag vinsert_insert,
495 SDNodeXForm INSERT_get_vinsert_imm> :
496 vinsert_for_size_no_alt<Opcode, From, To,
497 vinsert_insert, INSERT_get_vinsert_imm> {
498 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
499 // vinserti32x4. Only add this if 64x2 and friends are not supported
500 // natively via AVX512DQ.
501 let Predicates = [NoDQI] in
502 def : Pat<(vinsert_insert:$ins
503 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
505 VR512:$src1, From.RC:$src2,
506 (INSERT_get_vinsert_imm VR512:$ins)))>;
509 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
510 ValueType EltVT64, int Opcode256> {
511 defm NAME # "32x4" : vinsert_for_size<Opcode128,
512 X86VectorVTInfo< 4, EltVT32, VR128X>,
513 X86VectorVTInfo<16, EltVT32, VR512>,
514 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 X86VectorVTInfo< 8, EltVT64, VR512>,
517 INSERT_get_vinsert128_imm>;
518 let Predicates = [HasDQI] in
519 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
520 X86VectorVTInfo< 2, EltVT64, VR128X>,
521 X86VectorVTInfo< 8, EltVT64, VR512>,
523 INSERT_get_vinsert128_imm>, VEX_W;
524 defm NAME # "64x4" : vinsert_for_size<Opcode256,
525 X86VectorVTInfo< 4, EltVT64, VR256X>,
526 X86VectorVTInfo< 8, EltVT64, VR512>,
527 X86VectorVTInfo< 8, EltVT32, VR256>,
528 X86VectorVTInfo<16, EltVT32, VR512>,
530 INSERT_get_vinsert256_imm>, VEX_W;
531 let Predicates = [HasDQI] in
532 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
533 X86VectorVTInfo< 8, EltVT32, VR256X>,
534 X86VectorVTInfo<16, EltVT32, VR512>,
536 INSERT_get_vinsert256_imm>;
539 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
540 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
542 // vinsertps - insert f32 to XMM
543 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
544 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
545 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
546 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
548 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
549 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
550 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
551 [(set VR128X:$dst, (X86insertps VR128X:$src1,
552 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
553 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
555 //===----------------------------------------------------------------------===//
556 // AVX-512 VECTOR EXTRACT
559 multiclass vextract_for_size<int Opcode,
560 X86VectorVTInfo From, X86VectorVTInfo To,
561 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
562 PatFrag vextract_extract,
563 SDNodeXForm EXTRACT_get_vextract_imm> {
564 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
565 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
566 (ins VR512:$src1, u8imm:$idx),
567 "vextract" # To.EltTypeName # "x4",
568 "$idx, $src1", "$src1, $idx",
569 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
571 AVX512AIi8Base, EVEX, EVEX_V512;
573 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
574 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
575 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
576 "$dst, $src1, $src2}",
577 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
580 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
582 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
583 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
585 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
587 // A 128/256-bit subvector extract from the first 512-bit vector position is
588 // a subregister copy that needs no instruction.
589 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
591 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
593 // And for the alternative types.
594 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
596 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
598 // Intrinsic call with masking.
599 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
601 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
602 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
603 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
604 VR512:$src1, imm:$idx)>;
606 // Intrinsic call with zero-masking.
607 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
609 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
610 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
611 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
612 VR512:$src1, imm:$idx)>;
614 // Intrinsic call without masking.
615 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
617 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
618 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
619 VR512:$src1, imm:$idx)>;
622 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
623 ValueType EltVT64, int Opcode64> {
624 defm NAME # "32x4" : vextract_for_size<Opcode32,
625 X86VectorVTInfo<16, EltVT32, VR512>,
626 X86VectorVTInfo< 4, EltVT32, VR128X>,
627 X86VectorVTInfo< 8, EltVT64, VR512>,
628 X86VectorVTInfo< 2, EltVT64, VR128X>,
630 EXTRACT_get_vextract128_imm>;
631 defm NAME # "64x4" : vextract_for_size<Opcode64,
632 X86VectorVTInfo< 8, EltVT64, VR512>,
633 X86VectorVTInfo< 4, EltVT64, VR256X>,
634 X86VectorVTInfo<16, EltVT32, VR512>,
635 X86VectorVTInfo< 8, EltVT32, VR256>,
637 EXTRACT_get_vextract256_imm>, VEX_W;
640 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
641 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
643 // A 128-bit subvector insert to the first 512-bit vector position
644 // is a subregister copy that needs no instruction.
645 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
646 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
647 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
649 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
650 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
651 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
653 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
654 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
655 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
657 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
658 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
659 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
662 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
663 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
664 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
665 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
666 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
667 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
668 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
669 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
671 // vextractps - extract 32 bits from XMM
672 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
673 (ins VR128X:$src1, u8imm:$src2),
674 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
675 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
678 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
679 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
680 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
681 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
682 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
684 //===---------------------------------------------------------------------===//
687 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
688 ValueType svt, X86VectorVTInfo _> {
689 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
690 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
691 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
695 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
696 (ins _.ScalarMemOp:$src),
697 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
698 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
703 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
704 AVX512VLVectorVTInfo _> {
705 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
708 let Predicates = [HasVLX] in {
709 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
714 let ExeDomain = SSEPackedSingle in {
715 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
716 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
717 let Predicates = [HasVLX] in {
718 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
719 v4f32, v4f32x_info>, EVEX_V128,
720 EVEX_CD8<32, CD8VT1>;
724 let ExeDomain = SSEPackedDouble in {
725 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
726 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
729 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
730 // Later, we can canonize broadcast instructions before ISel phase and
731 // eliminate additional patterns on ISel.
732 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
733 // representations of source
734 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
735 X86VectorVTInfo _, RegisterClass SrcRC_v,
736 RegisterClass SrcRC_s> {
737 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
738 (!cast<Instruction>(InstName##"r")
739 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
741 let AddedComplexity = 30 in {
742 def : Pat<(_.VT (vselect _.KRCWM:$mask,
743 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
744 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
745 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
747 def : Pat<(_.VT(vselect _.KRCWM:$mask,
748 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
749 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
750 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
754 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
756 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
759 let Predicates = [HasVLX] in {
760 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
761 v8f32x_info, VR128X, FR32X>;
762 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
763 v4f32x_info, VR128X, FR32X>;
764 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
765 v4f64x_info, VR128X, FR64X>;
768 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
769 (VBROADCASTSSZm addr:$src)>;
770 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
771 (VBROADCASTSDZm addr:$src)>;
773 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
774 (VBROADCASTSSZm addr:$src)>;
775 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
776 (VBROADCASTSDZm addr:$src)>;
778 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
779 RegisterClass SrcRC> {
780 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
781 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
782 "$src", "$src", []>, T8PD, EVEX;
785 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
786 RegisterClass SrcRC, Predicate prd> {
787 let Predicates = [prd] in
788 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
789 let Predicates = [prd, HasVLX] in {
790 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
791 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
795 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
797 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
799 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
801 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
804 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
805 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
807 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
808 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
810 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
811 (VPBROADCASTDrZr GR32:$src)>;
812 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
813 (VPBROADCASTQrZr GR64:$src)>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
816 (VPBROADCASTDrZr GR32:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
818 (VPBROADCASTQrZr GR64:$src)>;
820 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
821 (v16i32 immAllZerosV), (i16 GR16:$mask))),
822 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
823 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
824 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
825 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
827 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86MemOperand x86memop, PatFrag ld_frag,
829 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
831 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
834 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
835 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
837 !strconcat(OpcodeStr,
838 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
840 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
842 !strconcat(OpcodeStr,
843 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
846 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
849 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
850 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
855 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
857 !strconcat(OpcodeStr,
858 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
859 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
860 (X86VBroadcast (ld_frag addr:$src)),
861 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
865 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
866 loadi32, VR512, v16i32, v4i32, VK16WM>,
867 EVEX_V512, EVEX_CD8<32, CD8VT1>;
868 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
869 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
870 EVEX_CD8<64, CD8VT1>;
872 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
873 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
875 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
878 (_Dst.VT (X86SubVBroadcast
879 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
880 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
882 !strconcat(OpcodeStr,
883 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
885 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
887 !strconcat(OpcodeStr,
888 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
893 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
894 v16i32_info, v4i32x_info>,
895 EVEX_V512, EVEX_CD8<32, CD8VT4>;
896 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
897 v16f32_info, v4f32x_info>,
898 EVEX_V512, EVEX_CD8<32, CD8VT4>;
899 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
900 v8i64_info, v4i64x_info>, VEX_W,
901 EVEX_V512, EVEX_CD8<64, CD8VT4>;
902 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
903 v8f64_info, v4f64x_info>, VEX_W,
904 EVEX_V512, EVEX_CD8<64, CD8VT4>;
906 let Predicates = [HasVLX] in {
907 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
908 v8i32x_info, v4i32x_info>,
909 EVEX_V256, EVEX_CD8<32, CD8VT4>;
910 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
911 v8f32x_info, v4f32x_info>,
912 EVEX_V256, EVEX_CD8<32, CD8VT4>;
914 let Predicates = [HasVLX, HasDQI] in {
915 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
916 v4i64x_info, v2i64x_info>, VEX_W,
917 EVEX_V256, EVEX_CD8<64, CD8VT2>;
918 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
919 v4f64x_info, v2f64x_info>, VEX_W,
920 EVEX_V256, EVEX_CD8<64, CD8VT2>;
922 let Predicates = [HasDQI] in {
923 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
924 v8i64_info, v2i64x_info>, VEX_W,
925 EVEX_V512, EVEX_CD8<64, CD8VT2>;
926 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
927 v16i32_info, v8i32x_info>,
928 EVEX_V512, EVEX_CD8<32, CD8VT8>;
929 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
930 v8f64_info, v2f64x_info>, VEX_W,
931 EVEX_V512, EVEX_CD8<64, CD8VT2>;
932 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
933 v16f32_info, v8f32x_info>,
934 EVEX_V512, EVEX_CD8<32, CD8VT8>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
938 (VPBROADCASTDZrr VR128X:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
940 (VPBROADCASTQZrr VR128X:$src)>;
942 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
943 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
944 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
945 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
947 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
948 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
949 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
950 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
952 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
953 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
954 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
955 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
957 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
958 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
959 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
960 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
962 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
963 (VBROADCASTSSZr VR128X:$src)>;
964 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
965 (VBROADCASTSDZr VR128X:$src)>;
967 // Provide fallback in case the load node that is used in the patterns above
968 // is used by additional users, which prevents the pattern selection.
969 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
970 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
971 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
972 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
975 //===----------------------------------------------------------------------===//
976 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
979 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
981 let Predicates = [HasCDI] in
982 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
984 []>, EVEX, EVEX_V512;
986 let Predicates = [HasCDI, HasVLX] in {
987 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
988 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
989 []>, EVEX, EVEX_V128;
990 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
991 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
992 []>, EVEX, EVEX_V256;
996 let Predicates = [HasCDI] in {
997 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
999 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1003 //===----------------------------------------------------------------------===//
1006 // -- immediate form --
1007 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1008 X86VectorVTInfo _> {
1009 let ExeDomain = _.ExeDomain in {
1010 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1011 (ins _.RC:$src1, u8imm:$src2),
1012 !strconcat(OpcodeStr,
1013 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1015 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1017 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1018 (ins _.MemOp:$src1, u8imm:$src2),
1019 !strconcat(OpcodeStr,
1020 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1022 (_.VT (OpNode (_.LdFrag addr:$src1),
1023 (i8 imm:$src2))))]>,
1024 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1028 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1029 X86VectorVTInfo Ctrl> :
1030 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1031 let ExeDomain = _.ExeDomain in {
1032 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1033 (ins _.RC:$src1, _.RC:$src2),
1034 !strconcat("vpermil" # _.Suffix,
1035 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 (_.VT (X86VPermilpv _.RC:$src1,
1038 (Ctrl.VT Ctrl.RC:$src2))))]>,
1040 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1041 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1042 !strconcat("vpermil" # _.Suffix,
1043 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1045 (_.VT (X86VPermilpv _.RC:$src1,
1046 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1051 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
1053 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
1056 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1058 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1061 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1062 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1063 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1064 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1066 // -- VPERM - register form --
1067 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1068 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
1070 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1071 (ins RC:$src1, RC:$src2),
1072 !strconcat(OpcodeStr,
1073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1075 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
1077 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1078 (ins RC:$src1, x86memop:$src2),
1079 !strconcat(OpcodeStr,
1080 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1082 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
1086 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
1087 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1088 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
1089 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1090 let ExeDomain = SSEPackedSingle in
1091 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
1092 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1093 let ExeDomain = SSEPackedDouble in
1094 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
1095 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1097 // -- VPERM2I - 3 source operands form --
1098 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
1099 PatFrag mem_frag, X86MemOperand x86memop,
1100 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
1101 let Constraints = "$src1 = $dst" in {
1102 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1103 (ins RC:$src1, RC:$src2, RC:$src3),
1104 !strconcat(OpcodeStr,
1105 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1107 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
1110 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1111 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1112 !strconcat(OpcodeStr,
1113 "\t{$src3, $src2, $dst {${mask}}|"
1114 "$dst {${mask}}, $src2, $src3}"),
1115 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1116 (OpNode RC:$src1, RC:$src2,
1121 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1122 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1123 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1124 !strconcat(OpcodeStr,
1125 "\t{$src3, $src2, $dst {${mask}} {z} |",
1126 "$dst {${mask}} {z}, $src2, $src3}"),
1127 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1128 (OpNode RC:$src1, RC:$src2,
1131 (v16i32 immAllZerosV))))))]>,
1134 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1135 (ins RC:$src1, RC:$src2, x86memop:$src3),
1136 !strconcat(OpcodeStr,
1137 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1139 (OpVT (OpNode RC:$src1, RC:$src2,
1140 (mem_frag addr:$src3))))]>, EVEX_4V;
1142 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1143 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1144 !strconcat(OpcodeStr,
1145 "\t{$src3, $src2, $dst {${mask}}|"
1146 "$dst {${mask}}, $src2, $src3}"),
1148 (OpVT (vselect KRC:$mask,
1149 (OpNode RC:$src1, RC:$src2,
1150 (mem_frag addr:$src3)),
1154 let AddedComplexity = 10 in // Prefer over the rrkz variant
1155 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1156 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1157 !strconcat(OpcodeStr,
1158 "\t{$src3, $src2, $dst {${mask}} {z}|"
1159 "$dst {${mask}} {z}, $src2, $src3}"),
1161 (OpVT (vselect KRC:$mask,
1162 (OpNode RC:$src1, RC:$src2,
1163 (mem_frag addr:$src3)),
1165 (v16i32 immAllZerosV))))))]>,
1169 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1170 i512mem, X86VPermiv3, v16i32, VK16WM>,
1171 EVEX_V512, EVEX_CD8<32, CD8VF>;
1172 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1173 i512mem, X86VPermiv3, v8i64, VK8WM>,
1174 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1175 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1176 i512mem, X86VPermiv3, v16f32, VK16WM>,
1177 EVEX_V512, EVEX_CD8<32, CD8VF>;
1178 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1179 i512mem, X86VPermiv3, v8f64, VK8WM>,
1180 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1182 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1183 PatFrag mem_frag, X86MemOperand x86memop,
1184 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1185 ValueType MaskVT, RegisterClass MRC> :
1186 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1188 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1189 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1190 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1192 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1193 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1194 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1195 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1198 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1199 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1200 EVEX_V512, EVEX_CD8<32, CD8VF>;
1201 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1202 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1203 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1204 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1205 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1206 EVEX_V512, EVEX_CD8<32, CD8VF>;
1207 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1208 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1209 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1211 //===----------------------------------------------------------------------===//
1212 // AVX-512 - BLEND using mask
1214 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1215 let ExeDomain = _.ExeDomain in {
1216 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1217 (ins _.RC:$src1, _.RC:$src2),
1218 !strconcat(OpcodeStr,
1219 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1221 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1222 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1223 !strconcat(OpcodeStr,
1224 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1225 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1226 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1227 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1228 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1229 !strconcat(OpcodeStr,
1230 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1231 []>, EVEX_4V, EVEX_KZ;
1232 let mayLoad = 1 in {
1233 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1234 (ins _.RC:$src1, _.MemOp:$src2),
1235 !strconcat(OpcodeStr,
1236 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1237 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1238 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1239 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1240 !strconcat(OpcodeStr,
1241 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1242 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1243 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1244 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1245 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1246 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1247 !strconcat(OpcodeStr,
1248 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1249 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1253 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1255 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1256 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1257 !strconcat(OpcodeStr,
1258 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1259 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1260 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1261 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1262 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1264 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1265 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1266 !strconcat(OpcodeStr,
1267 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1268 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1269 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1273 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1274 AVX512VLVectorVTInfo VTInfo> {
1275 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1276 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1278 let Predicates = [HasVLX] in {
1279 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1280 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1281 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1282 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1286 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1287 AVX512VLVectorVTInfo VTInfo> {
1288 let Predicates = [HasBWI] in
1289 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1291 let Predicates = [HasBWI, HasVLX] in {
1292 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1293 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1298 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1299 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1300 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1301 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1302 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1303 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1306 let Predicates = [HasAVX512] in {
1307 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1308 (v8f32 VR256X:$src2))),
1310 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1311 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1312 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1314 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1315 (v8i32 VR256X:$src2))),
1317 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1319 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1321 //===----------------------------------------------------------------------===//
1322 // Compare Instructions
1323 //===----------------------------------------------------------------------===//
1325 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1326 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1327 SDNode OpNode, ValueType VT,
1328 PatFrag ld_frag, string Suffix> {
1329 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1330 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1331 !strconcat("vcmp${cc}", Suffix,
1332 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1333 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1334 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1335 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1336 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1337 !strconcat("vcmp${cc}", Suffix,
1338 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1339 [(set VK1:$dst, (OpNode (VT RC:$src1),
1340 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1341 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1342 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1343 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1344 !strconcat("vcmp", Suffix,
1345 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1346 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1348 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1349 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1350 !strconcat("vcmp", Suffix,
1351 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1352 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1356 let Predicates = [HasAVX512] in {
1357 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1359 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1363 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1364 X86VectorVTInfo _> {
1365 def rr : AVX512BI<opc, MRMSrcReg,
1366 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1368 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1369 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1371 def rm : AVX512BI<opc, MRMSrcMem,
1372 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1374 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1375 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1376 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1377 def rrk : AVX512BI<opc, MRMSrcReg,
1378 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1379 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1380 "$dst {${mask}}, $src1, $src2}"),
1381 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1382 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1383 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1385 def rmk : AVX512BI<opc, MRMSrcMem,
1386 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1387 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1388 "$dst {${mask}}, $src1, $src2}"),
1389 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1390 (OpNode (_.VT _.RC:$src1),
1392 (_.LdFrag addr:$src2))))))],
1393 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1396 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1397 X86VectorVTInfo _> :
1398 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1399 let mayLoad = 1 in {
1400 def rmb : AVX512BI<opc, MRMSrcMem,
1401 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1402 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1403 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1404 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1405 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1406 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1407 def rmbk : AVX512BI<opc, MRMSrcMem,
1408 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1409 _.ScalarMemOp:$src2),
1410 !strconcat(OpcodeStr,
1411 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1412 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1413 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1414 (OpNode (_.VT _.RC:$src1),
1416 (_.ScalarLdFrag addr:$src2)))))],
1417 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1421 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1422 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1423 let Predicates = [prd] in
1424 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1427 let Predicates = [prd, HasVLX] in {
1428 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1430 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1435 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1436 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1438 let Predicates = [prd] in
1439 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1442 let Predicates = [prd, HasVLX] in {
1443 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1445 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1450 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1451 avx512vl_i8_info, HasBWI>,
1454 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1455 avx512vl_i16_info, HasBWI>,
1456 EVEX_CD8<16, CD8VF>;
1458 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1459 avx512vl_i32_info, HasAVX512>,
1460 EVEX_CD8<32, CD8VF>;
1462 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1463 avx512vl_i64_info, HasAVX512>,
1464 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1466 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1467 avx512vl_i8_info, HasBWI>,
1470 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1471 avx512vl_i16_info, HasBWI>,
1472 EVEX_CD8<16, CD8VF>;
1474 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1475 avx512vl_i32_info, HasAVX512>,
1476 EVEX_CD8<32, CD8VF>;
1478 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1479 avx512vl_i64_info, HasAVX512>,
1480 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1482 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1483 (COPY_TO_REGCLASS (VPCMPGTDZrr
1484 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1485 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1487 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1488 (COPY_TO_REGCLASS (VPCMPEQDZrr
1489 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1490 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1492 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1493 X86VectorVTInfo _> {
1494 def rri : AVX512AIi8<opc, MRMSrcReg,
1495 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1496 !strconcat("vpcmp${cc}", Suffix,
1497 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1498 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1500 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1502 def rmi : AVX512AIi8<opc, MRMSrcMem,
1503 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1504 !strconcat("vpcmp${cc}", Suffix,
1505 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1506 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1507 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1509 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1510 def rrik : AVX512AIi8<opc, MRMSrcReg,
1511 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1513 !strconcat("vpcmp${cc}", Suffix,
1514 "\t{$src2, $src1, $dst {${mask}}|",
1515 "$dst {${mask}}, $src1, $src2}"),
1516 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1517 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1519 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1521 def rmik : AVX512AIi8<opc, MRMSrcMem,
1522 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1524 !strconcat("vpcmp${cc}", Suffix,
1525 "\t{$src2, $src1, $dst {${mask}}|",
1526 "$dst {${mask}}, $src1, $src2}"),
1527 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1528 (OpNode (_.VT _.RC:$src1),
1529 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1531 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1533 // Accept explicit immediate argument form instead of comparison code.
1534 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1535 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1536 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1537 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1538 "$dst, $src1, $src2, $cc}"),
1539 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1541 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1542 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1543 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1544 "$dst, $src1, $src2, $cc}"),
1545 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1546 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1547 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1549 !strconcat("vpcmp", Suffix,
1550 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1551 "$dst {${mask}}, $src1, $src2, $cc}"),
1552 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1554 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1555 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1557 !strconcat("vpcmp", Suffix,
1558 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1559 "$dst {${mask}}, $src1, $src2, $cc}"),
1560 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1564 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1565 X86VectorVTInfo _> :
1566 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1567 def rmib : AVX512AIi8<opc, MRMSrcMem,
1568 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1570 !strconcat("vpcmp${cc}", Suffix,
1571 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1572 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1573 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1574 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1576 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1577 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1578 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1579 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1580 !strconcat("vpcmp${cc}", Suffix,
1581 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1582 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1583 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1584 (OpNode (_.VT _.RC:$src1),
1585 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1587 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1589 // Accept explicit immediate argument form instead of comparison code.
1590 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1591 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1592 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1594 !strconcat("vpcmp", Suffix,
1595 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1596 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1597 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1598 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1599 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1600 _.ScalarMemOp:$src2, u8imm:$cc),
1601 !strconcat("vpcmp", Suffix,
1602 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1603 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1604 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1608 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1609 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1610 let Predicates = [prd] in
1611 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1613 let Predicates = [prd, HasVLX] in {
1614 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1615 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1619 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1620 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1621 let Predicates = [prd] in
1622 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1625 let Predicates = [prd, HasVLX] in {
1626 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1628 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1633 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1634 HasBWI>, EVEX_CD8<8, CD8VF>;
1635 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1636 HasBWI>, EVEX_CD8<8, CD8VF>;
1638 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1639 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1640 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1641 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1643 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1644 HasAVX512>, EVEX_CD8<32, CD8VF>;
1645 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1646 HasAVX512>, EVEX_CD8<32, CD8VF>;
1648 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1649 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1650 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1651 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1653 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1655 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1656 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1657 "vcmp${cc}"#_.Suffix,
1658 "$src2, $src1", "$src1, $src2",
1659 (X86cmpm (_.VT _.RC:$src1),
1663 let mayLoad = 1 in {
1664 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1665 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1666 "vcmp${cc}"#_.Suffix,
1667 "$src2, $src1", "$src1, $src2",
1668 (X86cmpm (_.VT _.RC:$src1),
1669 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1672 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1674 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1675 "vcmp${cc}"#_.Suffix,
1676 "${src2}"##_.BroadcastStr##", $src1",
1677 "$src1, ${src2}"##_.BroadcastStr,
1678 (X86cmpm (_.VT _.RC:$src1),
1679 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1682 // Accept explicit immediate argument form instead of comparison code.
1683 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1684 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1686 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1688 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1690 let mayLoad = 1 in {
1691 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1693 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1695 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1697 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1699 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1701 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1702 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1707 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1708 // comparison code form (VCMP[EQ/LT/LE/...]
1709 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1710 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1711 "vcmp${cc}"#_.Suffix,
1712 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1713 (X86cmpmRnd (_.VT _.RC:$src1),
1716 (i32 FROUND_NO_EXC))>, EVEX_B;
1718 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1719 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1721 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1723 "$cc,{sae}, $src2, $src1",
1724 "$src1, $src2,{sae}, $cc">, EVEX_B;
1728 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1729 let Predicates = [HasAVX512] in {
1730 defm Z : avx512_vcmp_common<_.info512>,
1731 avx512_vcmp_sae<_.info512>, EVEX_V512;
1734 let Predicates = [HasAVX512,HasVLX] in {
1735 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1736 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1740 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1741 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1742 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1743 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1745 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1746 (COPY_TO_REGCLASS (VCMPPSZrri
1747 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1748 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1750 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1751 (COPY_TO_REGCLASS (VPCMPDZrri
1752 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1753 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1755 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1756 (COPY_TO_REGCLASS (VPCMPUDZrri
1757 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1758 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1761 //-----------------------------------------------------------------
1762 // Mask register copy, including
1763 // - copy between mask registers
1764 // - load/store mask registers
1765 // - copy from GPR to mask register and vice versa
1767 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1768 string OpcodeStr, RegisterClass KRC,
1769 ValueType vvt, X86MemOperand x86memop> {
1770 let hasSideEffects = 0 in {
1771 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1772 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1774 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1775 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1776 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1778 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1779 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1780 [(store KRC:$src, addr:$dst)]>;
1784 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1786 RegisterClass KRC, RegisterClass GRC> {
1787 let hasSideEffects = 0 in {
1788 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1789 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1790 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1795 let Predicates = [HasDQI] in
1796 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1797 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1800 let Predicates = [HasAVX512] in
1801 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1802 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1805 let Predicates = [HasBWI] in {
1806 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1808 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1812 let Predicates = [HasBWI] in {
1813 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1815 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1819 // GR from/to mask register
1820 let Predicates = [HasDQI] in {
1821 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1822 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1823 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1824 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1826 let Predicates = [HasAVX512] in {
1827 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1828 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1829 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1830 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1832 let Predicates = [HasBWI] in {
1833 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1834 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1836 let Predicates = [HasBWI] in {
1837 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1838 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1842 let Predicates = [HasDQI] in {
1843 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1844 (KMOVBmk addr:$dst, VK8:$src)>;
1845 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1846 (KMOVBkm addr:$src)>;
1848 let Predicates = [HasAVX512, NoDQI] in {
1849 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1850 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1851 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1852 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1854 let Predicates = [HasAVX512] in {
1855 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1856 (KMOVWmk addr:$dst, VK16:$src)>;
1857 def : Pat<(i1 (load addr:$src)),
1858 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1859 (MOV8rm addr:$src), sub_8bit)),
1861 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1862 (KMOVWkm addr:$src)>;
1864 let Predicates = [HasBWI] in {
1865 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1866 (KMOVDmk addr:$dst, VK32:$src)>;
1867 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1868 (KMOVDkm addr:$src)>;
1870 let Predicates = [HasBWI] in {
1871 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1872 (KMOVQmk addr:$dst, VK64:$src)>;
1873 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1874 (KMOVQkm addr:$src)>;
1877 let Predicates = [HasAVX512] in {
1878 def : Pat<(i1 (trunc (i64 GR64:$src))),
1879 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1882 def : Pat<(i1 (trunc (i32 GR32:$src))),
1883 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1885 def : Pat<(i1 (trunc (i8 GR8:$src))),
1887 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1889 def : Pat<(i1 (trunc (i16 GR16:$src))),
1891 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1894 def : Pat<(i32 (zext VK1:$src)),
1895 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1896 def : Pat<(i8 (zext VK1:$src)),
1899 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1900 def : Pat<(i64 (zext VK1:$src)),
1901 (AND64ri8 (SUBREG_TO_REG (i64 0),
1902 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1903 def : Pat<(i16 (zext VK1:$src)),
1905 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1907 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1908 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1909 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1910 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1912 let Predicates = [HasBWI] in {
1913 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1914 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1915 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1916 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1920 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1921 let Predicates = [HasAVX512, NoDQI] in {
1922 // GR from/to 8-bit mask without native support
1923 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1925 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1926 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1928 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1932 let Predicates = [HasAVX512] in {
1933 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1934 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1935 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1936 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1938 let Predicates = [HasBWI] in {
1939 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1940 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1941 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1942 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1945 // Mask unary operation
1947 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1948 RegisterClass KRC, SDPatternOperator OpNode,
1950 let Predicates = [prd] in
1951 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1952 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1953 [(set KRC:$dst, (OpNode KRC:$src))]>;
1956 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1957 SDPatternOperator OpNode> {
1958 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1960 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1961 HasAVX512>, VEX, PS;
1962 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1963 HasBWI>, VEX, PD, VEX_W;
1964 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1965 HasBWI>, VEX, PS, VEX_W;
1968 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1970 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1971 let Predicates = [HasAVX512] in
1972 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1974 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1975 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1977 defm : avx512_mask_unop_int<"knot", "KNOT">;
1979 let Predicates = [HasDQI] in
1980 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1981 let Predicates = [HasAVX512] in
1982 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1983 let Predicates = [HasBWI] in
1984 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1985 let Predicates = [HasBWI] in
1986 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1988 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1989 let Predicates = [HasAVX512, NoDQI] in {
1990 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1991 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1992 def : Pat<(not VK8:$src),
1994 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1996 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1997 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1998 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1999 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2001 // Mask binary operation
2002 // - KAND, KANDN, KOR, KXNOR, KXOR
2003 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2004 RegisterClass KRC, SDPatternOperator OpNode,
2005 Predicate prd, bit IsCommutable> {
2006 let Predicates = [prd], isCommutable = IsCommutable in
2007 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2008 !strconcat(OpcodeStr,
2009 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2010 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2013 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2014 SDPatternOperator OpNode, bit IsCommutable> {
2015 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2016 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2017 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2018 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
2019 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2020 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2021 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2022 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2025 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2026 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2028 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2029 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2030 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2031 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2032 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2034 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2035 let Predicates = [HasAVX512] in
2036 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2037 (i16 GR16:$src1), (i16 GR16:$src2)),
2038 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2039 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2040 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2043 defm : avx512_mask_binop_int<"kand", "KAND">;
2044 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2045 defm : avx512_mask_binop_int<"kor", "KOR">;
2046 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2047 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2049 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2050 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2051 // for the DQI set, this type is legal and KxxxB instruction is used
2052 let Predicates = [NoDQI] in
2053 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2055 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2056 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2058 // All types smaller than 8 bits require conversion anyway
2059 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2060 (COPY_TO_REGCLASS (Inst
2061 (COPY_TO_REGCLASS VK1:$src1, VK16),
2062 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2063 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2064 (COPY_TO_REGCLASS (Inst
2065 (COPY_TO_REGCLASS VK2:$src1, VK16),
2066 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2067 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2068 (COPY_TO_REGCLASS (Inst
2069 (COPY_TO_REGCLASS VK4:$src1, VK16),
2070 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2073 defm : avx512_binop_pat<and, KANDWrr>;
2074 defm : avx512_binop_pat<andn, KANDNWrr>;
2075 defm : avx512_binop_pat<or, KORWrr>;
2076 defm : avx512_binop_pat<xnor, KXNORWrr>;
2077 defm : avx512_binop_pat<xor, KXORWrr>;
2079 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2080 (KXNORWrr VK16:$src1, VK16:$src2)>;
2081 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2082 (KXNORBrr VK8:$src1, VK8:$src2)>;
2083 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2084 (KXNORDrr VK32:$src1, VK32:$src2)>;
2085 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2086 (KXNORQrr VK64:$src1, VK64:$src2)>;
2088 let Predicates = [NoDQI] in
2089 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2090 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2091 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2093 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2094 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2095 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2097 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2098 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2099 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2101 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2102 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2103 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2106 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2107 RegisterClass KRC> {
2108 let Predicates = [HasAVX512] in
2109 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2110 !strconcat(OpcodeStr,
2111 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2114 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2115 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2119 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2120 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2121 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2122 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2125 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2126 let Predicates = [HasAVX512] in
2127 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2128 (i16 GR16:$src1), (i16 GR16:$src2)),
2129 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2130 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2131 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2133 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2136 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2138 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2139 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2140 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2141 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2144 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2145 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2147 let Predicates = [HasDQI] in
2148 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2150 let Predicates = [HasBWI] in {
2151 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2153 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2158 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2161 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2163 let Predicates = [HasAVX512] in
2164 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2165 !strconcat(OpcodeStr,
2166 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2167 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2170 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2172 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2174 let Predicates = [HasDQI] in
2175 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2177 let Predicates = [HasBWI] in {
2178 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2180 let Predicates = [HasDQI] in
2181 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2186 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2187 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2189 // Mask setting all 0s or 1s
2190 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2191 let Predicates = [HasAVX512] in
2192 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2193 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2194 [(set KRC:$dst, (VT Val))]>;
2197 multiclass avx512_mask_setop_w<PatFrag Val> {
2198 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2199 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2200 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2201 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2204 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2205 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2207 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2208 let Predicates = [HasAVX512] in {
2209 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2210 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2211 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2212 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2213 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2214 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2215 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2217 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2218 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2220 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2221 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2223 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2224 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2226 let Predicates = [HasVLX] in {
2227 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2228 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2229 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2230 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2231 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2232 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2233 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2234 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2235 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2236 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2239 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2240 (v8i1 (COPY_TO_REGCLASS
2241 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2242 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2244 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2245 (v8i1 (COPY_TO_REGCLASS
2246 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2247 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2249 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2250 (v4i1 (COPY_TO_REGCLASS
2251 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2252 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2254 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2255 (v4i1 (COPY_TO_REGCLASS
2256 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2257 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2259 //===----------------------------------------------------------------------===//
2260 // AVX-512 - Aligned and unaligned load and store
2264 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2265 PatFrag ld_frag, PatFrag mload,
2266 bit IsReMaterializable = 1> {
2267 let hasSideEffects = 0 in {
2268 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2269 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2271 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2272 (ins _.KRCWM:$mask, _.RC:$src),
2273 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2274 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2277 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2278 SchedRW = [WriteLoad] in
2279 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2280 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2281 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2284 let Constraints = "$src0 = $dst" in {
2285 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2286 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2287 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2288 "${dst} {${mask}}, $src1}"),
2289 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2291 (_.VT _.RC:$src0))))], _.ExeDomain>,
2293 let mayLoad = 1, SchedRW = [WriteLoad] in
2294 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2295 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2296 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2297 "${dst} {${mask}}, $src1}"),
2298 [(set _.RC:$dst, (_.VT
2299 (vselect _.KRCWM:$mask,
2300 (_.VT (bitconvert (ld_frag addr:$src1))),
2301 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2303 let mayLoad = 1, SchedRW = [WriteLoad] in
2304 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2305 (ins _.KRCWM:$mask, _.MemOp:$src),
2306 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2307 "${dst} {${mask}} {z}, $src}",
2308 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2309 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2310 _.ExeDomain>, EVEX, EVEX_KZ;
2312 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2313 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2315 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2316 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2318 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2319 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2320 _.KRCWM:$mask, addr:$ptr)>;
2323 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2324 AVX512VLVectorVTInfo _,
2326 bit IsReMaterializable = 1> {
2327 let Predicates = [prd] in
2328 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2329 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2331 let Predicates = [prd, HasVLX] in {
2332 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2333 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2334 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2335 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2339 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2340 AVX512VLVectorVTInfo _,
2342 bit IsReMaterializable = 1> {
2343 let Predicates = [prd] in
2344 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2345 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2347 let Predicates = [prd, HasVLX] in {
2348 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2349 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2350 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2351 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2355 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2356 PatFrag st_frag, PatFrag mstore> {
2357 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2358 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2359 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2361 let Constraints = "$src1 = $dst" in
2362 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2363 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2365 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2366 [], _.ExeDomain>, EVEX, EVEX_K;
2367 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2368 (ins _.KRCWM:$mask, _.RC:$src),
2370 "\t{$src, ${dst} {${mask}} {z}|" #
2371 "${dst} {${mask}} {z}, $src}",
2372 [], _.ExeDomain>, EVEX, EVEX_KZ;
2374 let mayStore = 1 in {
2375 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2376 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2377 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2378 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2379 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2380 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2381 [], _.ExeDomain>, EVEX, EVEX_K;
2384 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2385 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2386 _.KRCWM:$mask, _.RC:$src)>;
2390 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2391 AVX512VLVectorVTInfo _, Predicate prd> {
2392 let Predicates = [prd] in
2393 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2394 masked_store_unaligned>, EVEX_V512;
2396 let Predicates = [prd, HasVLX] in {
2397 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2398 masked_store_unaligned>, EVEX_V256;
2399 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2400 masked_store_unaligned>, EVEX_V128;
2404 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2405 AVX512VLVectorVTInfo _, Predicate prd> {
2406 let Predicates = [prd] in
2407 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2408 masked_store_aligned512>, EVEX_V512;
2410 let Predicates = [prd, HasVLX] in {
2411 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2412 masked_store_aligned256>, EVEX_V256;
2413 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2414 masked_store_aligned128>, EVEX_V128;
2418 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2420 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2421 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2423 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2425 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2426 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2428 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2429 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2430 PS, EVEX_CD8<32, CD8VF>;
2432 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2433 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2434 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2436 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2437 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2438 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2440 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2441 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2442 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2444 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2445 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2446 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2448 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2449 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2450 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2452 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2453 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2454 (VMOVAPDZrm addr:$ptr)>;
2456 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2457 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2458 (VMOVAPSZrm addr:$ptr)>;
2460 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2462 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2464 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2466 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2469 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2471 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2473 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2475 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2478 let Predicates = [HasAVX512, NoVLX] in {
2479 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2480 (VMOVUPSZmrk addr:$ptr,
2481 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2482 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2484 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2485 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2486 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2488 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2489 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2490 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2491 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2494 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2496 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2497 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2499 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2501 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2502 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2504 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2505 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2506 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2508 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2509 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2510 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2512 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2513 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2514 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2516 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2517 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2518 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2520 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2521 (v16i32 immAllZerosV), GR16:$mask)),
2522 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2524 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2525 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2526 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2528 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2530 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2532 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2534 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2537 let AddedComplexity = 20 in {
2538 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2539 (bc_v8i64 (v16i32 immAllZerosV)))),
2540 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2542 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2543 (v8i64 VR512:$src))),
2544 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2547 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2548 (v16i32 immAllZerosV))),
2549 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2551 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2552 (v16i32 VR512:$src))),
2553 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2556 let Predicates = [HasAVX512, NoVLX] in {
2557 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2558 (VMOVDQU32Zmrk addr:$ptr,
2559 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2560 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2562 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2563 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2564 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2567 // Move Int Doubleword to Packed Double Int
2569 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2570 "vmovd\t{$src, $dst|$dst, $src}",
2572 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2574 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2575 "vmovd\t{$src, $dst|$dst, $src}",
2577 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2578 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2579 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2580 "vmovq\t{$src, $dst|$dst, $src}",
2582 (v2i64 (scalar_to_vector GR64:$src)))],
2583 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2584 let isCodeGenOnly = 1 in {
2585 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2586 "vmovq\t{$src, $dst|$dst, $src}",
2587 [(set FR64:$dst, (bitconvert GR64:$src))],
2588 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2589 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2590 "vmovq\t{$src, $dst|$dst, $src}",
2591 [(set GR64:$dst, (bitconvert FR64:$src))],
2592 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2594 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2595 "vmovq\t{$src, $dst|$dst, $src}",
2596 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2597 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2598 EVEX_CD8<64, CD8VT1>;
2600 // Move Int Doubleword to Single Scalar
2602 let isCodeGenOnly = 1 in {
2603 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2604 "vmovd\t{$src, $dst|$dst, $src}",
2605 [(set FR32X:$dst, (bitconvert GR32:$src))],
2606 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2608 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2609 "vmovd\t{$src, $dst|$dst, $src}",
2610 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2611 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2614 // Move doubleword from xmm register to r/m32
2616 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2617 "vmovd\t{$src, $dst|$dst, $src}",
2618 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2619 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2621 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2622 (ins i32mem:$dst, VR128X:$src),
2623 "vmovd\t{$src, $dst|$dst, $src}",
2624 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2625 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2626 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2628 // Move quadword from xmm1 register to r/m64
2630 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2631 "vmovq\t{$src, $dst|$dst, $src}",
2632 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2634 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2635 Requires<[HasAVX512, In64BitMode]>;
2637 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2638 (ins i64mem:$dst, VR128X:$src),
2639 "vmovq\t{$src, $dst|$dst, $src}",
2640 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2641 addr:$dst)], IIC_SSE_MOVDQ>,
2642 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2643 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2645 // Move Scalar Single to Double Int
2647 let isCodeGenOnly = 1 in {
2648 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2650 "vmovd\t{$src, $dst|$dst, $src}",
2651 [(set GR32:$dst, (bitconvert FR32X:$src))],
2652 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2653 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2654 (ins i32mem:$dst, FR32X:$src),
2655 "vmovd\t{$src, $dst|$dst, $src}",
2656 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2657 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2660 // Move Quadword Int to Packed Quadword Int
2662 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2664 "vmovq\t{$src, $dst|$dst, $src}",
2666 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2667 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2669 //===----------------------------------------------------------------------===//
2670 // AVX-512 MOVSS, MOVSD
2671 //===----------------------------------------------------------------------===//
2673 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2674 SDNode OpNode, ValueType vt,
2675 X86MemOperand x86memop, PatFrag mem_pat> {
2676 let hasSideEffects = 0 in {
2677 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2678 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2679 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2680 (scalar_to_vector RC:$src2))))],
2681 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2682 let Constraints = "$src1 = $dst" in
2683 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2684 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2686 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2687 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2688 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2689 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2690 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2692 let mayStore = 1 in {
2693 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2694 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2695 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2697 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2698 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2699 [], IIC_SSE_MOV_S_MR>,
2700 EVEX, VEX_LIG, EVEX_K;
2702 } //hasSideEffects = 0
2705 let ExeDomain = SSEPackedSingle in
2706 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2707 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2709 let ExeDomain = SSEPackedDouble in
2710 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2711 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2713 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2714 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2715 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2717 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2718 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2719 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2721 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2722 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2723 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2725 // For the disassembler
2726 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2727 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2728 (ins VR128X:$src1, FR32X:$src2),
2729 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2731 XS, EVEX_4V, VEX_LIG;
2732 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2733 (ins VR128X:$src1, FR64X:$src2),
2734 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2736 XD, EVEX_4V, VEX_LIG, VEX_W;
2739 let Predicates = [HasAVX512] in {
2740 let AddedComplexity = 15 in {
2741 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2742 // MOVS{S,D} to the lower bits.
2743 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2744 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2745 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2746 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2747 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2748 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2749 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2750 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2752 // Move low f32 and clear high bits.
2753 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2754 (SUBREG_TO_REG (i32 0),
2755 (VMOVSSZrr (v4f32 (V_SET0)),
2756 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2757 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2758 (SUBREG_TO_REG (i32 0),
2759 (VMOVSSZrr (v4i32 (V_SET0)),
2760 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2763 let AddedComplexity = 20 in {
2764 // MOVSSrm zeros the high parts of the register; represent this
2765 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2766 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2767 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2768 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2769 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2770 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2771 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2773 // MOVSDrm zeros the high parts of the register; represent this
2774 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2775 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2776 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2777 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2778 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2779 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2780 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2781 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2782 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2783 def : Pat<(v2f64 (X86vzload addr:$src)),
2784 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2786 // Represent the same patterns above but in the form they appear for
2788 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2789 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2790 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2791 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2792 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2793 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2794 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2795 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2796 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2798 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2799 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2800 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2801 FR32X:$src)), sub_xmm)>;
2802 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2803 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2804 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2805 FR64X:$src)), sub_xmm)>;
2806 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2807 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2808 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2810 // Move low f64 and clear high bits.
2811 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2812 (SUBREG_TO_REG (i32 0),
2813 (VMOVSDZrr (v2f64 (V_SET0)),
2814 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2816 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2817 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2818 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2820 // Extract and store.
2821 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2823 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2824 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2826 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2828 // Shuffle with VMOVSS
2829 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2830 (VMOVSSZrr (v4i32 VR128X:$src1),
2831 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2832 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2833 (VMOVSSZrr (v4f32 VR128X:$src1),
2834 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2837 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2838 (SUBREG_TO_REG (i32 0),
2839 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2840 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2842 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2843 (SUBREG_TO_REG (i32 0),
2844 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2845 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2848 // Shuffle with VMOVSD
2849 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2850 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2851 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2852 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2853 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2854 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2855 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2856 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2859 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2860 (SUBREG_TO_REG (i32 0),
2861 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2862 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2864 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2865 (SUBREG_TO_REG (i32 0),
2866 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2867 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2870 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2871 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2872 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2873 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2874 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2875 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2876 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2877 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2880 let AddedComplexity = 15 in
2881 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2883 "vmovq\t{$src, $dst|$dst, $src}",
2884 [(set VR128X:$dst, (v2i64 (X86vzmovl
2885 (v2i64 VR128X:$src))))],
2886 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2888 let AddedComplexity = 20 in
2889 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2891 "vmovq\t{$src, $dst|$dst, $src}",
2892 [(set VR128X:$dst, (v2i64 (X86vzmovl
2893 (loadv2i64 addr:$src))))],
2894 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2895 EVEX_CD8<8, CD8VT8>;
2897 let Predicates = [HasAVX512] in {
2898 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2899 let AddedComplexity = 20 in {
2900 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2901 (VMOVDI2PDIZrm addr:$src)>;
2902 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2903 (VMOV64toPQIZrr GR64:$src)>;
2904 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2905 (VMOVDI2PDIZrr GR32:$src)>;
2907 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2908 (VMOVDI2PDIZrm addr:$src)>;
2909 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2910 (VMOVDI2PDIZrm addr:$src)>;
2911 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2912 (VMOVZPQILo2PQIZrm addr:$src)>;
2913 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2914 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2915 def : Pat<(v2i64 (X86vzload addr:$src)),
2916 (VMOVZPQILo2PQIZrm addr:$src)>;
2919 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2920 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2921 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2922 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2923 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2924 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2925 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2928 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2929 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2931 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2932 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2934 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2935 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2937 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2938 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2940 //===----------------------------------------------------------------------===//
2941 // AVX-512 - Non-temporals
2942 //===----------------------------------------------------------------------===//
2943 let SchedRW = [WriteLoad] in {
2944 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2945 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2946 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2947 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2948 EVEX_CD8<64, CD8VF>;
2950 let Predicates = [HasAVX512, HasVLX] in {
2951 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2953 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2954 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2955 EVEX_CD8<64, CD8VF>;
2957 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2959 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2960 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2961 EVEX_CD8<64, CD8VF>;
2965 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2966 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2967 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2968 let SchedRW = [WriteStore], mayStore = 1,
2969 AddedComplexity = 400 in
2970 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2971 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2972 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2975 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2976 string elty, string elsz, string vsz512,
2977 string vsz256, string vsz128, Domain d,
2978 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2979 let Predicates = [prd] in
2980 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2981 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2982 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2985 let Predicates = [prd, HasVLX] in {
2986 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2987 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2988 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2991 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2992 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2993 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2998 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2999 "i", "64", "8", "4", "2", SSEPackedInt,
3000 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3002 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3003 "f", "64", "8", "4", "2", SSEPackedDouble,
3004 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3006 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3007 "f", "32", "16", "8", "4", SSEPackedSingle,
3008 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3010 //===----------------------------------------------------------------------===//
3011 // AVX-512 - Integer arithmetic
3013 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3014 X86VectorVTInfo _, OpndItins itins,
3015 bit IsCommutable = 0> {
3016 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3017 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3018 "$src2, $src1", "$src1, $src2",
3019 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3020 itins.rr, IsCommutable>,
3021 AVX512BIBase, EVEX_4V;
3024 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3025 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3026 "$src2, $src1", "$src1, $src2",
3027 (_.VT (OpNode _.RC:$src1,
3028 (bitconvert (_.LdFrag addr:$src2)))),
3030 AVX512BIBase, EVEX_4V;
3033 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3034 X86VectorVTInfo _, OpndItins itins,
3035 bit IsCommutable = 0> :
3036 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3038 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3039 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3040 "${src2}"##_.BroadcastStr##", $src1",
3041 "$src1, ${src2}"##_.BroadcastStr,
3042 (_.VT (OpNode _.RC:$src1,
3044 (_.ScalarLdFrag addr:$src2)))),
3046 AVX512BIBase, EVEX_4V, EVEX_B;
3049 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3050 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3051 Predicate prd, bit IsCommutable = 0> {
3052 let Predicates = [prd] in
3053 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3054 IsCommutable>, EVEX_V512;
3056 let Predicates = [prd, HasVLX] in {
3057 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3058 IsCommutable>, EVEX_V256;
3059 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3060 IsCommutable>, EVEX_V128;
3064 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3065 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3066 Predicate prd, bit IsCommutable = 0> {
3067 let Predicates = [prd] in
3068 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3069 IsCommutable>, EVEX_V512;
3071 let Predicates = [prd, HasVLX] in {
3072 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3073 IsCommutable>, EVEX_V256;
3074 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3075 IsCommutable>, EVEX_V128;
3079 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3080 OpndItins itins, Predicate prd,
3081 bit IsCommutable = 0> {
3082 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3083 itins, prd, IsCommutable>,
3084 VEX_W, EVEX_CD8<64, CD8VF>;
3087 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3088 OpndItins itins, Predicate prd,
3089 bit IsCommutable = 0> {
3090 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3091 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3094 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3095 OpndItins itins, Predicate prd,
3096 bit IsCommutable = 0> {
3097 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3098 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3101 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3102 OpndItins itins, Predicate prd,
3103 bit IsCommutable = 0> {
3104 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3105 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3108 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3109 SDNode OpNode, OpndItins itins, Predicate prd,
3110 bit IsCommutable = 0> {
3111 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
3114 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
3118 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3119 SDNode OpNode, OpndItins itins, Predicate prd,
3120 bit IsCommutable = 0> {
3121 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
3124 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
3128 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3129 bits<8> opc_d, bits<8> opc_q,
3130 string OpcodeStr, SDNode OpNode,
3131 OpndItins itins, bit IsCommutable = 0> {
3132 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3133 itins, HasAVX512, IsCommutable>,
3134 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3135 itins, HasBWI, IsCommutable>;
3138 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3139 SDNode OpNode,X86VectorVTInfo _Src,
3140 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3141 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3142 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3143 "$src2, $src1","$src1, $src2",
3145 (_Src.VT _Src.RC:$src1),
3146 (_Src.VT _Src.RC:$src2))),
3147 itins.rr, IsCommutable>,
3148 AVX512BIBase, EVEX_4V;
3149 let mayLoad = 1 in {
3150 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3151 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3152 "$src2, $src1", "$src1, $src2",
3153 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3154 (bitconvert (_Src.LdFrag addr:$src2)))),
3156 AVX512BIBase, EVEX_4V;
3158 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3159 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3161 "${src2}"##_Dst.BroadcastStr##", $src1",
3162 "$src1, ${src2}"##_Dst.BroadcastStr,
3163 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3164 (_Dst.VT (X86VBroadcast
3165 (_Dst.ScalarLdFrag addr:$src2)))))),
3167 AVX512BIBase, EVEX_4V, EVEX_B;
3171 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3172 SSE_INTALU_ITINS_P, 1>;
3173 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3174 SSE_INTALU_ITINS_P, 0>;
3175 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3176 SSE_INTALU_ITINS_P, HasBWI, 1>;
3177 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3178 SSE_INTALU_ITINS_P, HasBWI, 0>;
3179 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3180 SSE_INTALU_ITINS_P, HasBWI, 1>;
3181 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3182 SSE_INTALU_ITINS_P, HasBWI, 0>;
3183 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3184 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3185 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3186 SSE_INTALU_ITINS_P, HasBWI, 1>;
3187 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3188 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3191 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3192 SDNode OpNode, bit IsCommutable = 0> {
3194 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3195 v16i32_info, v8i64_info, IsCommutable>,
3196 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3197 let Predicates = [HasVLX] in {
3198 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3199 v8i32x_info, v4i64x_info, IsCommutable>,
3200 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3201 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3202 v4i32x_info, v2i64x_info, IsCommutable>,
3203 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3207 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3209 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3212 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3213 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3214 let mayLoad = 1 in {
3215 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3216 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3218 "${src2}"##_Src.BroadcastStr##", $src1",
3219 "$src1, ${src2}"##_Src.BroadcastStr,
3220 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3221 (_Src.VT (X86VBroadcast
3222 (_Src.ScalarLdFrag addr:$src2))))))>,
3223 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3227 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3228 SDNode OpNode,X86VectorVTInfo _Src,
3229 X86VectorVTInfo _Dst> {
3230 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3231 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3232 "$src2, $src1","$src1, $src2",
3234 (_Src.VT _Src.RC:$src1),
3235 (_Src.VT _Src.RC:$src2)))>,
3236 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3237 let mayLoad = 1 in {
3238 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3239 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3240 "$src2, $src1", "$src1, $src2",
3241 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3242 (bitconvert (_Src.LdFrag addr:$src2))))>,
3243 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3247 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3249 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3251 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3252 v32i16_info>, EVEX_V512;
3253 let Predicates = [HasVLX] in {
3254 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3256 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3257 v16i16x_info>, EVEX_V256;
3258 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3260 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3261 v8i16x_info>, EVEX_V128;
3264 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3266 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3267 v64i8_info>, EVEX_V512;
3268 let Predicates = [HasVLX] in {
3269 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3270 v32i8x_info>, EVEX_V256;
3271 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3272 v16i8x_info>, EVEX_V128;
3275 let Predicates = [HasBWI] in {
3276 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3277 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3278 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3279 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3282 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3283 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3284 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3285 SSE_INTALU_ITINS_P, HasBWI, 1>;
3286 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3287 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3289 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3290 SSE_INTALU_ITINS_P, HasBWI, 1>;
3291 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3292 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3293 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3294 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3296 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3297 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3298 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3299 SSE_INTALU_ITINS_P, HasBWI, 1>;
3300 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3301 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3303 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3304 SSE_INTALU_ITINS_P, HasBWI, 1>;
3305 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3306 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3307 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3308 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3310 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3311 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3312 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3313 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3314 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3315 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3316 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3317 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3318 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3319 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3320 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3321 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3322 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3323 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3324 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3325 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3326 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3327 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3328 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3329 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3330 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3331 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3332 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3333 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3334 //===----------------------------------------------------------------------===//
3335 // AVX-512 - Unpack Instructions
3336 //===----------------------------------------------------------------------===//
3338 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3339 PatFrag mem_frag, RegisterClass RC,
3340 X86MemOperand x86memop, string asm,
3342 def rr : AVX512PI<opc, MRMSrcReg,
3343 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3345 (vt (OpNode RC:$src1, RC:$src2)))],
3347 def rm : AVX512PI<opc, MRMSrcMem,
3348 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3350 (vt (OpNode RC:$src1,
3351 (bitconvert (mem_frag addr:$src2)))))],
3355 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3356 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3357 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3358 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3359 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3360 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3361 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3362 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3363 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3364 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3365 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3366 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3368 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3369 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3370 X86MemOperand x86memop> {
3371 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3372 (ins RC:$src1, RC:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3374 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3375 IIC_SSE_UNPCK>, EVEX_4V;
3376 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3377 (ins RC:$src1, x86memop:$src2),
3378 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3379 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3380 (bitconvert (memop_frag addr:$src2)))))],
3381 IIC_SSE_UNPCK>, EVEX_4V;
3383 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3384 VR512, loadv16i32, i512mem>, EVEX_V512,
3385 EVEX_CD8<32, CD8VF>;
3386 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3387 VR512, loadv8i64, i512mem>, EVEX_V512,
3388 VEX_W, EVEX_CD8<64, CD8VF>;
3389 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3390 VR512, loadv16i32, i512mem>, EVEX_V512,
3391 EVEX_CD8<32, CD8VF>;
3392 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3393 VR512, loadv8i64, i512mem>, EVEX_V512,
3394 VEX_W, EVEX_CD8<64, CD8VF>;
3395 //===----------------------------------------------------------------------===//
3399 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3400 SDNode OpNode, PatFrag mem_frag,
3401 X86MemOperand x86memop, ValueType OpVT> {
3402 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3403 (ins RC:$src1, u8imm:$src2),
3404 !strconcat(OpcodeStr,
3405 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3407 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3409 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3410 (ins x86memop:$src1, u8imm:$src2),
3411 !strconcat(OpcodeStr,
3412 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3414 (OpVT (OpNode (mem_frag addr:$src1),
3415 (i8 imm:$src2))))]>, EVEX;
3418 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3419 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3421 //===----------------------------------------------------------------------===//
3422 // AVX-512 Logical Instructions
3423 //===----------------------------------------------------------------------===//
3425 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3426 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3427 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3428 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3429 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3430 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3431 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3432 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3434 //===----------------------------------------------------------------------===//
3435 // AVX-512 FP arithmetic
3436 //===----------------------------------------------------------------------===//
3437 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3438 SDNode OpNode, SDNode VecNode, OpndItins itins,
3441 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3442 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3443 "$src2, $src1", "$src1, $src2",
3444 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3445 (i32 FROUND_CURRENT)),
3446 itins.rr, IsCommutable>;
3448 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3449 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3450 "$src2, $src1", "$src1, $src2",
3451 (VecNode (_.VT _.RC:$src1),
3452 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3453 (i32 FROUND_CURRENT)),
3454 itins.rm, IsCommutable>;
3455 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3456 Predicates = [HasAVX512] in {
3457 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3458 (ins _.FRC:$src1, _.FRC:$src2),
3459 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3460 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3462 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3463 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3464 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3465 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3466 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3470 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3471 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3473 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3474 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3475 "$rc, $src2, $src1", "$src1, $src2, $rc",
3476 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3477 (i32 imm:$rc)), itins.rr, IsCommutable>,
3480 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3481 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3483 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3484 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3485 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3486 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3487 (i32 FROUND_NO_EXC))>, EVEX_B;
3490 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3492 SizeItins itins, bit IsCommutable> {
3493 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3494 itins.s, IsCommutable>,
3495 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3496 itins.s, IsCommutable>,
3497 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3498 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3499 itins.d, IsCommutable>,
3500 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3501 itins.d, IsCommutable>,
3502 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3505 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3507 SizeItins itins, bit IsCommutable> {
3508 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3509 itins.s, IsCommutable>,
3510 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3511 itins.s, IsCommutable>,
3512 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3513 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3514 itins.d, IsCommutable>,
3515 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3516 itins.d, IsCommutable>,
3517 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3519 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3520 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3521 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3522 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3523 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3524 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3526 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3527 X86VectorVTInfo _, bit IsCommutable> {
3528 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3529 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3530 "$src2, $src1", "$src1, $src2",
3531 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3532 let mayLoad = 1 in {
3533 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3534 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3535 "$src2, $src1", "$src1, $src2",
3536 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3537 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3538 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3539 "${src2}"##_.BroadcastStr##", $src1",
3540 "$src1, ${src2}"##_.BroadcastStr,
3541 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3542 (_.ScalarLdFrag addr:$src2))))>,
3547 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3548 X86VectorVTInfo _, bit IsCommutable> {
3549 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3550 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3551 "$rc, $src2, $src1", "$src1, $src2, $rc",
3552 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3553 EVEX_4V, EVEX_B, EVEX_RC;
3557 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3558 X86VectorVTInfo _, bit IsCommutable> {
3559 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3560 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3561 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3562 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3566 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3567 bit IsCommutable = 0> {
3568 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3569 IsCommutable>, EVEX_V512, PS,
3570 EVEX_CD8<32, CD8VF>;
3571 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3572 IsCommutable>, EVEX_V512, PD, VEX_W,
3573 EVEX_CD8<64, CD8VF>;
3575 // Define only if AVX512VL feature is present.
3576 let Predicates = [HasVLX] in {
3577 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3578 IsCommutable>, EVEX_V128, PS,
3579 EVEX_CD8<32, CD8VF>;
3580 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3581 IsCommutable>, EVEX_V256, PS,
3582 EVEX_CD8<32, CD8VF>;
3583 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3584 IsCommutable>, EVEX_V128, PD, VEX_W,
3585 EVEX_CD8<64, CD8VF>;
3586 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3587 IsCommutable>, EVEX_V256, PD, VEX_W,
3588 EVEX_CD8<64, CD8VF>;
3592 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3593 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3594 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3595 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3596 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3599 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3600 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3601 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3602 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3603 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3606 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3607 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3608 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3609 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3610 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3611 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3612 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3613 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3614 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3615 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3616 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3617 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3618 let Predicates = [HasDQI] in {
3619 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3620 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3621 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3622 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3625 //===----------------------------------------------------------------------===//
3626 // AVX-512 VPTESTM instructions
3627 //===----------------------------------------------------------------------===//
3629 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3630 X86VectorVTInfo _> {
3631 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3632 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3633 "$src2, $src1", "$src1, $src2",
3634 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3637 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3638 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3639 "$src2, $src1", "$src1, $src2",
3640 (OpNode (_.VT _.RC:$src1),
3641 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3643 EVEX_CD8<_.EltSize, CD8VF>;
3646 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3647 X86VectorVTInfo _> {
3649 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3650 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3651 "${src2}"##_.BroadcastStr##", $src1",
3652 "$src1, ${src2}"##_.BroadcastStr,
3653 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3654 (_.ScalarLdFrag addr:$src2))))>,
3655 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3657 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3658 AVX512VLVectorVTInfo _> {
3659 let Predicates = [HasAVX512] in
3660 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3661 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3663 let Predicates = [HasAVX512, HasVLX] in {
3664 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3665 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3666 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3667 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3671 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3672 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3674 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3675 avx512vl_i64_info>, VEX_W;
3678 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3680 let Predicates = [HasBWI] in {
3681 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3683 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3686 let Predicates = [HasVLX, HasBWI] in {
3688 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3690 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3692 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3694 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3699 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3701 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3702 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3704 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3705 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3707 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3708 (v16i32 VR512:$src2), (i16 -1))),
3709 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3711 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3712 (v8i64 VR512:$src2), (i8 -1))),
3713 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3715 //===----------------------------------------------------------------------===//
3716 // AVX-512 Shift instructions
3717 //===----------------------------------------------------------------------===//
3718 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3719 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3720 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3721 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3722 "$src2, $src1", "$src1, $src2",
3723 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3724 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3726 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3727 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3728 "$src2, $src1", "$src1, $src2",
3729 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3731 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3734 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3735 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3737 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3738 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3739 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3740 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3741 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V, EVEX_B;
3744 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3745 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3746 // src2 is always 128-bit
3747 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3748 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3749 "$src2, $src1", "$src1, $src2",
3750 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3751 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3752 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3753 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3754 "$src2, $src1", "$src1, $src2",
3755 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3756 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3760 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3761 ValueType SrcVT, PatFrag bc_frag,
3762 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3763 let Predicates = [prd] in
3764 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3765 VTInfo.info512>, EVEX_V512,
3766 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3767 let Predicates = [prd, HasVLX] in {
3768 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3769 VTInfo.info256>, EVEX_V256,
3770 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3771 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3772 VTInfo.info128>, EVEX_V128,
3773 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3777 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3778 string OpcodeStr, SDNode OpNode> {
3779 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3780 avx512vl_i32_info, HasAVX512>;
3781 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3782 avx512vl_i64_info, HasAVX512>, VEX_W;
3783 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3784 avx512vl_i16_info, HasBWI>;
3787 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3788 string OpcodeStr, SDNode OpNode,
3789 AVX512VLVectorVTInfo VTInfo> {
3790 let Predicates = [HasAVX512] in
3791 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3793 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3794 VTInfo.info512>, EVEX_V512;
3795 let Predicates = [HasAVX512, HasVLX] in {
3796 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3798 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3799 VTInfo.info256>, EVEX_V256;
3800 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3802 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3803 VTInfo.info128>, EVEX_V128;
3807 multiclass avx512_shift_rmi_w<bits<8> opcw,
3808 Format ImmFormR, Format ImmFormM,
3809 string OpcodeStr, SDNode OpNode> {
3810 let Predicates = [HasBWI] in
3811 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3812 v32i16_info>, EVEX_V512;
3813 let Predicates = [HasVLX, HasBWI] in {
3814 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3815 v16i16x_info>, EVEX_V256;
3816 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3817 v8i16x_info>, EVEX_V128;
3821 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3822 Format ImmFormR, Format ImmFormM,
3823 string OpcodeStr, SDNode OpNode> {
3824 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3825 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3826 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3827 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3830 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3831 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>;
3833 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3834 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>;
3836 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3837 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>;
3839 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>;
3840 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>;
3842 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3843 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3844 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3846 //===-------------------------------------------------------------------===//
3847 // Variable Bit Shifts
3848 //===-------------------------------------------------------------------===//
3849 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3850 X86VectorVTInfo _> {
3851 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3852 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3853 "$src2, $src1", "$src1, $src2",
3854 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3855 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3857 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3858 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3859 "$src2, $src1", "$src1, $src2",
3860 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3861 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3862 EVEX_CD8<_.EltSize, CD8VF>;
3865 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3866 X86VectorVTInfo _> {
3868 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3869 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3870 "${src2}"##_.BroadcastStr##", $src1",
3871 "$src1, ${src2}"##_.BroadcastStr,
3872 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3873 (_.ScalarLdFrag addr:$src2))))),
3874 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3875 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3877 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3878 AVX512VLVectorVTInfo _> {
3879 let Predicates = [HasAVX512] in
3880 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3881 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3883 let Predicates = [HasAVX512, HasVLX] in {
3884 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3885 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3886 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3887 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3891 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3893 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3895 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3896 avx512vl_i64_info>, VEX_W;
3899 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3901 let Predicates = [HasBWI] in
3902 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3904 let Predicates = [HasVLX, HasBWI] in {
3906 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3908 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3913 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3914 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3915 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3916 avx512_var_shift_w<0x11, "vpsravw", sra>;
3917 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3918 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3919 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3920 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3922 //===----------------------------------------------------------------------===//
3923 // AVX-512 - MOVDDUP
3924 //===----------------------------------------------------------------------===//
3926 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3927 X86MemOperand x86memop, PatFrag memop_frag> {
3928 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3929 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3930 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3931 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3934 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3937 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3938 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3939 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3940 (VMOVDDUPZrm addr:$src)>;
3942 //===---------------------------------------------------------------------===//
3943 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3944 //===---------------------------------------------------------------------===//
3945 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3946 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3947 X86MemOperand x86memop> {
3948 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3950 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3952 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3953 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3954 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3957 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3958 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3959 EVEX_CD8<32, CD8VF>;
3960 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3961 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3962 EVEX_CD8<32, CD8VF>;
3964 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3965 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3966 (VMOVSHDUPZrm addr:$src)>;
3967 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3968 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3969 (VMOVSLDUPZrm addr:$src)>;
3971 //===----------------------------------------------------------------------===//
3972 // Move Low to High and High to Low packed FP Instructions
3973 //===----------------------------------------------------------------------===//
3974 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3975 (ins VR128X:$src1, VR128X:$src2),
3976 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3977 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3978 IIC_SSE_MOV_LH>, EVEX_4V;
3979 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3980 (ins VR128X:$src1, VR128X:$src2),
3981 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3982 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3983 IIC_SSE_MOV_LH>, EVEX_4V;
3985 let Predicates = [HasAVX512] in {
3987 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3988 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3989 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3990 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3993 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3994 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3997 //===----------------------------------------------------------------------===//
3998 // FMA - Fused Multiply Operations
4001 let Constraints = "$src1 = $dst" in {
4002 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
4003 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4004 SDPatternOperator OpNode = null_frag> {
4005 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4006 (ins _.RC:$src2, _.RC:$src3),
4007 OpcodeStr, "$src3, $src2", "$src2, $src3",
4008 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4012 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4013 (ins _.RC:$src2, _.MemOp:$src3),
4014 OpcodeStr, "$src3, $src2", "$src2, $src3",
4015 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4018 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4019 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4020 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4021 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4023 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4024 AVX512FMA3Base, EVEX_B;
4026 } // Constraints = "$src1 = $dst"
4028 let Constraints = "$src1 = $dst" in {
4029 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
4030 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
4032 SDPatternOperator OpNode> {
4033 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4034 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4035 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4036 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4037 AVX512FMA3Base, EVEX_B, EVEX_RC;
4039 } // Constraints = "$src1 = $dst"
4041 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
4042 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
4043 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4044 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4047 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
4048 string OpcodeStr, X86VectorVTInfo VTI,
4049 SDPatternOperator OpNode> {
4050 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4051 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4052 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
4053 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
4056 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
4058 SDPatternOperator OpNode,
4059 SDPatternOperator OpNodeRnd> {
4060 let ExeDomain = SSEPackedSingle in {
4061 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4062 v16f32_info, OpNode>,
4063 avx512_fma3_round_forms<opc213, OpcodeStr,
4064 v16f32_info, OpNodeRnd>, EVEX_V512;
4065 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4066 v8f32x_info, OpNode>, EVEX_V256;
4067 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4068 v4f32x_info, OpNode>, EVEX_V128;
4070 let ExeDomain = SSEPackedDouble in {
4071 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4072 v8f64_info, OpNode>,
4073 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
4074 OpNodeRnd>, EVEX_V512, VEX_W;
4075 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4076 v4f64x_info, OpNode>,
4078 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4079 v2f64x_info, OpNode>,
4084 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
4085 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
4086 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
4087 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
4088 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4089 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4091 let Constraints = "$src1 = $dst" in {
4092 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
4093 X86VectorVTInfo _> {
4095 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4096 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
4097 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
4098 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
4100 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4101 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
4102 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
4103 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
4105 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4106 (_.ScalarLdFrag addr:$src2))),
4107 _.RC:$src3))]>, EVEX_B;
4109 } // Constraints = "$src1 = $dst"
4111 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4113 let ExeDomain = SSEPackedSingle in {
4114 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
4115 OpNode,v16f32_info>, EVEX_V512,
4116 EVEX_CD8<32, CD8VF>;
4117 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4118 OpNode, v8f32x_info>, EVEX_V256,
4119 EVEX_CD8<32, CD8VF>;
4120 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4121 OpNode, v4f32x_info>, EVEX_V128,
4122 EVEX_CD8<32, CD8VF>;
4124 let ExeDomain = SSEPackedDouble in {
4125 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
4126 OpNode, v8f64_info>, EVEX_V512,
4127 VEX_W, EVEX_CD8<32, CD8VF>;
4128 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4129 OpNode, v4f64x_info>, EVEX_V256,
4130 VEX_W, EVEX_CD8<32, CD8VF>;
4131 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4132 OpNode, v2f64x_info>, EVEX_V128,
4133 VEX_W, EVEX_CD8<32, CD8VF>;
4137 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
4138 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
4139 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
4140 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
4141 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
4142 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
4145 let Constraints = "$src1 = $dst" in {
4146 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4147 RegisterClass RC, ValueType OpVT,
4148 X86MemOperand x86memop, Operand memop,
4150 let isCommutable = 1 in
4151 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
4152 (ins RC:$src1, RC:$src2, RC:$src3),
4153 !strconcat(OpcodeStr,
4154 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4156 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
4158 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
4159 (ins RC:$src1, RC:$src2, f128mem:$src3),
4160 !strconcat(OpcodeStr,
4161 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4163 (OpVT (OpNode RC:$src2, RC:$src1,
4164 (mem_frag addr:$src3))))]>;
4166 } // Constraints = "$src1 = $dst"
4168 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
4169 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4170 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
4171 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4172 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
4173 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4174 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
4175 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4176 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
4177 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4178 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
4179 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4180 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
4181 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4182 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
4183 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4185 //===----------------------------------------------------------------------===//
4186 // AVX-512 Scalar convert from sign integer to float/double
4187 //===----------------------------------------------------------------------===//
4189 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4190 X86MemOperand x86memop, string asm> {
4191 let hasSideEffects = 0 in {
4192 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
4193 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4196 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
4197 (ins DstRC:$src1, x86memop:$src),
4198 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4200 } // hasSideEffects = 0
4203 let Predicates = [HasAVX512] in {
4204 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
4205 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4206 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
4207 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4208 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
4209 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4210 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
4211 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4213 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4214 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4215 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4216 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4217 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4218 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4219 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4220 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4222 def : Pat<(f32 (sint_to_fp GR32:$src)),
4223 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4224 def : Pat<(f32 (sint_to_fp GR64:$src)),
4225 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4226 def : Pat<(f64 (sint_to_fp GR32:$src)),
4227 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4228 def : Pat<(f64 (sint_to_fp GR64:$src)),
4229 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4231 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
4232 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4233 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
4234 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4235 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
4236 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4237 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
4238 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4240 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4241 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4242 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4243 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4244 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4245 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4246 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4247 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4249 def : Pat<(f32 (uint_to_fp GR32:$src)),
4250 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4251 def : Pat<(f32 (uint_to_fp GR64:$src)),
4252 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4253 def : Pat<(f64 (uint_to_fp GR32:$src)),
4254 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4255 def : Pat<(f64 (uint_to_fp GR64:$src)),
4256 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4259 //===----------------------------------------------------------------------===//
4260 // AVX-512 Scalar convert from float/double to integer
4261 //===----------------------------------------------------------------------===//
4262 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4263 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4265 let hasSideEffects = 0 in {
4266 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4267 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4268 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4269 Requires<[HasAVX512]>;
4271 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4272 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4273 Requires<[HasAVX512]>;
4274 } // hasSideEffects = 0
4276 let Predicates = [HasAVX512] in {
4277 // Convert float/double to signed/unsigned int 32/64
4278 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4279 ssmem, sse_load_f32, "cvtss2si">,
4280 XS, EVEX_CD8<32, CD8VT1>;
4281 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4282 ssmem, sse_load_f32, "cvtss2si">,
4283 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4284 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4285 ssmem, sse_load_f32, "cvtss2usi">,
4286 XS, EVEX_CD8<32, CD8VT1>;
4287 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4288 int_x86_avx512_cvtss2usi64, ssmem,
4289 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4290 EVEX_CD8<32, CD8VT1>;
4291 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4292 sdmem, sse_load_f64, "cvtsd2si">,
4293 XD, EVEX_CD8<64, CD8VT1>;
4294 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4295 sdmem, sse_load_f64, "cvtsd2si">,
4296 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4297 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4298 sdmem, sse_load_f64, "cvtsd2usi">,
4299 XD, EVEX_CD8<64, CD8VT1>;
4300 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4301 int_x86_avx512_cvtsd2usi64, sdmem,
4302 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4303 EVEX_CD8<64, CD8VT1>;
4305 let isCodeGenOnly = 1 in {
4306 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4307 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4308 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4309 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4310 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4311 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4312 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4313 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4314 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4315 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4316 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4317 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4319 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4320 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
4321 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4322 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4323 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
4324 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4325 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4326 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4327 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4328 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4329 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
4330 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4331 } // isCodeGenOnly = 1
4333 // Convert float/double to signed/unsigned int 32/64 with truncation
4334 let isCodeGenOnly = 1 in {
4335 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4336 ssmem, sse_load_f32, "cvttss2si">,
4337 XS, EVEX_CD8<32, CD8VT1>;
4338 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4339 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4340 "cvttss2si">, XS, VEX_W,
4341 EVEX_CD8<32, CD8VT1>;
4342 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4343 sdmem, sse_load_f64, "cvttsd2si">, XD,
4344 EVEX_CD8<64, CD8VT1>;
4345 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4346 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4347 "cvttsd2si">, XD, VEX_W,
4348 EVEX_CD8<64, CD8VT1>;
4349 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4350 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4351 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4352 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4353 int_x86_avx512_cvttss2usi64, ssmem,
4354 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4355 EVEX_CD8<32, CD8VT1>;
4356 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4357 int_x86_avx512_cvttsd2usi,
4358 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4359 EVEX_CD8<64, CD8VT1>;
4360 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4361 int_x86_avx512_cvttsd2usi64, sdmem,
4362 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4363 EVEX_CD8<64, CD8VT1>;
4364 } // isCodeGenOnly = 1
4366 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4367 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4369 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4370 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4371 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4372 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4373 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4374 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4377 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4378 loadf32, "cvttss2si">, XS,
4379 EVEX_CD8<32, CD8VT1>;
4380 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4381 loadf32, "cvttss2usi">, XS,
4382 EVEX_CD8<32, CD8VT1>;
4383 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4384 loadf32, "cvttss2si">, XS, VEX_W,
4385 EVEX_CD8<32, CD8VT1>;
4386 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4387 loadf32, "cvttss2usi">, XS, VEX_W,
4388 EVEX_CD8<32, CD8VT1>;
4389 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4390 loadf64, "cvttsd2si">, XD,
4391 EVEX_CD8<64, CD8VT1>;
4392 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4393 loadf64, "cvttsd2usi">, XD,
4394 EVEX_CD8<64, CD8VT1>;
4395 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4396 loadf64, "cvttsd2si">, XD, VEX_W,
4397 EVEX_CD8<64, CD8VT1>;
4398 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4399 loadf64, "cvttsd2usi">, XD, VEX_W,
4400 EVEX_CD8<64, CD8VT1>;
4402 //===----------------------------------------------------------------------===//
4403 // AVX-512 Convert form float to double and back
4404 //===----------------------------------------------------------------------===//
4405 let hasSideEffects = 0 in {
4406 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4407 (ins FR32X:$src1, FR32X:$src2),
4408 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4409 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4411 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4412 (ins FR32X:$src1, f32mem:$src2),
4413 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4414 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4415 EVEX_CD8<32, CD8VT1>;
4417 // Convert scalar double to scalar single
4418 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4419 (ins FR64X:$src1, FR64X:$src2),
4420 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4421 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4423 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4424 (ins FR64X:$src1, f64mem:$src2),
4425 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4426 []>, EVEX_4V, VEX_LIG, VEX_W,
4427 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4430 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4431 Requires<[HasAVX512]>;
4432 def : Pat<(fextend (loadf32 addr:$src)),
4433 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4435 def : Pat<(extloadf32 addr:$src),
4436 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4437 Requires<[HasAVX512, OptForSize]>;
4439 def : Pat<(extloadf32 addr:$src),
4440 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4441 Requires<[HasAVX512, OptForSpeed]>;
4443 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4444 Requires<[HasAVX512]>;
4446 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4447 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4448 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4450 let hasSideEffects = 0 in {
4451 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4452 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4454 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4455 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4456 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4457 [], d>, EVEX, EVEX_B, EVEX_RC;
4459 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4460 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4462 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4463 } // hasSideEffects = 0
4466 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4467 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4468 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4470 let hasSideEffects = 0 in {
4471 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4472 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4474 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4476 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4477 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4479 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4480 } // hasSideEffects = 0
4483 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4484 loadv8f64, f512mem, v8f32, v8f64,
4485 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4486 EVEX_CD8<64, CD8VF>;
4488 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4489 loadv4f64, f256mem, v8f64, v8f32,
4490 SSEPackedDouble>, EVEX_V512, PS,
4491 EVEX_CD8<32, CD8VH>;
4492 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4493 (VCVTPS2PDZrm addr:$src)>;
4495 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4496 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4497 (VCVTPD2PSZrr VR512:$src)>;
4499 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4500 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4501 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4503 //===----------------------------------------------------------------------===//
4504 // AVX-512 Vector convert from sign integer to float/double
4505 //===----------------------------------------------------------------------===//
4507 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4508 loadv8i64, i512mem, v16f32, v16i32,
4509 SSEPackedSingle>, EVEX_V512, PS,
4510 EVEX_CD8<32, CD8VF>;
4512 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4513 loadv4i64, i256mem, v8f64, v8i32,
4514 SSEPackedDouble>, EVEX_V512, XS,
4515 EVEX_CD8<32, CD8VH>;
4517 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4518 loadv16f32, f512mem, v16i32, v16f32,
4519 SSEPackedSingle>, EVEX_V512, XS,
4520 EVEX_CD8<32, CD8VF>;
4522 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4523 loadv8f64, f512mem, v8i32, v8f64,
4524 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4525 EVEX_CD8<64, CD8VF>;
4527 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4528 loadv16f32, f512mem, v16i32, v16f32,
4529 SSEPackedSingle>, EVEX_V512, PS,
4530 EVEX_CD8<32, CD8VF>;
4532 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4533 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4534 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4535 (VCVTTPS2UDQZrr VR512:$src)>;
4537 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4538 loadv8f64, f512mem, v8i32, v8f64,
4539 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4540 EVEX_CD8<64, CD8VF>;
4542 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4543 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4544 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4545 (VCVTTPD2UDQZrr VR512:$src)>;
4547 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4548 loadv4i64, f256mem, v8f64, v8i32,
4549 SSEPackedDouble>, EVEX_V512, XS,
4550 EVEX_CD8<32, CD8VH>;
4552 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4553 loadv16i32, f512mem, v16f32, v16i32,
4554 SSEPackedSingle>, EVEX_V512, XD,
4555 EVEX_CD8<32, CD8VF>;
4557 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4558 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4559 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4561 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4562 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4563 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4565 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4566 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4567 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4569 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4570 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4571 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4573 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4574 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4575 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4577 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4578 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4579 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4580 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4581 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4582 (VCVTDQ2PDZrr VR256X:$src)>;
4583 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4584 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4585 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4586 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4587 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4588 (VCVTUDQ2PDZrr VR256X:$src)>;
4590 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4591 RegisterClass DstRC, PatFrag mem_frag,
4592 X86MemOperand x86memop, Domain d> {
4593 let hasSideEffects = 0 in {
4594 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4595 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4597 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4598 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4599 [], d>, EVEX, EVEX_B, EVEX_RC;
4601 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4602 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4604 } // hasSideEffects = 0
4607 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4608 loadv16f32, f512mem, SSEPackedSingle>, PD,
4609 EVEX_V512, EVEX_CD8<32, CD8VF>;
4610 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4611 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4612 EVEX_V512, EVEX_CD8<64, CD8VF>;
4614 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4615 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4616 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4618 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4619 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4620 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4622 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4623 loadv16f32, f512mem, SSEPackedSingle>,
4624 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4625 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4626 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4627 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4629 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4630 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4631 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4633 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4634 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4635 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4637 let Predicates = [HasAVX512] in {
4638 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4639 (VCVTPD2PSZrm addr:$src)>;
4640 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4641 (VCVTPS2PDZrm addr:$src)>;
4644 //===----------------------------------------------------------------------===//
4645 // Half precision conversion instructions
4646 //===----------------------------------------------------------------------===//
4647 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4648 X86MemOperand x86memop> {
4649 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4650 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4652 let hasSideEffects = 0, mayLoad = 1 in
4653 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4654 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4657 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4658 X86MemOperand x86memop> {
4659 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4660 (ins srcRC:$src1, i32u8imm:$src2),
4661 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4663 let hasSideEffects = 0, mayStore = 1 in
4664 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4665 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4666 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4669 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4670 EVEX_CD8<32, CD8VH>;
4671 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4672 EVEX_CD8<32, CD8VH>;
4674 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4675 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4676 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4678 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4679 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4680 (VCVTPH2PSZrr VR256X:$src)>;
4682 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4683 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4684 "ucomiss">, PS, EVEX, VEX_LIG,
4685 EVEX_CD8<32, CD8VT1>;
4686 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4687 "ucomisd">, PD, EVEX,
4688 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4689 let Pattern = []<dag> in {
4690 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4691 "comiss">, PS, EVEX, VEX_LIG,
4692 EVEX_CD8<32, CD8VT1>;
4693 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4694 "comisd">, PD, EVEX,
4695 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4697 let isCodeGenOnly = 1 in {
4698 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4699 load, "ucomiss">, PS, EVEX, VEX_LIG,
4700 EVEX_CD8<32, CD8VT1>;
4701 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4702 load, "ucomisd">, PD, EVEX,
4703 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4705 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4706 load, "comiss">, PS, EVEX, VEX_LIG,
4707 EVEX_CD8<32, CD8VT1>;
4708 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4709 load, "comisd">, PD, EVEX,
4710 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4714 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4715 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4716 X86MemOperand x86memop> {
4717 let hasSideEffects = 0 in {
4718 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4719 (ins RC:$src1, RC:$src2),
4720 !strconcat(OpcodeStr,
4721 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4722 let mayLoad = 1 in {
4723 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4724 (ins RC:$src1, x86memop:$src2),
4725 !strconcat(OpcodeStr,
4726 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4731 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4732 EVEX_CD8<32, CD8VT1>;
4733 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4734 VEX_W, EVEX_CD8<64, CD8VT1>;
4735 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4736 EVEX_CD8<32, CD8VT1>;
4737 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4738 VEX_W, EVEX_CD8<64, CD8VT1>;
4740 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4741 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4742 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4743 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4745 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4746 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4747 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4748 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4750 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4751 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4752 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4753 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4755 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4756 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4757 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4758 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4760 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4761 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4762 X86VectorVTInfo _> {
4763 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4764 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4765 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4766 let mayLoad = 1 in {
4767 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4768 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4770 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4771 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4772 (ins _.ScalarMemOp:$src), OpcodeStr,
4773 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4775 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4780 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4781 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4782 EVEX_V512, EVEX_CD8<32, CD8VF>;
4783 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4784 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4786 // Define only if AVX512VL feature is present.
4787 let Predicates = [HasVLX] in {
4788 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4789 OpNode, v4f32x_info>,
4790 EVEX_V128, EVEX_CD8<32, CD8VF>;
4791 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4792 OpNode, v8f32x_info>,
4793 EVEX_V256, EVEX_CD8<32, CD8VF>;
4794 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4795 OpNode, v2f64x_info>,
4796 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4797 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4798 OpNode, v4f64x_info>,
4799 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4803 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4804 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4806 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4807 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4808 (VRSQRT14PSZr VR512:$src)>;
4809 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4810 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4811 (VRSQRT14PDZr VR512:$src)>;
4813 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4814 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4815 (VRCP14PSZr VR512:$src)>;
4816 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4817 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4818 (VRCP14PDZr VR512:$src)>;
4820 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4821 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4824 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4825 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4826 "$src2, $src1", "$src1, $src2",
4827 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4828 (i32 FROUND_CURRENT))>;
4830 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4831 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4832 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4833 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4834 (i32 FROUND_NO_EXC))>, EVEX_B;
4836 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4837 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4838 "$src2, $src1", "$src1, $src2",
4839 (OpNode (_.VT _.RC:$src1),
4840 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4841 (i32 FROUND_CURRENT))>;
4844 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4845 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4846 EVEX_CD8<32, CD8VT1>;
4847 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4848 EVEX_CD8<64, CD8VT1>, VEX_W;
4851 let hasSideEffects = 0, Predicates = [HasERI] in {
4852 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4853 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4855 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4857 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4860 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4861 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4862 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4864 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4865 (ins _.RC:$src), OpcodeStr,
4866 "{sae}, $src", "$src, {sae}",
4867 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
4869 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4870 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4872 (bitconvert (_.LdFrag addr:$src))),
4873 (i32 FROUND_CURRENT))>;
4875 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4876 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4878 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4879 (i32 FROUND_CURRENT))>, EVEX_B;
4882 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4883 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4884 EVEX_CD8<32, CD8VF>;
4885 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4886 VEX_W, EVEX_CD8<32, CD8VF>;
4889 let Predicates = [HasERI], hasSideEffects = 0 in {
4891 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4892 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4893 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4896 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4897 SDNode OpNode, X86VectorVTInfo _>{
4898 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4899 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4900 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4901 let mayLoad = 1 in {
4902 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4903 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4905 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4907 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4908 (ins _.ScalarMemOp:$src), OpcodeStr,
4909 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4911 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4916 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4917 Intrinsic F32Int, Intrinsic F64Int,
4918 OpndItins itins_s, OpndItins itins_d> {
4919 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4920 (ins FR32X:$src1, FR32X:$src2),
4921 !strconcat(OpcodeStr,
4922 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4923 [], itins_s.rr>, XS, EVEX_4V;
4924 let isCodeGenOnly = 1 in
4925 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4926 (ins VR128X:$src1, VR128X:$src2),
4927 !strconcat(OpcodeStr,
4928 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4930 (F32Int VR128X:$src1, VR128X:$src2))],
4931 itins_s.rr>, XS, EVEX_4V;
4932 let mayLoad = 1 in {
4933 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4934 (ins FR32X:$src1, f32mem:$src2),
4935 !strconcat(OpcodeStr,
4936 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4937 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4938 let isCodeGenOnly = 1 in
4939 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4940 (ins VR128X:$src1, ssmem:$src2),
4941 !strconcat(OpcodeStr,
4942 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4944 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4945 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4947 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4948 (ins FR64X:$src1, FR64X:$src2),
4949 !strconcat(OpcodeStr,
4950 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4952 let isCodeGenOnly = 1 in
4953 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4954 (ins VR128X:$src1, VR128X:$src2),
4955 !strconcat(OpcodeStr,
4956 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4958 (F64Int VR128X:$src1, VR128X:$src2))],
4959 itins_s.rr>, XD, EVEX_4V, VEX_W;
4960 let mayLoad = 1 in {
4961 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4962 (ins FR64X:$src1, f64mem:$src2),
4963 !strconcat(OpcodeStr,
4964 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4965 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4966 let isCodeGenOnly = 1 in
4967 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4968 (ins VR128X:$src1, sdmem:$src2),
4969 !strconcat(OpcodeStr,
4970 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4972 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4973 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4977 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4979 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4981 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4982 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4984 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4985 // Define only if AVX512VL feature is present.
4986 let Predicates = [HasVLX] in {
4987 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4988 OpNode, v4f32x_info>,
4989 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4990 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4991 OpNode, v8f32x_info>,
4992 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4993 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4994 OpNode, v2f64x_info>,
4995 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4996 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4997 OpNode, v4f64x_info>,
4998 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5002 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
5004 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
5005 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
5006 SSE_SQRTSS, SSE_SQRTSD>;
5008 let Predicates = [HasAVX512] in {
5009 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
5010 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
5011 (VSQRTPSZr VR512:$src1)>;
5012 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
5013 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
5014 (VSQRTPDZr VR512:$src1)>;
5016 def : Pat<(f32 (fsqrt FR32X:$src)),
5017 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5018 def : Pat<(f32 (fsqrt (load addr:$src))),
5019 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5020 Requires<[OptForSize]>;
5021 def : Pat<(f64 (fsqrt FR64X:$src)),
5022 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5023 def : Pat<(f64 (fsqrt (load addr:$src))),
5024 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5025 Requires<[OptForSize]>;
5027 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5028 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5029 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5030 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5031 Requires<[OptForSize]>;
5033 def : Pat<(f32 (X86frcp FR32X:$src)),
5034 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5035 def : Pat<(f32 (X86frcp (load addr:$src))),
5036 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5037 Requires<[OptForSize]>;
5039 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5040 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5041 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5043 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5044 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5046 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5047 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5048 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5050 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5051 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5055 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
5056 X86MemOperand x86memop, RegisterClass RC,
5057 PatFrag mem_frag, Domain d> {
5058 let ExeDomain = d in {
5059 // Intrinsic operation, reg.
5060 // Vector intrinsic operation, reg
5061 def r : AVX512AIi8<opc, MRMSrcReg,
5062 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
5063 !strconcat(OpcodeStr,
5064 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5067 // Vector intrinsic operation, mem
5068 def m : AVX512AIi8<opc, MRMSrcMem,
5069 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
5070 !strconcat(OpcodeStr,
5071 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5076 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
5077 loadv16f32, SSEPackedSingle>, EVEX_V512,
5078 EVEX_CD8<32, CD8VF>;
5080 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
5081 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
5083 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
5086 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
5087 loadv8f64, SSEPackedDouble>, EVEX_V512,
5088 VEX_W, EVEX_CD8<64, CD8VF>;
5090 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
5091 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
5093 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
5096 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5098 let ExeDomain = _.ExeDomain in {
5099 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5100 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5101 "$src3, $src2, $src1", "$src1, $src2, $src3",
5102 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5103 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5105 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5106 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5107 "{sae}, $src3, $src2, $src1", "$src1, $src2, $src3, {sae}",
5108 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5109 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5112 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5113 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5114 "$src3, $src2, $src1", "$src1, $src2, $src3",
5115 (_.VT (X86RndScale (_.VT _.RC:$src1),
5116 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5117 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5119 let Predicates = [HasAVX512] in {
5120 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5121 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5122 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5123 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5124 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5125 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5126 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5127 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5128 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5129 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5130 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5131 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5132 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5133 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5134 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5136 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5137 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5138 addr:$src, (i32 0x1))), _.FRC)>;
5139 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5140 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5141 addr:$src, (i32 0x2))), _.FRC)>;
5142 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5143 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5144 addr:$src, (i32 0x3))), _.FRC)>;
5145 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5146 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5147 addr:$src, (i32 0x4))), _.FRC)>;
5148 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5149 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5150 addr:$src, (i32 0xc))), _.FRC)>;
5154 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5155 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5157 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5158 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5160 let Predicates = [HasAVX512] in {
5161 def : Pat<(v16f32 (ffloor VR512:$src)),
5162 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
5163 def : Pat<(v16f32 (fnearbyint VR512:$src)),
5164 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
5165 def : Pat<(v16f32 (fceil VR512:$src)),
5166 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
5167 def : Pat<(v16f32 (frint VR512:$src)),
5168 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
5169 def : Pat<(v16f32 (ftrunc VR512:$src)),
5170 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
5172 def : Pat<(v8f64 (ffloor VR512:$src)),
5173 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
5174 def : Pat<(v8f64 (fnearbyint VR512:$src)),
5175 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
5176 def : Pat<(v8f64 (fceil VR512:$src)),
5177 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
5178 def : Pat<(v8f64 (frint VR512:$src)),
5179 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
5180 def : Pat<(v8f64 (ftrunc VR512:$src)),
5181 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
5183 //-------------------------------------------------
5184 // Integer truncate and extend operations
5185 //-------------------------------------------------
5187 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
5188 RegisterClass dstRC, RegisterClass srcRC,
5189 RegisterClass KRC, X86MemOperand x86memop> {
5190 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5192 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5195 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5196 (ins KRC:$mask, srcRC:$src),
5197 !strconcat(OpcodeStr,
5198 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5201 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5202 (ins KRC:$mask, srcRC:$src),
5203 !strconcat(OpcodeStr,
5204 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5207 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
5208 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5211 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5212 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
5213 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
5217 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
5218 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5219 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
5220 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5221 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
5222 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5223 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
5224 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5225 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
5226 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5227 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
5228 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5229 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
5230 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5231 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
5232 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5233 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
5234 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5235 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
5236 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5237 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
5238 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5239 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
5240 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5241 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
5242 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5243 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
5244 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5245 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
5246 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5248 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
5249 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
5250 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
5251 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
5252 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
5254 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5255 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
5256 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5257 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
5258 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5259 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
5260 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5261 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
5264 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
5265 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
5266 PatFrag mem_frag, X86MemOperand x86memop,
5267 ValueType OpVT, ValueType InVT> {
5269 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5271 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5272 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
5274 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5275 (ins KRC:$mask, SrcRC:$src),
5276 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
5279 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5280 (ins KRC:$mask, SrcRC:$src),
5281 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5284 let mayLoad = 1 in {
5285 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5286 (ins x86memop:$src),
5287 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5289 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
5292 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5293 (ins KRC:$mask, x86memop:$src),
5294 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
5298 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5299 (ins KRC:$mask, x86memop:$src),
5300 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5306 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
5307 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5309 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
5310 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5312 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
5313 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5314 EVEX_CD8<16, CD8VH>;
5315 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
5316 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5317 EVEX_CD8<16, CD8VQ>;
5318 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
5319 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5320 EVEX_CD8<32, CD8VH>;
5322 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
5323 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5325 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
5326 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5328 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
5329 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5330 EVEX_CD8<16, CD8VH>;
5331 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
5332 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5333 EVEX_CD8<16, CD8VQ>;
5334 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
5335 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5336 EVEX_CD8<32, CD8VH>;
5338 //===----------------------------------------------------------------------===//
5339 // GATHER - SCATTER Operations
5341 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5342 X86MemOperand memop, PatFrag GatherNode> {
5343 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5344 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5345 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5346 !strconcat(OpcodeStr,
5347 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5348 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5349 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5350 vectoraddr:$src2))]>, EVEX, EVEX_K,
5351 EVEX_CD8<_.EltSize, CD8VT1>;
5354 let ExeDomain = SSEPackedDouble in {
5355 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", v8f64_info, vy64xmem,
5356 mgatherv8i32>, EVEX_V512, VEX_W;
5357 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", v8f64_info, vz64mem,
5358 mgatherv8i64>, EVEX_V512, VEX_W;
5361 let ExeDomain = SSEPackedSingle in {
5362 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", v16f32_info, vz32mem,
5363 mgatherv16i32>, EVEX_V512;
5364 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", v8f32x_info, vz64mem,
5365 mgatherv8i64>, EVEX_V512;
5368 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", v8i64_info, vy64xmem,
5369 mgatherv8i32>, EVEX_V512, VEX_W;
5370 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", v16i32_info, vz32mem,
5371 mgatherv16i32>, EVEX_V512;
5373 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", v8i64_info, vz64mem,
5374 mgatherv8i64>, EVEX_V512, VEX_W;
5375 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", v8i32x_info, vz64mem,
5376 mgatherv8i64>, EVEX_V512;
5378 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5379 X86MemOperand memop, PatFrag ScatterNode> {
5381 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5383 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5384 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5385 !strconcat(OpcodeStr,
5386 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5387 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5388 _.KRCWM:$mask, vectoraddr:$dst))]>,
5389 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5392 let ExeDomain = SSEPackedDouble in {
5393 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", v8f64_info, vy64xmem,
5394 mscatterv8i32>, EVEX_V512, VEX_W;
5395 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", v8f64_info, vz64mem,
5396 mscatterv8i64>, EVEX_V512, VEX_W;
5399 let ExeDomain = SSEPackedSingle in {
5400 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", v16f32_info, vz32mem,
5401 mscatterv16i32>, EVEX_V512;
5402 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", v8f32x_info, vz64mem,
5403 mscatterv8i64>, EVEX_V512;
5406 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", v8i64_info, vy64xmem,
5407 mscatterv8i32>, EVEX_V512, VEX_W;
5408 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", v16i32_info, vz32mem,
5409 mscatterv16i32>, EVEX_V512;
5411 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", v8i64_info, vz64mem,
5412 mscatterv8i64>, EVEX_V512, VEX_W;
5413 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", v8i32x_info, vz64mem,
5414 mscatterv8i64>, EVEX_V512;
5417 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5418 RegisterClass KRC, X86MemOperand memop> {
5419 let Predicates = [HasPFI], hasSideEffects = 1 in
5420 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5421 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5425 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5426 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5428 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5429 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5431 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5432 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5434 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5435 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5437 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5438 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5440 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5441 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5443 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5444 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5446 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5447 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5449 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5450 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5452 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5453 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5455 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5456 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5458 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5459 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5461 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5462 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5464 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5465 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5467 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5468 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5470 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5471 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5472 //===----------------------------------------------------------------------===//
5473 // VSHUFPS - VSHUFPD Operations
5475 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5476 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5478 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5479 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5480 !strconcat(OpcodeStr,
5481 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5482 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5483 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5484 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5485 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5486 (ins RC:$src1, RC:$src2, u8imm:$src3),
5487 !strconcat(OpcodeStr,
5488 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5489 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5490 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5491 EVEX_4V, Sched<[WriteShuffle]>;
5494 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5495 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5496 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5497 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5499 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5500 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5501 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5502 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5503 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5505 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5506 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5507 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5508 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5509 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5511 multiclass avx512_valign<X86VectorVTInfo _> {
5512 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5513 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5515 "$src3, $src2, $src1", "$src1, $src2, $src3",
5516 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5518 AVX512AIi8Base, EVEX_4V;
5520 // Also match valign of packed floats.
5521 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5522 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5525 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5526 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5527 !strconcat("valign"##_.Suffix,
5528 "\t{$src3, $src2, $src1, $dst|"
5529 "$dst, $src1, $src2, $src3}"),
5532 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5533 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5535 // Helper fragments to match sext vXi1 to vXiY.
5536 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5537 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5539 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5540 RegisterClass KRC, RegisterClass RC,
5541 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5543 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5544 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5546 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5547 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5549 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5550 !strconcat(OpcodeStr,
5551 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5553 let mayLoad = 1 in {
5554 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5555 (ins x86memop:$src),
5556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5558 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5559 (ins KRC:$mask, x86memop:$src),
5560 !strconcat(OpcodeStr,
5561 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5563 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5564 (ins KRC:$mask, x86memop:$src),
5565 !strconcat(OpcodeStr,
5566 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5568 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5569 (ins x86scalar_mop:$src),
5570 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5571 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5573 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5574 (ins KRC:$mask, x86scalar_mop:$src),
5575 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5576 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5577 []>, EVEX, EVEX_B, EVEX_K;
5578 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5579 (ins KRC:$mask, x86scalar_mop:$src),
5580 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5581 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5583 []>, EVEX, EVEX_B, EVEX_KZ;
5587 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5588 i512mem, i32mem, "{1to16}">, EVEX_V512,
5589 EVEX_CD8<32, CD8VF>;
5590 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5591 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5592 EVEX_CD8<64, CD8VF>;
5595 (bc_v16i32 (v16i1sextv16i32)),
5596 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5597 (VPABSDZrr VR512:$src)>;
5599 (bc_v8i64 (v8i1sextv8i64)),
5600 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5601 (VPABSQZrr VR512:$src)>;
5603 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5604 (v16i32 immAllZerosV), (i16 -1))),
5605 (VPABSDZrr VR512:$src)>;
5606 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5607 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5608 (VPABSQZrr VR512:$src)>;
5610 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5611 RegisterClass RC, RegisterClass KRC,
5612 X86MemOperand x86memop,
5613 X86MemOperand x86scalar_mop, string BrdcstStr> {
5614 let hasSideEffects = 0 in {
5615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5617 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5620 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5621 (ins x86memop:$src),
5622 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5625 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5626 (ins x86scalar_mop:$src),
5627 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5628 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5630 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5631 (ins KRC:$mask, RC:$src),
5632 !strconcat(OpcodeStr,
5633 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5636 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5637 (ins KRC:$mask, x86memop:$src),
5638 !strconcat(OpcodeStr,
5639 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5642 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5643 (ins KRC:$mask, x86scalar_mop:$src),
5644 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5645 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5647 []>, EVEX, EVEX_KZ, EVEX_B;
5649 let Constraints = "$src1 = $dst" in {
5650 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5651 (ins RC:$src1, KRC:$mask, RC:$src2),
5652 !strconcat(OpcodeStr,
5653 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5656 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5657 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5658 !strconcat(OpcodeStr,
5659 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5662 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5663 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5664 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5665 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5666 []>, EVEX, EVEX_K, EVEX_B;
5671 let Predicates = [HasCDI] in {
5672 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5673 i512mem, i32mem, "{1to16}">,
5674 EVEX_V512, EVEX_CD8<32, CD8VF>;
5677 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5678 i512mem, i64mem, "{1to8}">,
5679 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5683 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5685 (VPCONFLICTDrrk VR512:$src1,
5686 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5688 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5690 (VPCONFLICTQrrk VR512:$src1,
5691 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5693 let Predicates = [HasCDI] in {
5694 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5695 i512mem, i32mem, "{1to16}">,
5696 EVEX_V512, EVEX_CD8<32, CD8VF>;
5699 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5700 i512mem, i64mem, "{1to8}">,
5701 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5705 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5707 (VPLZCNTDrrk VR512:$src1,
5708 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5710 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5712 (VPLZCNTQrrk VR512:$src1,
5713 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5715 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5716 (VPLZCNTDrm addr:$src)>;
5717 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5718 (VPLZCNTDrr VR512:$src)>;
5719 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5720 (VPLZCNTQrm addr:$src)>;
5721 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5722 (VPLZCNTQrr VR512:$src)>;
5724 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5725 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5726 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5728 def : Pat<(store VK1:$src, addr:$dst),
5730 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5731 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5733 def : Pat<(store VK8:$src, addr:$dst),
5735 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5736 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5738 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5739 (truncstore node:$val, node:$ptr), [{
5740 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5743 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5744 (MOV8mr addr:$dst, GR8:$src)>;
5746 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5747 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5748 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5749 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5752 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5753 string OpcodeStr, Predicate prd> {
5754 let Predicates = [prd] in
5755 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5757 let Predicates = [prd, HasVLX] in {
5758 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5759 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5763 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5764 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5766 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5768 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5770 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5774 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5776 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
5777 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
5778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5779 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
5782 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
5783 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
5784 let Predicates = [prd] in
5785 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
5788 let Predicates = [prd, HasVLX] in {
5789 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
5791 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
5796 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
5797 avx512vl_i8_info, HasBWI>;
5798 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
5799 avx512vl_i16_info, HasBWI>, VEX_W;
5800 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
5801 avx512vl_i32_info, HasDQI>;
5802 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
5803 avx512vl_i64_info, HasDQI>, VEX_W;
5805 //===----------------------------------------------------------------------===//
5806 // AVX-512 - COMPRESS and EXPAND
5808 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5810 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5811 (ins _.KRCWM:$mask, _.RC:$src),
5812 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5813 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5814 _.ImmAllZerosV)))]>, EVEX_KZ;
5816 let Constraints = "$src0 = $dst" in
5817 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5818 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5819 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5820 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5821 _.RC:$src0)))]>, EVEX_K;
5823 let mayStore = 1 in {
5824 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5825 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5826 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5827 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5829 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5833 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5834 AVX512VLVectorVTInfo VTInfo> {
5835 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5837 let Predicates = [HasVLX] in {
5838 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5839 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5843 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5845 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5847 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5849 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5853 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5855 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5856 (ins _.KRCWM:$mask, _.RC:$src),
5857 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5858 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5859 _.ImmAllZerosV)))]>, EVEX_KZ;
5861 let Constraints = "$src0 = $dst" in
5862 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5863 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5864 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5865 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5866 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5868 let mayLoad = 1, Constraints = "$src0 = $dst" in
5869 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5870 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5871 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5872 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5874 (_.LdFrag addr:$src))),
5876 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5879 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5880 (ins _.KRCWM:$mask, _.MemOp:$src),
5881 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5882 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5883 (_.VT (bitconvert (_.LdFrag addr:$src))),
5884 _.ImmAllZerosV)))]>,
5885 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5889 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5890 AVX512VLVectorVTInfo VTInfo> {
5891 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5893 let Predicates = [HasVLX] in {
5894 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5895 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5899 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5901 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5903 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5905 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,