1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
755 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
756 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
758 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
759 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
760 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
761 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
763 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
764 (COPY_TO_REGCLASS (VPCMPGTDZrr
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
766 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
768 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
769 (COPY_TO_REGCLASS (VPCMPEQDZrr
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
771 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
773 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
774 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
775 SDNode OpNode, ValueType vt, Operand CC, string asm,
777 def rri : AVX512AIi8<opc, MRMSrcReg,
778 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
779 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
780 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
781 def rmi : AVX512AIi8<opc, MRMSrcMem,
782 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
784 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
785 // Accept explicit immediate argument form instead of comparison code.
786 let isAsmParserOnly = 1, hasSideEffects = 0 in {
787 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
788 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
789 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
790 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
791 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
792 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
796 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
797 X86cmpm, v16i32, AVXCC,
798 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
799 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
800 EVEX_V512, EVEX_CD8<32, CD8VF>;
801 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
802 X86cmpmu, v16i32, AVXCC,
803 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
805 EVEX_V512, EVEX_CD8<32, CD8VF>;
807 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
808 X86cmpm, v8i64, AVXCC,
809 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
810 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
811 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
812 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
813 X86cmpmu, v8i64, AVXCC,
814 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
815 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
816 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
818 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
819 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
820 X86MemOperand x86memop, ValueType vt,
821 string suffix, Domain d> {
822 def rri : AVX512PIi8<0xC2, MRMSrcReg,
823 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
824 !strconcat("vcmp${cc}", suffix,
825 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
826 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
827 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
828 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
829 !strconcat("vcmp${cc}", suffix,
830 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
832 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
833 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
834 !strconcat("vcmp${cc}", suffix,
835 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
837 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
839 // Accept explicit immediate argument form instead of comparison code.
840 let isAsmParserOnly = 1, hasSideEffects = 0 in {
841 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
842 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
843 !strconcat("vcmp", suffix,
844 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
845 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
846 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
852 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
853 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
855 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
856 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
859 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
860 (COPY_TO_REGCLASS (VCMPPSZrri
861 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
862 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
864 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
865 (COPY_TO_REGCLASS (VPCMPDZrri
866 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
867 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
869 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
870 (COPY_TO_REGCLASS (VPCMPUDZrri
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
872 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
875 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
876 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
878 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
879 (I8Imm imm:$cc)), GR16)>;
881 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
882 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
884 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
885 (I8Imm imm:$cc)), GR8)>;
887 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
888 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
890 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
891 (I8Imm imm:$cc)), GR16)>;
893 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
894 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
896 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
897 (I8Imm imm:$cc)), GR8)>;
899 // Mask register copy, including
900 // - copy between mask registers
901 // - load/store mask registers
902 // - copy from GPR to mask register and vice versa
904 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
905 string OpcodeStr, RegisterClass KRC,
906 ValueType vt, X86MemOperand x86memop> {
907 let hasSideEffects = 0 in {
908 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
909 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
911 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
912 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
913 [(set KRC:$dst, (vt (load addr:$src)))]>;
915 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
920 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
922 RegisterClass KRC, RegisterClass GRC> {
923 let hasSideEffects = 0 in {
924 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
925 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
926 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
927 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
931 let Predicates = [HasAVX512] in {
932 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
934 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
938 let Predicates = [HasAVX512] in {
939 // GR16 from/to 16-bit mask
940 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
941 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
942 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
943 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
945 // Store kreg in memory
946 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
947 (KMOVWmk addr:$dst, VK16:$src)>;
949 def : Pat<(store VK8:$src, addr:$dst),
950 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
952 def : Pat<(i1 (load addr:$src)),
953 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
955 def : Pat<(v8i1 (load addr:$src)),
956 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
958 def : Pat<(i1 (trunc (i32 GR32:$src))),
959 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
961 def : Pat<(i1 (trunc (i8 GR8:$src))),
963 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
965 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
966 def : Pat<(i8 (zext VK1:$src)),
968 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
969 def : Pat<(i64 (zext VK1:$src)),
970 (SUBREG_TO_REG (i64 0),
971 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
972 def : Pat<(i16 (zext VK1:$src)),
974 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_16bit)>;
976 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
977 let Predicates = [HasAVX512] in {
978 // GR from/to 8-bit mask without native support
979 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
981 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
983 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
985 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
988 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
989 (COPY_TO_REGCLASS VK16:$src, VK1)>;
990 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
991 (COPY_TO_REGCLASS VK8:$src, VK1)>;
995 // Mask unary operation
997 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
998 RegisterClass KRC, SDPatternOperator OpNode> {
999 let Predicates = [HasAVX512] in
1000 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1001 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1002 [(set KRC:$dst, (OpNode KRC:$src))]>;
1005 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1006 SDPatternOperator OpNode> {
1007 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1011 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1013 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1014 let Predicates = [HasAVX512] in
1015 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1017 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1018 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1020 defm : avx512_mask_unop_int<"knot", "KNOT">;
1022 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1023 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1024 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1026 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1027 def : Pat<(not VK8:$src),
1029 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1031 // Mask binary operation
1032 // - KAND, KANDN, KOR, KXNOR, KXOR
1033 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1034 RegisterClass KRC, SDPatternOperator OpNode> {
1035 let Predicates = [HasAVX512] in
1036 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1037 !strconcat(OpcodeStr,
1038 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1039 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1042 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1043 SDPatternOperator OpNode> {
1044 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1048 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1049 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1051 let isCommutable = 1 in {
1052 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1053 let isCommutable = 0 in
1054 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1055 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1056 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1057 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1060 def : Pat<(xor VK1:$src1, VK1:$src2),
1061 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1062 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1064 def : Pat<(or VK1:$src1, VK1:$src2),
1065 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1066 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1068 def : Pat<(and VK1:$src1, VK1:$src2),
1069 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1070 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1072 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1073 let Predicates = [HasAVX512] in
1074 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1075 (i16 GR16:$src1), (i16 GR16:$src2)),
1076 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1077 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1078 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1081 defm : avx512_mask_binop_int<"kand", "KAND">;
1082 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1083 defm : avx512_mask_binop_int<"kor", "KOR">;
1084 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1085 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1087 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1088 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1089 let Predicates = [HasAVX512] in
1090 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1092 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1093 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1096 defm : avx512_binop_pat<and, KANDWrr>;
1097 defm : avx512_binop_pat<andn, KANDNWrr>;
1098 defm : avx512_binop_pat<or, KORWrr>;
1099 defm : avx512_binop_pat<xnor, KXNORWrr>;
1100 defm : avx512_binop_pat<xor, KXORWrr>;
1103 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1104 RegisterClass KRC> {
1105 let Predicates = [HasAVX512] in
1106 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1107 !strconcat(OpcodeStr,
1108 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1111 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1112 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1116 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1117 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1118 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1119 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1122 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1123 let Predicates = [HasAVX512] in
1124 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1125 (i16 GR16:$src1), (i16 GR16:$src2)),
1126 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1127 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1128 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1130 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1133 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1135 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1136 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1137 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1138 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1141 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1142 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1146 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1148 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1149 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1150 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1153 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1155 let Predicates = [HasAVX512] in
1156 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1157 !strconcat(OpcodeStr,
1158 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1159 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1162 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1164 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1168 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1169 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1171 // Mask setting all 0s or 1s
1172 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1173 let Predicates = [HasAVX512] in
1174 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1175 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1176 [(set KRC:$dst, (VT Val))]>;
1179 multiclass avx512_mask_setop_w<PatFrag Val> {
1180 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1181 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1184 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1185 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1187 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1188 let Predicates = [HasAVX512] in {
1189 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1190 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1191 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1192 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1193 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1195 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1196 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1198 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1199 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1201 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1202 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1204 //===----------------------------------------------------------------------===//
1205 // AVX-512 - Aligned and unaligned load and store
1208 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1209 X86MemOperand x86memop, PatFrag ld_frag,
1210 string asm, Domain d, bit IsReMaterializable = 1> {
1211 let hasSideEffects = 0 in
1212 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1213 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1215 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1216 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1217 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1218 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1219 let Constraints = "$src1 = $dst" in {
1220 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1221 (ins RC:$src1, KRC:$mask, RC:$src2),
1223 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1225 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1226 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1228 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1229 [], d>, EVEX, EVEX_K;
1233 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1234 "vmovaps", SSEPackedSingle>,
1235 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1236 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1237 "vmovapd", SSEPackedDouble>,
1238 PD, EVEX_V512, VEX_W,
1239 EVEX_CD8<64, CD8VF>;
1240 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1241 "vmovups", SSEPackedSingle>,
1242 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1243 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1244 "vmovupd", SSEPackedDouble, 0>,
1245 PD, EVEX_V512, VEX_W,
1246 EVEX_CD8<64, CD8VF>;
1247 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1248 "vmovaps\t{$src, $dst|$dst, $src}",
1249 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1250 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
1251 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1252 "vmovapd\t{$src, $dst|$dst, $src}",
1253 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1254 SSEPackedDouble>, EVEX, EVEX_V512,
1255 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1256 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1257 "vmovups\t{$src, $dst|$dst, $src}",
1258 [(store (v16f32 VR512:$src), addr:$dst)],
1259 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
1260 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1261 "vmovupd\t{$src, $dst|$dst, $src}",
1262 [(store (v8f64 VR512:$src), addr:$dst)],
1263 SSEPackedDouble>, EVEX, EVEX_V512,
1264 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1266 let hasSideEffects = 0 in {
1267 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1269 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1271 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1273 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1274 EVEX, EVEX_V512, VEX_W;
1275 let mayStore = 1 in {
1276 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1277 (ins i512mem:$dst, VR512:$src),
1278 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1279 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1280 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1281 (ins i512mem:$dst, VR512:$src),
1282 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1283 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1285 let mayLoad = 1 in {
1286 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1288 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1289 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1290 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1292 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1293 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1297 // 512-bit aligned load/store
1298 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1299 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1301 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1302 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1303 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1304 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1306 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1307 RegisterClass RC, RegisterClass KRC,
1308 PatFrag ld_frag, X86MemOperand x86memop> {
1309 let hasSideEffects = 0 in
1310 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1311 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1312 let canFoldAsLoad = 1 in
1313 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1314 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1315 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1317 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1318 (ins x86memop:$dst, VR512:$src),
1319 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1320 let Constraints = "$src1 = $dst" in {
1321 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1322 (ins RC:$src1, KRC:$mask, RC:$src2),
1324 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1326 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1327 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1329 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1332 def rrkz : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1333 (ins KRC:$mask, RC:$src),
1335 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), []>,
1339 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1340 memopv16i32, i512mem>,
1341 EVEX_V512, EVEX_CD8<32, CD8VF>;
1342 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1343 memopv8i64, i512mem>,
1344 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1346 // 512-bit unaligned load/store
1347 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1348 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1350 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1351 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1352 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1353 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1355 let AddedComplexity = 20 in {
1356 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1357 (bc_v8i64 (v16i32 immAllZerosV)))),
1358 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1360 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1361 (v8i64 VR512:$src))),
1362 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1365 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1366 (v16i32 immAllZerosV))),
1367 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1369 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1370 (v16i32 VR512:$src))),
1371 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1373 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1374 (v16f32 VR512:$src2))),
1375 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1376 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1377 (v8f64 VR512:$src2))),
1378 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1379 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1380 (v16i32 VR512:$src2))),
1381 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1382 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1383 (v8i64 VR512:$src2))),
1384 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1386 // Move Int Doubleword to Packed Double Int
1388 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1389 "vmovd\t{$src, $dst|$dst, $src}",
1391 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1393 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1394 "vmovd\t{$src, $dst|$dst, $src}",
1396 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1397 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1398 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1399 "vmovq\t{$src, $dst|$dst, $src}",
1401 (v2i64 (scalar_to_vector GR64:$src)))],
1402 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1403 let isCodeGenOnly = 1 in {
1404 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1405 "vmovq\t{$src, $dst|$dst, $src}",
1406 [(set FR64:$dst, (bitconvert GR64:$src))],
1407 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1408 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1409 "vmovq\t{$src, $dst|$dst, $src}",
1410 [(set GR64:$dst, (bitconvert FR64:$src))],
1411 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1413 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1414 "vmovq\t{$src, $dst|$dst, $src}",
1415 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1416 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1417 EVEX_CD8<64, CD8VT1>;
1419 // Move Int Doubleword to Single Scalar
1421 let isCodeGenOnly = 1 in {
1422 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1423 "vmovd\t{$src, $dst|$dst, $src}",
1424 [(set FR32X:$dst, (bitconvert GR32:$src))],
1425 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1427 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1428 "vmovd\t{$src, $dst|$dst, $src}",
1429 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1430 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1433 // Move doubleword from xmm register to r/m32
1435 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1436 "vmovd\t{$src, $dst|$dst, $src}",
1437 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1438 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1440 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1441 (ins i32mem:$dst, VR128X:$src),
1442 "vmovd\t{$src, $dst|$dst, $src}",
1443 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1444 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1445 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1447 // Move quadword from xmm1 register to r/m64
1449 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1450 "vmovq\t{$src, $dst|$dst, $src}",
1451 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1453 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1454 Requires<[HasAVX512, In64BitMode]>;
1456 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1457 (ins i64mem:$dst, VR128X:$src),
1458 "vmovq\t{$src, $dst|$dst, $src}",
1459 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1460 addr:$dst)], IIC_SSE_MOVDQ>,
1461 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1462 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1464 // Move Scalar Single to Double Int
1466 let isCodeGenOnly = 1 in {
1467 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1469 "vmovd\t{$src, $dst|$dst, $src}",
1470 [(set GR32:$dst, (bitconvert FR32X:$src))],
1471 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1472 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1473 (ins i32mem:$dst, FR32X:$src),
1474 "vmovd\t{$src, $dst|$dst, $src}",
1475 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1476 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1479 // Move Quadword Int to Packed Quadword Int
1481 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1483 "vmovq\t{$src, $dst|$dst, $src}",
1485 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1486 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1488 //===----------------------------------------------------------------------===//
1489 // AVX-512 MOVSS, MOVSD
1490 //===----------------------------------------------------------------------===//
1492 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1493 SDNode OpNode, ValueType vt,
1494 X86MemOperand x86memop, PatFrag mem_pat> {
1495 let hasSideEffects = 0 in {
1496 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1497 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1498 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1499 (scalar_to_vector RC:$src2))))],
1500 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1501 let Constraints = "$src1 = $dst" in
1502 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1503 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1505 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1506 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1507 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1508 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1509 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1511 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1512 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1513 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1515 } //hasSideEffects = 0
1518 let ExeDomain = SSEPackedSingle in
1519 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1520 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1522 let ExeDomain = SSEPackedDouble in
1523 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1524 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1526 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1527 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1528 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1530 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1531 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1532 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1534 // For the disassembler
1535 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1536 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1537 (ins VR128X:$src1, FR32X:$src2),
1538 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1540 XS, EVEX_4V, VEX_LIG;
1541 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1542 (ins VR128X:$src1, FR64X:$src2),
1543 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1545 XD, EVEX_4V, VEX_LIG, VEX_W;
1548 let Predicates = [HasAVX512] in {
1549 let AddedComplexity = 15 in {
1550 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1551 // MOVS{S,D} to the lower bits.
1552 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1553 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1554 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1555 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1556 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1557 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1558 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1559 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1561 // Move low f32 and clear high bits.
1562 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1563 (SUBREG_TO_REG (i32 0),
1564 (VMOVSSZrr (v4f32 (V_SET0)),
1565 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1566 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1567 (SUBREG_TO_REG (i32 0),
1568 (VMOVSSZrr (v4i32 (V_SET0)),
1569 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1572 let AddedComplexity = 20 in {
1573 // MOVSSrm zeros the high parts of the register; represent this
1574 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1575 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1576 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1577 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1578 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1579 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1580 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1582 // MOVSDrm zeros the high parts of the register; represent this
1583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1584 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1585 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1586 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1587 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1588 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1589 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1590 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1591 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1592 def : Pat<(v2f64 (X86vzload addr:$src)),
1593 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1595 // Represent the same patterns above but in the form they appear for
1597 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1598 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1599 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1600 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1601 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1602 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1603 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1604 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1605 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1607 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1608 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1609 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1610 FR32X:$src)), sub_xmm)>;
1611 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1612 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1613 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1614 FR64X:$src)), sub_xmm)>;
1615 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1616 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1617 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1619 // Move low f64 and clear high bits.
1620 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1621 (SUBREG_TO_REG (i32 0),
1622 (VMOVSDZrr (v2f64 (V_SET0)),
1623 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1625 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1626 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1627 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1629 // Extract and store.
1630 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1632 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1633 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1635 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1637 // Shuffle with VMOVSS
1638 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1639 (VMOVSSZrr (v4i32 VR128X:$src1),
1640 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1641 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1642 (VMOVSSZrr (v4f32 VR128X:$src1),
1643 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1646 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1647 (SUBREG_TO_REG (i32 0),
1648 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1649 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1651 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1652 (SUBREG_TO_REG (i32 0),
1653 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1654 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1657 // Shuffle with VMOVSD
1658 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1659 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1660 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1661 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1662 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1663 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1664 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1665 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1668 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1669 (SUBREG_TO_REG (i32 0),
1670 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1671 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1673 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1674 (SUBREG_TO_REG (i32 0),
1675 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1676 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1679 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1680 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1681 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1682 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1683 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1684 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1685 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1686 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1689 let AddedComplexity = 15 in
1690 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1692 "vmovq\t{$src, $dst|$dst, $src}",
1693 [(set VR128X:$dst, (v2i64 (X86vzmovl
1694 (v2i64 VR128X:$src))))],
1695 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1697 let AddedComplexity = 20 in
1698 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1700 "vmovq\t{$src, $dst|$dst, $src}",
1701 [(set VR128X:$dst, (v2i64 (X86vzmovl
1702 (loadv2i64 addr:$src))))],
1703 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1704 EVEX_CD8<8, CD8VT8>;
1706 let Predicates = [HasAVX512] in {
1707 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1708 let AddedComplexity = 20 in {
1709 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1710 (VMOVDI2PDIZrm addr:$src)>;
1711 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1712 (VMOV64toPQIZrr GR64:$src)>;
1713 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1714 (VMOVDI2PDIZrr GR32:$src)>;
1716 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1717 (VMOVDI2PDIZrm addr:$src)>;
1718 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1719 (VMOVDI2PDIZrm addr:$src)>;
1720 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1721 (VMOVZPQILo2PQIZrm addr:$src)>;
1722 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1723 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1724 def : Pat<(v2i64 (X86vzload addr:$src)),
1725 (VMOVZPQILo2PQIZrm addr:$src)>;
1728 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1729 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1730 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1731 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1732 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1733 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1734 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1737 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1738 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1740 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1741 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1743 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1744 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1746 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1747 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1749 //===----------------------------------------------------------------------===//
1750 // AVX-512 - Integer arithmetic
1752 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1753 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1754 X86MemOperand x86memop, PatFrag scalar_mfrag,
1755 X86MemOperand x86scalar_mop, string BrdcstStr,
1756 OpndItins itins, bit IsCommutable = 0> {
1757 let isCommutable = IsCommutable in
1758 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1759 (ins RC:$src1, RC:$src2),
1760 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1761 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1763 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1764 (ins RC:$src1, x86memop:$src2),
1765 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1766 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1768 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1769 (ins RC:$src1, x86scalar_mop:$src2),
1770 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1771 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1772 [(set RC:$dst, (OpNode RC:$src1,
1773 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1774 itins.rm>, EVEX_4V, EVEX_B;
1776 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1777 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1778 PatFrag memop_frag, X86MemOperand x86memop,
1780 bit IsCommutable = 0> {
1781 let isCommutable = IsCommutable in
1782 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1783 (ins RC:$src1, RC:$src2),
1784 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1785 []>, EVEX_4V, VEX_W;
1786 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1787 (ins RC:$src1, x86memop:$src2),
1788 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1789 []>, EVEX_4V, VEX_W;
1792 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1793 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1794 EVEX_V512, EVEX_CD8<32, CD8VF>;
1796 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1797 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1798 EVEX_V512, EVEX_CD8<32, CD8VF>;
1800 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1801 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1802 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1804 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1805 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1806 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1808 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1809 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1810 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1812 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1813 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1814 EVEX_V512, EVEX_CD8<64, CD8VF>;
1816 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1817 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1818 EVEX_CD8<64, CD8VF>;
1820 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1821 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1823 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1824 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1825 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1826 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1827 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1828 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1830 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1831 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1832 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1833 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1834 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1835 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1837 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1838 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1839 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1840 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1841 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1842 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1844 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1845 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1846 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1847 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1848 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1849 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1851 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1852 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1853 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1854 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1855 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1856 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1858 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1859 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1860 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1861 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1862 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1863 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1864 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1865 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1866 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1867 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1868 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1869 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1870 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1871 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1872 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1873 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1874 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1875 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1876 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1877 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1878 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1879 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1880 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1881 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1882 //===----------------------------------------------------------------------===//
1883 // AVX-512 - Unpack Instructions
1884 //===----------------------------------------------------------------------===//
1886 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1887 PatFrag mem_frag, RegisterClass RC,
1888 X86MemOperand x86memop, string asm,
1890 def rr : AVX512PI<opc, MRMSrcReg,
1891 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1893 (vt (OpNode RC:$src1, RC:$src2)))],
1895 def rm : AVX512PI<opc, MRMSrcMem,
1896 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1898 (vt (OpNode RC:$src1,
1899 (bitconvert (mem_frag addr:$src2)))))],
1903 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1904 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1905 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1906 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1907 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1908 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1909 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1910 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1911 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1912 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1913 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1914 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1916 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1917 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1918 X86MemOperand x86memop> {
1919 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1920 (ins RC:$src1, RC:$src2),
1921 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1922 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1923 IIC_SSE_UNPCK>, EVEX_4V;
1924 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1925 (ins RC:$src1, x86memop:$src2),
1926 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1927 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1928 (bitconvert (memop_frag addr:$src2)))))],
1929 IIC_SSE_UNPCK>, EVEX_4V;
1931 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1932 VR512, memopv16i32, i512mem>, EVEX_V512,
1933 EVEX_CD8<32, CD8VF>;
1934 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1935 VR512, memopv8i64, i512mem>, EVEX_V512,
1936 VEX_W, EVEX_CD8<64, CD8VF>;
1937 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1938 VR512, memopv16i32, i512mem>, EVEX_V512,
1939 EVEX_CD8<32, CD8VF>;
1940 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1941 VR512, memopv8i64, i512mem>, EVEX_V512,
1942 VEX_W, EVEX_CD8<64, CD8VF>;
1943 //===----------------------------------------------------------------------===//
1947 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1948 SDNode OpNode, PatFrag mem_frag,
1949 X86MemOperand x86memop, ValueType OpVT> {
1950 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1951 (ins RC:$src1, i8imm:$src2),
1952 !strconcat(OpcodeStr,
1953 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1955 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1957 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1958 (ins x86memop:$src1, i8imm:$src2),
1959 !strconcat(OpcodeStr,
1960 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1962 (OpVT (OpNode (mem_frag addr:$src1),
1963 (i8 imm:$src2))))]>, EVEX;
1966 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1967 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1969 let ExeDomain = SSEPackedSingle in
1970 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1971 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1972 EVEX_CD8<32, CD8VF>;
1973 let ExeDomain = SSEPackedDouble in
1974 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1975 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1976 VEX_W, EVEX_CD8<32, CD8VF>;
1978 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1979 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1980 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1981 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1983 //===----------------------------------------------------------------------===//
1984 // AVX-512 Logical Instructions
1985 //===----------------------------------------------------------------------===//
1987 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1988 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1989 EVEX_V512, EVEX_CD8<32, CD8VF>;
1990 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1991 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1992 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1993 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1994 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1995 EVEX_V512, EVEX_CD8<32, CD8VF>;
1996 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1997 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1998 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1999 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
2000 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2001 EVEX_V512, EVEX_CD8<32, CD8VF>;
2002 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
2003 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2004 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2005 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
2006 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2007 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2008 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
2009 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
2010 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2012 //===----------------------------------------------------------------------===//
2013 // AVX-512 FP arithmetic
2014 //===----------------------------------------------------------------------===//
2016 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2018 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2019 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2020 EVEX_CD8<32, CD8VT1>;
2021 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2022 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2023 EVEX_CD8<64, CD8VT1>;
2026 let isCommutable = 1 in {
2027 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2028 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2029 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2030 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2032 let isCommutable = 0 in {
2033 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2034 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2037 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2038 RegisterClass RC, ValueType vt,
2039 X86MemOperand x86memop, PatFrag mem_frag,
2040 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2042 Domain d, OpndItins itins, bit commutable> {
2043 let isCommutable = commutable in
2044 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2045 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2046 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2048 let mayLoad = 1 in {
2049 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2050 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2051 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2052 itins.rm, d>, EVEX_4V;
2053 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2054 (ins RC:$src1, x86scalar_mop:$src2),
2055 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2056 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2057 [(set RC:$dst, (OpNode RC:$src1,
2058 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2059 itins.rm, d>, EVEX_4V, EVEX_B;
2063 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2064 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2065 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2067 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2068 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2069 SSE_ALU_ITINS_P.d, 1>,
2070 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2072 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2073 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2074 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2075 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2076 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2077 SSE_ALU_ITINS_P.d, 1>,
2078 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2080 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2081 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2082 SSE_ALU_ITINS_P.s, 1>,
2083 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2084 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2085 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2086 SSE_ALU_ITINS_P.s, 1>,
2087 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2089 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2090 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2091 SSE_ALU_ITINS_P.d, 1>,
2092 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2093 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2094 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2095 SSE_ALU_ITINS_P.d, 1>,
2096 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2098 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2099 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2100 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2101 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2102 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2103 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2105 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2106 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2107 SSE_ALU_ITINS_P.d, 0>,
2108 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2109 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2110 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2111 SSE_ALU_ITINS_P.d, 0>,
2112 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2114 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2115 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2116 (i16 -1), FROUND_CURRENT)),
2117 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2119 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2120 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2121 (i8 -1), FROUND_CURRENT)),
2122 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2124 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2125 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2126 (i16 -1), FROUND_CURRENT)),
2127 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2129 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2130 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2131 (i8 -1), FROUND_CURRENT)),
2132 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2133 //===----------------------------------------------------------------------===//
2134 // AVX-512 VPTESTM instructions
2135 //===----------------------------------------------------------------------===//
2137 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2138 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2139 SDNode OpNode, ValueType vt> {
2140 def rr : AVX512PI<opc, MRMSrcReg,
2141 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2142 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2143 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2144 SSEPackedInt>, EVEX_4V;
2145 def rm : AVX512PI<opc, MRMSrcMem,
2146 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2147 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2148 [(set KRC:$dst, (OpNode (vt RC:$src1),
2149 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2152 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2153 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2154 EVEX_CD8<32, CD8VF>;
2155 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2156 memopv8i64, X86testm, v8i64>, T8XS, EVEX_V512, VEX_W,
2157 EVEX_CD8<64, CD8VF>;
2159 let Predicates = [HasCDI] in {
2160 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2161 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2162 EVEX_CD8<32, CD8VF>;
2163 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2164 memopv8i64, X86testnm, v8i64>, T8PD, EVEX_V512, VEX_W,
2165 EVEX_CD8<64, CD8VF>;
2168 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2169 (v16i32 VR512:$src2), (i16 -1))),
2170 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2172 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2173 (v8i64 VR512:$src2), (i8 -1))),
2174 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR8)>;
2175 //===----------------------------------------------------------------------===//
2176 // AVX-512 Shift instructions
2177 //===----------------------------------------------------------------------===//
2178 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2179 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2180 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2181 RegisterClass KRC> {
2182 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2183 (ins RC:$src1, i8imm:$src2),
2184 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2185 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2186 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2187 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2188 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2189 !strconcat(OpcodeStr,
2190 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2191 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2192 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2193 (ins x86memop:$src1, i8imm:$src2),
2194 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2195 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2196 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2197 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2198 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2199 !strconcat(OpcodeStr,
2200 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2201 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2204 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2205 RegisterClass RC, ValueType vt, ValueType SrcVT,
2206 PatFrag bc_frag, RegisterClass KRC> {
2207 // src2 is always 128-bit
2208 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2209 (ins RC:$src1, VR128X:$src2),
2210 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2211 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2212 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2213 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2214 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2215 !strconcat(OpcodeStr,
2216 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2217 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2218 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2219 (ins RC:$src1, i128mem:$src2),
2220 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2221 [(set RC:$dst, (vt (OpNode RC:$src1,
2222 (bc_frag (memopv2i64 addr:$src2)))))],
2223 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2224 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2225 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2226 !strconcat(OpcodeStr,
2227 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2228 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2231 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2232 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2233 EVEX_V512, EVEX_CD8<32, CD8VF>;
2234 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2235 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2236 EVEX_CD8<32, CD8VQ>;
2238 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2239 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2240 EVEX_CD8<64, CD8VF>, VEX_W;
2241 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2242 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2243 EVEX_CD8<64, CD8VQ>, VEX_W;
2245 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2246 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2247 EVEX_CD8<32, CD8VF>;
2248 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2249 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2250 EVEX_CD8<32, CD8VQ>;
2252 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2253 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2254 EVEX_CD8<64, CD8VF>, VEX_W;
2255 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2256 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2257 EVEX_CD8<64, CD8VQ>, VEX_W;
2259 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2260 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2261 EVEX_V512, EVEX_CD8<32, CD8VF>;
2262 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2263 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2264 EVEX_CD8<32, CD8VQ>;
2266 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2267 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2268 EVEX_CD8<64, CD8VF>, VEX_W;
2269 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2270 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2271 EVEX_CD8<64, CD8VQ>, VEX_W;
2273 //===-------------------------------------------------------------------===//
2274 // Variable Bit Shifts
2275 //===-------------------------------------------------------------------===//
2276 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2277 RegisterClass RC, ValueType vt,
2278 X86MemOperand x86memop, PatFrag mem_frag> {
2279 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2280 (ins RC:$src1, RC:$src2),
2281 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2283 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2285 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2286 (ins RC:$src1, x86memop:$src2),
2287 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2289 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2293 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2294 i512mem, memopv16i32>, EVEX_V512,
2295 EVEX_CD8<32, CD8VF>;
2296 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2297 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2298 EVEX_CD8<64, CD8VF>;
2299 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2300 i512mem, memopv16i32>, EVEX_V512,
2301 EVEX_CD8<32, CD8VF>;
2302 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2303 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2304 EVEX_CD8<64, CD8VF>;
2305 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2306 i512mem, memopv16i32>, EVEX_V512,
2307 EVEX_CD8<32, CD8VF>;
2308 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2309 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2310 EVEX_CD8<64, CD8VF>;
2312 //===----------------------------------------------------------------------===//
2313 // AVX-512 - MOVDDUP
2314 //===----------------------------------------------------------------------===//
2316 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2317 X86MemOperand x86memop, PatFrag memop_frag> {
2318 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2319 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2320 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2321 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2322 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2324 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2327 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2328 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2329 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2330 (VMOVDDUPZrm addr:$src)>;
2332 //===---------------------------------------------------------------------===//
2333 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2334 //===---------------------------------------------------------------------===//
2335 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2336 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2337 X86MemOperand x86memop> {
2338 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2339 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2340 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2342 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2343 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2344 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2347 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2348 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2349 EVEX_CD8<32, CD8VF>;
2350 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2351 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2352 EVEX_CD8<32, CD8VF>;
2354 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2355 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2356 (VMOVSHDUPZrm addr:$src)>;
2357 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2358 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2359 (VMOVSLDUPZrm addr:$src)>;
2361 //===----------------------------------------------------------------------===//
2362 // Move Low to High and High to Low packed FP Instructions
2363 //===----------------------------------------------------------------------===//
2364 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2365 (ins VR128X:$src1, VR128X:$src2),
2366 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2367 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2368 IIC_SSE_MOV_LH>, EVEX_4V;
2369 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2370 (ins VR128X:$src1, VR128X:$src2),
2371 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2372 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2373 IIC_SSE_MOV_LH>, EVEX_4V;
2375 let Predicates = [HasAVX512] in {
2377 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2378 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2379 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2380 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2383 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2384 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2387 //===----------------------------------------------------------------------===//
2388 // FMA - Fused Multiply Operations
2390 let Constraints = "$src1 = $dst" in {
2391 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2392 RegisterClass RC, X86MemOperand x86memop,
2393 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2394 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2395 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2396 (ins RC:$src1, RC:$src2, RC:$src3),
2397 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2398 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2401 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2402 (ins RC:$src1, RC:$src2, x86memop:$src3),
2403 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2404 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2405 (mem_frag addr:$src3))))]>;
2406 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2407 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2408 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2409 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2410 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2411 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2413 } // Constraints = "$src1 = $dst"
2415 let ExeDomain = SSEPackedSingle in {
2416 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2417 memopv16f32, f32mem, loadf32, "{1to16}",
2418 X86Fmadd, v16f32>, EVEX_V512,
2419 EVEX_CD8<32, CD8VF>;
2420 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2421 memopv16f32, f32mem, loadf32, "{1to16}",
2422 X86Fmsub, v16f32>, EVEX_V512,
2423 EVEX_CD8<32, CD8VF>;
2424 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2425 memopv16f32, f32mem, loadf32, "{1to16}",
2426 X86Fmaddsub, v16f32>,
2427 EVEX_V512, EVEX_CD8<32, CD8VF>;
2428 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2429 memopv16f32, f32mem, loadf32, "{1to16}",
2430 X86Fmsubadd, v16f32>,
2431 EVEX_V512, EVEX_CD8<32, CD8VF>;
2432 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2433 memopv16f32, f32mem, loadf32, "{1to16}",
2434 X86Fnmadd, v16f32>, EVEX_V512,
2435 EVEX_CD8<32, CD8VF>;
2436 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2437 memopv16f32, f32mem, loadf32, "{1to16}",
2438 X86Fnmsub, v16f32>, EVEX_V512,
2439 EVEX_CD8<32, CD8VF>;
2441 let ExeDomain = SSEPackedDouble in {
2442 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2443 memopv8f64, f64mem, loadf64, "{1to8}",
2444 X86Fmadd, v8f64>, EVEX_V512,
2445 VEX_W, EVEX_CD8<64, CD8VF>;
2446 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2447 memopv8f64, f64mem, loadf64, "{1to8}",
2448 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2449 EVEX_CD8<64, CD8VF>;
2450 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2451 memopv8f64, f64mem, loadf64, "{1to8}",
2452 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2453 EVEX_CD8<64, CD8VF>;
2454 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2455 memopv8f64, f64mem, loadf64, "{1to8}",
2456 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2457 EVEX_CD8<64, CD8VF>;
2458 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2459 memopv8f64, f64mem, loadf64, "{1to8}",
2460 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2461 EVEX_CD8<64, CD8VF>;
2462 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2463 memopv8f64, f64mem, loadf64, "{1to8}",
2464 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2465 EVEX_CD8<64, CD8VF>;
2468 let Constraints = "$src1 = $dst" in {
2469 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2470 RegisterClass RC, X86MemOperand x86memop,
2471 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2472 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2474 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2475 (ins RC:$src1, RC:$src3, x86memop:$src2),
2476 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2477 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2478 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2479 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2480 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2481 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2482 [(set RC:$dst, (OpNode RC:$src1,
2483 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2485 } // Constraints = "$src1 = $dst"
2488 let ExeDomain = SSEPackedSingle in {
2489 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2490 memopv16f32, f32mem, loadf32, "{1to16}",
2491 X86Fmadd, v16f32>, EVEX_V512,
2492 EVEX_CD8<32, CD8VF>;
2493 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2494 memopv16f32, f32mem, loadf32, "{1to16}",
2495 X86Fmsub, v16f32>, EVEX_V512,
2496 EVEX_CD8<32, CD8VF>;
2497 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2498 memopv16f32, f32mem, loadf32, "{1to16}",
2499 X86Fmaddsub, v16f32>,
2500 EVEX_V512, EVEX_CD8<32, CD8VF>;
2501 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2502 memopv16f32, f32mem, loadf32, "{1to16}",
2503 X86Fmsubadd, v16f32>,
2504 EVEX_V512, EVEX_CD8<32, CD8VF>;
2505 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2506 memopv16f32, f32mem, loadf32, "{1to16}",
2507 X86Fnmadd, v16f32>, EVEX_V512,
2508 EVEX_CD8<32, CD8VF>;
2509 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2510 memopv16f32, f32mem, loadf32, "{1to16}",
2511 X86Fnmsub, v16f32>, EVEX_V512,
2512 EVEX_CD8<32, CD8VF>;
2514 let ExeDomain = SSEPackedDouble in {
2515 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2516 memopv8f64, f64mem, loadf64, "{1to8}",
2517 X86Fmadd, v8f64>, EVEX_V512,
2518 VEX_W, EVEX_CD8<64, CD8VF>;
2519 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2520 memopv8f64, f64mem, loadf64, "{1to8}",
2521 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2522 EVEX_CD8<64, CD8VF>;
2523 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2524 memopv8f64, f64mem, loadf64, "{1to8}",
2525 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2526 EVEX_CD8<64, CD8VF>;
2527 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2528 memopv8f64, f64mem, loadf64, "{1to8}",
2529 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2530 EVEX_CD8<64, CD8VF>;
2531 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2532 memopv8f64, f64mem, loadf64, "{1to8}",
2533 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2534 EVEX_CD8<64, CD8VF>;
2535 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2536 memopv8f64, f64mem, loadf64, "{1to8}",
2537 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2538 EVEX_CD8<64, CD8VF>;
2542 let Constraints = "$src1 = $dst" in {
2543 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2544 RegisterClass RC, ValueType OpVT,
2545 X86MemOperand x86memop, Operand memop,
2547 let isCommutable = 1 in
2548 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2549 (ins RC:$src1, RC:$src2, RC:$src3),
2550 !strconcat(OpcodeStr,
2551 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2553 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2555 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2556 (ins RC:$src1, RC:$src2, f128mem:$src3),
2557 !strconcat(OpcodeStr,
2558 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2560 (OpVT (OpNode RC:$src2, RC:$src1,
2561 (mem_frag addr:$src3))))]>;
2564 } // Constraints = "$src1 = $dst"
2566 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2567 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2568 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2569 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2570 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2571 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2572 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2573 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2574 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2575 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2576 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2577 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2578 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2579 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2580 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2581 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2583 //===----------------------------------------------------------------------===//
2584 // AVX-512 Scalar convert from sign integer to float/double
2585 //===----------------------------------------------------------------------===//
2587 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2588 X86MemOperand x86memop, string asm> {
2589 let hasSideEffects = 0 in {
2590 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2591 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2594 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2595 (ins DstRC:$src1, x86memop:$src),
2596 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2598 } // hasSideEffects = 0
2600 let Predicates = [HasAVX512] in {
2601 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2602 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2603 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2604 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2605 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2606 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2607 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2608 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2610 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2611 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2612 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2613 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2614 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2615 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2616 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2617 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2619 def : Pat<(f32 (sint_to_fp GR32:$src)),
2620 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2621 def : Pat<(f32 (sint_to_fp GR64:$src)),
2622 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2623 def : Pat<(f64 (sint_to_fp GR32:$src)),
2624 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2625 def : Pat<(f64 (sint_to_fp GR64:$src)),
2626 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2628 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2629 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2630 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2631 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2632 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2633 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2634 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2635 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2637 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2638 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2639 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2640 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2641 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2642 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2643 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2644 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2646 def : Pat<(f32 (uint_to_fp GR32:$src)),
2647 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2648 def : Pat<(f32 (uint_to_fp GR64:$src)),
2649 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2650 def : Pat<(f64 (uint_to_fp GR32:$src)),
2651 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2652 def : Pat<(f64 (uint_to_fp GR64:$src)),
2653 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2656 //===----------------------------------------------------------------------===//
2657 // AVX-512 Scalar convert from float/double to integer
2658 //===----------------------------------------------------------------------===//
2659 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2660 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2662 let hasSideEffects = 0 in {
2663 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2664 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2665 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2666 Requires<[HasAVX512]>;
2668 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2669 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2670 Requires<[HasAVX512]>;
2671 } // hasSideEffects = 0
2673 let Predicates = [HasAVX512] in {
2674 // Convert float/double to signed/unsigned int 32/64
2675 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2676 ssmem, sse_load_f32, "cvtss2si">,
2677 XS, EVEX_CD8<32, CD8VT1>;
2678 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2679 ssmem, sse_load_f32, "cvtss2si">,
2680 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2681 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2682 ssmem, sse_load_f32, "cvtss2usi">,
2683 XS, EVEX_CD8<32, CD8VT1>;
2684 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2685 int_x86_avx512_cvtss2usi64, ssmem,
2686 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2687 EVEX_CD8<32, CD8VT1>;
2688 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2689 sdmem, sse_load_f64, "cvtsd2si">,
2690 XD, EVEX_CD8<64, CD8VT1>;
2691 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2692 sdmem, sse_load_f64, "cvtsd2si">,
2693 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2694 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2695 sdmem, sse_load_f64, "cvtsd2usi">,
2696 XD, EVEX_CD8<64, CD8VT1>;
2697 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2698 int_x86_avx512_cvtsd2usi64, sdmem,
2699 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2700 EVEX_CD8<64, CD8VT1>;
2702 let isCodeGenOnly = 1 in {
2703 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2704 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2705 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2706 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2707 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2708 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2709 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2710 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2711 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2712 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2713 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2714 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2716 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2717 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2718 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2719 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2720 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2721 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2722 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2723 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2724 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2725 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2726 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2727 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2728 } // isCodeGenOnly = 1
2730 // Convert float/double to signed/unsigned int 32/64 with truncation
2731 let isCodeGenOnly = 1 in {
2732 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2733 ssmem, sse_load_f32, "cvttss2si">,
2734 XS, EVEX_CD8<32, CD8VT1>;
2735 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2736 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2737 "cvttss2si">, XS, VEX_W,
2738 EVEX_CD8<32, CD8VT1>;
2739 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2740 sdmem, sse_load_f64, "cvttsd2si">, XD,
2741 EVEX_CD8<64, CD8VT1>;
2742 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2743 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2744 "cvttsd2si">, XD, VEX_W,
2745 EVEX_CD8<64, CD8VT1>;
2746 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2747 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2748 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2749 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2750 int_x86_avx512_cvttss2usi64, ssmem,
2751 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2752 EVEX_CD8<32, CD8VT1>;
2753 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2754 int_x86_avx512_cvttsd2usi,
2755 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2756 EVEX_CD8<64, CD8VT1>;
2757 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2758 int_x86_avx512_cvttsd2usi64, sdmem,
2759 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2760 EVEX_CD8<64, CD8VT1>;
2761 } // isCodeGenOnly = 1
2763 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2764 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2766 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2767 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2768 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2769 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2770 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2771 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2774 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2775 loadf32, "cvttss2si">, XS,
2776 EVEX_CD8<32, CD8VT1>;
2777 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2778 loadf32, "cvttss2usi">, XS,
2779 EVEX_CD8<32, CD8VT1>;
2780 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2781 loadf32, "cvttss2si">, XS, VEX_W,
2782 EVEX_CD8<32, CD8VT1>;
2783 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2784 loadf32, "cvttss2usi">, XS, VEX_W,
2785 EVEX_CD8<32, CD8VT1>;
2786 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2787 loadf64, "cvttsd2si">, XD,
2788 EVEX_CD8<64, CD8VT1>;
2789 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2790 loadf64, "cvttsd2usi">, XD,
2791 EVEX_CD8<64, CD8VT1>;
2792 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2793 loadf64, "cvttsd2si">, XD, VEX_W,
2794 EVEX_CD8<64, CD8VT1>;
2795 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2796 loadf64, "cvttsd2usi">, XD, VEX_W,
2797 EVEX_CD8<64, CD8VT1>;
2799 //===----------------------------------------------------------------------===//
2800 // AVX-512 Convert form float to double and back
2801 //===----------------------------------------------------------------------===//
2802 let hasSideEffects = 0 in {
2803 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2804 (ins FR32X:$src1, FR32X:$src2),
2805 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2806 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2808 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2809 (ins FR32X:$src1, f32mem:$src2),
2810 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2811 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2812 EVEX_CD8<32, CD8VT1>;
2814 // Convert scalar double to scalar single
2815 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2816 (ins FR64X:$src1, FR64X:$src2),
2817 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2818 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2820 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2821 (ins FR64X:$src1, f64mem:$src2),
2822 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2823 []>, EVEX_4V, VEX_LIG, VEX_W,
2824 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2827 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2828 Requires<[HasAVX512]>;
2829 def : Pat<(fextend (loadf32 addr:$src)),
2830 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2832 def : Pat<(extloadf32 addr:$src),
2833 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2834 Requires<[HasAVX512, OptForSize]>;
2836 def : Pat<(extloadf32 addr:$src),
2837 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2838 Requires<[HasAVX512, OptForSpeed]>;
2840 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2841 Requires<[HasAVX512]>;
2843 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2844 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2845 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2847 let hasSideEffects = 0 in {
2848 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2849 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2851 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2852 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2853 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2854 [], d>, EVEX, EVEX_B, EVEX_RC;
2856 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2857 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2859 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2860 } // hasSideEffects = 0
2863 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2864 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2865 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2867 let hasSideEffects = 0 in {
2868 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2869 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2871 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2873 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2874 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2876 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2877 } // hasSideEffects = 0
2880 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2881 memopv8f64, f512mem, v8f32, v8f64,
2882 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2883 EVEX_CD8<64, CD8VF>;
2885 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2886 memopv4f64, f256mem, v8f64, v8f32,
2887 SSEPackedDouble>, EVEX_V512, PS,
2888 EVEX_CD8<32, CD8VH>;
2889 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2890 (VCVTPS2PDZrm addr:$src)>;
2892 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2893 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2894 (VCVTPD2PSZrr VR512:$src)>;
2896 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2897 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2898 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2900 //===----------------------------------------------------------------------===//
2901 // AVX-512 Vector convert from sign integer to float/double
2902 //===----------------------------------------------------------------------===//
2904 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2905 memopv8i64, i512mem, v16f32, v16i32,
2906 SSEPackedSingle>, EVEX_V512, PS,
2907 EVEX_CD8<32, CD8VF>;
2909 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2910 memopv4i64, i256mem, v8f64, v8i32,
2911 SSEPackedDouble>, EVEX_V512, XS,
2912 EVEX_CD8<32, CD8VH>;
2914 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2915 memopv16f32, f512mem, v16i32, v16f32,
2916 SSEPackedSingle>, EVEX_V512, XS,
2917 EVEX_CD8<32, CD8VF>;
2919 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2920 memopv8f64, f512mem, v8i32, v8f64,
2921 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2922 EVEX_CD8<64, CD8VF>;
2924 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2925 memopv16f32, f512mem, v16i32, v16f32,
2926 SSEPackedSingle>, EVEX_V512, PS,
2927 EVEX_CD8<32, CD8VF>;
2929 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2930 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2931 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2932 (VCVTTPS2UDQZrr VR512:$src)>;
2934 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2935 memopv8f64, f512mem, v8i32, v8f64,
2936 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
2937 EVEX_CD8<64, CD8VF>;
2939 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2940 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2941 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2942 (VCVTTPD2UDQZrr VR512:$src)>;
2944 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2945 memopv4i64, f256mem, v8f64, v8i32,
2946 SSEPackedDouble>, EVEX_V512, XS,
2947 EVEX_CD8<32, CD8VH>;
2949 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2950 memopv16i32, f512mem, v16f32, v16i32,
2951 SSEPackedSingle>, EVEX_V512, XD,
2952 EVEX_CD8<32, CD8VF>;
2954 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2955 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2956 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2959 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2960 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2961 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2962 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2963 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2964 (VCVTDQ2PDZrr VR256X:$src)>;
2965 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2966 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2967 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2968 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2969 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2970 (VCVTUDQ2PDZrr VR256X:$src)>;
2972 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2973 RegisterClass DstRC, PatFrag mem_frag,
2974 X86MemOperand x86memop, Domain d> {
2975 let hasSideEffects = 0 in {
2976 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2977 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2979 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2980 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2981 [], d>, EVEX, EVEX_B, EVEX_RC;
2983 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2984 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2986 } // hasSideEffects = 0
2989 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2990 memopv16f32, f512mem, SSEPackedSingle>, PD,
2991 EVEX_V512, EVEX_CD8<32, CD8VF>;
2992 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2993 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2994 EVEX_V512, EVEX_CD8<64, CD8VF>;
2996 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2997 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2998 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3000 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3001 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3002 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3004 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3005 memopv16f32, f512mem, SSEPackedSingle>,
3006 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3007 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3008 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3009 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3011 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3012 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3013 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3015 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3016 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3017 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3019 let Predicates = [HasAVX512] in {
3020 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3021 (VCVTPD2PSZrm addr:$src)>;
3022 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3023 (VCVTPS2PDZrm addr:$src)>;
3026 //===----------------------------------------------------------------------===//
3027 // Half precision conversion instructions
3028 //===----------------------------------------------------------------------===//
3029 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3030 X86MemOperand x86memop> {
3031 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3032 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3034 let hasSideEffects = 0, mayLoad = 1 in
3035 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3036 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3039 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3040 X86MemOperand x86memop> {
3041 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3042 (ins srcRC:$src1, i32i8imm:$src2),
3043 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3045 let hasSideEffects = 0, mayStore = 1 in
3046 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3047 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3048 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3051 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3052 EVEX_CD8<32, CD8VH>;
3053 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3054 EVEX_CD8<32, CD8VH>;
3056 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3057 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3058 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3060 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3061 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3062 (VCVTPH2PSZrr VR256X:$src)>;
3064 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3065 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3066 "ucomiss">, PS, EVEX, VEX_LIG,
3067 EVEX_CD8<32, CD8VT1>;
3068 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3069 "ucomisd">, PD, EVEX,
3070 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3071 let Pattern = []<dag> in {
3072 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3073 "comiss">, PS, EVEX, VEX_LIG,
3074 EVEX_CD8<32, CD8VT1>;
3075 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3076 "comisd">, PD, EVEX,
3077 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3079 let isCodeGenOnly = 1 in {
3080 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3081 load, "ucomiss">, PS, EVEX, VEX_LIG,
3082 EVEX_CD8<32, CD8VT1>;
3083 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3084 load, "ucomisd">, PD, EVEX,
3085 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3087 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3088 load, "comiss">, PS, EVEX, VEX_LIG,
3089 EVEX_CD8<32, CD8VT1>;
3090 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3091 load, "comisd">, PD, EVEX,
3092 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3096 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3097 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3098 X86MemOperand x86memop> {
3099 let hasSideEffects = 0 in {
3100 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3101 (ins RC:$src1, RC:$src2),
3102 !strconcat(OpcodeStr,
3103 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3104 let mayLoad = 1 in {
3105 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3106 (ins RC:$src1, x86memop:$src2),
3107 !strconcat(OpcodeStr,
3108 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3113 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3114 EVEX_CD8<32, CD8VT1>;
3115 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3116 VEX_W, EVEX_CD8<64, CD8VT1>;
3117 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3118 EVEX_CD8<32, CD8VT1>;
3119 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3120 VEX_W, EVEX_CD8<64, CD8VT1>;
3122 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3123 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3124 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3125 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3127 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3128 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3129 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3130 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3132 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3133 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3134 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3135 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3137 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3138 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3139 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3140 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3142 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3143 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3144 RegisterClass RC, X86MemOperand x86memop,
3145 PatFrag mem_frag, ValueType OpVt> {
3146 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3147 !strconcat(OpcodeStr,
3148 " \t{$src, $dst|$dst, $src}"),
3149 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3151 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3152 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3153 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3156 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3157 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3158 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3159 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3160 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3161 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3162 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3163 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3165 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3166 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3167 (VRSQRT14PSZr VR512:$src)>;
3168 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3169 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3170 (VRSQRT14PDZr VR512:$src)>;
3172 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3173 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3174 (VRCP14PSZr VR512:$src)>;
3175 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3176 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3177 (VRCP14PDZr VR512:$src)>;
3179 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3180 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3181 X86MemOperand x86memop> {
3182 let hasSideEffects = 0, Predicates = [HasERI] in {
3183 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3184 (ins RC:$src1, RC:$src2),
3185 !strconcat(OpcodeStr,
3186 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3187 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3188 (ins RC:$src1, RC:$src2),
3189 !strconcat(OpcodeStr,
3190 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3191 []>, EVEX_4V, EVEX_B;
3192 let mayLoad = 1 in {
3193 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3194 (ins RC:$src1, x86memop:$src2),
3195 !strconcat(OpcodeStr,
3196 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3201 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3202 EVEX_CD8<32, CD8VT1>;
3203 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3204 VEX_W, EVEX_CD8<64, CD8VT1>;
3205 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3206 EVEX_CD8<32, CD8VT1>;
3207 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3208 VEX_W, EVEX_CD8<64, CD8VT1>;
3210 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3211 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3213 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3214 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3216 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3217 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3219 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3220 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3222 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3223 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3225 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3226 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3228 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3229 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3231 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3232 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3234 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3235 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3236 RegisterClass RC, X86MemOperand x86memop> {
3237 let hasSideEffects = 0, Predicates = [HasERI] in {
3238 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3239 !strconcat(OpcodeStr,
3240 " \t{$src, $dst|$dst, $src}"),
3242 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3243 !strconcat(OpcodeStr,
3244 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3246 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3247 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3251 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3252 EVEX_V512, EVEX_CD8<32, CD8VF>;
3253 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3254 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3255 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3256 EVEX_V512, EVEX_CD8<32, CD8VF>;
3257 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3258 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3260 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3261 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3262 (VRSQRT28PSZrb VR512:$src)>;
3263 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3264 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3265 (VRSQRT28PDZrb VR512:$src)>;
3267 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3268 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3269 (VRCP28PSZrb VR512:$src)>;
3270 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3271 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3272 (VRCP28PDZrb VR512:$src)>;
3274 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3275 Intrinsic V16F32Int, Intrinsic V8F64Int,
3276 OpndItins itins_s, OpndItins itins_d> {
3277 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3278 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3279 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3283 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3284 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3286 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3287 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3289 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3290 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3291 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3295 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3296 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3297 [(set VR512:$dst, (OpNode
3298 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3299 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3301 let isCodeGenOnly = 1 in {
3302 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3303 !strconcat(OpcodeStr,
3304 "ps\t{$src, $dst|$dst, $src}"),
3305 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3307 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3308 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3310 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3311 EVEX_V512, EVEX_CD8<32, CD8VF>;
3312 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3313 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3314 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3315 EVEX, EVEX_V512, VEX_W;
3316 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3317 !strconcat(OpcodeStr,
3318 "pd\t{$src, $dst|$dst, $src}"),
3319 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3320 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3321 } // isCodeGenOnly = 1
3324 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3325 Intrinsic F32Int, Intrinsic F64Int,
3326 OpndItins itins_s, OpndItins itins_d> {
3327 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3328 (ins FR32X:$src1, FR32X:$src2),
3329 !strconcat(OpcodeStr,
3330 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3331 [], itins_s.rr>, XS, EVEX_4V;
3332 let isCodeGenOnly = 1 in
3333 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3334 (ins VR128X:$src1, VR128X:$src2),
3335 !strconcat(OpcodeStr,
3336 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3338 (F32Int VR128X:$src1, VR128X:$src2))],
3339 itins_s.rr>, XS, EVEX_4V;
3340 let mayLoad = 1 in {
3341 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3342 (ins FR32X:$src1, f32mem:$src2),
3343 !strconcat(OpcodeStr,
3344 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3345 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3346 let isCodeGenOnly = 1 in
3347 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3348 (ins VR128X:$src1, ssmem:$src2),
3349 !strconcat(OpcodeStr,
3350 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3352 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3353 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3355 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3356 (ins FR64X:$src1, FR64X:$src2),
3357 !strconcat(OpcodeStr,
3358 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3360 let isCodeGenOnly = 1 in
3361 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3362 (ins VR128X:$src1, VR128X:$src2),
3363 !strconcat(OpcodeStr,
3364 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3366 (F64Int VR128X:$src1, VR128X:$src2))],
3367 itins_s.rr>, XD, EVEX_4V, VEX_W;
3368 let mayLoad = 1 in {
3369 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3370 (ins FR64X:$src1, f64mem:$src2),
3371 !strconcat(OpcodeStr,
3372 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3373 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3374 let isCodeGenOnly = 1 in
3375 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3376 (ins VR128X:$src1, sdmem:$src2),
3377 !strconcat(OpcodeStr,
3378 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3380 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3381 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3386 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3387 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3388 SSE_SQRTSS, SSE_SQRTSD>,
3389 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3390 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3391 SSE_SQRTPS, SSE_SQRTPD>;
3393 let Predicates = [HasAVX512] in {
3394 def : Pat<(f32 (fsqrt FR32X:$src)),
3395 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3396 def : Pat<(f32 (fsqrt (load addr:$src))),
3397 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3398 Requires<[OptForSize]>;
3399 def : Pat<(f64 (fsqrt FR64X:$src)),
3400 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3401 def : Pat<(f64 (fsqrt (load addr:$src))),
3402 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3403 Requires<[OptForSize]>;
3405 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3406 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3407 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3408 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3409 Requires<[OptForSize]>;
3411 def : Pat<(f32 (X86frcp FR32X:$src)),
3412 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3413 def : Pat<(f32 (X86frcp (load addr:$src))),
3414 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3415 Requires<[OptForSize]>;
3417 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3418 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3419 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3421 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3422 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3424 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3425 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3426 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3428 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3429 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3433 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3434 X86MemOperand x86memop, RegisterClass RC,
3435 PatFrag mem_frag32, PatFrag mem_frag64,
3436 Intrinsic V4F32Int, Intrinsic V2F64Int,
3438 let ExeDomain = SSEPackedSingle in {
3439 // Intrinsic operation, reg.
3440 // Vector intrinsic operation, reg
3441 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3442 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3443 !strconcat(OpcodeStr,
3444 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3445 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3447 // Vector intrinsic operation, mem
3448 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3449 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3450 !strconcat(OpcodeStr,
3451 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3453 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3454 EVEX_CD8<32, VForm>;
3455 } // ExeDomain = SSEPackedSingle
3457 let ExeDomain = SSEPackedDouble in {
3458 // Vector intrinsic operation, reg
3459 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3460 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3461 !strconcat(OpcodeStr,
3462 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3463 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3465 // Vector intrinsic operation, mem
3466 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3467 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3468 !strconcat(OpcodeStr,
3469 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3471 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3472 EVEX_CD8<64, VForm>;
3473 } // ExeDomain = SSEPackedDouble
3476 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3480 let ExeDomain = GenericDomain in {
3482 let hasSideEffects = 0 in
3483 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3484 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3485 !strconcat(OpcodeStr,
3486 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3489 // Intrinsic operation, reg.
3490 let isCodeGenOnly = 1 in
3491 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3492 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3493 !strconcat(OpcodeStr,
3494 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3495 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3497 // Intrinsic operation, mem.
3498 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3499 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3500 !strconcat(OpcodeStr,
3501 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3502 [(set VR128X:$dst, (F32Int VR128X:$src1,
3503 sse_load_f32:$src2, imm:$src3))]>,
3504 EVEX_CD8<32, CD8VT1>;
3507 let hasSideEffects = 0 in
3508 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3509 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3510 !strconcat(OpcodeStr,
3511 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3514 // Intrinsic operation, reg.
3515 let isCodeGenOnly = 1 in
3516 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3517 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3518 !strconcat(OpcodeStr,
3519 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3520 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3523 // Intrinsic operation, mem.
3524 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3525 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3526 !strconcat(OpcodeStr,
3527 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3529 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3530 VEX_W, EVEX_CD8<64, CD8VT1>;
3531 } // ExeDomain = GenericDomain
3534 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3535 X86MemOperand x86memop, RegisterClass RC,
3536 PatFrag mem_frag, Domain d> {
3537 let ExeDomain = d in {
3538 // Intrinsic operation, reg.
3539 // Vector intrinsic operation, reg
3540 def r : AVX512AIi8<opc, MRMSrcReg,
3541 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3542 !strconcat(OpcodeStr,
3543 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3546 // Vector intrinsic operation, mem
3547 def m : AVX512AIi8<opc, MRMSrcMem,
3548 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3549 !strconcat(OpcodeStr,
3550 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3556 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3557 memopv16f32, SSEPackedSingle>, EVEX_V512,
3558 EVEX_CD8<32, CD8VF>;
3560 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3561 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3563 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3566 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3567 memopv8f64, SSEPackedDouble>, EVEX_V512,
3568 VEX_W, EVEX_CD8<64, CD8VF>;
3570 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3571 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3573 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3575 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3576 Operand x86memop, RegisterClass RC, Domain d> {
3577 let ExeDomain = d in {
3578 def r : AVX512AIi8<opc, MRMSrcReg,
3579 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3580 !strconcat(OpcodeStr,
3581 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3584 def m : AVX512AIi8<opc, MRMSrcMem,
3585 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3586 !strconcat(OpcodeStr,
3587 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3592 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3593 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3595 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3596 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3598 def : Pat<(ffloor FR32X:$src),
3599 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3600 def : Pat<(f64 (ffloor FR64X:$src)),
3601 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3602 def : Pat<(f32 (fnearbyint FR32X:$src)),
3603 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3604 def : Pat<(f64 (fnearbyint FR64X:$src)),
3605 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3606 def : Pat<(f32 (fceil FR32X:$src)),
3607 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3608 def : Pat<(f64 (fceil FR64X:$src)),
3609 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3610 def : Pat<(f32 (frint FR32X:$src)),
3611 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3612 def : Pat<(f64 (frint FR64X:$src)),
3613 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3614 def : Pat<(f32 (ftrunc FR32X:$src)),
3615 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3616 def : Pat<(f64 (ftrunc FR64X:$src)),
3617 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3619 def : Pat<(v16f32 (ffloor VR512:$src)),
3620 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3621 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3622 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3623 def : Pat<(v16f32 (fceil VR512:$src)),
3624 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3625 def : Pat<(v16f32 (frint VR512:$src)),
3626 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3627 def : Pat<(v16f32 (ftrunc VR512:$src)),
3628 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3630 def : Pat<(v8f64 (ffloor VR512:$src)),
3631 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3632 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3633 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3634 def : Pat<(v8f64 (fceil VR512:$src)),
3635 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3636 def : Pat<(v8f64 (frint VR512:$src)),
3637 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3638 def : Pat<(v8f64 (ftrunc VR512:$src)),
3639 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3641 //-------------------------------------------------
3642 // Integer truncate and extend operations
3643 //-------------------------------------------------
3645 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3646 RegisterClass dstRC, RegisterClass srcRC,
3647 RegisterClass KRC, X86MemOperand x86memop> {
3648 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3650 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3653 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3654 (ins KRC:$mask, srcRC:$src),
3655 !strconcat(OpcodeStr,
3656 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3659 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3660 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3663 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3664 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3665 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3666 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3667 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3668 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3669 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3670 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3671 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3672 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3673 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3674 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3675 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3676 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3677 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3678 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3679 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3680 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3681 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3682 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3683 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3684 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3685 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3686 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3687 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3688 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3689 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3690 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3691 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3692 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3694 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3695 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3696 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3697 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3698 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3700 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3701 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3702 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3703 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3704 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3705 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3706 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3707 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3710 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3711 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3712 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3714 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3716 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3717 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3718 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3719 (ins x86memop:$src),
3720 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3722 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3726 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3727 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3729 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3730 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3732 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3733 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3734 EVEX_CD8<16, CD8VH>;
3735 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3736 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3737 EVEX_CD8<16, CD8VQ>;
3738 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3739 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3740 EVEX_CD8<32, CD8VH>;
3742 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3743 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3745 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3746 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3748 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3749 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3750 EVEX_CD8<16, CD8VH>;
3751 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3752 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3753 EVEX_CD8<16, CD8VQ>;
3754 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3755 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3756 EVEX_CD8<32, CD8VH>;
3758 //===----------------------------------------------------------------------===//
3759 // GATHER - SCATTER Operations
3761 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3762 RegisterClass RC, X86MemOperand memop> {
3764 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3765 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3766 (ins RC:$src1, KRC:$mask, memop:$src2),
3767 !strconcat(OpcodeStr,
3768 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3771 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3772 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3773 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3774 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3776 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3777 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3778 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3779 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3781 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3782 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3783 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3784 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3786 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3787 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3788 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3789 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3791 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3792 RegisterClass RC, X86MemOperand memop> {
3793 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3794 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3795 (ins memop:$dst, KRC:$mask, RC:$src2),
3796 !strconcat(OpcodeStr,
3797 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3801 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3802 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3803 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3804 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3806 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3807 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3808 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3809 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3811 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3812 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3813 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3814 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3816 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3817 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3818 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3819 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3821 //===----------------------------------------------------------------------===//
3822 // VSHUFPS - VSHUFPD Operations
3824 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3825 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3827 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3828 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3829 !strconcat(OpcodeStr,
3830 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3831 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3832 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3833 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3834 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3835 (ins RC:$src1, RC:$src2, i8imm:$src3),
3836 !strconcat(OpcodeStr,
3837 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3838 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3839 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3840 EVEX_4V, Sched<[WriteShuffle]>;
3843 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3844 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3845 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3846 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3848 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3849 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3850 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3851 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3852 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3854 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3855 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3856 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3857 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3858 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3860 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3861 X86MemOperand x86memop> {
3862 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3863 (ins RC:$src1, RC:$src2, i8imm:$src3),
3864 !strconcat(OpcodeStr,
3865 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3868 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3869 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3870 !strconcat(OpcodeStr,
3871 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3874 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3875 EVEX_V512, EVEX_CD8<32, CD8VF>;
3876 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3877 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3879 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3880 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3881 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3882 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3883 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3884 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3885 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3886 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3888 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3889 X86MemOperand x86memop> {
3890 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3891 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3893 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3894 (ins x86memop:$src),
3895 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3899 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3900 EVEX_CD8<32, CD8VF>;
3901 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3902 EVEX_CD8<64, CD8VF>;
3904 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3905 (v16i32 immAllZerosV), (i16 -1))),
3906 (VPABSDrr VR512:$src)>;
3907 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3908 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3909 (VPABSQrr VR512:$src)>;
3911 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3912 RegisterClass RC, RegisterClass KRC,
3913 X86MemOperand x86memop,
3914 X86MemOperand x86scalar_mop, string BrdcstStr> {
3915 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3917 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3919 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3920 (ins x86memop:$src),
3921 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3923 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3924 (ins x86scalar_mop:$src),
3925 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3926 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3928 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3929 (ins KRC:$mask, RC:$src),
3930 !strconcat(OpcodeStr,
3931 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3933 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3934 (ins KRC:$mask, x86memop:$src),
3935 !strconcat(OpcodeStr,
3936 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3938 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3939 (ins KRC:$mask, x86scalar_mop:$src),
3940 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3941 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3943 []>, EVEX, EVEX_KZ, EVEX_B;
3945 let Constraints = "$src1 = $dst" in {
3946 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3947 (ins RC:$src1, KRC:$mask, RC:$src2),
3948 !strconcat(OpcodeStr,
3949 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3951 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3952 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3953 !strconcat(OpcodeStr,
3954 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3956 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3957 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3958 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3959 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3960 []>, EVEX, EVEX_K, EVEX_B;
3964 let Predicates = [HasCDI] in {
3965 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3966 i512mem, i32mem, "{1to16}">,
3967 EVEX_V512, EVEX_CD8<32, CD8VF>;
3970 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3971 i512mem, i64mem, "{1to8}">,
3972 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3976 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3978 (VPCONFLICTDrrk VR512:$src1,
3979 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3981 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3983 (VPCONFLICTQrrk VR512:$src1,
3984 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;