1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 string VTName = "v" # NumElts # EltVT;
29 ValueType VT = !cast<ValueType>(VTName);
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
36 // "i" for integer types and "f" for floating-point types
37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
39 // Size of RC in bits, e.g. 512 for VR512.
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
95 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
97 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
99 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
102 // "x" in v32i8x_info means RC = VR256X
103 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
108 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
109 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
110 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
111 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
113 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
114 X86VectorVTInfo i128> {
115 X86VectorVTInfo info512 = i512;
116 X86VectorVTInfo info256 = i256;
117 X86VectorVTInfo info128 = i128;
120 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
122 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
124 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
126 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
129 // This multiclass generates the masking variants from the non-masking
130 // variant. It only provides the assembly pieces for the masking variants.
131 // It assumes custom ISel patterns for masking which can be provided as
132 // template arguments.
133 multiclass AVX512_maskable_custom<bits<8> O, Format F,
135 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
137 string AttSrcAsm, string IntelSrcAsm,
139 list<dag> MaskingPattern,
140 list<dag> ZeroMaskingPattern,
141 string MaskingConstraint = "",
142 InstrItinClass itin = NoItinerary,
143 bit IsCommutable = 0> {
144 let isCommutable = IsCommutable in
145 def NAME: AVX512<O, F, Outs, Ins,
146 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
147 "$dst, "#IntelSrcAsm#"}",
150 // Prefer over VMOV*rrk Pat<>
151 let AddedComplexity = 20 in
152 def NAME#k: AVX512<O, F, Outs, MaskingIns,
153 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
154 "$dst {${mask}}, "#IntelSrcAsm#"}",
155 MaskingPattern, itin>,
157 // In case of the 3src subclass this is overridden with a let.
158 string Constraints = MaskingConstraint;
160 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
161 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
163 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
170 // Common base class of AVX512_maskable and AVX512_maskable_3src.
171 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
173 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
175 string AttSrcAsm, string IntelSrcAsm,
176 dag RHS, dag MaskingRHS,
177 string MaskingConstraint = "",
178 InstrItinClass itin = NoItinerary,
179 bit IsCommutable = 0> :
180 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
181 AttSrcAsm, IntelSrcAsm,
182 [(set _.RC:$dst, RHS)],
183 [(set _.RC:$dst, MaskingRHS)],
185 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
186 MaskingConstraint, NoItinerary, IsCommutable>;
188 // This multiclass generates the unconditional/non-masking, the masking and
189 // the zero-masking variant of the instruction. In the masking case, the
190 // perserved vector elements come from a new dummy input operand tied to $dst.
191 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
192 dag Outs, dag Ins, string OpcodeStr,
193 string AttSrcAsm, string IntelSrcAsm,
194 dag RHS, InstrItinClass itin = NoItinerary,
195 bit IsCommutable = 0> :
196 AVX512_maskable_common<O, F, _, Outs, Ins,
197 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
198 !con((ins _.KRCWM:$mask), Ins),
199 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
200 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
201 "$src0 = $dst", itin, IsCommutable>;
203 // Similar to AVX512_maskable but in this case one of the source operands
204 // ($src1) is already tied to $dst so we just use that for the preserved
205 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
207 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
208 dag Outs, dag NonTiedIns, string OpcodeStr,
209 string AttSrcAsm, string IntelSrcAsm,
211 AVX512_maskable_common<O, F, _, Outs,
212 !con((ins _.RC:$src1), NonTiedIns),
213 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
214 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
215 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
216 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
219 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
222 string AttSrcAsm, string IntelSrcAsm,
224 AVX512_maskable_custom<O, F, Outs, Ins,
225 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
226 !con((ins _.KRCWM:$mask), Ins),
227 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
230 // Bitcasts between 512-bit vector types. Return the original type since
231 // no instruction is needed for the conversion
232 let Predicates = [HasAVX512] in {
233 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
234 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
235 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
236 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
237 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
238 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
239 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
240 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
241 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
242 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
243 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
244 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
245 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
246 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
247 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
248 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
249 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
250 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
251 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
252 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
253 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
254 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
255 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
256 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
257 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
258 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
259 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
260 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
261 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
262 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
263 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
265 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
266 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
267 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
268 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
269 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
270 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
271 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
272 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
273 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
274 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
275 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
276 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
277 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
278 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
279 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
280 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
281 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
282 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
283 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
284 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
285 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
286 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
287 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
288 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
289 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
290 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
291 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
292 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
293 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
294 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
296 // Bitcasts between 256-bit vector types. Return the original type since
297 // no instruction is needed for the conversion
298 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
299 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
300 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
301 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
302 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
303 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
304 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
305 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
306 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
307 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
308 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
309 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
310 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
311 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
312 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
313 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
314 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
315 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
316 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
317 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
318 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
319 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
320 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
321 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
322 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
323 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
324 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
325 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
326 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
327 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
331 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
334 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
335 isPseudo = 1, Predicates = [HasAVX512] in {
336 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
337 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
340 let Predicates = [HasAVX512] in {
341 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
342 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
343 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
346 //===----------------------------------------------------------------------===//
347 // AVX-512 - VECTOR INSERT
350 multiclass vinsert_for_size_no_alt<int Opcode,
351 X86VectorVTInfo From, X86VectorVTInfo To,
352 PatFrag vinsert_insert,
353 SDNodeXForm INSERT_get_vinsert_imm> {
354 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
355 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
356 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
357 "vinsert" # From.EltTypeName # "x" # From.NumElts #
358 "\t{$src3, $src2, $src1, $dst|"
359 "$dst, $src1, $src2, $src3}",
360 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
361 (From.VT From.RC:$src2),
366 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
367 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
368 "vinsert" # From.EltTypeName # "x" # From.NumElts #
369 "\t{$src3, $src2, $src1, $dst|"
370 "$dst, $src1, $src2, $src3}",
372 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
376 multiclass vinsert_for_size<int Opcode,
377 X86VectorVTInfo From, X86VectorVTInfo To,
378 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
379 PatFrag vinsert_insert,
380 SDNodeXForm INSERT_get_vinsert_imm> :
381 vinsert_for_size_no_alt<Opcode, From, To,
382 vinsert_insert, INSERT_get_vinsert_imm> {
383 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
384 // vinserti32x4. Only add this if 64x2 and friends are not supported
385 // natively via AVX512DQ.
386 let Predicates = [NoDQI] in
387 def : Pat<(vinsert_insert:$ins
388 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
389 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
390 VR512:$src1, From.RC:$src2,
391 (INSERT_get_vinsert_imm VR512:$ins)))>;
394 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
395 ValueType EltVT64, int Opcode256> {
396 defm NAME # "32x4" : vinsert_for_size<Opcode128,
397 X86VectorVTInfo< 4, EltVT32, VR128X>,
398 X86VectorVTInfo<16, EltVT32, VR512>,
399 X86VectorVTInfo< 2, EltVT64, VR128X>,
400 X86VectorVTInfo< 8, EltVT64, VR512>,
402 INSERT_get_vinsert128_imm>;
403 let Predicates = [HasDQI] in
404 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
405 X86VectorVTInfo< 2, EltVT64, VR128X>,
406 X86VectorVTInfo< 8, EltVT64, VR512>,
408 INSERT_get_vinsert128_imm>, VEX_W;
409 defm NAME # "64x4" : vinsert_for_size<Opcode256,
410 X86VectorVTInfo< 4, EltVT64, VR256X>,
411 X86VectorVTInfo< 8, EltVT64, VR512>,
412 X86VectorVTInfo< 8, EltVT32, VR256>,
413 X86VectorVTInfo<16, EltVT32, VR512>,
415 INSERT_get_vinsert256_imm>, VEX_W;
416 let Predicates = [HasDQI] in
417 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
418 X86VectorVTInfo< 8, EltVT32, VR256X>,
419 X86VectorVTInfo<16, EltVT32, VR512>,
421 INSERT_get_vinsert256_imm>;
424 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
425 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
427 // vinsertps - insert f32 to XMM
428 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
429 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
430 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
431 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
433 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
434 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
435 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
436 [(set VR128X:$dst, (X86insertps VR128X:$src1,
437 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
438 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
440 //===----------------------------------------------------------------------===//
441 // AVX-512 VECTOR EXTRACT
444 multiclass vextract_for_size<int Opcode,
445 X86VectorVTInfo From, X86VectorVTInfo To,
446 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
447 PatFrag vextract_extract,
448 SDNodeXForm EXTRACT_get_vextract_imm> {
449 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
450 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
451 (ins VR512:$src1, i8imm:$idx),
452 "vextract" # To.EltTypeName # "x4",
453 "$idx, $src1", "$src1, $idx",
454 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
456 AVX512AIi8Base, EVEX, EVEX_V512;
458 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
459 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
460 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
461 "$dst, $src1, $src2}",
462 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
465 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
467 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
468 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
470 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
472 // A 128/256-bit subvector extract from the first 512-bit vector position is
473 // a subregister copy that needs no instruction.
474 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
476 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
478 // And for the alternative types.
479 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
481 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
483 // Intrinsic call with masking.
484 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
486 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
487 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
488 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
489 VR512:$src1, imm:$idx)>;
491 // Intrinsic call with zero-masking.
492 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
494 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
495 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
496 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
497 VR512:$src1, imm:$idx)>;
499 // Intrinsic call without masking.
500 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
502 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
503 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
504 VR512:$src1, imm:$idx)>;
507 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
508 ValueType EltVT64, int Opcode64> {
509 defm NAME # "32x4" : vextract_for_size<Opcode32,
510 X86VectorVTInfo<16, EltVT32, VR512>,
511 X86VectorVTInfo< 4, EltVT32, VR128X>,
512 X86VectorVTInfo< 8, EltVT64, VR512>,
513 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 EXTRACT_get_vextract128_imm>;
516 defm NAME # "64x4" : vextract_for_size<Opcode64,
517 X86VectorVTInfo< 8, EltVT64, VR512>,
518 X86VectorVTInfo< 4, EltVT64, VR256X>,
519 X86VectorVTInfo<16, EltVT32, VR512>,
520 X86VectorVTInfo< 8, EltVT32, VR256>,
522 EXTRACT_get_vextract256_imm>, VEX_W;
525 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
526 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
528 // A 128-bit subvector insert to the first 512-bit vector position
529 // is a subregister copy that needs no instruction.
530 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
531 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
532 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
534 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
535 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
536 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
538 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
539 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
540 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
542 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
543 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
544 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
547 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
548 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
549 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
550 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
551 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
552 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
553 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
556 // vextractps - extract 32 bits from XMM
557 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
558 (ins VR128X:$src1, i32i8imm:$src2),
559 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
560 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
563 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
564 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
565 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
566 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
567 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
569 //===---------------------------------------------------------------------===//
572 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
573 RegisterClass DestRC,
574 RegisterClass SrcRC, X86MemOperand x86memop> {
575 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
578 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
579 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
581 let ExeDomain = SSEPackedSingle in {
582 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
584 EVEX_V512, EVEX_CD8<32, CD8VT1>;
587 let ExeDomain = SSEPackedDouble in {
588 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
590 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
593 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
594 (VBROADCASTSSZrm addr:$src)>;
595 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
596 (VBROADCASTSDZrm addr:$src)>;
598 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
599 (VBROADCASTSSZrm addr:$src)>;
600 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
601 (VBROADCASTSDZrm addr:$src)>;
603 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
604 RegisterClass SrcRC, RegisterClass KRC> {
605 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
606 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
607 []>, EVEX, EVEX_V512;
608 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
609 (ins KRC:$mask, SrcRC:$src),
610 !strconcat(OpcodeStr,
611 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
612 []>, EVEX, EVEX_V512, EVEX_KZ;
615 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
616 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
619 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
620 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
622 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
623 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
625 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
626 (VPBROADCASTDrZrr GR32:$src)>;
627 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
628 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
629 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
630 (VPBROADCASTQrZrr GR64:$src)>;
631 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
632 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
634 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
635 (VPBROADCASTDrZrr GR32:$src)>;
636 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
637 (VPBROADCASTQrZrr GR64:$src)>;
639 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
640 (v16i32 immAllZerosV), (i16 GR16:$mask))),
641 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
642 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
643 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
644 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
646 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
647 X86MemOperand x86memop, PatFrag ld_frag,
648 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
650 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
651 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
653 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
654 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
656 !strconcat(OpcodeStr,
657 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
659 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
662 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
663 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
665 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
666 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
668 !strconcat(OpcodeStr,
669 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
670 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
671 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
675 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
676 loadi32, VR512, v16i32, v4i32, VK16WM>,
677 EVEX_V512, EVEX_CD8<32, CD8VT1>;
678 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
679 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
680 EVEX_CD8<64, CD8VT1>;
682 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
683 X86MemOperand x86memop, PatFrag ld_frag,
686 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
687 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
689 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
691 !strconcat(OpcodeStr,
692 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
697 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
698 i128mem, loadv2i64, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
701 i256mem, loadv4i64, VK16WM>, VEX_W,
702 EVEX_V512, EVEX_CD8<64, CD8VT4>;
704 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
705 (VPBROADCASTDZrr VR128X:$src)>;
706 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
707 (VPBROADCASTQZrr VR128X:$src)>;
709 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
710 (VBROADCASTSSZrr VR128X:$src)>;
711 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
712 (VBROADCASTSDZrr VR128X:$src)>;
714 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
715 (VBROADCASTSSZrr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
716 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
717 (VBROADCASTSDZrr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
719 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
720 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
721 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
722 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
724 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
725 (VBROADCASTSSZrr VR128X:$src)>;
726 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
727 (VBROADCASTSDZrr VR128X:$src)>;
729 // Provide fallback in case the load node that is used in the patterns above
730 // is used by additional users, which prevents the pattern selection.
731 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
732 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
733 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
734 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
737 let Predicates = [HasAVX512] in {
738 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
740 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
741 addr:$src)), sub_ymm)>;
743 //===----------------------------------------------------------------------===//
744 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
747 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
749 let Predicates = [HasCDI] in
750 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
751 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
752 []>, EVEX, EVEX_V512;
754 let Predicates = [HasCDI, HasVLX] in {
755 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
756 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
757 []>, EVEX, EVEX_V128;
758 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
759 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
760 []>, EVEX, EVEX_V256;
764 let Predicates = [HasCDI] in {
765 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
767 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
771 //===----------------------------------------------------------------------===//
774 // -- immediate form --
775 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
777 let ExeDomain = _.ExeDomain in {
778 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
779 (ins _.RC:$src1, i8imm:$src2),
780 !strconcat(OpcodeStr,
781 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
783 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
785 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
786 (ins _.MemOp:$src1, i8imm:$src2),
787 !strconcat(OpcodeStr,
788 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
790 (_.VT (OpNode (_.MemOpFrag addr:$src1),
792 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
796 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
797 X86VectorVTInfo Ctrl> :
798 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
799 let ExeDomain = _.ExeDomain in {
800 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
801 (ins _.RC:$src1, _.RC:$src2),
802 !strconcat("vpermil" # _.Suffix,
803 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
805 (_.VT (X86VPermilpv _.RC:$src1,
806 (Ctrl.VT Ctrl.RC:$src2))))]>,
808 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
809 (ins _.RC:$src1, Ctrl.MemOp:$src2),
810 !strconcat("vpermil" # _.Suffix,
811 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
813 (_.VT (X86VPermilpv _.RC:$src1,
814 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
819 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
821 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
824 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
826 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
829 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
830 (VPERMILPSZri VR512:$src1, imm:$imm)>;
831 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
832 (VPERMILPDZri VR512:$src1, imm:$imm)>;
834 // -- VPERM - register form --
835 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
836 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
838 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
839 (ins RC:$src1, RC:$src2),
840 !strconcat(OpcodeStr,
841 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
843 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
845 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
846 (ins RC:$src1, x86memop:$src2),
847 !strconcat(OpcodeStr,
848 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
850 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
854 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
855 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
856 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
857 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
858 let ExeDomain = SSEPackedSingle in
859 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
860 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
861 let ExeDomain = SSEPackedDouble in
862 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
863 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
865 // -- VPERM2I - 3 source operands form --
866 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
867 PatFrag mem_frag, X86MemOperand x86memop,
868 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
869 let Constraints = "$src1 = $dst" in {
870 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
871 (ins RC:$src1, RC:$src2, RC:$src3),
872 !strconcat(OpcodeStr,
873 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
875 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
878 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
879 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
880 !strconcat(OpcodeStr,
881 " \t{$src3, $src2, $dst {${mask}}|"
882 "$dst {${mask}}, $src2, $src3}"),
883 [(set RC:$dst, (OpVT (vselect KRC:$mask,
884 (OpNode RC:$src1, RC:$src2,
889 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
890 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
891 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
892 !strconcat(OpcodeStr,
893 " \t{$src3, $src2, $dst {${mask}} {z} |",
894 "$dst {${mask}} {z}, $src2, $src3}"),
895 [(set RC:$dst, (OpVT (vselect KRC:$mask,
896 (OpNode RC:$src1, RC:$src2,
899 (v16i32 immAllZerosV))))))]>,
902 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
903 (ins RC:$src1, RC:$src2, x86memop:$src3),
904 !strconcat(OpcodeStr,
905 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
907 (OpVT (OpNode RC:$src1, RC:$src2,
908 (mem_frag addr:$src3))))]>, EVEX_4V;
910 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
911 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
912 !strconcat(OpcodeStr,
913 " \t{$src3, $src2, $dst {${mask}}|"
914 "$dst {${mask}}, $src2, $src3}"),
916 (OpVT (vselect KRC:$mask,
917 (OpNode RC:$src1, RC:$src2,
918 (mem_frag addr:$src3)),
922 let AddedComplexity = 10 in // Prefer over the rrkz variant
923 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
924 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
925 !strconcat(OpcodeStr,
926 " \t{$src3, $src2, $dst {${mask}} {z}|"
927 "$dst {${mask}} {z}, $src2, $src3}"),
929 (OpVT (vselect KRC:$mask,
930 (OpNode RC:$src1, RC:$src2,
931 (mem_frag addr:$src3)),
933 (v16i32 immAllZerosV))))))]>,
937 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
938 i512mem, X86VPermiv3, v16i32, VK16WM>,
939 EVEX_V512, EVEX_CD8<32, CD8VF>;
940 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
941 i512mem, X86VPermiv3, v8i64, VK8WM>,
942 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
943 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
944 i512mem, X86VPermiv3, v16f32, VK16WM>,
945 EVEX_V512, EVEX_CD8<32, CD8VF>;
946 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
947 i512mem, X86VPermiv3, v8f64, VK8WM>,
948 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
950 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
951 PatFrag mem_frag, X86MemOperand x86memop,
952 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
953 ValueType MaskVT, RegisterClass MRC> :
954 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
956 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
957 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
958 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
960 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
961 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
962 (!cast<Instruction>(NAME#rrk) VR512:$src1,
963 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
966 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
967 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
968 EVEX_V512, EVEX_CD8<32, CD8VF>;
969 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
970 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
971 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
972 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
973 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
974 EVEX_V512, EVEX_CD8<32, CD8VF>;
975 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
976 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
977 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
979 //===----------------------------------------------------------------------===//
980 // AVX-512 - BLEND using mask
982 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
983 RegisterClass KRC, RegisterClass RC,
984 X86MemOperand x86memop, PatFrag mem_frag,
985 SDNode OpNode, ValueType vt> {
986 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
987 (ins KRC:$mask, RC:$src1, RC:$src2),
988 !strconcat(OpcodeStr,
989 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
990 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
991 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
993 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
994 (ins KRC:$mask, RC:$src1, x86memop:$src2),
995 !strconcat(OpcodeStr,
996 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
997 []>, EVEX_4V, EVEX_K;
1000 let ExeDomain = SSEPackedSingle in
1001 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1002 VK16WM, VR512, f512mem,
1003 memopv16f32, vselect, v16f32>,
1004 EVEX_CD8<32, CD8VF>, EVEX_V512;
1005 let ExeDomain = SSEPackedDouble in
1006 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1007 VK8WM, VR512, f512mem,
1008 memopv8f64, vselect, v8f64>,
1009 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1011 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1012 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1013 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1014 VR512:$src1, VR512:$src2)>;
1016 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1017 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1018 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1019 VR512:$src1, VR512:$src2)>;
1021 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1022 VK16WM, VR512, f512mem,
1023 memopv16i32, vselect, v16i32>,
1024 EVEX_CD8<32, CD8VF>, EVEX_V512;
1026 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1027 VK8WM, VR512, f512mem,
1028 memopv8i64, vselect, v8i64>,
1029 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1031 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1032 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1033 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1034 VR512:$src1, VR512:$src2)>;
1036 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1037 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1038 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1039 VR512:$src1, VR512:$src2)>;
1041 let Predicates = [HasAVX512] in {
1042 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1043 (v8f32 VR256X:$src2))),
1045 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1046 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1047 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1049 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1050 (v8i32 VR256X:$src2))),
1052 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1053 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1054 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1056 //===----------------------------------------------------------------------===//
1057 // Compare Instructions
1058 //===----------------------------------------------------------------------===//
1060 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1061 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1062 Operand CC, SDNode OpNode, ValueType VT,
1063 PatFrag ld_frag, string asm, string asm_alt> {
1064 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1065 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1066 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1067 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1068 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1069 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1070 [(set VK1:$dst, (OpNode (VT RC:$src1),
1071 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1072 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1073 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1074 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1075 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1076 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1077 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1078 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1082 let Predicates = [HasAVX512] in {
1083 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1084 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1085 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1087 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1088 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1089 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1093 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1094 X86VectorVTInfo _> {
1095 def rr : AVX512BI<opc, MRMSrcReg,
1096 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1097 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1098 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1099 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1101 def rm : AVX512BI<opc, MRMSrcMem,
1102 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1104 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1105 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1106 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1107 def rrk : AVX512BI<opc, MRMSrcReg,
1108 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1109 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1110 "$dst {${mask}}, $src1, $src2}"),
1111 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1112 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1113 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1115 def rmk : AVX512BI<opc, MRMSrcMem,
1116 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1117 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1118 "$dst {${mask}}, $src1, $src2}"),
1119 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1120 (OpNode (_.VT _.RC:$src1),
1122 (_.LdFrag addr:$src2))))))],
1123 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1126 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1127 X86VectorVTInfo _> :
1128 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1129 let mayLoad = 1 in {
1130 def rmb : AVX512BI<opc, MRMSrcMem,
1131 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1132 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1133 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1134 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1135 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1136 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1137 def rmbk : AVX512BI<opc, MRMSrcMem,
1138 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1139 _.ScalarMemOp:$src2),
1140 !strconcat(OpcodeStr,
1141 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1142 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1143 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1144 (OpNode (_.VT _.RC:$src1),
1146 (_.ScalarLdFrag addr:$src2)))))],
1147 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1151 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1152 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1153 let Predicates = [prd] in
1154 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1157 let Predicates = [prd, HasVLX] in {
1158 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1160 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1165 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1166 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1168 let Predicates = [prd] in
1169 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1172 let Predicates = [prd, HasVLX] in {
1173 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1175 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1180 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1181 avx512vl_i8_info, HasBWI>,
1184 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1185 avx512vl_i16_info, HasBWI>,
1186 EVEX_CD8<16, CD8VF>;
1188 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1189 avx512vl_i32_info, HasAVX512>,
1190 EVEX_CD8<32, CD8VF>;
1192 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1193 avx512vl_i64_info, HasAVX512>,
1194 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1196 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1197 avx512vl_i8_info, HasBWI>,
1200 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1201 avx512vl_i16_info, HasBWI>,
1202 EVEX_CD8<16, CD8VF>;
1204 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1205 avx512vl_i32_info, HasAVX512>,
1206 EVEX_CD8<32, CD8VF>;
1208 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1209 avx512vl_i64_info, HasAVX512>,
1210 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1212 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1213 (COPY_TO_REGCLASS (VPCMPGTDZrr
1214 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1215 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1217 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1218 (COPY_TO_REGCLASS (VPCMPEQDZrr
1219 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1220 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1222 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1223 X86VectorVTInfo _> {
1224 def rri : AVX512AIi8<opc, MRMSrcReg,
1225 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1226 !strconcat("vpcmp${cc}", Suffix,
1227 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1228 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1230 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1232 def rmi : AVX512AIi8<opc, MRMSrcMem,
1233 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1234 !strconcat("vpcmp${cc}", Suffix,
1235 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1236 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1237 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1239 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1240 def rrik : AVX512AIi8<opc, MRMSrcReg,
1241 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1243 !strconcat("vpcmp${cc}", Suffix,
1244 "\t{$src2, $src1, $dst {${mask}}|",
1245 "$dst {${mask}}, $src1, $src2}"),
1246 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1247 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1249 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1251 def rmik : AVX512AIi8<opc, MRMSrcMem,
1252 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1254 !strconcat("vpcmp${cc}", Suffix,
1255 "\t{$src2, $src1, $dst {${mask}}|",
1256 "$dst {${mask}}, $src1, $src2}"),
1257 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1258 (OpNode (_.VT _.RC:$src1),
1259 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1261 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1263 // Accept explicit immediate argument form instead of comparison code.
1264 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1265 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1266 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1267 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1268 "$dst, $src1, $src2, $cc}"),
1269 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1270 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1271 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1272 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1273 "$dst, $src1, $src2, $cc}"),
1274 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1275 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1276 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1278 !strconcat("vpcmp", Suffix,
1279 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1280 "$dst {${mask}}, $src1, $src2, $cc}"),
1281 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1282 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1283 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1285 !strconcat("vpcmp", Suffix,
1286 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1287 "$dst {${mask}}, $src1, $src2, $cc}"),
1288 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1292 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1293 X86VectorVTInfo _> :
1294 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1295 let mayLoad = 1 in {
1296 def rmib : AVX512AIi8<opc, MRMSrcMem,
1297 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1299 !strconcat("vpcmp${cc}", Suffix,
1300 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1301 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1302 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1303 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1305 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1306 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1307 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1308 _.ScalarMemOp:$src2, AVXCC:$cc),
1309 !strconcat("vpcmp${cc}", Suffix,
1310 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1311 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1312 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1313 (OpNode (_.VT _.RC:$src1),
1314 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1316 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1319 // Accept explicit immediate argument form instead of comparison code.
1320 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1321 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1322 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1324 !strconcat("vpcmp", Suffix,
1325 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1326 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1327 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1328 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1329 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1330 _.ScalarMemOp:$src2, i8imm:$cc),
1331 !strconcat("vpcmp", Suffix,
1332 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1333 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1334 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1338 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1339 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1340 let Predicates = [prd] in
1341 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1343 let Predicates = [prd, HasVLX] in {
1344 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1345 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1349 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1350 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1351 let Predicates = [prd] in
1352 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1355 let Predicates = [prd, HasVLX] in {
1356 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1358 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1363 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1364 HasBWI>, EVEX_CD8<8, CD8VF>;
1365 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1366 HasBWI>, EVEX_CD8<8, CD8VF>;
1368 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1369 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1370 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1371 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1373 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1374 HasAVX512>, EVEX_CD8<32, CD8VF>;
1375 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1376 HasAVX512>, EVEX_CD8<32, CD8VF>;
1378 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1379 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1380 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1381 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1383 // avx512_cmp_packed - compare packed instructions
1384 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1385 X86MemOperand x86memop, ValueType vt,
1386 string suffix, Domain d> {
1387 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1388 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1389 !strconcat("vcmp${cc}", suffix,
1390 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1391 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1392 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1393 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1394 !strconcat("vcmp${cc}", suffix,
1395 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1397 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1398 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1399 !strconcat("vcmp${cc}", suffix,
1400 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1402 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1404 // Accept explicit immediate argument form instead of comparison code.
1405 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1406 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1407 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1408 !strconcat("vcmp", suffix,
1409 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1410 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1411 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1412 !strconcat("vcmp", suffix,
1413 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1417 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1418 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1419 EVEX_CD8<32, CD8VF>;
1420 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1421 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1422 EVEX_CD8<64, CD8VF>;
1424 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1425 (COPY_TO_REGCLASS (VCMPPSZrri
1426 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1427 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1429 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1430 (COPY_TO_REGCLASS (VPCMPDZrri
1431 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1432 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1434 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1435 (COPY_TO_REGCLASS (VPCMPUDZrri
1436 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1437 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1440 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1441 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1443 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1444 (I8Imm imm:$cc)), GR16)>;
1446 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1447 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1449 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1450 (I8Imm imm:$cc)), GR8)>;
1452 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1453 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1455 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1456 (I8Imm imm:$cc)), GR16)>;
1458 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1459 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1461 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1462 (I8Imm imm:$cc)), GR8)>;
1464 // Mask register copy, including
1465 // - copy between mask registers
1466 // - load/store mask registers
1467 // - copy from GPR to mask register and vice versa
1469 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1470 string OpcodeStr, RegisterClass KRC,
1471 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1472 let hasSideEffects = 0 in {
1473 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1474 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1476 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1477 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1478 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1480 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1481 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1485 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1487 RegisterClass KRC, RegisterClass GRC> {
1488 let hasSideEffects = 0 in {
1489 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1490 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1491 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1492 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1496 let Predicates = [HasDQI] in
1497 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1499 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1502 let Predicates = [HasAVX512] in
1503 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1505 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1508 let Predicates = [HasBWI] in {
1509 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1510 i32mem>, VEX, PD, VEX_W;
1511 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1515 let Predicates = [HasBWI] in {
1516 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1517 i64mem>, VEX, PS, VEX_W;
1518 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1522 // GR from/to mask register
1523 let Predicates = [HasDQI] in {
1524 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1525 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1526 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1527 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1529 let Predicates = [HasAVX512] in {
1530 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1531 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1532 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1533 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1535 let Predicates = [HasBWI] in {
1536 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1537 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1539 let Predicates = [HasBWI] in {
1540 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1541 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1545 let Predicates = [HasDQI] in {
1546 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1547 (KMOVBmk addr:$dst, VK8:$src)>;
1549 let Predicates = [HasAVX512] in {
1550 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1551 (KMOVWmk addr:$dst, VK16:$src)>;
1552 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1553 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1554 def : Pat<(i1 (load addr:$src)),
1555 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1556 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1557 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1559 let Predicates = [HasBWI] in {
1560 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1561 (KMOVDmk addr:$dst, VK32:$src)>;
1563 let Predicates = [HasBWI] in {
1564 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1565 (KMOVQmk addr:$dst, VK64:$src)>;
1568 let Predicates = [HasAVX512] in {
1569 def : Pat<(i1 (trunc (i64 GR64:$src))),
1570 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1573 def : Pat<(i1 (trunc (i32 GR32:$src))),
1574 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1576 def : Pat<(i1 (trunc (i8 GR8:$src))),
1578 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1580 def : Pat<(i1 (trunc (i16 GR16:$src))),
1582 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1585 def : Pat<(i32 (zext VK1:$src)),
1586 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1587 def : Pat<(i8 (zext VK1:$src)),
1590 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1591 def : Pat<(i64 (zext VK1:$src)),
1592 (AND64ri8 (SUBREG_TO_REG (i64 0),
1593 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1594 def : Pat<(i16 (zext VK1:$src)),
1596 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1598 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1599 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1600 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1601 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1603 let Predicates = [HasBWI] in {
1604 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1605 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1606 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1607 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1611 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1612 let Predicates = [HasAVX512] in {
1613 // GR from/to 8-bit mask without native support
1614 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1616 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1618 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1620 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1623 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1624 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1625 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1626 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1628 let Predicates = [HasBWI] in {
1629 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1630 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1631 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1632 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1635 // Mask unary operation
1637 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1638 RegisterClass KRC, SDPatternOperator OpNode,
1640 let Predicates = [prd] in
1641 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1642 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1643 [(set KRC:$dst, (OpNode KRC:$src))]>;
1646 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1647 SDPatternOperator OpNode> {
1648 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1650 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1651 HasAVX512>, VEX, PS;
1652 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1653 HasBWI>, VEX, PD, VEX_W;
1654 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1655 HasBWI>, VEX, PS, VEX_W;
1658 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1660 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1661 let Predicates = [HasAVX512] in
1662 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1664 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1665 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1667 defm : avx512_mask_unop_int<"knot", "KNOT">;
1669 let Predicates = [HasDQI] in
1670 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1671 let Predicates = [HasAVX512] in
1672 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1673 let Predicates = [HasBWI] in
1674 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1675 let Predicates = [HasBWI] in
1676 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1678 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1679 let Predicates = [HasAVX512] in {
1680 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1681 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1683 def : Pat<(not VK8:$src),
1685 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1688 // Mask binary operation
1689 // - KAND, KANDN, KOR, KXNOR, KXOR
1690 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1691 RegisterClass KRC, SDPatternOperator OpNode,
1693 let Predicates = [prd] in
1694 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1695 !strconcat(OpcodeStr,
1696 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1697 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1700 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1701 SDPatternOperator OpNode> {
1702 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1703 HasDQI>, VEX_4V, VEX_L, PD;
1704 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1705 HasAVX512>, VEX_4V, VEX_L, PS;
1706 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1707 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1708 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1709 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1712 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1713 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1715 let isCommutable = 1 in {
1716 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1717 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1718 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1719 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1721 let isCommutable = 0 in
1722 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1724 def : Pat<(xor VK1:$src1, VK1:$src2),
1725 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1726 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1728 def : Pat<(or VK1:$src1, VK1:$src2),
1729 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1730 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1732 def : Pat<(and VK1:$src1, VK1:$src2),
1733 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1734 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1736 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1737 let Predicates = [HasAVX512] in
1738 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1739 (i16 GR16:$src1), (i16 GR16:$src2)),
1740 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1741 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1742 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1745 defm : avx512_mask_binop_int<"kand", "KAND">;
1746 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1747 defm : avx512_mask_binop_int<"kor", "KOR">;
1748 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1749 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1751 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1752 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1753 let Predicates = [HasAVX512] in
1754 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1756 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1757 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1760 defm : avx512_binop_pat<and, KANDWrr>;
1761 defm : avx512_binop_pat<andn, KANDNWrr>;
1762 defm : avx512_binop_pat<or, KORWrr>;
1763 defm : avx512_binop_pat<xnor, KXNORWrr>;
1764 defm : avx512_binop_pat<xor, KXORWrr>;
1767 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1768 RegisterClass KRC> {
1769 let Predicates = [HasAVX512] in
1770 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1771 !strconcat(OpcodeStr,
1772 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1775 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1776 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1780 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1781 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1782 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1783 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1786 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1787 let Predicates = [HasAVX512] in
1788 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1789 (i16 GR16:$src1), (i16 GR16:$src2)),
1790 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1791 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1792 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1794 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1797 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1799 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1800 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1801 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1802 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1805 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1806 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1810 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1812 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1813 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1814 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1817 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1819 let Predicates = [HasAVX512] in
1820 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1821 !strconcat(OpcodeStr,
1822 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1823 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1826 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1828 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1832 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1833 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1835 // Mask setting all 0s or 1s
1836 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1837 let Predicates = [HasAVX512] in
1838 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1839 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1840 [(set KRC:$dst, (VT Val))]>;
1843 multiclass avx512_mask_setop_w<PatFrag Val> {
1844 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1845 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1848 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1849 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1851 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1852 let Predicates = [HasAVX512] in {
1853 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1854 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1855 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1856 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1857 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1859 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1860 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1862 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1863 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1865 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1866 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1868 let Predicates = [HasVLX] in {
1869 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1870 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1871 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1872 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1873 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1874 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1875 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1876 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1879 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1880 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1882 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1883 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1884 //===----------------------------------------------------------------------===//
1885 // AVX-512 - Aligned and unaligned load and store
1888 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1889 RegisterClass KRC, RegisterClass RC,
1890 ValueType vt, ValueType zvt, X86MemOperand memop,
1891 Domain d, bit IsReMaterializable = 1> {
1892 let hasSideEffects = 0 in {
1893 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1894 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1896 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1897 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1898 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1900 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1901 SchedRW = [WriteLoad] in
1902 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1903 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1904 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1907 let AddedComplexity = 20 in {
1908 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1909 let hasSideEffects = 0 in
1910 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1911 (ins RC:$src0, KRC:$mask, RC:$src1),
1912 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1913 "${dst} {${mask}}, $src1}"),
1914 [(set RC:$dst, (vt (vselect KRC:$mask,
1918 let mayLoad = 1, SchedRW = [WriteLoad] in
1919 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1920 (ins RC:$src0, KRC:$mask, memop:$src1),
1921 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1922 "${dst} {${mask}}, $src1}"),
1925 (vt (bitconvert (ld_frag addr:$src1))),
1929 let mayLoad = 1, SchedRW = [WriteLoad] in
1930 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1931 (ins KRC:$mask, memop:$src),
1932 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1933 "${dst} {${mask}} {z}, $src}"),
1936 (vt (bitconvert (ld_frag addr:$src))),
1937 (vt (bitconvert (zvt immAllZerosV))))))],
1942 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1943 string elty, string elsz, string vsz512,
1944 string vsz256, string vsz128, Domain d,
1945 Predicate prd, bit IsReMaterializable = 1> {
1946 let Predicates = [prd] in
1947 defm Z : avx512_load<opc, OpcodeStr,
1948 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1949 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1950 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1951 !cast<X86MemOperand>(elty##"512mem"), d,
1952 IsReMaterializable>, EVEX_V512;
1954 let Predicates = [prd, HasVLX] in {
1955 defm Z256 : avx512_load<opc, OpcodeStr,
1956 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1957 "v"##vsz256##elty##elsz, "v4i64")),
1958 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1959 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1960 !cast<X86MemOperand>(elty##"256mem"), d,
1961 IsReMaterializable>, EVEX_V256;
1963 defm Z128 : avx512_load<opc, OpcodeStr,
1964 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1965 "v"##vsz128##elty##elsz, "v2i64")),
1966 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1967 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1968 !cast<X86MemOperand>(elty##"128mem"), d,
1969 IsReMaterializable>, EVEX_V128;
1974 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1975 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1976 X86MemOperand memop, Domain d> {
1977 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1978 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1981 let Constraints = "$src1 = $dst" in
1982 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1983 (ins RC:$src1, KRC:$mask, RC:$src2),
1984 !strconcat(OpcodeStr,
1985 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1987 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1988 (ins KRC:$mask, RC:$src),
1989 !strconcat(OpcodeStr,
1990 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1991 [], d>, EVEX, EVEX_KZ;
1993 let mayStore = 1 in {
1994 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1996 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1997 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1998 (ins memop:$dst, KRC:$mask, RC:$src),
1999 !strconcat(OpcodeStr,
2000 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2001 [], d>, EVEX, EVEX_K;
2006 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2007 string st_suff_512, string st_suff_256,
2008 string st_suff_128, string elty, string elsz,
2009 string vsz512, string vsz256, string vsz128,
2010 Domain d, Predicate prd> {
2011 let Predicates = [prd] in
2012 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2013 !cast<ValueType>("v"##vsz512##elty##elsz),
2014 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2015 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2017 let Predicates = [prd, HasVLX] in {
2018 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2019 !cast<ValueType>("v"##vsz256##elty##elsz),
2020 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2021 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2023 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2024 !cast<ValueType>("v"##vsz128##elty##elsz),
2025 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2026 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2030 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2031 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2032 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2033 "512", "256", "", "f", "32", "16", "8", "4",
2034 SSEPackedSingle, HasAVX512>,
2035 PS, EVEX_CD8<32, CD8VF>;
2037 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2038 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2039 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2040 "512", "256", "", "f", "64", "8", "4", "2",
2041 SSEPackedDouble, HasAVX512>,
2042 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2044 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2045 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2046 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2047 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2048 PS, EVEX_CD8<32, CD8VF>;
2050 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2051 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2052 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2053 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2054 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2056 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2057 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2058 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2060 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2061 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2062 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2064 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2066 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2068 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2070 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2073 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2074 "16", "8", "4", SSEPackedInt, HasAVX512>,
2075 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2076 "512", "256", "", "i", "32", "16", "8", "4",
2077 SSEPackedInt, HasAVX512>,
2078 PD, EVEX_CD8<32, CD8VF>;
2080 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2081 "8", "4", "2", SSEPackedInt, HasAVX512>,
2082 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2083 "512", "256", "", "i", "64", "8", "4", "2",
2084 SSEPackedInt, HasAVX512>,
2085 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2087 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2088 "64", "32", "16", SSEPackedInt, HasBWI>,
2089 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2090 "i", "8", "64", "32", "16", SSEPackedInt,
2091 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2093 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2094 "32", "16", "8", SSEPackedInt, HasBWI>,
2095 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2096 "i", "16", "32", "16", "8", SSEPackedInt,
2097 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2099 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2100 "16", "8", "4", SSEPackedInt, HasAVX512>,
2101 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2102 "i", "32", "16", "8", "4", SSEPackedInt,
2103 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2105 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2106 "8", "4", "2", SSEPackedInt, HasAVX512>,
2107 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2108 "i", "64", "8", "4", "2", SSEPackedInt,
2109 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2111 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2112 (v16i32 immAllZerosV), GR16:$mask)),
2113 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2115 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2116 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2117 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2119 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2121 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2123 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2125 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2128 let AddedComplexity = 20 in {
2129 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2130 (bc_v8i64 (v16i32 immAllZerosV)))),
2131 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2133 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2134 (v8i64 VR512:$src))),
2135 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2138 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2139 (v16i32 immAllZerosV))),
2140 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2142 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2143 (v16i32 VR512:$src))),
2144 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2147 // Move Int Doubleword to Packed Double Int
2149 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2150 "vmovd\t{$src, $dst|$dst, $src}",
2152 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2154 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2155 "vmovd\t{$src, $dst|$dst, $src}",
2157 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2158 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2159 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2160 "vmovq\t{$src, $dst|$dst, $src}",
2162 (v2i64 (scalar_to_vector GR64:$src)))],
2163 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2164 let isCodeGenOnly = 1 in {
2165 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2166 "vmovq\t{$src, $dst|$dst, $src}",
2167 [(set FR64:$dst, (bitconvert GR64:$src))],
2168 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2169 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2170 "vmovq\t{$src, $dst|$dst, $src}",
2171 [(set GR64:$dst, (bitconvert FR64:$src))],
2172 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2174 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2175 "vmovq\t{$src, $dst|$dst, $src}",
2176 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2177 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2178 EVEX_CD8<64, CD8VT1>;
2180 // Move Int Doubleword to Single Scalar
2182 let isCodeGenOnly = 1 in {
2183 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2184 "vmovd\t{$src, $dst|$dst, $src}",
2185 [(set FR32X:$dst, (bitconvert GR32:$src))],
2186 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2188 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2189 "vmovd\t{$src, $dst|$dst, $src}",
2190 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2191 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2194 // Move doubleword from xmm register to r/m32
2196 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2197 "vmovd\t{$src, $dst|$dst, $src}",
2198 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2199 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2201 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2202 (ins i32mem:$dst, VR128X:$src),
2203 "vmovd\t{$src, $dst|$dst, $src}",
2204 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2205 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2206 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2208 // Move quadword from xmm1 register to r/m64
2210 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2211 "vmovq\t{$src, $dst|$dst, $src}",
2212 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2214 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2215 Requires<[HasAVX512, In64BitMode]>;
2217 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2218 (ins i64mem:$dst, VR128X:$src),
2219 "vmovq\t{$src, $dst|$dst, $src}",
2220 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2221 addr:$dst)], IIC_SSE_MOVDQ>,
2222 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2223 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2225 // Move Scalar Single to Double Int
2227 let isCodeGenOnly = 1 in {
2228 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2230 "vmovd\t{$src, $dst|$dst, $src}",
2231 [(set GR32:$dst, (bitconvert FR32X:$src))],
2232 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2233 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2234 (ins i32mem:$dst, FR32X:$src),
2235 "vmovd\t{$src, $dst|$dst, $src}",
2236 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2237 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2240 // Move Quadword Int to Packed Quadword Int
2242 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2244 "vmovq\t{$src, $dst|$dst, $src}",
2246 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2247 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2249 //===----------------------------------------------------------------------===//
2250 // AVX-512 MOVSS, MOVSD
2251 //===----------------------------------------------------------------------===//
2253 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2254 SDNode OpNode, ValueType vt,
2255 X86MemOperand x86memop, PatFrag mem_pat> {
2256 let hasSideEffects = 0 in {
2257 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2258 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2259 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2260 (scalar_to_vector RC:$src2))))],
2261 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2262 let Constraints = "$src1 = $dst" in
2263 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2264 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2266 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2267 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2268 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2269 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2270 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2272 let mayStore = 1 in {
2273 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2274 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2275 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2277 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2278 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2279 [], IIC_SSE_MOV_S_MR>,
2280 EVEX, VEX_LIG, EVEX_K;
2282 } //hasSideEffects = 0
2285 let ExeDomain = SSEPackedSingle in
2286 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2287 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2289 let ExeDomain = SSEPackedDouble in
2290 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2291 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2293 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2294 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2295 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2297 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2298 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2299 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2301 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2302 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2303 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2305 // For the disassembler
2306 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2307 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2308 (ins VR128X:$src1, FR32X:$src2),
2309 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2311 XS, EVEX_4V, VEX_LIG;
2312 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2313 (ins VR128X:$src1, FR64X:$src2),
2314 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2316 XD, EVEX_4V, VEX_LIG, VEX_W;
2319 let Predicates = [HasAVX512] in {
2320 let AddedComplexity = 15 in {
2321 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2322 // MOVS{S,D} to the lower bits.
2323 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2324 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2325 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2326 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2327 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2328 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2329 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2330 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2332 // Move low f32 and clear high bits.
2333 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2334 (SUBREG_TO_REG (i32 0),
2335 (VMOVSSZrr (v4f32 (V_SET0)),
2336 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2337 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2338 (SUBREG_TO_REG (i32 0),
2339 (VMOVSSZrr (v4i32 (V_SET0)),
2340 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2343 let AddedComplexity = 20 in {
2344 // MOVSSrm zeros the high parts of the register; represent this
2345 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2346 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2347 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2348 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2349 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2350 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2351 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2353 // MOVSDrm zeros the high parts of the register; represent this
2354 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2355 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2356 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2357 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2358 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2359 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2360 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2361 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2362 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2363 def : Pat<(v2f64 (X86vzload addr:$src)),
2364 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2366 // Represent the same patterns above but in the form they appear for
2368 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2369 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2370 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2371 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2372 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2373 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2374 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2375 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2376 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2378 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2379 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2380 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2381 FR32X:$src)), sub_xmm)>;
2382 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2383 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2384 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2385 FR64X:$src)), sub_xmm)>;
2386 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2387 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2388 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2390 // Move low f64 and clear high bits.
2391 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2392 (SUBREG_TO_REG (i32 0),
2393 (VMOVSDZrr (v2f64 (V_SET0)),
2394 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2396 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2397 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2398 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2400 // Extract and store.
2401 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2403 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2404 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2406 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2408 // Shuffle with VMOVSS
2409 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2410 (VMOVSSZrr (v4i32 VR128X:$src1),
2411 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2412 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2413 (VMOVSSZrr (v4f32 VR128X:$src1),
2414 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2417 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2418 (SUBREG_TO_REG (i32 0),
2419 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2420 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2422 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2423 (SUBREG_TO_REG (i32 0),
2424 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2425 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2428 // Shuffle with VMOVSD
2429 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2430 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2431 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2432 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2433 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2434 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2435 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2436 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2439 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2440 (SUBREG_TO_REG (i32 0),
2441 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2442 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2444 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2445 (SUBREG_TO_REG (i32 0),
2446 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2447 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2450 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2451 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2452 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2453 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2454 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2455 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2456 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2457 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2460 let AddedComplexity = 15 in
2461 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2463 "vmovq\t{$src, $dst|$dst, $src}",
2464 [(set VR128X:$dst, (v2i64 (X86vzmovl
2465 (v2i64 VR128X:$src))))],
2466 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2468 let AddedComplexity = 20 in
2469 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2471 "vmovq\t{$src, $dst|$dst, $src}",
2472 [(set VR128X:$dst, (v2i64 (X86vzmovl
2473 (loadv2i64 addr:$src))))],
2474 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2475 EVEX_CD8<8, CD8VT8>;
2477 let Predicates = [HasAVX512] in {
2478 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2479 let AddedComplexity = 20 in {
2480 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2481 (VMOVDI2PDIZrm addr:$src)>;
2482 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2483 (VMOV64toPQIZrr GR64:$src)>;
2484 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2485 (VMOVDI2PDIZrr GR32:$src)>;
2487 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2488 (VMOVDI2PDIZrm addr:$src)>;
2489 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2490 (VMOVDI2PDIZrm addr:$src)>;
2491 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2492 (VMOVZPQILo2PQIZrm addr:$src)>;
2493 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2494 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2495 def : Pat<(v2i64 (X86vzload addr:$src)),
2496 (VMOVZPQILo2PQIZrm addr:$src)>;
2499 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2500 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2501 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2502 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2503 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2504 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2505 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2508 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2509 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2511 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2512 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2514 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2515 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2517 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2518 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2520 //===----------------------------------------------------------------------===//
2521 // AVX-512 - Non-temporals
2522 //===----------------------------------------------------------------------===//
2523 let SchedRW = [WriteLoad] in {
2524 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2525 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2526 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2527 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2528 EVEX_CD8<64, CD8VF>;
2530 let Predicates = [HasAVX512, HasVLX] in {
2531 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2533 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2534 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2535 EVEX_CD8<64, CD8VF>;
2537 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2539 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2540 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2541 EVEX_CD8<64, CD8VF>;
2545 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2546 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2547 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2548 let SchedRW = [WriteStore], mayStore = 1,
2549 AddedComplexity = 400 in
2550 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2551 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2552 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2555 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2556 string elty, string elsz, string vsz512,
2557 string vsz256, string vsz128, Domain d,
2558 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2559 let Predicates = [prd] in
2560 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2561 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2562 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2565 let Predicates = [prd, HasVLX] in {
2566 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2567 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2568 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2571 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2572 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2573 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2578 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2579 "i", "64", "8", "4", "2", SSEPackedInt,
2580 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2582 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2583 "f", "64", "8", "4", "2", SSEPackedDouble,
2584 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2586 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2587 "f", "32", "16", "8", "4", SSEPackedSingle,
2588 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2590 //===----------------------------------------------------------------------===//
2591 // AVX-512 - Integer arithmetic
2593 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2594 X86VectorVTInfo _, OpndItins itins,
2595 bit IsCommutable = 0> {
2596 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2597 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2598 "$src2, $src1", "$src1, $src2",
2599 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2600 itins.rr, IsCommutable>,
2601 AVX512BIBase, EVEX_4V;
2604 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2605 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2606 "$src2, $src1", "$src1, $src2",
2607 (_.VT (OpNode _.RC:$src1,
2608 (bitconvert (_.LdFrag addr:$src2)))),
2610 AVX512BIBase, EVEX_4V;
2613 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2614 X86VectorVTInfo _, OpndItins itins,
2615 bit IsCommutable = 0> :
2616 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2618 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2619 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2620 "${src2}"##_.BroadcastStr##", $src1",
2621 "$src1, ${src2}"##_.BroadcastStr,
2622 (_.VT (OpNode _.RC:$src1,
2624 (_.ScalarLdFrag addr:$src2)))),
2626 AVX512BIBase, EVEX_4V, EVEX_B;
2629 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2630 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2631 Predicate prd, bit IsCommutable = 0> {
2632 let Predicates = [prd] in
2633 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2634 IsCommutable>, EVEX_V512;
2636 let Predicates = [prd, HasVLX] in {
2637 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2638 IsCommutable>, EVEX_V256;
2639 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2640 IsCommutable>, EVEX_V128;
2644 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2645 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2646 Predicate prd, bit IsCommutable = 0> {
2647 let Predicates = [prd] in
2648 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2649 IsCommutable>, EVEX_V512;
2651 let Predicates = [prd, HasVLX] in {
2652 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2653 IsCommutable>, EVEX_V256;
2654 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2655 IsCommutable>, EVEX_V128;
2659 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2660 OpndItins itins, Predicate prd,
2661 bit IsCommutable = 0> {
2662 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2663 itins, prd, IsCommutable>,
2664 VEX_W, EVEX_CD8<64, CD8VF>;
2667 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2668 OpndItins itins, Predicate prd,
2669 bit IsCommutable = 0> {
2670 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2671 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2674 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2675 OpndItins itins, Predicate prd,
2676 bit IsCommutable = 0> {
2677 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2678 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2681 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2682 OpndItins itins, Predicate prd,
2683 bit IsCommutable = 0> {
2684 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2685 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2688 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2689 SDNode OpNode, OpndItins itins, Predicate prd,
2690 bit IsCommutable = 0> {
2691 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2694 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2698 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2699 SDNode OpNode, OpndItins itins, Predicate prd,
2700 bit IsCommutable = 0> {
2701 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2704 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2708 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2709 bits<8> opc_d, bits<8> opc_q,
2710 string OpcodeStr, SDNode OpNode,
2711 OpndItins itins, bit IsCommutable = 0> {
2712 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2713 itins, HasAVX512, IsCommutable>,
2714 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2715 itins, HasBWI, IsCommutable>;
2718 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2719 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2720 PatFrag memop_frag, X86MemOperand x86memop,
2721 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2722 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2723 let isCommutable = IsCommutable in
2725 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2726 (ins RC:$src1, RC:$src2),
2727 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2729 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2730 (ins KRC:$mask, RC:$src1, RC:$src2),
2731 !strconcat(OpcodeStr,
2732 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2733 [], itins.rr>, EVEX_4V, EVEX_K;
2734 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2735 (ins KRC:$mask, RC:$src1, RC:$src2),
2736 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2737 "|$dst {${mask}} {z}, $src1, $src2}"),
2738 [], itins.rr>, EVEX_4V, EVEX_KZ;
2740 let mayLoad = 1 in {
2741 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2742 (ins RC:$src1, x86memop:$src2),
2743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2745 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2746 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2747 !strconcat(OpcodeStr,
2748 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2749 [], itins.rm>, EVEX_4V, EVEX_K;
2750 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2751 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2752 !strconcat(OpcodeStr,
2753 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2754 [], itins.rm>, EVEX_4V, EVEX_KZ;
2755 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2756 (ins RC:$src1, x86scalar_mop:$src2),
2757 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2758 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2759 [], itins.rm>, EVEX_4V, EVEX_B;
2760 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2761 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2762 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2763 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2765 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2766 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2767 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2768 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2769 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2771 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2775 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2776 SSE_INTALU_ITINS_P, 1>;
2777 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2778 SSE_INTALU_ITINS_P, 0>;
2779 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2780 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2781 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2782 SSE_INTALU_ITINS_P, HasBWI, 1>;
2783 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2784 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2786 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2787 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2788 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2789 EVEX_CD8<64, CD8VF>, VEX_W;
2791 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2792 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2793 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2795 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2796 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2798 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2799 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2800 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2801 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2802 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2803 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2805 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2806 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2807 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2808 SSE_INTALU_ITINS_P, HasBWI, 1>;
2809 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2810 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2812 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2813 SSE_INTALU_ITINS_P, HasBWI, 1>;
2814 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2815 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2816 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2817 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2819 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2820 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2821 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2822 SSE_INTALU_ITINS_P, HasBWI, 1>;
2823 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2824 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2826 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2827 SSE_INTALU_ITINS_P, HasBWI, 1>;
2828 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2829 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2830 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2831 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2833 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2834 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2835 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2836 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2837 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2838 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2839 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2840 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2841 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2842 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2843 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2844 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2845 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2846 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2847 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2848 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2849 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2850 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2851 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2852 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2853 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2854 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2855 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2856 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2857 //===----------------------------------------------------------------------===//
2858 // AVX-512 - Unpack Instructions
2859 //===----------------------------------------------------------------------===//
2861 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2862 PatFrag mem_frag, RegisterClass RC,
2863 X86MemOperand x86memop, string asm,
2865 def rr : AVX512PI<opc, MRMSrcReg,
2866 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2868 (vt (OpNode RC:$src1, RC:$src2)))],
2870 def rm : AVX512PI<opc, MRMSrcMem,
2871 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2873 (vt (OpNode RC:$src1,
2874 (bitconvert (mem_frag addr:$src2)))))],
2878 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2879 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2880 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2881 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2882 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2883 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2884 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2885 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2886 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2887 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2888 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2889 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2891 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2892 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2893 X86MemOperand x86memop> {
2894 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2895 (ins RC:$src1, RC:$src2),
2896 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2897 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2898 IIC_SSE_UNPCK>, EVEX_4V;
2899 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2900 (ins RC:$src1, x86memop:$src2),
2901 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2902 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2903 (bitconvert (memop_frag addr:$src2)))))],
2904 IIC_SSE_UNPCK>, EVEX_4V;
2906 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2907 VR512, memopv16i32, i512mem>, EVEX_V512,
2908 EVEX_CD8<32, CD8VF>;
2909 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2910 VR512, memopv8i64, i512mem>, EVEX_V512,
2911 VEX_W, EVEX_CD8<64, CD8VF>;
2912 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2913 VR512, memopv16i32, i512mem>, EVEX_V512,
2914 EVEX_CD8<32, CD8VF>;
2915 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2916 VR512, memopv8i64, i512mem>, EVEX_V512,
2917 VEX_W, EVEX_CD8<64, CD8VF>;
2918 //===----------------------------------------------------------------------===//
2922 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2923 SDNode OpNode, PatFrag mem_frag,
2924 X86MemOperand x86memop, ValueType OpVT> {
2925 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2926 (ins RC:$src1, i8imm:$src2),
2927 !strconcat(OpcodeStr,
2928 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2930 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2932 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2933 (ins x86memop:$src1, i8imm:$src2),
2934 !strconcat(OpcodeStr,
2935 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2937 (OpVT (OpNode (mem_frag addr:$src1),
2938 (i8 imm:$src2))))]>, EVEX;
2941 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2942 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2944 //===----------------------------------------------------------------------===//
2945 // AVX-512 Logical Instructions
2946 //===----------------------------------------------------------------------===//
2948 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2949 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2950 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2951 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2952 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2953 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2954 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2955 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2957 //===----------------------------------------------------------------------===//
2958 // AVX-512 FP arithmetic
2959 //===----------------------------------------------------------------------===//
2961 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2963 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2964 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2965 EVEX_CD8<32, CD8VT1>;
2966 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2967 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2968 EVEX_CD8<64, CD8VT1>;
2971 let isCommutable = 1 in {
2972 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2973 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2974 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2975 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2977 let isCommutable = 0 in {
2978 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2979 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2982 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2984 RegisterClass RC, ValueType vt,
2985 X86MemOperand x86memop, PatFrag mem_frag,
2986 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2988 Domain d, OpndItins itins, bit commutable> {
2989 let isCommutable = commutable in {
2990 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2991 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2992 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2995 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2996 !strconcat(OpcodeStr,
2997 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2998 [], itins.rr, d>, EVEX_4V, EVEX_K;
3000 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
3001 !strconcat(OpcodeStr,
3002 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3003 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
3006 let mayLoad = 1 in {
3007 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3008 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3009 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
3010 itins.rm, d>, EVEX_4V;
3012 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
3013 (ins RC:$src1, x86scalar_mop:$src2),
3014 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3015 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3016 [(set RC:$dst, (OpNode RC:$src1,
3017 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
3018 itins.rm, d>, EVEX_4V, EVEX_B;
3020 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
3021 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
3022 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3023 [], itins.rm, d>, EVEX_4V, EVEX_K;
3025 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
3026 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
3027 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3028 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
3030 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
3031 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
3032 " \t{${src2}", BrdcstStr,
3033 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
3034 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
3036 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
3037 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
3038 " \t{${src2}", BrdcstStr,
3039 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3041 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
3045 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
3046 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3047 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3049 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
3050 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3051 SSE_ALU_ITINS_P.d, 1>,
3052 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3054 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
3055 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3056 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3057 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
3058 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3059 SSE_ALU_ITINS_P.d, 1>,
3060 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3062 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
3063 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3064 SSE_ALU_ITINS_P.s, 1>,
3065 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3066 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
3067 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3068 SSE_ALU_ITINS_P.s, 1>,
3069 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3071 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
3072 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3073 SSE_ALU_ITINS_P.d, 1>,
3074 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3075 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
3076 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3077 SSE_ALU_ITINS_P.d, 1>,
3078 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3080 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
3081 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3082 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3083 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
3084 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3085 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3087 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
3088 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3089 SSE_ALU_ITINS_P.d, 0>,
3090 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3091 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
3092 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3093 SSE_ALU_ITINS_P.d, 0>,
3094 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3096 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3097 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3098 (i16 -1), FROUND_CURRENT)),
3099 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3101 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3102 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3103 (i8 -1), FROUND_CURRENT)),
3104 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3106 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3107 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3108 (i16 -1), FROUND_CURRENT)),
3109 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3111 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3112 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3113 (i8 -1), FROUND_CURRENT)),
3114 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3115 //===----------------------------------------------------------------------===//
3116 // AVX-512 VPTESTM instructions
3117 //===----------------------------------------------------------------------===//
3119 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3120 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3121 SDNode OpNode, ValueType vt> {
3122 def rr : AVX512PI<opc, MRMSrcReg,
3123 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3124 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3125 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3126 SSEPackedInt>, EVEX_4V;
3127 def rm : AVX512PI<opc, MRMSrcMem,
3128 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3129 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3130 [(set KRC:$dst, (OpNode (vt RC:$src1),
3131 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3134 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3135 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3136 EVEX_CD8<32, CD8VF>;
3137 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3138 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3139 EVEX_CD8<64, CD8VF>;
3141 let Predicates = [HasCDI] in {
3142 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3143 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3144 EVEX_CD8<32, CD8VF>;
3145 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3146 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3147 EVEX_CD8<64, CD8VF>;
3150 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3151 (v16i32 VR512:$src2), (i16 -1))),
3152 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3154 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3155 (v8i64 VR512:$src2), (i8 -1))),
3156 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3157 //===----------------------------------------------------------------------===//
3158 // AVX-512 Shift instructions
3159 //===----------------------------------------------------------------------===//
3160 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3161 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3162 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3163 RegisterClass KRC> {
3164 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3165 (ins RC:$src1, i8imm:$src2),
3166 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3167 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
3168 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3169 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3170 (ins KRC:$mask, RC:$src1, i8imm:$src2),
3171 !strconcat(OpcodeStr,
3172 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3173 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3174 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3175 (ins x86memop:$src1, i8imm:$src2),
3176 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3177 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
3178 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3179 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3180 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
3181 !strconcat(OpcodeStr,
3182 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3183 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3186 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3187 RegisterClass RC, ValueType vt, ValueType SrcVT,
3188 PatFrag bc_frag, RegisterClass KRC> {
3189 // src2 is always 128-bit
3190 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3191 (ins RC:$src1, VR128X:$src2),
3192 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3193 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3194 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3195 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3196 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3197 !strconcat(OpcodeStr,
3198 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3199 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3200 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3201 (ins RC:$src1, i128mem:$src2),
3202 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3203 [(set RC:$dst, (vt (OpNode RC:$src1,
3204 (bc_frag (memopv2i64 addr:$src2)))))],
3205 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3206 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3207 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3208 !strconcat(OpcodeStr,
3209 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3210 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3213 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3214 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3215 EVEX_V512, EVEX_CD8<32, CD8VF>;
3216 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3217 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3218 EVEX_CD8<32, CD8VQ>;
3220 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3221 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3222 EVEX_CD8<64, CD8VF>, VEX_W;
3223 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3224 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3225 EVEX_CD8<64, CD8VQ>, VEX_W;
3227 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3228 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3229 EVEX_CD8<32, CD8VF>;
3230 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3231 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3232 EVEX_CD8<32, CD8VQ>;
3234 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3235 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3236 EVEX_CD8<64, CD8VF>, VEX_W;
3237 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3238 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3239 EVEX_CD8<64, CD8VQ>, VEX_W;
3241 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3242 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3243 EVEX_V512, EVEX_CD8<32, CD8VF>;
3244 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3245 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3246 EVEX_CD8<32, CD8VQ>;
3248 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3249 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3250 EVEX_CD8<64, CD8VF>, VEX_W;
3251 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3252 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3253 EVEX_CD8<64, CD8VQ>, VEX_W;
3255 //===-------------------------------------------------------------------===//
3256 // Variable Bit Shifts
3257 //===-------------------------------------------------------------------===//
3258 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3259 RegisterClass RC, ValueType vt,
3260 X86MemOperand x86memop, PatFrag mem_frag> {
3261 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3262 (ins RC:$src1, RC:$src2),
3263 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3265 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3267 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3268 (ins RC:$src1, x86memop:$src2),
3269 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3271 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3275 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3276 i512mem, memopv16i32>, EVEX_V512,
3277 EVEX_CD8<32, CD8VF>;
3278 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3279 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3280 EVEX_CD8<64, CD8VF>;
3281 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3282 i512mem, memopv16i32>, EVEX_V512,
3283 EVEX_CD8<32, CD8VF>;
3284 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3285 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3286 EVEX_CD8<64, CD8VF>;
3287 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3288 i512mem, memopv16i32>, EVEX_V512,
3289 EVEX_CD8<32, CD8VF>;
3290 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3291 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3292 EVEX_CD8<64, CD8VF>;
3294 //===----------------------------------------------------------------------===//
3295 // AVX-512 - MOVDDUP
3296 //===----------------------------------------------------------------------===//
3298 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3299 X86MemOperand x86memop, PatFrag memop_frag> {
3300 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3301 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3302 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3303 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3304 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3306 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3309 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3310 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3311 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3312 (VMOVDDUPZrm addr:$src)>;
3314 //===---------------------------------------------------------------------===//
3315 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3316 //===---------------------------------------------------------------------===//
3317 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3318 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3319 X86MemOperand x86memop> {
3320 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3321 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3322 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3324 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3325 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3326 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3329 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3330 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3331 EVEX_CD8<32, CD8VF>;
3332 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3333 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3334 EVEX_CD8<32, CD8VF>;
3336 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3337 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3338 (VMOVSHDUPZrm addr:$src)>;
3339 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3340 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3341 (VMOVSLDUPZrm addr:$src)>;
3343 //===----------------------------------------------------------------------===//
3344 // Move Low to High and High to Low packed FP Instructions
3345 //===----------------------------------------------------------------------===//
3346 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3347 (ins VR128X:$src1, VR128X:$src2),
3348 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3349 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3350 IIC_SSE_MOV_LH>, EVEX_4V;
3351 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3352 (ins VR128X:$src1, VR128X:$src2),
3353 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3354 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3355 IIC_SSE_MOV_LH>, EVEX_4V;
3357 let Predicates = [HasAVX512] in {
3359 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3360 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3361 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3362 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3365 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3366 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3369 //===----------------------------------------------------------------------===//
3370 // FMA - Fused Multiply Operations
3373 let Constraints = "$src1 = $dst" in {
3374 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3375 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3376 SDPatternOperator OpNode = null_frag> {
3377 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3378 (ins _.RC:$src2, _.RC:$src3),
3379 OpcodeStr, "$src3, $src2", "$src2, $src3",
3380 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3384 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3385 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3386 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3387 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3388 (_.MemOpFrag addr:$src3))))]>;
3389 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3390 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3391 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3392 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3393 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3394 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3396 } // Constraints = "$src1 = $dst"
3398 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3399 string OpcodeStr, X86VectorVTInfo VTI,
3400 SDPatternOperator OpNode> {
3401 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3403 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3405 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3407 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3410 let ExeDomain = SSEPackedSingle in {
3411 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3412 v16f32_info, X86Fmadd>;
3413 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3414 v16f32_info, X86Fmsub>;
3415 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3416 v16f32_info, X86Fmaddsub>;
3417 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3418 v16f32_info, X86Fmsubadd>;
3419 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3420 v16f32_info, X86Fnmadd>;
3421 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3422 v16f32_info, X86Fnmsub>;
3424 let ExeDomain = SSEPackedDouble in {
3425 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3426 v8f64_info, X86Fmadd>, VEX_W;
3427 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3428 v8f64_info, X86Fmsub>, VEX_W;
3429 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3430 v8f64_info, X86Fmaddsub>, VEX_W;
3431 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3432 v8f64_info, X86Fmsubadd>, VEX_W;
3433 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3434 v8f64_info, X86Fnmadd>, VEX_W;
3435 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3436 v8f64_info, X86Fnmsub>, VEX_W;
3439 let Constraints = "$src1 = $dst" in {
3440 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3441 X86VectorVTInfo _> {
3443 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3444 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3445 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3446 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3448 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3449 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3450 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3451 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3453 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3454 (_.ScalarLdFrag addr:$src2))),
3455 _.RC:$src3))]>, EVEX_B;
3457 } // Constraints = "$src1 = $dst"
3460 let ExeDomain = SSEPackedSingle in {
3461 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3463 EVEX_V512, EVEX_CD8<32, CD8VF>;
3464 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3466 EVEX_V512, EVEX_CD8<32, CD8VF>;
3467 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3469 EVEX_V512, EVEX_CD8<32, CD8VF>;
3470 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3472 EVEX_V512, EVEX_CD8<32, CD8VF>;
3473 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3475 EVEX_V512, EVEX_CD8<32, CD8VF>;
3476 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3478 EVEX_V512, EVEX_CD8<32, CD8VF>;
3480 let ExeDomain = SSEPackedDouble in {
3481 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3483 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3484 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3486 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3487 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3489 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3490 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3492 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3493 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3495 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3496 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3498 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3502 let Constraints = "$src1 = $dst" in {
3503 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3504 RegisterClass RC, ValueType OpVT,
3505 X86MemOperand x86memop, Operand memop,
3507 let isCommutable = 1 in
3508 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3509 (ins RC:$src1, RC:$src2, RC:$src3),
3510 !strconcat(OpcodeStr,
3511 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3513 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3515 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3516 (ins RC:$src1, RC:$src2, f128mem:$src3),
3517 !strconcat(OpcodeStr,
3518 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3520 (OpVT (OpNode RC:$src2, RC:$src1,
3521 (mem_frag addr:$src3))))]>;
3524 } // Constraints = "$src1 = $dst"
3526 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3527 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3528 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3529 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3530 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3531 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3532 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3533 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3534 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3535 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3536 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3537 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3538 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3539 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3540 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3541 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3543 //===----------------------------------------------------------------------===//
3544 // AVX-512 Scalar convert from sign integer to float/double
3545 //===----------------------------------------------------------------------===//
3547 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3548 X86MemOperand x86memop, string asm> {
3549 let hasSideEffects = 0 in {
3550 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3551 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3554 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3555 (ins DstRC:$src1, x86memop:$src),
3556 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3558 } // hasSideEffects = 0
3560 let Predicates = [HasAVX512] in {
3561 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3562 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3563 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3564 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3565 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3566 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3567 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3568 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3570 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3571 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3572 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3573 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3574 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3575 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3576 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3577 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3579 def : Pat<(f32 (sint_to_fp GR32:$src)),
3580 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3581 def : Pat<(f32 (sint_to_fp GR64:$src)),
3582 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3583 def : Pat<(f64 (sint_to_fp GR32:$src)),
3584 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3585 def : Pat<(f64 (sint_to_fp GR64:$src)),
3586 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3588 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3589 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3590 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3591 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3592 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3593 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3594 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3595 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3597 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3598 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3599 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3600 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3601 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3602 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3603 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3604 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3606 def : Pat<(f32 (uint_to_fp GR32:$src)),
3607 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3608 def : Pat<(f32 (uint_to_fp GR64:$src)),
3609 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3610 def : Pat<(f64 (uint_to_fp GR32:$src)),
3611 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3612 def : Pat<(f64 (uint_to_fp GR64:$src)),
3613 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3616 //===----------------------------------------------------------------------===//
3617 // AVX-512 Scalar convert from float/double to integer
3618 //===----------------------------------------------------------------------===//
3619 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3620 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3622 let hasSideEffects = 0 in {
3623 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3624 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3625 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3626 Requires<[HasAVX512]>;
3628 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3629 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3630 Requires<[HasAVX512]>;
3631 } // hasSideEffects = 0
3633 let Predicates = [HasAVX512] in {
3634 // Convert float/double to signed/unsigned int 32/64
3635 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3636 ssmem, sse_load_f32, "cvtss2si">,
3637 XS, EVEX_CD8<32, CD8VT1>;
3638 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3639 ssmem, sse_load_f32, "cvtss2si">,
3640 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3641 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3642 ssmem, sse_load_f32, "cvtss2usi">,
3643 XS, EVEX_CD8<32, CD8VT1>;
3644 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3645 int_x86_avx512_cvtss2usi64, ssmem,
3646 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3647 EVEX_CD8<32, CD8VT1>;
3648 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3649 sdmem, sse_load_f64, "cvtsd2si">,
3650 XD, EVEX_CD8<64, CD8VT1>;
3651 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3652 sdmem, sse_load_f64, "cvtsd2si">,
3653 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3654 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3655 sdmem, sse_load_f64, "cvtsd2usi">,
3656 XD, EVEX_CD8<64, CD8VT1>;
3657 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3658 int_x86_avx512_cvtsd2usi64, sdmem,
3659 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3660 EVEX_CD8<64, CD8VT1>;
3662 let isCodeGenOnly = 1 in {
3663 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3664 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3665 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3666 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3667 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3668 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3669 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3670 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3671 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3672 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3673 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3674 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3676 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3677 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3678 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3679 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3680 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3681 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3682 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3683 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3684 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3685 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3686 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3687 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3688 } // isCodeGenOnly = 1
3690 // Convert float/double to signed/unsigned int 32/64 with truncation
3691 let isCodeGenOnly = 1 in {
3692 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3693 ssmem, sse_load_f32, "cvttss2si">,
3694 XS, EVEX_CD8<32, CD8VT1>;
3695 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3696 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3697 "cvttss2si">, XS, VEX_W,
3698 EVEX_CD8<32, CD8VT1>;
3699 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3700 sdmem, sse_load_f64, "cvttsd2si">, XD,
3701 EVEX_CD8<64, CD8VT1>;
3702 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3703 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3704 "cvttsd2si">, XD, VEX_W,
3705 EVEX_CD8<64, CD8VT1>;
3706 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3707 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3708 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3709 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3710 int_x86_avx512_cvttss2usi64, ssmem,
3711 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3712 EVEX_CD8<32, CD8VT1>;
3713 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3714 int_x86_avx512_cvttsd2usi,
3715 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3716 EVEX_CD8<64, CD8VT1>;
3717 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3718 int_x86_avx512_cvttsd2usi64, sdmem,
3719 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3720 EVEX_CD8<64, CD8VT1>;
3721 } // isCodeGenOnly = 1
3723 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3724 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3726 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3727 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3728 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3729 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3730 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3731 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3734 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3735 loadf32, "cvttss2si">, XS,
3736 EVEX_CD8<32, CD8VT1>;
3737 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3738 loadf32, "cvttss2usi">, XS,
3739 EVEX_CD8<32, CD8VT1>;
3740 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3741 loadf32, "cvttss2si">, XS, VEX_W,
3742 EVEX_CD8<32, CD8VT1>;
3743 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3744 loadf32, "cvttss2usi">, XS, VEX_W,
3745 EVEX_CD8<32, CD8VT1>;
3746 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3747 loadf64, "cvttsd2si">, XD,
3748 EVEX_CD8<64, CD8VT1>;
3749 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3750 loadf64, "cvttsd2usi">, XD,
3751 EVEX_CD8<64, CD8VT1>;
3752 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3753 loadf64, "cvttsd2si">, XD, VEX_W,
3754 EVEX_CD8<64, CD8VT1>;
3755 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3756 loadf64, "cvttsd2usi">, XD, VEX_W,
3757 EVEX_CD8<64, CD8VT1>;
3759 //===----------------------------------------------------------------------===//
3760 // AVX-512 Convert form float to double and back
3761 //===----------------------------------------------------------------------===//
3762 let hasSideEffects = 0 in {
3763 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3764 (ins FR32X:$src1, FR32X:$src2),
3765 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3766 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3768 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3769 (ins FR32X:$src1, f32mem:$src2),
3770 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3771 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3772 EVEX_CD8<32, CD8VT1>;
3774 // Convert scalar double to scalar single
3775 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3776 (ins FR64X:$src1, FR64X:$src2),
3777 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3778 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3780 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3781 (ins FR64X:$src1, f64mem:$src2),
3782 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3783 []>, EVEX_4V, VEX_LIG, VEX_W,
3784 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3787 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3788 Requires<[HasAVX512]>;
3789 def : Pat<(fextend (loadf32 addr:$src)),
3790 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3792 def : Pat<(extloadf32 addr:$src),
3793 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3794 Requires<[HasAVX512, OptForSize]>;
3796 def : Pat<(extloadf32 addr:$src),
3797 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3798 Requires<[HasAVX512, OptForSpeed]>;
3800 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3801 Requires<[HasAVX512]>;
3803 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3804 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3805 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3807 let hasSideEffects = 0 in {
3808 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3809 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3811 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3812 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3813 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3814 [], d>, EVEX, EVEX_B, EVEX_RC;
3816 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3817 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3819 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3820 } // hasSideEffects = 0
3823 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3824 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3825 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3827 let hasSideEffects = 0 in {
3828 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3829 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3831 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3833 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3834 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3836 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3837 } // hasSideEffects = 0
3840 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3841 memopv8f64, f512mem, v8f32, v8f64,
3842 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3843 EVEX_CD8<64, CD8VF>;
3845 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3846 memopv4f64, f256mem, v8f64, v8f32,
3847 SSEPackedDouble>, EVEX_V512, PS,
3848 EVEX_CD8<32, CD8VH>;
3849 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3850 (VCVTPS2PDZrm addr:$src)>;
3852 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3853 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3854 (VCVTPD2PSZrr VR512:$src)>;
3856 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3857 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3858 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3860 //===----------------------------------------------------------------------===//
3861 // AVX-512 Vector convert from sign integer to float/double
3862 //===----------------------------------------------------------------------===//
3864 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3865 memopv8i64, i512mem, v16f32, v16i32,
3866 SSEPackedSingle>, EVEX_V512, PS,
3867 EVEX_CD8<32, CD8VF>;
3869 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3870 memopv4i64, i256mem, v8f64, v8i32,
3871 SSEPackedDouble>, EVEX_V512, XS,
3872 EVEX_CD8<32, CD8VH>;
3874 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3875 memopv16f32, f512mem, v16i32, v16f32,
3876 SSEPackedSingle>, EVEX_V512, XS,
3877 EVEX_CD8<32, CD8VF>;
3879 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3880 memopv8f64, f512mem, v8i32, v8f64,
3881 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3882 EVEX_CD8<64, CD8VF>;
3884 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3885 memopv16f32, f512mem, v16i32, v16f32,
3886 SSEPackedSingle>, EVEX_V512, PS,
3887 EVEX_CD8<32, CD8VF>;
3889 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3890 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3891 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3892 (VCVTTPS2UDQZrr VR512:$src)>;
3894 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3895 memopv8f64, f512mem, v8i32, v8f64,
3896 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3897 EVEX_CD8<64, CD8VF>;
3899 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3900 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3901 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3902 (VCVTTPD2UDQZrr VR512:$src)>;
3904 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3905 memopv4i64, f256mem, v8f64, v8i32,
3906 SSEPackedDouble>, EVEX_V512, XS,
3907 EVEX_CD8<32, CD8VH>;
3909 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3910 memopv16i32, f512mem, v16f32, v16i32,
3911 SSEPackedSingle>, EVEX_V512, XD,
3912 EVEX_CD8<32, CD8VF>;
3914 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3915 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3916 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3918 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3919 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3920 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3922 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3923 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3924 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3926 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3927 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3928 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3930 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3931 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3932 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3934 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3935 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3936 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3937 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3938 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3939 (VCVTDQ2PDZrr VR256X:$src)>;
3940 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3941 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3942 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3943 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3944 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3945 (VCVTUDQ2PDZrr VR256X:$src)>;
3947 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3948 RegisterClass DstRC, PatFrag mem_frag,
3949 X86MemOperand x86memop, Domain d> {
3950 let hasSideEffects = 0 in {
3951 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3952 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3954 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3955 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3956 [], d>, EVEX, EVEX_B, EVEX_RC;
3958 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3959 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3961 } // hasSideEffects = 0
3964 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3965 memopv16f32, f512mem, SSEPackedSingle>, PD,
3966 EVEX_V512, EVEX_CD8<32, CD8VF>;
3967 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3968 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3969 EVEX_V512, EVEX_CD8<64, CD8VF>;
3971 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3972 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3973 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3975 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3976 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3977 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3979 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3980 memopv16f32, f512mem, SSEPackedSingle>,
3981 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3982 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3983 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3984 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3986 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3987 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3988 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3990 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3991 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3992 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3994 let Predicates = [HasAVX512] in {
3995 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3996 (VCVTPD2PSZrm addr:$src)>;
3997 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3998 (VCVTPS2PDZrm addr:$src)>;
4001 //===----------------------------------------------------------------------===//
4002 // Half precision conversion instructions
4003 //===----------------------------------------------------------------------===//
4004 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4005 X86MemOperand x86memop> {
4006 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4007 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4009 let hasSideEffects = 0, mayLoad = 1 in
4010 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4011 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4014 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4015 X86MemOperand x86memop> {
4016 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4017 (ins srcRC:$src1, i32i8imm:$src2),
4018 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4020 let hasSideEffects = 0, mayStore = 1 in
4021 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4022 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4023 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4026 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4027 EVEX_CD8<32, CD8VH>;
4028 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4029 EVEX_CD8<32, CD8VH>;
4031 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4032 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4033 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4035 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4036 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4037 (VCVTPH2PSZrr VR256X:$src)>;
4039 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4040 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4041 "ucomiss">, PS, EVEX, VEX_LIG,
4042 EVEX_CD8<32, CD8VT1>;
4043 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4044 "ucomisd">, PD, EVEX,
4045 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4046 let Pattern = []<dag> in {
4047 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4048 "comiss">, PS, EVEX, VEX_LIG,
4049 EVEX_CD8<32, CD8VT1>;
4050 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4051 "comisd">, PD, EVEX,
4052 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4054 let isCodeGenOnly = 1 in {
4055 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4056 load, "ucomiss">, PS, EVEX, VEX_LIG,
4057 EVEX_CD8<32, CD8VT1>;
4058 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4059 load, "ucomisd">, PD, EVEX,
4060 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4062 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4063 load, "comiss">, PS, EVEX, VEX_LIG,
4064 EVEX_CD8<32, CD8VT1>;
4065 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4066 load, "comisd">, PD, EVEX,
4067 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4071 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4072 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4073 X86MemOperand x86memop> {
4074 let hasSideEffects = 0 in {
4075 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4076 (ins RC:$src1, RC:$src2),
4077 !strconcat(OpcodeStr,
4078 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4079 let mayLoad = 1 in {
4080 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4081 (ins RC:$src1, x86memop:$src2),
4082 !strconcat(OpcodeStr,
4083 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4088 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4089 EVEX_CD8<32, CD8VT1>;
4090 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4091 VEX_W, EVEX_CD8<64, CD8VT1>;
4092 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4093 EVEX_CD8<32, CD8VT1>;
4094 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4095 VEX_W, EVEX_CD8<64, CD8VT1>;
4097 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4098 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4099 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4100 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4102 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4103 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4104 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4105 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4107 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4108 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4109 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4110 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4112 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4113 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4114 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4115 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4117 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4118 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4119 RegisterClass RC, X86MemOperand x86memop,
4120 PatFrag mem_frag, ValueType OpVt> {
4121 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4122 !strconcat(OpcodeStr,
4123 " \t{$src, $dst|$dst, $src}"),
4124 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
4126 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4127 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4128 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
4131 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
4132 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4133 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4134 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4135 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4136 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4137 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4138 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4140 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4141 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4142 (VRSQRT14PSZr VR512:$src)>;
4143 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4144 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4145 (VRSQRT14PDZr VR512:$src)>;
4147 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4148 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4149 (VRCP14PSZr VR512:$src)>;
4150 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4151 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4152 (VRCP14PDZr VR512:$src)>;
4154 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4155 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4156 X86MemOperand x86memop> {
4157 let hasSideEffects = 0, Predicates = [HasERI] in {
4158 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4159 (ins RC:$src1, RC:$src2),
4160 !strconcat(OpcodeStr,
4161 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4162 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4163 (ins RC:$src1, RC:$src2),
4164 !strconcat(OpcodeStr,
4165 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4166 []>, EVEX_4V, EVEX_B;
4167 let mayLoad = 1 in {
4168 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4169 (ins RC:$src1, x86memop:$src2),
4170 !strconcat(OpcodeStr,
4171 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4176 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4177 EVEX_CD8<32, CD8VT1>;
4178 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4179 VEX_W, EVEX_CD8<64, CD8VT1>;
4180 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4181 EVEX_CD8<32, CD8VT1>;
4182 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4183 VEX_W, EVEX_CD8<64, CD8VT1>;
4185 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4186 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4188 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4189 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4191 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4192 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4194 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4195 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4197 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4198 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4200 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4201 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4203 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4204 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4206 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4207 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4209 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4210 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4211 RegisterClass RC, X86MemOperand x86memop> {
4212 let hasSideEffects = 0, Predicates = [HasERI] in {
4213 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4214 !strconcat(OpcodeStr,
4215 " \t{$src, $dst|$dst, $src}"),
4217 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4218 !strconcat(OpcodeStr,
4219 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4221 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4222 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4226 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4227 EVEX_V512, EVEX_CD8<32, CD8VF>;
4228 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4229 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4230 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4231 EVEX_V512, EVEX_CD8<32, CD8VF>;
4232 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4233 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4235 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4236 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4237 (VRSQRT28PSZrb VR512:$src)>;
4238 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4239 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4240 (VRSQRT28PDZrb VR512:$src)>;
4242 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4243 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4244 (VRCP28PSZrb VR512:$src)>;
4245 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4246 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4247 (VRCP28PDZrb VR512:$src)>;
4249 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4250 OpndItins itins_s, OpndItins itins_d> {
4251 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4252 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4253 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4257 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4258 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4260 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4261 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4263 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4264 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4265 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4269 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4270 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4271 [(set VR512:$dst, (OpNode
4272 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4273 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4277 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4278 Intrinsic F32Int, Intrinsic F64Int,
4279 OpndItins itins_s, OpndItins itins_d> {
4280 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4281 (ins FR32X:$src1, FR32X:$src2),
4282 !strconcat(OpcodeStr,
4283 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4284 [], itins_s.rr>, XS, EVEX_4V;
4285 let isCodeGenOnly = 1 in
4286 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4287 (ins VR128X:$src1, VR128X:$src2),
4288 !strconcat(OpcodeStr,
4289 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4291 (F32Int VR128X:$src1, VR128X:$src2))],
4292 itins_s.rr>, XS, EVEX_4V;
4293 let mayLoad = 1 in {
4294 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4295 (ins FR32X:$src1, f32mem:$src2),
4296 !strconcat(OpcodeStr,
4297 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4298 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4299 let isCodeGenOnly = 1 in
4300 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4301 (ins VR128X:$src1, ssmem:$src2),
4302 !strconcat(OpcodeStr,
4303 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4305 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4306 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4308 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4309 (ins FR64X:$src1, FR64X:$src2),
4310 !strconcat(OpcodeStr,
4311 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4313 let isCodeGenOnly = 1 in
4314 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4315 (ins VR128X:$src1, VR128X:$src2),
4316 !strconcat(OpcodeStr,
4317 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4319 (F64Int VR128X:$src1, VR128X:$src2))],
4320 itins_s.rr>, XD, EVEX_4V, VEX_W;
4321 let mayLoad = 1 in {
4322 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4323 (ins FR64X:$src1, f64mem:$src2),
4324 !strconcat(OpcodeStr,
4325 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4326 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4327 let isCodeGenOnly = 1 in
4328 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4329 (ins VR128X:$src1, sdmem:$src2),
4330 !strconcat(OpcodeStr,
4331 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4333 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4334 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4339 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4340 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4341 SSE_SQRTSS, SSE_SQRTSD>,
4342 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
4343 SSE_SQRTPS, SSE_SQRTPD>;
4345 let Predicates = [HasAVX512] in {
4346 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4347 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4348 (VSQRTPSZrr VR512:$src1)>;
4349 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4350 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4351 (VSQRTPDZrr VR512:$src1)>;
4353 def : Pat<(f32 (fsqrt FR32X:$src)),
4354 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4355 def : Pat<(f32 (fsqrt (load addr:$src))),
4356 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4357 Requires<[OptForSize]>;
4358 def : Pat<(f64 (fsqrt FR64X:$src)),
4359 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4360 def : Pat<(f64 (fsqrt (load addr:$src))),
4361 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4362 Requires<[OptForSize]>;
4364 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4365 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4366 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4367 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4368 Requires<[OptForSize]>;
4370 def : Pat<(f32 (X86frcp FR32X:$src)),
4371 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4372 def : Pat<(f32 (X86frcp (load addr:$src))),
4373 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4374 Requires<[OptForSize]>;
4376 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4377 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4378 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4380 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4381 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4383 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4384 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4385 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4387 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4388 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4392 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4393 X86MemOperand x86memop, RegisterClass RC,
4394 PatFrag mem_frag32, PatFrag mem_frag64,
4395 Intrinsic V4F32Int, Intrinsic V2F64Int,
4397 let ExeDomain = SSEPackedSingle in {
4398 // Intrinsic operation, reg.
4399 // Vector intrinsic operation, reg
4400 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4401 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4402 !strconcat(OpcodeStr,
4403 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4404 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4406 // Vector intrinsic operation, mem
4407 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4408 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4409 !strconcat(OpcodeStr,
4410 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4412 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4413 EVEX_CD8<32, VForm>;
4414 } // ExeDomain = SSEPackedSingle
4416 let ExeDomain = SSEPackedDouble in {
4417 // Vector intrinsic operation, reg
4418 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4419 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4420 !strconcat(OpcodeStr,
4421 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4422 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4424 // Vector intrinsic operation, mem
4425 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4426 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4427 !strconcat(OpcodeStr,
4428 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4430 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4431 EVEX_CD8<64, VForm>;
4432 } // ExeDomain = SSEPackedDouble
4435 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4439 let ExeDomain = GenericDomain in {
4441 let hasSideEffects = 0 in
4442 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4443 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4444 !strconcat(OpcodeStr,
4445 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4448 // Intrinsic operation, reg.
4449 let isCodeGenOnly = 1 in
4450 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4451 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4452 !strconcat(OpcodeStr,
4453 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4454 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4456 // Intrinsic operation, mem.
4457 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4458 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4459 !strconcat(OpcodeStr,
4460 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4461 [(set VR128X:$dst, (F32Int VR128X:$src1,
4462 sse_load_f32:$src2, imm:$src3))]>,
4463 EVEX_CD8<32, CD8VT1>;
4466 let hasSideEffects = 0 in
4467 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4468 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4469 !strconcat(OpcodeStr,
4470 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4473 // Intrinsic operation, reg.
4474 let isCodeGenOnly = 1 in
4475 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4476 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4477 !strconcat(OpcodeStr,
4478 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4479 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4482 // Intrinsic operation, mem.
4483 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4484 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4485 !strconcat(OpcodeStr,
4486 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4488 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4489 VEX_W, EVEX_CD8<64, CD8VT1>;
4490 } // ExeDomain = GenericDomain
4493 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4494 X86MemOperand x86memop, RegisterClass RC,
4495 PatFrag mem_frag, Domain d> {
4496 let ExeDomain = d in {
4497 // Intrinsic operation, reg.
4498 // Vector intrinsic operation, reg
4499 def r : AVX512AIi8<opc, MRMSrcReg,
4500 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4501 !strconcat(OpcodeStr,
4502 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4505 // Vector intrinsic operation, mem
4506 def m : AVX512AIi8<opc, MRMSrcMem,
4507 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4508 !strconcat(OpcodeStr,
4509 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4515 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4516 memopv16f32, SSEPackedSingle>, EVEX_V512,
4517 EVEX_CD8<32, CD8VF>;
4519 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4520 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4522 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4525 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4526 memopv8f64, SSEPackedDouble>, EVEX_V512,
4527 VEX_W, EVEX_CD8<64, CD8VF>;
4529 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4530 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4532 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4534 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4535 Operand x86memop, RegisterClass RC, Domain d> {
4536 let ExeDomain = d in {
4537 def r : AVX512AIi8<opc, MRMSrcReg,
4538 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4539 !strconcat(OpcodeStr,
4540 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4543 def m : AVX512AIi8<opc, MRMSrcMem,
4544 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4545 !strconcat(OpcodeStr,
4546 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4551 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4552 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4554 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4555 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4557 def : Pat<(ffloor FR32X:$src),
4558 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4559 def : Pat<(f64 (ffloor FR64X:$src)),
4560 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4561 def : Pat<(f32 (fnearbyint FR32X:$src)),
4562 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4563 def : Pat<(f64 (fnearbyint FR64X:$src)),
4564 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4565 def : Pat<(f32 (fceil FR32X:$src)),
4566 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4567 def : Pat<(f64 (fceil FR64X:$src)),
4568 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4569 def : Pat<(f32 (frint FR32X:$src)),
4570 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4571 def : Pat<(f64 (frint FR64X:$src)),
4572 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4573 def : Pat<(f32 (ftrunc FR32X:$src)),
4574 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4575 def : Pat<(f64 (ftrunc FR64X:$src)),
4576 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4578 def : Pat<(v16f32 (ffloor VR512:$src)),
4579 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4580 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4581 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4582 def : Pat<(v16f32 (fceil VR512:$src)),
4583 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4584 def : Pat<(v16f32 (frint VR512:$src)),
4585 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4586 def : Pat<(v16f32 (ftrunc VR512:$src)),
4587 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4589 def : Pat<(v8f64 (ffloor VR512:$src)),
4590 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4591 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4592 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4593 def : Pat<(v8f64 (fceil VR512:$src)),
4594 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4595 def : Pat<(v8f64 (frint VR512:$src)),
4596 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4597 def : Pat<(v8f64 (ftrunc VR512:$src)),
4598 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4600 //-------------------------------------------------
4601 // Integer truncate and extend operations
4602 //-------------------------------------------------
4604 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4605 RegisterClass dstRC, RegisterClass srcRC,
4606 RegisterClass KRC, X86MemOperand x86memop> {
4607 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4609 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4612 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4613 (ins KRC:$mask, srcRC:$src),
4614 !strconcat(OpcodeStr,
4615 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4618 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4619 (ins KRC:$mask, srcRC:$src),
4620 !strconcat(OpcodeStr,
4621 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4624 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4625 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4628 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4629 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4630 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4634 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4635 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4636 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4637 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4638 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4639 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4640 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4641 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4642 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4643 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4644 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4645 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4646 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4647 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4648 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4649 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4650 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4651 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4652 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4653 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4654 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4655 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4656 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4657 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4658 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4659 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4660 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4661 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4662 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4663 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4665 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4666 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4667 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4668 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4669 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4671 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4672 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4673 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4674 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4675 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4676 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4677 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4678 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4681 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4682 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4683 PatFrag mem_frag, X86MemOperand x86memop,
4684 ValueType OpVT, ValueType InVT> {
4686 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4688 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4689 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4691 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4692 (ins KRC:$mask, SrcRC:$src),
4693 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4696 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4697 (ins KRC:$mask, SrcRC:$src),
4698 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4701 let mayLoad = 1 in {
4702 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4703 (ins x86memop:$src),
4704 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4706 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4709 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4710 (ins KRC:$mask, x86memop:$src),
4711 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4715 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4716 (ins KRC:$mask, x86memop:$src),
4717 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4723 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4724 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4726 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4727 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4729 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4730 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4731 EVEX_CD8<16, CD8VH>;
4732 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4733 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4734 EVEX_CD8<16, CD8VQ>;
4735 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4736 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4737 EVEX_CD8<32, CD8VH>;
4739 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4740 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4742 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4743 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4745 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4746 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4747 EVEX_CD8<16, CD8VH>;
4748 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4749 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4750 EVEX_CD8<16, CD8VQ>;
4751 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4752 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4753 EVEX_CD8<32, CD8VH>;
4755 //===----------------------------------------------------------------------===//
4756 // GATHER - SCATTER Operations
4758 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4759 RegisterClass RC, X86MemOperand memop> {
4761 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4762 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4763 (ins RC:$src1, KRC:$mask, memop:$src2),
4764 !strconcat(OpcodeStr,
4765 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4769 let ExeDomain = SSEPackedDouble in {
4770 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4771 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4772 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4773 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4776 let ExeDomain = SSEPackedSingle in {
4777 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4778 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4779 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4780 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4783 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4784 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4785 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4786 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4788 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4789 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4790 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4791 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4793 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4794 RegisterClass RC, X86MemOperand memop> {
4795 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4796 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4797 (ins memop:$dst, KRC:$mask, RC:$src2),
4798 !strconcat(OpcodeStr,
4799 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4803 let ExeDomain = SSEPackedDouble in {
4804 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4805 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4806 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4807 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4810 let ExeDomain = SSEPackedSingle in {
4811 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4812 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4813 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4814 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4817 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4818 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4819 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4820 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4822 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4823 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4824 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4825 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4828 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4829 RegisterClass KRC, X86MemOperand memop> {
4830 let Predicates = [HasPFI], hasSideEffects = 1 in
4831 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4832 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4836 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4837 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4839 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4840 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4842 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4843 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4845 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4846 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4848 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4849 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4851 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4852 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4854 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4855 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4857 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4858 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4860 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4861 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4863 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4864 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4866 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4867 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4869 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4870 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4872 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4873 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4875 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4876 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4878 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4879 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4881 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4882 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4883 //===----------------------------------------------------------------------===//
4884 // VSHUFPS - VSHUFPD Operations
4886 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4887 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4889 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4890 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4891 !strconcat(OpcodeStr,
4892 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4893 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4894 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4895 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4896 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4897 (ins RC:$src1, RC:$src2, i8imm:$src3),
4898 !strconcat(OpcodeStr,
4899 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4900 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4901 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4902 EVEX_4V, Sched<[WriteShuffle]>;
4905 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4906 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4907 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4908 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4910 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4911 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4912 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4913 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4914 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4916 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4917 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4918 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4919 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4920 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4922 multiclass avx512_valign<X86VectorVTInfo _> {
4923 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4924 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4926 "$src3, $src2, $src1", "$src1, $src2, $src3",
4927 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4929 AVX512AIi8Base, EVEX_4V;
4931 // Also match valign of packed floats.
4932 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4933 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4936 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4937 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4938 !strconcat("valign"##_.Suffix,
4939 " \t{$src3, $src2, $src1, $dst|"
4940 "$dst, $src1, $src2, $src3}"),
4943 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4944 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4946 // Helper fragments to match sext vXi1 to vXiY.
4947 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4948 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4950 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4951 RegisterClass KRC, RegisterClass RC,
4952 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4954 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4955 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4957 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4958 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4960 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4961 !strconcat(OpcodeStr,
4962 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4964 let mayLoad = 1 in {
4965 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4966 (ins x86memop:$src),
4967 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4969 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4970 (ins KRC:$mask, x86memop:$src),
4971 !strconcat(OpcodeStr,
4972 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4974 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4975 (ins KRC:$mask, x86memop:$src),
4976 !strconcat(OpcodeStr,
4977 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4979 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4980 (ins x86scalar_mop:$src),
4981 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4982 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4984 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4985 (ins KRC:$mask, x86scalar_mop:$src),
4986 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4987 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4988 []>, EVEX, EVEX_B, EVEX_K;
4989 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4990 (ins KRC:$mask, x86scalar_mop:$src),
4991 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4992 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4994 []>, EVEX, EVEX_B, EVEX_KZ;
4998 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4999 i512mem, i32mem, "{1to16}">, EVEX_V512,
5000 EVEX_CD8<32, CD8VF>;
5001 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5002 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5003 EVEX_CD8<64, CD8VF>;
5006 (bc_v16i32 (v16i1sextv16i32)),
5007 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5008 (VPABSDZrr VR512:$src)>;
5010 (bc_v8i64 (v8i1sextv8i64)),
5011 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5012 (VPABSQZrr VR512:$src)>;
5014 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5015 (v16i32 immAllZerosV), (i16 -1))),
5016 (VPABSDZrr VR512:$src)>;
5017 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5018 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5019 (VPABSQZrr VR512:$src)>;
5021 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5022 RegisterClass RC, RegisterClass KRC,
5023 X86MemOperand x86memop,
5024 X86MemOperand x86scalar_mop, string BrdcstStr> {
5025 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5027 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
5029 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5030 (ins x86memop:$src),
5031 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
5033 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5034 (ins x86scalar_mop:$src),
5035 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5036 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5038 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5039 (ins KRC:$mask, RC:$src),
5040 !strconcat(OpcodeStr,
5041 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5043 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5044 (ins KRC:$mask, x86memop:$src),
5045 !strconcat(OpcodeStr,
5046 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5048 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5049 (ins KRC:$mask, x86scalar_mop:$src),
5050 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5051 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5053 []>, EVEX, EVEX_KZ, EVEX_B;
5055 let Constraints = "$src1 = $dst" in {
5056 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5057 (ins RC:$src1, KRC:$mask, RC:$src2),
5058 !strconcat(OpcodeStr,
5059 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5061 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5062 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5063 !strconcat(OpcodeStr,
5064 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5066 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5067 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5068 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
5069 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5070 []>, EVEX, EVEX_K, EVEX_B;
5074 let Predicates = [HasCDI] in {
5075 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5076 i512mem, i32mem, "{1to16}">,
5077 EVEX_V512, EVEX_CD8<32, CD8VF>;
5080 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5081 i512mem, i64mem, "{1to8}">,
5082 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5086 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5088 (VPCONFLICTDrrk VR512:$src1,
5089 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5091 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5093 (VPCONFLICTQrrk VR512:$src1,
5094 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5096 let Predicates = [HasCDI] in {
5097 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5098 i512mem, i32mem, "{1to16}">,
5099 EVEX_V512, EVEX_CD8<32, CD8VF>;
5102 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5103 i512mem, i64mem, "{1to8}">,
5104 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5108 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5110 (VPLZCNTDrrk VR512:$src1,
5111 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5113 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5115 (VPLZCNTQrrk VR512:$src1,
5116 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5118 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5119 (VPLZCNTDrm addr:$src)>;
5120 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5121 (VPLZCNTDrr VR512:$src)>;
5122 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5123 (VPLZCNTQrm addr:$src)>;
5124 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5125 (VPLZCNTQrr VR512:$src)>;
5127 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5128 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5129 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5131 def : Pat<(store VK1:$src, addr:$dst),
5132 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5134 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5135 (truncstore node:$val, node:$ptr), [{
5136 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5139 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5140 (MOV8mr addr:$dst, GR8:$src)>;
5142 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5143 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5144 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5145 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5148 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5149 string OpcodeStr, Predicate prd> {
5150 let Predicates = [prd] in
5151 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5153 let Predicates = [prd, HasVLX] in {
5154 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5155 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5159 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5160 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5162 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5164 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5166 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5170 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;