1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 let Predicates = [HasCDI] in {
521 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
522 VK16, v16i32, v16i1>, EVEX_V512;
523 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
524 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
527 //===----------------------------------------------------------------------===//
530 // -- immediate form --
531 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
532 SDNode OpNode, PatFrag mem_frag,
533 X86MemOperand x86memop, ValueType OpVT> {
534 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
535 (ins RC:$src1, i8imm:$src2),
536 !strconcat(OpcodeStr,
537 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
539 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
541 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
542 (ins x86memop:$src1, i8imm:$src2),
543 !strconcat(OpcodeStr,
544 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
546 (OpVT (OpNode (mem_frag addr:$src1),
547 (i8 imm:$src2))))]>, EVEX;
550 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
551 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
552 let ExeDomain = SSEPackedDouble in
553 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
554 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
556 // -- VPERM - register form --
557 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
558 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
560 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
561 (ins RC:$src1, RC:$src2),
562 !strconcat(OpcodeStr,
563 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
565 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
567 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
568 (ins RC:$src1, x86memop:$src2),
569 !strconcat(OpcodeStr,
570 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
572 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
576 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
577 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
578 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
579 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
580 let ExeDomain = SSEPackedSingle in
581 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
582 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
583 let ExeDomain = SSEPackedDouble in
584 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
585 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
587 // -- VPERM2I - 3 source operands form --
588 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
589 PatFrag mem_frag, X86MemOperand x86memop,
590 SDNode OpNode, ValueType OpVT> {
591 let Constraints = "$src1 = $dst" in {
592 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
593 (ins RC:$src1, RC:$src2, RC:$src3),
594 !strconcat(OpcodeStr,
595 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
597 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
600 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
601 (ins RC:$src1, RC:$src2, x86memop:$src3),
602 !strconcat(OpcodeStr,
603 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
605 (OpVT (OpNode RC:$src1, RC:$src2,
606 (mem_frag addr:$src3))))]>, EVEX_4V;
609 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
610 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
611 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
612 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
613 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
614 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
615 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
616 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
618 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
619 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
620 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
621 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
622 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
623 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
624 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
625 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
627 def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
628 (v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
629 (VPERMT2PSrr VR512:$src1, VR512:$idx, VR512:$src2)>;
631 def : Pat<(v16i32 (int_x86_avx512_mask_vpermt_d_512 (v16i32 VR512:$idx),
632 (v16i32 VR512:$src1), (v16i32 VR512:$src2), (i16 -1))),
633 (VPERMT2Drr VR512:$src1, VR512:$idx, VR512:$src2)>;
635 def : Pat<(v8f64 (int_x86_avx512_mask_vpermt_pd_512 (v8i64 VR512:$idx),
636 (v8f64 VR512:$src1), (v8f64 VR512:$src2), (i8 -1))),
637 (VPERMT2PDrr VR512:$src1, VR512:$idx, VR512:$src2)>;
639 def : Pat<(v8i64 (int_x86_avx512_mask_vpermt_q_512 (v8i64 VR512:$idx),
640 (v8i64 VR512:$src1), (v8i64 VR512:$src2), (i8 -1))),
641 (VPERMT2Qrr VR512:$src1, VR512:$idx, VR512:$src2)>;
642 //===----------------------------------------------------------------------===//
643 // AVX-512 - BLEND using mask
645 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
646 RegisterClass KRC, RegisterClass RC,
647 X86MemOperand x86memop, PatFrag mem_frag,
648 SDNode OpNode, ValueType vt> {
649 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
650 (ins KRC:$mask, RC:$src1, RC:$src2),
651 !strconcat(OpcodeStr,
652 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
653 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
654 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
656 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
657 (ins KRC:$mask, RC:$src1, x86memop:$src2),
658 !strconcat(OpcodeStr,
659 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
660 []>, EVEX_4V, EVEX_K;
663 let ExeDomain = SSEPackedSingle in
664 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
665 VK16WM, VR512, f512mem,
666 memopv16f32, vselect, v16f32>,
667 EVEX_CD8<32, CD8VF>, EVEX_V512;
668 let ExeDomain = SSEPackedDouble in
669 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
670 VK8WM, VR512, f512mem,
671 memopv8f64, vselect, v8f64>,
672 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
674 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
675 (v16f32 VR512:$src2), (i16 GR16:$mask))),
676 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
677 VR512:$src1, VR512:$src2)>;
679 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
680 (v8f64 VR512:$src2), (i8 GR8:$mask))),
681 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
682 VR512:$src1, VR512:$src2)>;
684 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
685 VK16WM, VR512, f512mem,
686 memopv16i32, vselect, v16i32>,
687 EVEX_CD8<32, CD8VF>, EVEX_V512;
689 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
690 VK8WM, VR512, f512mem,
691 memopv8i64, vselect, v8i64>,
692 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
694 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
695 (v16i32 VR512:$src2), (i16 GR16:$mask))),
696 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
697 VR512:$src1, VR512:$src2)>;
699 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
700 (v8i64 VR512:$src2), (i8 GR8:$mask))),
701 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
702 VR512:$src1, VR512:$src2)>;
704 let Predicates = [HasAVX512] in {
705 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
706 (v8f32 VR256X:$src2))),
708 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
709 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
710 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
712 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
713 (v8i32 VR256X:$src2))),
715 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
716 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
717 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
719 //===----------------------------------------------------------------------===//
720 // Compare Instructions
721 //===----------------------------------------------------------------------===//
723 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
724 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
725 Operand CC, SDNode OpNode, ValueType VT,
726 PatFrag ld_frag, string asm, string asm_alt> {
727 def rr : AVX512Ii8<0xC2, MRMSrcReg,
728 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
729 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
730 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
731 def rm : AVX512Ii8<0xC2, MRMSrcMem,
732 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
733 [(set VK1:$dst, (OpNode (VT RC:$src1),
734 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
735 let isAsmParserOnly = 1, hasSideEffects = 0 in {
736 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
737 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
739 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
740 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
741 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
745 let Predicates = [HasAVX512] in {
746 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
747 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
750 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
751 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
752 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
756 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
757 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
758 SDNode OpNode, ValueType vt> {
759 def rr : AVX512BI<opc, MRMSrcReg,
760 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
761 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
762 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
763 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
764 def rm : AVX512BI<opc, MRMSrcMem,
765 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
766 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
767 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
768 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
771 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
772 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
774 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
775 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
776 VEX_W, EVEX_CD8<64, CD8VF>;
778 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
779 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
781 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
782 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
783 VEX_W, EVEX_CD8<64, CD8VF>;
785 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
786 (COPY_TO_REGCLASS (VPCMPGTDZrr
787 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
788 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
790 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
791 (COPY_TO_REGCLASS (VPCMPEQDZrr
792 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
793 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
795 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
796 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
797 SDNode OpNode, ValueType vt, Operand CC, string asm,
799 def rri : AVX512AIi8<opc, MRMSrcReg,
800 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
801 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
802 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
803 def rmi : AVX512AIi8<opc, MRMSrcMem,
804 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
805 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
806 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
807 // Accept explicit immediate argument form instead of comparison code.
808 let isAsmParserOnly = 1, hasSideEffects = 0 in {
809 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
810 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
811 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
812 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
813 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
814 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
818 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
819 X86cmpm, v16i32, AVXCC,
820 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
821 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
822 EVEX_V512, EVEX_CD8<32, CD8VF>;
823 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
824 X86cmpmu, v16i32, AVXCC,
825 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
826 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
827 EVEX_V512, EVEX_CD8<32, CD8VF>;
829 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
830 X86cmpm, v8i64, AVXCC,
831 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
832 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
833 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
834 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
835 X86cmpmu, v8i64, AVXCC,
836 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
837 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
838 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
840 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
841 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
842 X86MemOperand x86memop, ValueType vt,
843 string suffix, Domain d> {
844 def rri : AVX512PIi8<0xC2, MRMSrcReg,
845 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
846 !strconcat("vcmp${cc}", suffix,
847 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
848 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
849 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
850 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
851 !strconcat("vcmp${cc}", suffix,
852 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
854 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
855 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
856 !strconcat("vcmp${cc}", suffix,
857 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
859 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
861 // Accept explicit immediate argument form instead of comparison code.
862 let isAsmParserOnly = 1, hasSideEffects = 0 in {
863 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
864 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
865 !strconcat("vcmp", suffix,
866 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
867 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
868 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
869 !strconcat("vcmp", suffix,
870 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
874 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
875 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
877 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
878 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
881 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
882 (COPY_TO_REGCLASS (VCMPPSZrri
883 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
884 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
886 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
887 (COPY_TO_REGCLASS (VPCMPDZrri
888 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
889 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
891 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
892 (COPY_TO_REGCLASS (VPCMPUDZrri
893 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
894 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
897 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
898 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
900 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
901 (I8Imm imm:$cc)), GR16)>;
903 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
904 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
906 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
907 (I8Imm imm:$cc)), GR8)>;
909 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
910 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
912 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
913 (I8Imm imm:$cc)), GR16)>;
915 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
916 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
918 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
919 (I8Imm imm:$cc)), GR8)>;
921 // Mask register copy, including
922 // - copy between mask registers
923 // - load/store mask registers
924 // - copy from GPR to mask register and vice versa
926 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
927 string OpcodeStr, RegisterClass KRC,
928 ValueType vt, X86MemOperand x86memop> {
929 let hasSideEffects = 0 in {
930 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
931 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
933 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
934 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
935 [(set KRC:$dst, (vt (load addr:$src)))]>;
937 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
938 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
942 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
944 RegisterClass KRC, RegisterClass GRC> {
945 let hasSideEffects = 0 in {
946 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
947 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
948 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
949 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
953 let Predicates = [HasAVX512] in {
954 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
956 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
960 let Predicates = [HasAVX512] in {
961 // GR16 from/to 16-bit mask
962 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
963 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
964 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
965 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
967 // Store kreg in memory
968 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
969 (KMOVWmk addr:$dst, VK16:$src)>;
971 def : Pat<(store VK8:$src, addr:$dst),
972 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
974 def : Pat<(i1 (load addr:$src)),
975 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
977 def : Pat<(v8i1 (load addr:$src)),
978 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
980 def : Pat<(i1 (trunc (i32 GR32:$src))),
981 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
983 def : Pat<(i1 (trunc (i8 GR8:$src))),
985 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
987 def : Pat<(i1 (trunc (i16 GR16:$src))),
989 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
992 def : Pat<(i32 (zext VK1:$src)),
993 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
994 def : Pat<(i8 (zext VK1:$src)),
997 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
998 def : Pat<(i64 (zext VK1:$src)),
999 (AND64ri8 (SUBREG_TO_REG (i64 0),
1000 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1001 def : Pat<(i16 (zext VK1:$src)),
1003 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1005 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1006 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1007 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1008 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1010 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1011 let Predicates = [HasAVX512] in {
1012 // GR from/to 8-bit mask without native support
1013 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1015 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1017 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1019 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1022 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1023 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1024 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1025 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1029 // Mask unary operation
1031 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1032 RegisterClass KRC, SDPatternOperator OpNode> {
1033 let Predicates = [HasAVX512] in
1034 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1035 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1036 [(set KRC:$dst, (OpNode KRC:$src))]>;
1039 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1040 SDPatternOperator OpNode> {
1041 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1045 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1047 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1048 let Predicates = [HasAVX512] in
1049 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1051 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1052 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1054 defm : avx512_mask_unop_int<"knot", "KNOT">;
1056 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1057 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1058 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1060 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1061 def : Pat<(not VK8:$src),
1063 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1065 // Mask binary operation
1066 // - KAND, KANDN, KOR, KXNOR, KXOR
1067 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1068 RegisterClass KRC, SDPatternOperator OpNode> {
1069 let Predicates = [HasAVX512] in
1070 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1071 !strconcat(OpcodeStr,
1072 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1073 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1076 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1077 SDPatternOperator OpNode> {
1078 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1082 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1083 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1085 let isCommutable = 1 in {
1086 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1087 let isCommutable = 0 in
1088 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1089 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1090 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1091 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1094 def : Pat<(xor VK1:$src1, VK1:$src2),
1095 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1096 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1098 def : Pat<(or VK1:$src1, VK1:$src2),
1099 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1100 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1102 def : Pat<(and VK1:$src1, VK1:$src2),
1103 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1104 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1106 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1107 let Predicates = [HasAVX512] in
1108 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1109 (i16 GR16:$src1), (i16 GR16:$src2)),
1110 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1111 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1112 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1115 defm : avx512_mask_binop_int<"kand", "KAND">;
1116 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1117 defm : avx512_mask_binop_int<"kor", "KOR">;
1118 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1119 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1121 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1122 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1123 let Predicates = [HasAVX512] in
1124 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1126 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1127 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1130 defm : avx512_binop_pat<and, KANDWrr>;
1131 defm : avx512_binop_pat<andn, KANDNWrr>;
1132 defm : avx512_binop_pat<or, KORWrr>;
1133 defm : avx512_binop_pat<xnor, KXNORWrr>;
1134 defm : avx512_binop_pat<xor, KXORWrr>;
1137 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1138 RegisterClass KRC> {
1139 let Predicates = [HasAVX512] in
1140 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1141 !strconcat(OpcodeStr,
1142 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1145 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1146 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1150 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1151 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1152 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1153 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1156 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1157 let Predicates = [HasAVX512] in
1158 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1159 (i16 GR16:$src1), (i16 GR16:$src2)),
1160 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1161 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1162 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1164 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1167 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1169 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1170 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1171 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1172 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1175 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1176 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1180 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1182 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1183 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1184 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1187 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1189 let Predicates = [HasAVX512] in
1190 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1191 !strconcat(OpcodeStr,
1192 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1193 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1196 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1198 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1202 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1203 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1205 // Mask setting all 0s or 1s
1206 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1207 let Predicates = [HasAVX512] in
1208 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1209 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1210 [(set KRC:$dst, (VT Val))]>;
1213 multiclass avx512_mask_setop_w<PatFrag Val> {
1214 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1215 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1218 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1219 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1221 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1222 let Predicates = [HasAVX512] in {
1223 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1224 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1225 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1226 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1227 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1229 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1230 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1232 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1233 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1235 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1236 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1238 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1239 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1241 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1242 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1243 //===----------------------------------------------------------------------===//
1244 // AVX-512 - Aligned and unaligned load and store
1247 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1248 X86MemOperand x86memop, PatFrag ld_frag,
1249 string asm, Domain d,
1250 ValueType vt, bit IsReMaterializable = 1> {
1251 let hasSideEffects = 0 in {
1252 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1253 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1255 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1257 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1258 [], d>, EVEX, EVEX_KZ;
1260 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1261 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1262 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1263 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1264 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1265 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1266 (ins RC:$src1, KRC:$mask, RC:$src2),
1268 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1271 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1272 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1274 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1275 [], d>, EVEX, EVEX_K;
1278 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1279 (ins KRC:$mask, x86memop:$src2),
1281 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1282 [], d>, EVEX, EVEX_KZ;
1285 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1286 X86MemOperand x86memop, PatFrag store_frag,
1287 string asm, Domain d, ValueType vt> {
1288 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1289 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1290 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1292 let Constraints = "$src1 = $dst" in
1293 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1294 (ins RC:$src1, KRC:$mask, RC:$src2),
1296 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1298 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1299 (ins KRC:$mask, RC:$src),
1301 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1302 [], d>, EVEX, EVEX_KZ;
1304 let mayStore = 1 in {
1305 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1306 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1307 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1308 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1309 (ins x86memop:$dst, KRC:$mask, RC:$src),
1311 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1312 [], d>, EVEX, EVEX_K;
1313 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1314 (ins x86memop:$dst, KRC:$mask, RC:$src),
1316 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1317 [], d>, EVEX, EVEX_KZ;
1321 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1322 "vmovaps", SSEPackedSingle, v16f32>,
1323 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1324 "vmovaps", SSEPackedSingle, v16f32>,
1325 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1326 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1327 "vmovapd", SSEPackedDouble, v8f64>,
1328 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1329 "vmovapd", SSEPackedDouble, v8f64>,
1330 PD, EVEX_V512, VEX_W,
1331 EVEX_CD8<64, CD8VF>;
1332 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1333 "vmovups", SSEPackedSingle, v16f32>,
1334 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1335 "vmovups", SSEPackedSingle, v16f32>,
1336 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1337 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1338 "vmovupd", SSEPackedDouble, v8f64, 0>,
1339 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1340 "vmovupd", SSEPackedDouble, v8f64>,
1341 PD, EVEX_V512, VEX_W,
1342 EVEX_CD8<64, CD8VF>;
1343 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1344 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1345 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1347 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1348 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1349 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1351 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1353 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1355 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1357 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1360 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1361 "vmovdqa32", SSEPackedInt, v16i32>,
1362 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1363 "vmovdqa32", SSEPackedInt, v16i32>,
1364 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1365 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1366 "vmovdqa64", SSEPackedInt, v8i64>,
1367 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1368 "vmovdqa64", SSEPackedInt, v8i64>,
1369 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1370 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1371 "vmovdqu32", SSEPackedInt, v16i32>,
1372 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1373 "vmovdqu32", SSEPackedInt, v16i32>,
1374 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1375 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1376 "vmovdqu64", SSEPackedInt, v8i64>,
1377 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1378 "vmovdqu64", SSEPackedInt, v8i64>,
1379 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1381 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1382 (v16i32 immAllZerosV), GR16:$mask)),
1383 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1385 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1386 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1387 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1389 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1391 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1393 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1395 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1398 let AddedComplexity = 20 in {
1399 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1400 (bc_v8i64 (v16i32 immAllZerosV)))),
1401 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1403 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1404 (v8i64 VR512:$src))),
1405 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1408 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1409 (v16i32 immAllZerosV))),
1410 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1412 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1413 (v16i32 VR512:$src))),
1414 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1416 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1417 (v16f32 VR512:$src2))),
1418 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1419 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1420 (v8f64 VR512:$src2))),
1421 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1422 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1423 (v16i32 VR512:$src2))),
1424 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1425 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1426 (v8i64 VR512:$src2))),
1427 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1429 // Move Int Doubleword to Packed Double Int
1431 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1432 "vmovd\t{$src, $dst|$dst, $src}",
1434 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1436 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1437 "vmovd\t{$src, $dst|$dst, $src}",
1439 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1440 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1441 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1442 "vmovq\t{$src, $dst|$dst, $src}",
1444 (v2i64 (scalar_to_vector GR64:$src)))],
1445 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1446 let isCodeGenOnly = 1 in {
1447 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1448 "vmovq\t{$src, $dst|$dst, $src}",
1449 [(set FR64:$dst, (bitconvert GR64:$src))],
1450 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1451 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1452 "vmovq\t{$src, $dst|$dst, $src}",
1453 [(set GR64:$dst, (bitconvert FR64:$src))],
1454 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1456 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1457 "vmovq\t{$src, $dst|$dst, $src}",
1458 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1459 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1460 EVEX_CD8<64, CD8VT1>;
1462 // Move Int Doubleword to Single Scalar
1464 let isCodeGenOnly = 1 in {
1465 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1466 "vmovd\t{$src, $dst|$dst, $src}",
1467 [(set FR32X:$dst, (bitconvert GR32:$src))],
1468 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1470 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1471 "vmovd\t{$src, $dst|$dst, $src}",
1472 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1473 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1476 // Move doubleword from xmm register to r/m32
1478 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1479 "vmovd\t{$src, $dst|$dst, $src}",
1480 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1481 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1483 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1484 (ins i32mem:$dst, VR128X:$src),
1485 "vmovd\t{$src, $dst|$dst, $src}",
1486 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1487 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1488 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1490 // Move quadword from xmm1 register to r/m64
1492 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1493 "vmovq\t{$src, $dst|$dst, $src}",
1494 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1496 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1497 Requires<[HasAVX512, In64BitMode]>;
1499 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1500 (ins i64mem:$dst, VR128X:$src),
1501 "vmovq\t{$src, $dst|$dst, $src}",
1502 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1503 addr:$dst)], IIC_SSE_MOVDQ>,
1504 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1505 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1507 // Move Scalar Single to Double Int
1509 let isCodeGenOnly = 1 in {
1510 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1512 "vmovd\t{$src, $dst|$dst, $src}",
1513 [(set GR32:$dst, (bitconvert FR32X:$src))],
1514 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1515 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1516 (ins i32mem:$dst, FR32X:$src),
1517 "vmovd\t{$src, $dst|$dst, $src}",
1518 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1519 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1522 // Move Quadword Int to Packed Quadword Int
1524 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1526 "vmovq\t{$src, $dst|$dst, $src}",
1528 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1529 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1531 //===----------------------------------------------------------------------===//
1532 // AVX-512 MOVSS, MOVSD
1533 //===----------------------------------------------------------------------===//
1535 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1536 SDNode OpNode, ValueType vt,
1537 X86MemOperand x86memop, PatFrag mem_pat> {
1538 let hasSideEffects = 0 in {
1539 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1540 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1541 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1542 (scalar_to_vector RC:$src2))))],
1543 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1544 let Constraints = "$src1 = $dst" in
1545 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1546 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1548 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1549 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1550 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1551 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1552 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1554 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1555 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1556 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1558 } //hasSideEffects = 0
1561 let ExeDomain = SSEPackedSingle in
1562 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1563 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1565 let ExeDomain = SSEPackedDouble in
1566 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1567 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1569 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1570 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1571 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1573 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1574 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1575 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1577 // For the disassembler
1578 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1579 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1580 (ins VR128X:$src1, FR32X:$src2),
1581 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1583 XS, EVEX_4V, VEX_LIG;
1584 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1585 (ins VR128X:$src1, FR64X:$src2),
1586 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1588 XD, EVEX_4V, VEX_LIG, VEX_W;
1591 let Predicates = [HasAVX512] in {
1592 let AddedComplexity = 15 in {
1593 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1594 // MOVS{S,D} to the lower bits.
1595 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1596 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1597 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1598 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1599 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1600 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1601 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1602 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1604 // Move low f32 and clear high bits.
1605 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1606 (SUBREG_TO_REG (i32 0),
1607 (VMOVSSZrr (v4f32 (V_SET0)),
1608 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1609 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1610 (SUBREG_TO_REG (i32 0),
1611 (VMOVSSZrr (v4i32 (V_SET0)),
1612 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1615 let AddedComplexity = 20 in {
1616 // MOVSSrm zeros the high parts of the register; represent this
1617 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1619 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1620 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1621 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1622 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1623 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1625 // MOVSDrm zeros the high parts of the register; represent this
1626 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1627 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1628 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1629 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1630 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1631 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1632 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1633 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1634 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1635 def : Pat<(v2f64 (X86vzload addr:$src)),
1636 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1638 // Represent the same patterns above but in the form they appear for
1640 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1641 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1642 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1643 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1644 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1645 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1646 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1647 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1648 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1650 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1651 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1652 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1653 FR32X:$src)), sub_xmm)>;
1654 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1655 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1656 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1657 FR64X:$src)), sub_xmm)>;
1658 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1659 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1660 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1662 // Move low f64 and clear high bits.
1663 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1664 (SUBREG_TO_REG (i32 0),
1665 (VMOVSDZrr (v2f64 (V_SET0)),
1666 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1668 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1669 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1670 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1672 // Extract and store.
1673 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1675 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1676 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1678 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1680 // Shuffle with VMOVSS
1681 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1682 (VMOVSSZrr (v4i32 VR128X:$src1),
1683 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1684 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1685 (VMOVSSZrr (v4f32 VR128X:$src1),
1686 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1689 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1690 (SUBREG_TO_REG (i32 0),
1691 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1692 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1694 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1695 (SUBREG_TO_REG (i32 0),
1696 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1697 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1700 // Shuffle with VMOVSD
1701 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1702 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1703 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1704 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1705 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1706 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1707 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1708 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1711 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1712 (SUBREG_TO_REG (i32 0),
1713 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1714 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1716 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1717 (SUBREG_TO_REG (i32 0),
1718 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1719 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1722 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1723 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1724 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1725 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1726 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1727 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1728 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1729 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1732 let AddedComplexity = 15 in
1733 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1735 "vmovq\t{$src, $dst|$dst, $src}",
1736 [(set VR128X:$dst, (v2i64 (X86vzmovl
1737 (v2i64 VR128X:$src))))],
1738 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1740 let AddedComplexity = 20 in
1741 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1743 "vmovq\t{$src, $dst|$dst, $src}",
1744 [(set VR128X:$dst, (v2i64 (X86vzmovl
1745 (loadv2i64 addr:$src))))],
1746 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1747 EVEX_CD8<8, CD8VT8>;
1749 let Predicates = [HasAVX512] in {
1750 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1751 let AddedComplexity = 20 in {
1752 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1753 (VMOVDI2PDIZrm addr:$src)>;
1754 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1755 (VMOV64toPQIZrr GR64:$src)>;
1756 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1757 (VMOVDI2PDIZrr GR32:$src)>;
1759 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1760 (VMOVDI2PDIZrm addr:$src)>;
1761 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1762 (VMOVDI2PDIZrm addr:$src)>;
1763 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1764 (VMOVZPQILo2PQIZrm addr:$src)>;
1765 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1766 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1767 def : Pat<(v2i64 (X86vzload addr:$src)),
1768 (VMOVZPQILo2PQIZrm addr:$src)>;
1771 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1772 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1773 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1774 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1775 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1776 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1777 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1780 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1781 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1783 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1784 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1786 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1787 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1789 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1790 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1792 //===----------------------------------------------------------------------===//
1793 // AVX-512 - Non-temporals
1794 //===----------------------------------------------------------------------===//
1796 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1798 "vmovntdqa\t{$src, $dst|$dst, $src}",
1800 (int_x86_avx512_movntdqa addr:$src))]>,
1801 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1803 // Prefer non-temporal over temporal versions
1804 let AddedComplexity = 400, SchedRW = [WriteStore] in {
1806 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
1807 (ins f512mem:$dst, VR512:$src),
1808 "vmovntps\t{$src, $dst|$dst, $src}",
1809 [(alignednontemporalstore (v16f32 VR512:$src),
1812 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1814 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
1815 (ins f512mem:$dst, VR512:$src),
1816 "vmovntpd\t{$src, $dst|$dst, $src}",
1817 [(alignednontemporalstore (v8f64 VR512:$src),
1820 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1823 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
1824 (ins i512mem:$dst, VR512:$src),
1825 "vmovntdq\t{$src, $dst|$dst, $src}",
1826 [(alignednontemporalstore (v8i64 VR512:$src),
1829 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1832 //===----------------------------------------------------------------------===//
1833 // AVX-512 - Integer arithmetic
1835 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1836 ValueType OpVT, RegisterClass KRC,
1837 RegisterClass RC, PatFrag memop_frag,
1838 X86MemOperand x86memop, PatFrag scalar_mfrag,
1839 X86MemOperand x86scalar_mop, string BrdcstStr,
1840 OpndItins itins, bit IsCommutable = 0> {
1841 let isCommutable = IsCommutable in
1842 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1843 (ins RC:$src1, RC:$src2),
1844 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1845 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1847 let AddedComplexity = 30 in {
1848 let Constraints = "$src0 = $dst" in
1849 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1850 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1851 !strconcat(OpcodeStr,
1852 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1853 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1854 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1856 itins.rr>, EVEX_4V, EVEX_K;
1857 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1858 (ins KRC:$mask, RC:$src1, RC:$src2),
1859 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1860 "|$dst {${mask}} {z}, $src1, $src2}"),
1861 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1862 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1863 (OpVT immAllZerosV))))],
1864 itins.rr>, EVEX_4V, EVEX_KZ;
1867 let mayLoad = 1 in {
1868 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1869 (ins RC:$src1, x86memop:$src2),
1870 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1871 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1873 let AddedComplexity = 30 in {
1874 let Constraints = "$src0 = $dst" in
1875 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1876 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1877 !strconcat(OpcodeStr,
1878 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1879 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1880 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1882 itins.rm>, EVEX_4V, EVEX_K;
1883 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1884 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1885 !strconcat(OpcodeStr,
1886 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1887 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1888 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1889 (OpVT immAllZerosV))))],
1890 itins.rm>, EVEX_4V, EVEX_KZ;
1892 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1893 (ins RC:$src1, x86scalar_mop:$src2),
1894 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1895 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1896 [(set RC:$dst, (OpNode RC:$src1,
1897 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1898 itins.rm>, EVEX_4V, EVEX_B;
1899 let AddedComplexity = 30 in {
1900 let Constraints = "$src0 = $dst" in
1901 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1902 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1903 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1904 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1906 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1907 (OpNode (OpVT RC:$src1),
1908 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1910 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1911 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1912 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1913 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1914 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1916 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1917 (OpNode (OpVT RC:$src1),
1918 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1919 (OpVT immAllZerosV))))],
1920 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1925 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
1926 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
1927 PatFrag memop_frag, X86MemOperand x86memop,
1928 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
1929 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
1930 let isCommutable = IsCommutable in
1932 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1933 (ins RC:$src1, RC:$src2),
1934 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1936 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1937 (ins KRC:$mask, RC:$src1, RC:$src2),
1938 !strconcat(OpcodeStr,
1939 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1940 [], itins.rr>, EVEX_4V, EVEX_K;
1941 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1942 (ins KRC:$mask, RC:$src1, RC:$src2),
1943 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1944 "|$dst {${mask}} {z}, $src1, $src2}"),
1945 [], itins.rr>, EVEX_4V, EVEX_KZ;
1947 let mayLoad = 1 in {
1948 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1949 (ins RC:$src1, x86memop:$src2),
1950 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1952 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1953 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1954 !strconcat(OpcodeStr,
1955 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1956 [], itins.rm>, EVEX_4V, EVEX_K;
1957 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1958 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1959 !strconcat(OpcodeStr,
1960 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1961 [], itins.rm>, EVEX_4V, EVEX_KZ;
1962 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1963 (ins RC:$src1, x86scalar_mop:$src2),
1964 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1965 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1966 [], itins.rm>, EVEX_4V, EVEX_B;
1967 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1968 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1969 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1970 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1972 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1973 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1974 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1975 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1976 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1978 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1982 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
1983 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1984 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1986 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
1987 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1988 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1990 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
1991 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1992 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1994 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
1995 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1996 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1998 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
1999 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2000 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2002 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2003 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2004 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2005 EVEX_CD8<64, CD8VF>, VEX_W;
2007 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2008 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2009 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2011 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2012 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2014 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2015 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2016 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2017 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2018 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2019 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2021 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2022 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2023 SSE_INTALU_ITINS_P, 1>,
2024 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2025 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2026 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2027 SSE_INTALU_ITINS_P, 0>,
2028 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2030 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2031 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2032 SSE_INTALU_ITINS_P, 1>,
2033 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2034 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2035 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2036 SSE_INTALU_ITINS_P, 0>,
2037 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2039 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2040 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2041 SSE_INTALU_ITINS_P, 1>,
2042 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2043 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2044 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2045 SSE_INTALU_ITINS_P, 0>,
2046 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2048 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2049 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2050 SSE_INTALU_ITINS_P, 1>,
2051 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2052 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2053 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2054 SSE_INTALU_ITINS_P, 0>,
2055 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2057 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2058 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2059 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2060 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2061 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2062 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2063 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2064 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2065 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2066 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2067 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2068 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2069 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2070 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2071 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2072 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2073 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2074 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2075 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2076 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2077 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2078 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2079 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2080 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2081 //===----------------------------------------------------------------------===//
2082 // AVX-512 - Unpack Instructions
2083 //===----------------------------------------------------------------------===//
2085 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2086 PatFrag mem_frag, RegisterClass RC,
2087 X86MemOperand x86memop, string asm,
2089 def rr : AVX512PI<opc, MRMSrcReg,
2090 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2092 (vt (OpNode RC:$src1, RC:$src2)))],
2094 def rm : AVX512PI<opc, MRMSrcMem,
2095 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2097 (vt (OpNode RC:$src1,
2098 (bitconvert (mem_frag addr:$src2)))))],
2102 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2103 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2104 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2105 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2106 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2107 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2108 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2109 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2110 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2111 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2112 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2113 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2115 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2116 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2117 X86MemOperand x86memop> {
2118 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2119 (ins RC:$src1, RC:$src2),
2120 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2121 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2122 IIC_SSE_UNPCK>, EVEX_4V;
2123 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2124 (ins RC:$src1, x86memop:$src2),
2125 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2126 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2127 (bitconvert (memop_frag addr:$src2)))))],
2128 IIC_SSE_UNPCK>, EVEX_4V;
2130 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2131 VR512, memopv16i32, i512mem>, EVEX_V512,
2132 EVEX_CD8<32, CD8VF>;
2133 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2134 VR512, memopv8i64, i512mem>, EVEX_V512,
2135 VEX_W, EVEX_CD8<64, CD8VF>;
2136 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2137 VR512, memopv16i32, i512mem>, EVEX_V512,
2138 EVEX_CD8<32, CD8VF>;
2139 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2140 VR512, memopv8i64, i512mem>, EVEX_V512,
2141 VEX_W, EVEX_CD8<64, CD8VF>;
2142 //===----------------------------------------------------------------------===//
2146 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2147 SDNode OpNode, PatFrag mem_frag,
2148 X86MemOperand x86memop, ValueType OpVT> {
2149 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2150 (ins RC:$src1, i8imm:$src2),
2151 !strconcat(OpcodeStr,
2152 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2154 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2156 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2157 (ins x86memop:$src1, i8imm:$src2),
2158 !strconcat(OpcodeStr,
2159 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2161 (OpVT (OpNode (mem_frag addr:$src1),
2162 (i8 imm:$src2))))]>, EVEX;
2165 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2166 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2168 let ExeDomain = SSEPackedSingle in
2169 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2170 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2171 EVEX_CD8<32, CD8VF>;
2172 let ExeDomain = SSEPackedDouble in
2173 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2174 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2175 VEX_W, EVEX_CD8<32, CD8VF>;
2177 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2178 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2179 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2180 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2182 //===----------------------------------------------------------------------===//
2183 // AVX-512 Logical Instructions
2184 //===----------------------------------------------------------------------===//
2186 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2187 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2188 EVEX_V512, EVEX_CD8<32, CD8VF>;
2189 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2190 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2191 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2192 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2193 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2194 EVEX_V512, EVEX_CD8<32, CD8VF>;
2195 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2196 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2197 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2198 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2199 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2200 EVEX_V512, EVEX_CD8<32, CD8VF>;
2201 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2202 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2203 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2204 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2205 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2206 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2207 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2208 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2209 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2211 //===----------------------------------------------------------------------===//
2212 // AVX-512 FP arithmetic
2213 //===----------------------------------------------------------------------===//
2215 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2217 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2218 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2219 EVEX_CD8<32, CD8VT1>;
2220 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2221 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2222 EVEX_CD8<64, CD8VT1>;
2225 let isCommutable = 1 in {
2226 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2227 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2228 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2229 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2231 let isCommutable = 0 in {
2232 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2233 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2236 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2238 RegisterClass RC, ValueType vt,
2239 X86MemOperand x86memop, PatFrag mem_frag,
2240 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2242 Domain d, OpndItins itins, bit commutable> {
2243 let isCommutable = commutable in {
2244 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2245 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2246 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2249 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2250 !strconcat(OpcodeStr,
2251 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2252 [], itins.rr, d>, EVEX_4V, EVEX_K;
2254 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2255 !strconcat(OpcodeStr,
2256 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2257 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2260 let mayLoad = 1 in {
2261 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2262 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2263 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2264 itins.rm, d>, EVEX_4V;
2266 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2267 (ins RC:$src1, x86scalar_mop:$src2),
2268 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2269 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2270 [(set RC:$dst, (OpNode RC:$src1,
2271 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2272 itins.rm, d>, EVEX_4V, EVEX_B;
2274 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2275 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2276 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2277 [], itins.rm, d>, EVEX_4V, EVEX_K;
2279 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2280 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2281 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2282 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2284 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2285 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2286 " \t{${src2}", BrdcstStr,
2287 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2288 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2290 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2291 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2292 " \t{${src2}", BrdcstStr,
2293 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2295 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2299 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2300 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2301 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2303 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2304 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2305 SSE_ALU_ITINS_P.d, 1>,
2306 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2308 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2309 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2310 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2311 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2312 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2313 SSE_ALU_ITINS_P.d, 1>,
2314 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2316 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2317 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2318 SSE_ALU_ITINS_P.s, 1>,
2319 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2320 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2321 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2322 SSE_ALU_ITINS_P.s, 1>,
2323 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2325 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2326 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2327 SSE_ALU_ITINS_P.d, 1>,
2328 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2329 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2330 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2331 SSE_ALU_ITINS_P.d, 1>,
2332 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2334 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2335 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2336 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2337 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2338 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2339 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2341 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2342 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2343 SSE_ALU_ITINS_P.d, 0>,
2344 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2345 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2346 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2347 SSE_ALU_ITINS_P.d, 0>,
2348 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2350 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2351 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2352 (i16 -1), FROUND_CURRENT)),
2353 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2355 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2356 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2357 (i8 -1), FROUND_CURRENT)),
2358 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2360 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2361 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2362 (i16 -1), FROUND_CURRENT)),
2363 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2365 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2366 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2367 (i8 -1), FROUND_CURRENT)),
2368 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2369 //===----------------------------------------------------------------------===//
2370 // AVX-512 VPTESTM instructions
2371 //===----------------------------------------------------------------------===//
2373 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2374 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2375 SDNode OpNode, ValueType vt> {
2376 def rr : AVX512PI<opc, MRMSrcReg,
2377 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2378 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2379 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2380 SSEPackedInt>, EVEX_4V;
2381 def rm : AVX512PI<opc, MRMSrcMem,
2382 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2383 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2384 [(set KRC:$dst, (OpNode (vt RC:$src1),
2385 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2388 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2389 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2390 EVEX_CD8<32, CD8VF>;
2391 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2392 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2393 EVEX_CD8<64, CD8VF>;
2395 let Predicates = [HasCDI] in {
2396 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2397 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2398 EVEX_CD8<32, CD8VF>;
2399 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2400 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2401 EVEX_CD8<64, CD8VF>;
2404 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2405 (v16i32 VR512:$src2), (i16 -1))),
2406 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2408 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2409 (v8i64 VR512:$src2), (i8 -1))),
2410 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2411 //===----------------------------------------------------------------------===//
2412 // AVX-512 Shift instructions
2413 //===----------------------------------------------------------------------===//
2414 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2415 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2416 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2417 RegisterClass KRC> {
2418 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2419 (ins RC:$src1, i8imm:$src2),
2420 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2421 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2422 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2423 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2424 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2425 !strconcat(OpcodeStr,
2426 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2427 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2428 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2429 (ins x86memop:$src1, i8imm:$src2),
2430 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2431 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2432 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2433 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2434 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2435 !strconcat(OpcodeStr,
2436 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2437 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2440 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2441 RegisterClass RC, ValueType vt, ValueType SrcVT,
2442 PatFrag bc_frag, RegisterClass KRC> {
2443 // src2 is always 128-bit
2444 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2445 (ins RC:$src1, VR128X:$src2),
2446 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2447 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2448 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2449 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2450 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2451 !strconcat(OpcodeStr,
2452 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2453 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2454 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2455 (ins RC:$src1, i128mem:$src2),
2456 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2457 [(set RC:$dst, (vt (OpNode RC:$src1,
2458 (bc_frag (memopv2i64 addr:$src2)))))],
2459 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2460 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2461 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2462 !strconcat(OpcodeStr,
2463 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2464 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2467 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2468 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2469 EVEX_V512, EVEX_CD8<32, CD8VF>;
2470 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2471 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2472 EVEX_CD8<32, CD8VQ>;
2474 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2475 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2476 EVEX_CD8<64, CD8VF>, VEX_W;
2477 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2478 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2479 EVEX_CD8<64, CD8VQ>, VEX_W;
2481 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2482 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2483 EVEX_CD8<32, CD8VF>;
2484 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2485 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2486 EVEX_CD8<32, CD8VQ>;
2488 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2489 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2490 EVEX_CD8<64, CD8VF>, VEX_W;
2491 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2492 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2493 EVEX_CD8<64, CD8VQ>, VEX_W;
2495 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2496 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2497 EVEX_V512, EVEX_CD8<32, CD8VF>;
2498 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2499 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2500 EVEX_CD8<32, CD8VQ>;
2502 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2503 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2504 EVEX_CD8<64, CD8VF>, VEX_W;
2505 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2506 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2507 EVEX_CD8<64, CD8VQ>, VEX_W;
2509 //===-------------------------------------------------------------------===//
2510 // Variable Bit Shifts
2511 //===-------------------------------------------------------------------===//
2512 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2513 RegisterClass RC, ValueType vt,
2514 X86MemOperand x86memop, PatFrag mem_frag> {
2515 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2516 (ins RC:$src1, RC:$src2),
2517 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2519 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2521 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2522 (ins RC:$src1, x86memop:$src2),
2523 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2525 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2529 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2530 i512mem, memopv16i32>, EVEX_V512,
2531 EVEX_CD8<32, CD8VF>;
2532 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2533 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2534 EVEX_CD8<64, CD8VF>;
2535 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2536 i512mem, memopv16i32>, EVEX_V512,
2537 EVEX_CD8<32, CD8VF>;
2538 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2539 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2540 EVEX_CD8<64, CD8VF>;
2541 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2542 i512mem, memopv16i32>, EVEX_V512,
2543 EVEX_CD8<32, CD8VF>;
2544 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2545 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2546 EVEX_CD8<64, CD8VF>;
2548 //===----------------------------------------------------------------------===//
2549 // AVX-512 - MOVDDUP
2550 //===----------------------------------------------------------------------===//
2552 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2553 X86MemOperand x86memop, PatFrag memop_frag> {
2554 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2555 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2556 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2557 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2558 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2560 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2563 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2564 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2565 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2566 (VMOVDDUPZrm addr:$src)>;
2568 //===---------------------------------------------------------------------===//
2569 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2570 //===---------------------------------------------------------------------===//
2571 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2572 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2573 X86MemOperand x86memop> {
2574 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2575 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2576 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2578 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2579 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2580 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2583 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2584 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2585 EVEX_CD8<32, CD8VF>;
2586 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2587 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2588 EVEX_CD8<32, CD8VF>;
2590 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2591 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2592 (VMOVSHDUPZrm addr:$src)>;
2593 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2594 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2595 (VMOVSLDUPZrm addr:$src)>;
2597 //===----------------------------------------------------------------------===//
2598 // Move Low to High and High to Low packed FP Instructions
2599 //===----------------------------------------------------------------------===//
2600 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2601 (ins VR128X:$src1, VR128X:$src2),
2602 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2603 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2604 IIC_SSE_MOV_LH>, EVEX_4V;
2605 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2606 (ins VR128X:$src1, VR128X:$src2),
2607 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2608 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2609 IIC_SSE_MOV_LH>, EVEX_4V;
2611 let Predicates = [HasAVX512] in {
2613 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2614 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2615 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2616 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2619 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2620 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2623 //===----------------------------------------------------------------------===//
2624 // FMA - Fused Multiply Operations
2626 let Constraints = "$src1 = $dst" in {
2627 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2628 RegisterClass RC, X86MemOperand x86memop,
2629 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2630 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2631 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2632 (ins RC:$src1, RC:$src2, RC:$src3),
2633 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2634 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2637 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2638 (ins RC:$src1, RC:$src2, x86memop:$src3),
2639 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2640 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2641 (mem_frag addr:$src3))))]>;
2642 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2643 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2644 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2645 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2646 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2647 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2649 } // Constraints = "$src1 = $dst"
2651 let ExeDomain = SSEPackedSingle in {
2652 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2653 memopv16f32, f32mem, loadf32, "{1to16}",
2654 X86Fmadd, v16f32>, EVEX_V512,
2655 EVEX_CD8<32, CD8VF>;
2656 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2657 memopv16f32, f32mem, loadf32, "{1to16}",
2658 X86Fmsub, v16f32>, EVEX_V512,
2659 EVEX_CD8<32, CD8VF>;
2660 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2661 memopv16f32, f32mem, loadf32, "{1to16}",
2662 X86Fmaddsub, v16f32>,
2663 EVEX_V512, EVEX_CD8<32, CD8VF>;
2664 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2665 memopv16f32, f32mem, loadf32, "{1to16}",
2666 X86Fmsubadd, v16f32>,
2667 EVEX_V512, EVEX_CD8<32, CD8VF>;
2668 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2669 memopv16f32, f32mem, loadf32, "{1to16}",
2670 X86Fnmadd, v16f32>, EVEX_V512,
2671 EVEX_CD8<32, CD8VF>;
2672 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2673 memopv16f32, f32mem, loadf32, "{1to16}",
2674 X86Fnmsub, v16f32>, EVEX_V512,
2675 EVEX_CD8<32, CD8VF>;
2677 let ExeDomain = SSEPackedDouble in {
2678 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2679 memopv8f64, f64mem, loadf64, "{1to8}",
2680 X86Fmadd, v8f64>, EVEX_V512,
2681 VEX_W, EVEX_CD8<64, CD8VF>;
2682 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2683 memopv8f64, f64mem, loadf64, "{1to8}",
2684 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2685 EVEX_CD8<64, CD8VF>;
2686 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2687 memopv8f64, f64mem, loadf64, "{1to8}",
2688 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2689 EVEX_CD8<64, CD8VF>;
2690 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2691 memopv8f64, f64mem, loadf64, "{1to8}",
2692 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2693 EVEX_CD8<64, CD8VF>;
2694 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2695 memopv8f64, f64mem, loadf64, "{1to8}",
2696 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2697 EVEX_CD8<64, CD8VF>;
2698 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2699 memopv8f64, f64mem, loadf64, "{1to8}",
2700 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2701 EVEX_CD8<64, CD8VF>;
2704 let Constraints = "$src1 = $dst" in {
2705 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2706 RegisterClass RC, X86MemOperand x86memop,
2707 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2708 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2710 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2711 (ins RC:$src1, RC:$src3, x86memop:$src2),
2712 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2713 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2714 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2715 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2716 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2717 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2718 [(set RC:$dst, (OpNode RC:$src1,
2719 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2721 } // Constraints = "$src1 = $dst"
2724 let ExeDomain = SSEPackedSingle in {
2725 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2726 memopv16f32, f32mem, loadf32, "{1to16}",
2727 X86Fmadd, v16f32>, EVEX_V512,
2728 EVEX_CD8<32, CD8VF>;
2729 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2730 memopv16f32, f32mem, loadf32, "{1to16}",
2731 X86Fmsub, v16f32>, EVEX_V512,
2732 EVEX_CD8<32, CD8VF>;
2733 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2734 memopv16f32, f32mem, loadf32, "{1to16}",
2735 X86Fmaddsub, v16f32>,
2736 EVEX_V512, EVEX_CD8<32, CD8VF>;
2737 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2738 memopv16f32, f32mem, loadf32, "{1to16}",
2739 X86Fmsubadd, v16f32>,
2740 EVEX_V512, EVEX_CD8<32, CD8VF>;
2741 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2742 memopv16f32, f32mem, loadf32, "{1to16}",
2743 X86Fnmadd, v16f32>, EVEX_V512,
2744 EVEX_CD8<32, CD8VF>;
2745 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2746 memopv16f32, f32mem, loadf32, "{1to16}",
2747 X86Fnmsub, v16f32>, EVEX_V512,
2748 EVEX_CD8<32, CD8VF>;
2750 let ExeDomain = SSEPackedDouble in {
2751 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2752 memopv8f64, f64mem, loadf64, "{1to8}",
2753 X86Fmadd, v8f64>, EVEX_V512,
2754 VEX_W, EVEX_CD8<64, CD8VF>;
2755 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2756 memopv8f64, f64mem, loadf64, "{1to8}",
2757 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2758 EVEX_CD8<64, CD8VF>;
2759 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2760 memopv8f64, f64mem, loadf64, "{1to8}",
2761 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2762 EVEX_CD8<64, CD8VF>;
2763 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2764 memopv8f64, f64mem, loadf64, "{1to8}",
2765 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2766 EVEX_CD8<64, CD8VF>;
2767 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2768 memopv8f64, f64mem, loadf64, "{1to8}",
2769 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2770 EVEX_CD8<64, CD8VF>;
2771 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2772 memopv8f64, f64mem, loadf64, "{1to8}",
2773 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2774 EVEX_CD8<64, CD8VF>;
2778 let Constraints = "$src1 = $dst" in {
2779 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2780 RegisterClass RC, ValueType OpVT,
2781 X86MemOperand x86memop, Operand memop,
2783 let isCommutable = 1 in
2784 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2785 (ins RC:$src1, RC:$src2, RC:$src3),
2786 !strconcat(OpcodeStr,
2787 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2789 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2791 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2792 (ins RC:$src1, RC:$src2, f128mem:$src3),
2793 !strconcat(OpcodeStr,
2794 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2796 (OpVT (OpNode RC:$src2, RC:$src1,
2797 (mem_frag addr:$src3))))]>;
2800 } // Constraints = "$src1 = $dst"
2802 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2803 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2804 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2805 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2806 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2807 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2808 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2809 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2810 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2811 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2812 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2813 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2814 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2815 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2816 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2817 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2819 //===----------------------------------------------------------------------===//
2820 // AVX-512 Scalar convert from sign integer to float/double
2821 //===----------------------------------------------------------------------===//
2823 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2824 X86MemOperand x86memop, string asm> {
2825 let hasSideEffects = 0 in {
2826 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2827 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2830 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2831 (ins DstRC:$src1, x86memop:$src),
2832 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2834 } // hasSideEffects = 0
2836 let Predicates = [HasAVX512] in {
2837 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2838 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2839 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2840 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2841 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2842 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2843 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2844 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2846 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2847 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2848 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2849 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2850 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2851 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2852 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2853 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2855 def : Pat<(f32 (sint_to_fp GR32:$src)),
2856 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2857 def : Pat<(f32 (sint_to_fp GR64:$src)),
2858 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2859 def : Pat<(f64 (sint_to_fp GR32:$src)),
2860 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2861 def : Pat<(f64 (sint_to_fp GR64:$src)),
2862 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2864 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2865 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2866 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2867 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2868 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2869 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2870 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2871 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2873 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2874 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2875 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2876 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2877 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2878 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2879 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2880 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2882 def : Pat<(f32 (uint_to_fp GR32:$src)),
2883 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2884 def : Pat<(f32 (uint_to_fp GR64:$src)),
2885 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2886 def : Pat<(f64 (uint_to_fp GR32:$src)),
2887 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2888 def : Pat<(f64 (uint_to_fp GR64:$src)),
2889 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2892 //===----------------------------------------------------------------------===//
2893 // AVX-512 Scalar convert from float/double to integer
2894 //===----------------------------------------------------------------------===//
2895 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2896 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2898 let hasSideEffects = 0 in {
2899 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2900 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2901 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2902 Requires<[HasAVX512]>;
2904 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2905 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2906 Requires<[HasAVX512]>;
2907 } // hasSideEffects = 0
2909 let Predicates = [HasAVX512] in {
2910 // Convert float/double to signed/unsigned int 32/64
2911 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2912 ssmem, sse_load_f32, "cvtss2si">,
2913 XS, EVEX_CD8<32, CD8VT1>;
2914 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2915 ssmem, sse_load_f32, "cvtss2si">,
2916 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2917 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2918 ssmem, sse_load_f32, "cvtss2usi">,
2919 XS, EVEX_CD8<32, CD8VT1>;
2920 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2921 int_x86_avx512_cvtss2usi64, ssmem,
2922 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2923 EVEX_CD8<32, CD8VT1>;
2924 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2925 sdmem, sse_load_f64, "cvtsd2si">,
2926 XD, EVEX_CD8<64, CD8VT1>;
2927 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2928 sdmem, sse_load_f64, "cvtsd2si">,
2929 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2930 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2931 sdmem, sse_load_f64, "cvtsd2usi">,
2932 XD, EVEX_CD8<64, CD8VT1>;
2933 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2934 int_x86_avx512_cvtsd2usi64, sdmem,
2935 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2936 EVEX_CD8<64, CD8VT1>;
2938 let isCodeGenOnly = 1 in {
2939 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2940 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2941 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2942 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2943 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2944 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2945 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2946 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2947 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2948 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2949 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2950 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2952 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2953 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2954 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2955 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2956 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2957 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2958 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2959 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2960 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2961 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2962 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2963 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2964 } // isCodeGenOnly = 1
2966 // Convert float/double to signed/unsigned int 32/64 with truncation
2967 let isCodeGenOnly = 1 in {
2968 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2969 ssmem, sse_load_f32, "cvttss2si">,
2970 XS, EVEX_CD8<32, CD8VT1>;
2971 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2972 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2973 "cvttss2si">, XS, VEX_W,
2974 EVEX_CD8<32, CD8VT1>;
2975 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2976 sdmem, sse_load_f64, "cvttsd2si">, XD,
2977 EVEX_CD8<64, CD8VT1>;
2978 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2979 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2980 "cvttsd2si">, XD, VEX_W,
2981 EVEX_CD8<64, CD8VT1>;
2982 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2983 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2984 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2985 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2986 int_x86_avx512_cvttss2usi64, ssmem,
2987 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2988 EVEX_CD8<32, CD8VT1>;
2989 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2990 int_x86_avx512_cvttsd2usi,
2991 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2992 EVEX_CD8<64, CD8VT1>;
2993 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2994 int_x86_avx512_cvttsd2usi64, sdmem,
2995 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2996 EVEX_CD8<64, CD8VT1>;
2997 } // isCodeGenOnly = 1
2999 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3000 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3002 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3003 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3004 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3005 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3006 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3007 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3010 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3011 loadf32, "cvttss2si">, XS,
3012 EVEX_CD8<32, CD8VT1>;
3013 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3014 loadf32, "cvttss2usi">, XS,
3015 EVEX_CD8<32, CD8VT1>;
3016 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3017 loadf32, "cvttss2si">, XS, VEX_W,
3018 EVEX_CD8<32, CD8VT1>;
3019 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3020 loadf32, "cvttss2usi">, XS, VEX_W,
3021 EVEX_CD8<32, CD8VT1>;
3022 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3023 loadf64, "cvttsd2si">, XD,
3024 EVEX_CD8<64, CD8VT1>;
3025 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3026 loadf64, "cvttsd2usi">, XD,
3027 EVEX_CD8<64, CD8VT1>;
3028 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3029 loadf64, "cvttsd2si">, XD, VEX_W,
3030 EVEX_CD8<64, CD8VT1>;
3031 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3032 loadf64, "cvttsd2usi">, XD, VEX_W,
3033 EVEX_CD8<64, CD8VT1>;
3035 //===----------------------------------------------------------------------===//
3036 // AVX-512 Convert form float to double and back
3037 //===----------------------------------------------------------------------===//
3038 let hasSideEffects = 0 in {
3039 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3040 (ins FR32X:$src1, FR32X:$src2),
3041 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3042 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3044 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3045 (ins FR32X:$src1, f32mem:$src2),
3046 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3047 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3048 EVEX_CD8<32, CD8VT1>;
3050 // Convert scalar double to scalar single
3051 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3052 (ins FR64X:$src1, FR64X:$src2),
3053 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3054 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3056 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3057 (ins FR64X:$src1, f64mem:$src2),
3058 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3059 []>, EVEX_4V, VEX_LIG, VEX_W,
3060 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3063 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3064 Requires<[HasAVX512]>;
3065 def : Pat<(fextend (loadf32 addr:$src)),
3066 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3068 def : Pat<(extloadf32 addr:$src),
3069 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3070 Requires<[HasAVX512, OptForSize]>;
3072 def : Pat<(extloadf32 addr:$src),
3073 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3074 Requires<[HasAVX512, OptForSpeed]>;
3076 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3077 Requires<[HasAVX512]>;
3079 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3080 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3081 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3083 let hasSideEffects = 0 in {
3084 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3085 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3087 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3088 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3089 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3090 [], d>, EVEX, EVEX_B, EVEX_RC;
3092 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3093 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3095 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3096 } // hasSideEffects = 0
3099 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3100 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3101 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3103 let hasSideEffects = 0 in {
3104 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3105 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3107 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3109 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3110 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3112 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3113 } // hasSideEffects = 0
3116 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3117 memopv8f64, f512mem, v8f32, v8f64,
3118 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3119 EVEX_CD8<64, CD8VF>;
3121 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3122 memopv4f64, f256mem, v8f64, v8f32,
3123 SSEPackedDouble>, EVEX_V512, PS,
3124 EVEX_CD8<32, CD8VH>;
3125 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3126 (VCVTPS2PDZrm addr:$src)>;
3128 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3129 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3130 (VCVTPD2PSZrr VR512:$src)>;
3132 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3133 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3134 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3136 //===----------------------------------------------------------------------===//
3137 // AVX-512 Vector convert from sign integer to float/double
3138 //===----------------------------------------------------------------------===//
3140 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3141 memopv8i64, i512mem, v16f32, v16i32,
3142 SSEPackedSingle>, EVEX_V512, PS,
3143 EVEX_CD8<32, CD8VF>;
3145 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3146 memopv4i64, i256mem, v8f64, v8i32,
3147 SSEPackedDouble>, EVEX_V512, XS,
3148 EVEX_CD8<32, CD8VH>;
3150 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3151 memopv16f32, f512mem, v16i32, v16f32,
3152 SSEPackedSingle>, EVEX_V512, XS,
3153 EVEX_CD8<32, CD8VF>;
3155 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3156 memopv8f64, f512mem, v8i32, v8f64,
3157 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3158 EVEX_CD8<64, CD8VF>;
3160 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3161 memopv16f32, f512mem, v16i32, v16f32,
3162 SSEPackedSingle>, EVEX_V512, PS,
3163 EVEX_CD8<32, CD8VF>;
3165 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3166 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3167 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3168 (VCVTTPS2UDQZrr VR512:$src)>;
3170 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3171 memopv8f64, f512mem, v8i32, v8f64,
3172 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3173 EVEX_CD8<64, CD8VF>;
3175 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3176 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3177 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3178 (VCVTTPD2UDQZrr VR512:$src)>;
3180 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3181 memopv4i64, f256mem, v8f64, v8i32,
3182 SSEPackedDouble>, EVEX_V512, XS,
3183 EVEX_CD8<32, CD8VH>;
3185 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3186 memopv16i32, f512mem, v16f32, v16i32,
3187 SSEPackedSingle>, EVEX_V512, XD,
3188 EVEX_CD8<32, CD8VF>;
3190 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3191 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3192 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3194 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3195 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3196 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3198 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3199 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3200 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3202 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3203 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3204 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3206 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3207 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3208 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3210 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3211 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3212 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3213 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3214 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3215 (VCVTDQ2PDZrr VR256X:$src)>;
3216 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3217 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3218 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3219 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3220 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3221 (VCVTUDQ2PDZrr VR256X:$src)>;
3223 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3224 RegisterClass DstRC, PatFrag mem_frag,
3225 X86MemOperand x86memop, Domain d> {
3226 let hasSideEffects = 0 in {
3227 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3228 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3230 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3231 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3232 [], d>, EVEX, EVEX_B, EVEX_RC;
3234 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3235 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3237 } // hasSideEffects = 0
3240 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3241 memopv16f32, f512mem, SSEPackedSingle>, PD,
3242 EVEX_V512, EVEX_CD8<32, CD8VF>;
3243 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3244 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3245 EVEX_V512, EVEX_CD8<64, CD8VF>;
3247 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3248 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3249 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3251 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3252 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3253 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3255 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3256 memopv16f32, f512mem, SSEPackedSingle>,
3257 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3258 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3259 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3260 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3262 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3263 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3264 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3266 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3267 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3268 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3270 let Predicates = [HasAVX512] in {
3271 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3272 (VCVTPD2PSZrm addr:$src)>;
3273 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3274 (VCVTPS2PDZrm addr:$src)>;
3277 //===----------------------------------------------------------------------===//
3278 // Half precision conversion instructions
3279 //===----------------------------------------------------------------------===//
3280 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3281 X86MemOperand x86memop> {
3282 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3283 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3285 let hasSideEffects = 0, mayLoad = 1 in
3286 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3287 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3290 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3291 X86MemOperand x86memop> {
3292 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3293 (ins srcRC:$src1, i32i8imm:$src2),
3294 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3296 let hasSideEffects = 0, mayStore = 1 in
3297 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3298 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3299 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3302 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3303 EVEX_CD8<32, CD8VH>;
3304 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3305 EVEX_CD8<32, CD8VH>;
3307 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3308 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3309 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3311 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3312 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3313 (VCVTPH2PSZrr VR256X:$src)>;
3315 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3316 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3317 "ucomiss">, PS, EVEX, VEX_LIG,
3318 EVEX_CD8<32, CD8VT1>;
3319 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3320 "ucomisd">, PD, EVEX,
3321 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3322 let Pattern = []<dag> in {
3323 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3324 "comiss">, PS, EVEX, VEX_LIG,
3325 EVEX_CD8<32, CD8VT1>;
3326 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3327 "comisd">, PD, EVEX,
3328 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3330 let isCodeGenOnly = 1 in {
3331 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3332 load, "ucomiss">, PS, EVEX, VEX_LIG,
3333 EVEX_CD8<32, CD8VT1>;
3334 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3335 load, "ucomisd">, PD, EVEX,
3336 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3338 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3339 load, "comiss">, PS, EVEX, VEX_LIG,
3340 EVEX_CD8<32, CD8VT1>;
3341 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3342 load, "comisd">, PD, EVEX,
3343 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3347 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3348 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3349 X86MemOperand x86memop> {
3350 let hasSideEffects = 0 in {
3351 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3352 (ins RC:$src1, RC:$src2),
3353 !strconcat(OpcodeStr,
3354 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3355 let mayLoad = 1 in {
3356 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3357 (ins RC:$src1, x86memop:$src2),
3358 !strconcat(OpcodeStr,
3359 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3364 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3365 EVEX_CD8<32, CD8VT1>;
3366 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3367 VEX_W, EVEX_CD8<64, CD8VT1>;
3368 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3369 EVEX_CD8<32, CD8VT1>;
3370 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3371 VEX_W, EVEX_CD8<64, CD8VT1>;
3373 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3374 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3375 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3376 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3378 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3379 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3380 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3381 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3383 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3384 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3385 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3386 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3388 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3389 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3390 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3391 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3393 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3394 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3395 RegisterClass RC, X86MemOperand x86memop,
3396 PatFrag mem_frag, ValueType OpVt> {
3397 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3398 !strconcat(OpcodeStr,
3399 " \t{$src, $dst|$dst, $src}"),
3400 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3402 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3404 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3407 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3408 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3409 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3410 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3411 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3412 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3413 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3414 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3416 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3417 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3418 (VRSQRT14PSZr VR512:$src)>;
3419 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3420 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3421 (VRSQRT14PDZr VR512:$src)>;
3423 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3424 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3425 (VRCP14PSZr VR512:$src)>;
3426 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3427 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3428 (VRCP14PDZr VR512:$src)>;
3430 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3431 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3432 X86MemOperand x86memop> {
3433 let hasSideEffects = 0, Predicates = [HasERI] in {
3434 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3435 (ins RC:$src1, RC:$src2),
3436 !strconcat(OpcodeStr,
3437 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3438 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3439 (ins RC:$src1, RC:$src2),
3440 !strconcat(OpcodeStr,
3441 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3442 []>, EVEX_4V, EVEX_B;
3443 let mayLoad = 1 in {
3444 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3445 (ins RC:$src1, x86memop:$src2),
3446 !strconcat(OpcodeStr,
3447 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3452 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3453 EVEX_CD8<32, CD8VT1>;
3454 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3455 VEX_W, EVEX_CD8<64, CD8VT1>;
3456 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3457 EVEX_CD8<32, CD8VT1>;
3458 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3459 VEX_W, EVEX_CD8<64, CD8VT1>;
3461 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3462 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3464 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3465 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3467 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3468 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3470 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3471 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3473 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3474 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3476 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3477 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3479 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3480 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3482 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3483 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3485 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3486 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3487 RegisterClass RC, X86MemOperand x86memop> {
3488 let hasSideEffects = 0, Predicates = [HasERI] in {
3489 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3490 !strconcat(OpcodeStr,
3491 " \t{$src, $dst|$dst, $src}"),
3493 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3494 !strconcat(OpcodeStr,
3495 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3497 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3498 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3502 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3503 EVEX_V512, EVEX_CD8<32, CD8VF>;
3504 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3505 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3506 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3507 EVEX_V512, EVEX_CD8<32, CD8VF>;
3508 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3509 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3511 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3512 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3513 (VRSQRT28PSZrb VR512:$src)>;
3514 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3515 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3516 (VRSQRT28PDZrb VR512:$src)>;
3518 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3519 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3520 (VRCP28PSZrb VR512:$src)>;
3521 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3522 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3523 (VRCP28PDZrb VR512:$src)>;
3525 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3526 Intrinsic V16F32Int, Intrinsic V8F64Int,
3527 OpndItins itins_s, OpndItins itins_d> {
3528 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3529 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3530 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3534 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3535 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3537 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3538 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3540 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3541 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3542 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3546 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3547 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3548 [(set VR512:$dst, (OpNode
3549 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3550 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3552 let isCodeGenOnly = 1 in {
3553 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3554 !strconcat(OpcodeStr,
3555 "ps\t{$src, $dst|$dst, $src}"),
3556 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3558 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3559 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3561 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3562 EVEX_V512, EVEX_CD8<32, CD8VF>;
3563 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3564 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3565 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3566 EVEX, EVEX_V512, VEX_W;
3567 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3568 !strconcat(OpcodeStr,
3569 "pd\t{$src, $dst|$dst, $src}"),
3570 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3571 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3572 } // isCodeGenOnly = 1
3575 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3576 Intrinsic F32Int, Intrinsic F64Int,
3577 OpndItins itins_s, OpndItins itins_d> {
3578 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3579 (ins FR32X:$src1, FR32X:$src2),
3580 !strconcat(OpcodeStr,
3581 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3582 [], itins_s.rr>, XS, EVEX_4V;
3583 let isCodeGenOnly = 1 in
3584 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3585 (ins VR128X:$src1, VR128X:$src2),
3586 !strconcat(OpcodeStr,
3587 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3589 (F32Int VR128X:$src1, VR128X:$src2))],
3590 itins_s.rr>, XS, EVEX_4V;
3591 let mayLoad = 1 in {
3592 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3593 (ins FR32X:$src1, f32mem:$src2),
3594 !strconcat(OpcodeStr,
3595 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3596 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3597 let isCodeGenOnly = 1 in
3598 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3599 (ins VR128X:$src1, ssmem:$src2),
3600 !strconcat(OpcodeStr,
3601 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3603 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3604 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3606 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3607 (ins FR64X:$src1, FR64X:$src2),
3608 !strconcat(OpcodeStr,
3609 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3611 let isCodeGenOnly = 1 in
3612 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3613 (ins VR128X:$src1, VR128X:$src2),
3614 !strconcat(OpcodeStr,
3615 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3617 (F64Int VR128X:$src1, VR128X:$src2))],
3618 itins_s.rr>, XD, EVEX_4V, VEX_W;
3619 let mayLoad = 1 in {
3620 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3621 (ins FR64X:$src1, f64mem:$src2),
3622 !strconcat(OpcodeStr,
3623 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3624 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3625 let isCodeGenOnly = 1 in
3626 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3627 (ins VR128X:$src1, sdmem:$src2),
3628 !strconcat(OpcodeStr,
3629 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3631 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3632 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3637 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3638 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3639 SSE_SQRTSS, SSE_SQRTSD>,
3640 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3641 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3642 SSE_SQRTPS, SSE_SQRTPD>;
3644 let Predicates = [HasAVX512] in {
3645 def : Pat<(f32 (fsqrt FR32X:$src)),
3646 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3647 def : Pat<(f32 (fsqrt (load addr:$src))),
3648 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3649 Requires<[OptForSize]>;
3650 def : Pat<(f64 (fsqrt FR64X:$src)),
3651 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3652 def : Pat<(f64 (fsqrt (load addr:$src))),
3653 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3654 Requires<[OptForSize]>;
3656 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3657 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3658 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3659 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3660 Requires<[OptForSize]>;
3662 def : Pat<(f32 (X86frcp FR32X:$src)),
3663 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3664 def : Pat<(f32 (X86frcp (load addr:$src))),
3665 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3666 Requires<[OptForSize]>;
3668 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3669 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3670 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3672 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3673 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3675 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3676 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3677 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3679 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3680 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3684 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3685 X86MemOperand x86memop, RegisterClass RC,
3686 PatFrag mem_frag32, PatFrag mem_frag64,
3687 Intrinsic V4F32Int, Intrinsic V2F64Int,
3689 let ExeDomain = SSEPackedSingle in {
3690 // Intrinsic operation, reg.
3691 // Vector intrinsic operation, reg
3692 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3693 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3694 !strconcat(OpcodeStr,
3695 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3696 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3698 // Vector intrinsic operation, mem
3699 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3700 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3701 !strconcat(OpcodeStr,
3702 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3704 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3705 EVEX_CD8<32, VForm>;
3706 } // ExeDomain = SSEPackedSingle
3708 let ExeDomain = SSEPackedDouble in {
3709 // Vector intrinsic operation, reg
3710 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3711 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3712 !strconcat(OpcodeStr,
3713 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3714 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3716 // Vector intrinsic operation, mem
3717 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3718 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3719 !strconcat(OpcodeStr,
3720 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3722 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3723 EVEX_CD8<64, VForm>;
3724 } // ExeDomain = SSEPackedDouble
3727 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3731 let ExeDomain = GenericDomain in {
3733 let hasSideEffects = 0 in
3734 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3735 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3736 !strconcat(OpcodeStr,
3737 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3740 // Intrinsic operation, reg.
3741 let isCodeGenOnly = 1 in
3742 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3743 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3744 !strconcat(OpcodeStr,
3745 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3746 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3748 // Intrinsic operation, mem.
3749 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3750 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3751 !strconcat(OpcodeStr,
3752 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3753 [(set VR128X:$dst, (F32Int VR128X:$src1,
3754 sse_load_f32:$src2, imm:$src3))]>,
3755 EVEX_CD8<32, CD8VT1>;
3758 let hasSideEffects = 0 in
3759 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3760 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3761 !strconcat(OpcodeStr,
3762 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3765 // Intrinsic operation, reg.
3766 let isCodeGenOnly = 1 in
3767 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3768 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3769 !strconcat(OpcodeStr,
3770 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3771 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3774 // Intrinsic operation, mem.
3775 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3776 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3777 !strconcat(OpcodeStr,
3778 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3780 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3781 VEX_W, EVEX_CD8<64, CD8VT1>;
3782 } // ExeDomain = GenericDomain
3785 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3786 X86MemOperand x86memop, RegisterClass RC,
3787 PatFrag mem_frag, Domain d> {
3788 let ExeDomain = d in {
3789 // Intrinsic operation, reg.
3790 // Vector intrinsic operation, reg
3791 def r : AVX512AIi8<opc, MRMSrcReg,
3792 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3793 !strconcat(OpcodeStr,
3794 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3797 // Vector intrinsic operation, mem
3798 def m : AVX512AIi8<opc, MRMSrcMem,
3799 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3800 !strconcat(OpcodeStr,
3801 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3807 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3808 memopv16f32, SSEPackedSingle>, EVEX_V512,
3809 EVEX_CD8<32, CD8VF>;
3811 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3812 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3814 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3817 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3818 memopv8f64, SSEPackedDouble>, EVEX_V512,
3819 VEX_W, EVEX_CD8<64, CD8VF>;
3821 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3822 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3824 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3826 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3827 Operand x86memop, RegisterClass RC, Domain d> {
3828 let ExeDomain = d in {
3829 def r : AVX512AIi8<opc, MRMSrcReg,
3830 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3831 !strconcat(OpcodeStr,
3832 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3835 def m : AVX512AIi8<opc, MRMSrcMem,
3836 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3837 !strconcat(OpcodeStr,
3838 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3843 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3844 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3846 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3847 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3849 def : Pat<(ffloor FR32X:$src),
3850 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3851 def : Pat<(f64 (ffloor FR64X:$src)),
3852 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3853 def : Pat<(f32 (fnearbyint FR32X:$src)),
3854 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3855 def : Pat<(f64 (fnearbyint FR64X:$src)),
3856 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3857 def : Pat<(f32 (fceil FR32X:$src)),
3858 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3859 def : Pat<(f64 (fceil FR64X:$src)),
3860 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3861 def : Pat<(f32 (frint FR32X:$src)),
3862 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3863 def : Pat<(f64 (frint FR64X:$src)),
3864 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3865 def : Pat<(f32 (ftrunc FR32X:$src)),
3866 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3867 def : Pat<(f64 (ftrunc FR64X:$src)),
3868 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3870 def : Pat<(v16f32 (ffloor VR512:$src)),
3871 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3872 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3873 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3874 def : Pat<(v16f32 (fceil VR512:$src)),
3875 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3876 def : Pat<(v16f32 (frint VR512:$src)),
3877 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3878 def : Pat<(v16f32 (ftrunc VR512:$src)),
3879 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3881 def : Pat<(v8f64 (ffloor VR512:$src)),
3882 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3883 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3884 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3885 def : Pat<(v8f64 (fceil VR512:$src)),
3886 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3887 def : Pat<(v8f64 (frint VR512:$src)),
3888 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3889 def : Pat<(v8f64 (ftrunc VR512:$src)),
3890 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3892 //-------------------------------------------------
3893 // Integer truncate and extend operations
3894 //-------------------------------------------------
3896 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3897 RegisterClass dstRC, RegisterClass srcRC,
3898 RegisterClass KRC, X86MemOperand x86memop> {
3899 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3901 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3904 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3905 (ins KRC:$mask, srcRC:$src),
3906 !strconcat(OpcodeStr,
3907 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
3910 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3911 (ins KRC:$mask, srcRC:$src),
3912 !strconcat(OpcodeStr,
3913 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3916 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3917 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3920 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
3921 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
3922 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
3926 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3927 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3928 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3929 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3930 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3931 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3932 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3933 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3934 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3935 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3936 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3937 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3938 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3939 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3940 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3941 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3942 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3943 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3944 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3945 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3946 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3947 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3948 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3949 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3950 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3951 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3952 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3953 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3954 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3955 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3957 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3958 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3959 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3960 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3961 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3963 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3964 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
3965 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3966 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
3967 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3968 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
3969 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3970 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
3973 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3974 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
3975 PatFrag mem_frag, X86MemOperand x86memop,
3976 ValueType OpVT, ValueType InVT> {
3978 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3980 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3981 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3983 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3984 (ins KRC:$mask, SrcRC:$src),
3985 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
3988 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3989 (ins KRC:$mask, SrcRC:$src),
3990 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
3993 let mayLoad = 1 in {
3994 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3995 (ins x86memop:$src),
3996 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3998 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4001 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4002 (ins KRC:$mask, x86memop:$src),
4003 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4007 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4008 (ins KRC:$mask, x86memop:$src),
4009 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4015 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4016 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4018 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4019 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4021 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4022 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4023 EVEX_CD8<16, CD8VH>;
4024 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4025 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4026 EVEX_CD8<16, CD8VQ>;
4027 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4028 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4029 EVEX_CD8<32, CD8VH>;
4031 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4032 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4034 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4035 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4037 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4038 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4039 EVEX_CD8<16, CD8VH>;
4040 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4041 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4042 EVEX_CD8<16, CD8VQ>;
4043 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4044 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4045 EVEX_CD8<32, CD8VH>;
4047 //===----------------------------------------------------------------------===//
4048 // GATHER - SCATTER Operations
4050 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4051 RegisterClass RC, X86MemOperand memop> {
4053 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4054 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4055 (ins RC:$src1, KRC:$mask, memop:$src2),
4056 !strconcat(OpcodeStr,
4057 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4061 let ExeDomain = SSEPackedDouble in {
4062 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4063 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4064 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4065 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4068 let ExeDomain = SSEPackedSingle in {
4069 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4070 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4071 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4072 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4075 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4076 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4077 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4078 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4080 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4081 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4082 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4083 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4085 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4086 RegisterClass RC, X86MemOperand memop> {
4087 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4088 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4089 (ins memop:$dst, KRC:$mask, RC:$src2),
4090 !strconcat(OpcodeStr,
4091 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4095 let ExeDomain = SSEPackedDouble in {
4096 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4097 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4098 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4099 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4102 let ExeDomain = SSEPackedSingle in {
4103 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4104 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4105 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4106 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4109 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4110 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4111 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4112 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4114 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4115 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4116 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4117 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4120 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4121 RegisterClass KRC, X86MemOperand memop> {
4122 let Predicates = [HasPFI], hasSideEffects = 1 in
4123 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4124 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4128 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4129 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4131 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4132 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4134 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4135 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4137 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4138 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4140 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4141 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4143 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4144 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4146 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4147 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4149 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4150 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4152 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4153 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4155 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4156 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4158 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4159 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4161 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4162 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4164 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4165 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4167 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4168 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4170 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4171 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4173 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4174 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4175 //===----------------------------------------------------------------------===//
4176 // VSHUFPS - VSHUFPD Operations
4178 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4179 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4181 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4182 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4183 !strconcat(OpcodeStr,
4184 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4185 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4186 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4187 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4188 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4189 (ins RC:$src1, RC:$src2, i8imm:$src3),
4190 !strconcat(OpcodeStr,
4191 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4192 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4193 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4194 EVEX_4V, Sched<[WriteShuffle]>;
4197 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4198 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4199 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4200 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4202 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4203 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4204 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4205 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4206 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4208 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4209 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4210 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4211 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4212 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4214 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4215 X86MemOperand x86memop> {
4216 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4217 (ins RC:$src1, RC:$src2, i8imm:$src3),
4218 !strconcat(OpcodeStr,
4219 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4222 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4223 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4224 !strconcat(OpcodeStr,
4225 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4228 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4229 EVEX_V512, EVEX_CD8<32, CD8VF>;
4230 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4231 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4233 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4234 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4235 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4236 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4237 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4238 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4239 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4240 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4242 // Helper fragments to match sext vXi1 to vXiY.
4243 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4244 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4246 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4247 RegisterClass KRC, RegisterClass RC,
4248 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4250 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4251 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4253 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4254 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4256 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4257 !strconcat(OpcodeStr,
4258 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4260 let mayLoad = 1 in {
4261 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4262 (ins x86memop:$src),
4263 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4265 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4266 (ins KRC:$mask, x86memop:$src),
4267 !strconcat(OpcodeStr,
4268 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4270 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4271 (ins KRC:$mask, x86memop:$src),
4272 !strconcat(OpcodeStr,
4273 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4275 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4276 (ins x86scalar_mop:$src),
4277 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4278 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4280 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4281 (ins KRC:$mask, x86scalar_mop:$src),
4282 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4283 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4284 []>, EVEX, EVEX_B, EVEX_K;
4285 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4286 (ins KRC:$mask, x86scalar_mop:$src),
4287 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4288 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4290 []>, EVEX, EVEX_B, EVEX_KZ;
4294 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4295 i512mem, i32mem, "{1to16}">, EVEX_V512,
4296 EVEX_CD8<32, CD8VF>;
4297 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4298 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4299 EVEX_CD8<64, CD8VF>;
4302 (bc_v16i32 (v16i1sextv16i32)),
4303 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4304 (VPABSDZrr VR512:$src)>;
4306 (bc_v8i64 (v8i1sextv8i64)),
4307 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4308 (VPABSQZrr VR512:$src)>;
4310 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4311 (v16i32 immAllZerosV), (i16 -1))),
4312 (VPABSDZrr VR512:$src)>;
4313 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4314 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4315 (VPABSQZrr VR512:$src)>;
4317 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4318 RegisterClass RC, RegisterClass KRC,
4319 X86MemOperand x86memop,
4320 X86MemOperand x86scalar_mop, string BrdcstStr> {
4321 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4323 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4325 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4326 (ins x86memop:$src),
4327 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4329 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4330 (ins x86scalar_mop:$src),
4331 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4332 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4334 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4335 (ins KRC:$mask, RC:$src),
4336 !strconcat(OpcodeStr,
4337 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4339 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4340 (ins KRC:$mask, x86memop:$src),
4341 !strconcat(OpcodeStr,
4342 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4344 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4345 (ins KRC:$mask, x86scalar_mop:$src),
4346 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4347 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4349 []>, EVEX, EVEX_KZ, EVEX_B;
4351 let Constraints = "$src1 = $dst" in {
4352 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4353 (ins RC:$src1, KRC:$mask, RC:$src2),
4354 !strconcat(OpcodeStr,
4355 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4357 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4358 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4359 !strconcat(OpcodeStr,
4360 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4362 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4363 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4364 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4365 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4366 []>, EVEX, EVEX_K, EVEX_B;
4370 let Predicates = [HasCDI] in {
4371 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4372 i512mem, i32mem, "{1to16}">,
4373 EVEX_V512, EVEX_CD8<32, CD8VF>;
4376 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4377 i512mem, i64mem, "{1to8}">,
4378 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4382 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4384 (VPCONFLICTDrrk VR512:$src1,
4385 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4387 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4389 (VPCONFLICTQrrk VR512:$src1,
4390 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4392 let Predicates = [HasCDI] in {
4393 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4394 i512mem, i32mem, "{1to16}">,
4395 EVEX_V512, EVEX_CD8<32, CD8VF>;
4398 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4399 i512mem, i64mem, "{1to8}">,
4400 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4404 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4406 (VPLZCNTDrrk VR512:$src1,
4407 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4409 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4411 (VPLZCNTQrrk VR512:$src1,
4412 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4414 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4415 (VPLZCNTDrm addr:$src)>;
4416 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4417 (VPLZCNTDrr VR512:$src)>;
4418 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4419 (VPLZCNTQrm addr:$src)>;
4420 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4421 (VPLZCNTQrr VR512:$src)>;
4423 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4424 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4425 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4427 def : Pat<(store VK1:$src, addr:$dst),
4428 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4430 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4431 (truncstore node:$val, node:$ptr), [{
4432 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4435 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4436 (MOV8mr addr:$dst, GR8:$src)>;