1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // Codegen pattern for the alternative types
681 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
682 X86VectorVTInfo To, PatFrag vextract_extract,
683 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
684 vextract_for_size_first_position_lowering<From, To> {
686 let Predicates = p in
687 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
688 (To.VT (!cast<Instruction>(InstrStr#"rr")
690 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
693 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
694 ValueType EltVT64, int Opcode256> {
695 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
696 X86VectorVTInfo<16, EltVT32, VR512>,
697 X86VectorVTInfo< 4, EltVT32, VR128X>,
698 vextract128_extract>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
701 X86VectorVTInfo< 8, EltVT64, VR512>,
702 X86VectorVTInfo< 4, EltVT64, VR256X>,
703 vextract256_extract>,
704 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
705 let Predicates = [HasVLX] in
706 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
707 X86VectorVTInfo< 8, EltVT32, VR256X>,
708 X86VectorVTInfo< 4, EltVT32, VR128X>,
709 vextract128_extract>,
710 EVEX_V256, EVEX_CD8<32, CD8VT4>;
711 let Predicates = [HasVLX, HasDQI] in
712 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo< 2, EltVT64, VR128X>,
715 vextract128_extract>,
716 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
717 let Predicates = [HasDQI] in {
718 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
719 X86VectorVTInfo< 8, EltVT64, VR512>,
720 X86VectorVTInfo< 2, EltVT64, VR128X>,
721 vextract128_extract>,
722 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
723 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
724 X86VectorVTInfo<16, EltVT32, VR512>,
725 X86VectorVTInfo< 8, EltVT32, VR256X>,
726 vextract256_extract>,
727 EVEX_V512, EVEX_CD8<32, CD8VT8>;
731 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
732 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
734 // extract_subvector codegen patterns with the alternative types.
735 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
736 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
737 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
738 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
739 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
741 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
742 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
743 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
744 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
746 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
747 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
748 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
749 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
751 // Codegen pattern with the alternative types extract VEC128 from VEC512
752 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
756 // Codegen pattern with the alternative types extract VEC256 from VEC512
757 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
762 // A 128-bit subvector insert to the first 512-bit vector position
763 // is a subregister copy that needs no instruction.
764 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
765 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
766 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
768 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
769 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
770 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
772 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
774 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
776 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
778 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
781 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
782 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
783 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
784 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
785 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
786 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
787 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
789 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
790 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
791 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
792 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
794 // vextractps - extract 32 bits from XMM
795 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
796 (ins VR128X:$src1, u8imm:$src2),
797 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
798 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
801 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
802 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
803 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
805 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
807 //===---------------------------------------------------------------------===//
811 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
812 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
814 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
815 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
816 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
819 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
820 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
821 (DestInfo.VT (X86VBroadcast
822 (SrcInfo.ScalarLdFrag addr:$src)))>,
823 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
826 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
827 AVX512VLVectorVTInfo _> {
828 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
831 let Predicates = [HasVLX] in {
832 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
837 let ExeDomain = SSEPackedSingle in {
838 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
840 let Predicates = [HasVLX] in {
841 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
842 v4f32x_info, v4f32x_info>, EVEX_V128;
846 let ExeDomain = SSEPackedDouble in {
847 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
848 avx512vl_f64_info>, VEX_W;
851 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
852 // Later, we can canonize broadcast instructions before ISel phase and
853 // eliminate additional patterns on ISel.
854 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
855 // representations of source
856 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
857 X86VectorVTInfo _, RegisterClass SrcRC_v,
858 RegisterClass SrcRC_s> {
859 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
860 (!cast<Instruction>(InstName##"r")
861 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
863 let AddedComplexity = 30 in {
864 def : Pat<(_.VT (vselect _.KRCWM:$mask,
865 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
866 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
867 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
869 def : Pat<(_.VT(vselect _.KRCWM:$mask,
870 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
871 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
872 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
876 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
878 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
881 let Predicates = [HasVLX] in {
882 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
883 v8f32x_info, VR128X, FR32X>;
884 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
885 v4f32x_info, VR128X, FR32X>;
886 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
887 v4f64x_info, VR128X, FR64X>;
890 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
891 (VBROADCASTSSZm addr:$src)>;
892 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
893 (VBROADCASTSDZm addr:$src)>;
895 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
896 (VBROADCASTSSZm addr:$src)>;
897 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
898 (VBROADCASTSDZm addr:$src)>;
900 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
901 RegisterClass SrcRC> {
902 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
903 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
904 "$src", "$src", []>, T8PD, EVEX;
907 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
908 RegisterClass SrcRC, Predicate prd> {
909 let Predicates = [prd] in
910 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
911 let Predicates = [prd, HasVLX] in {
912 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
913 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
917 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
919 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
921 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
923 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
926 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
927 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
929 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
930 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
932 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
933 (VPBROADCASTDrZr GR32:$src)>;
934 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
935 (VPBROADCASTQrZr GR64:$src)>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
938 (VPBROADCASTDrZr GR32:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
940 (VPBROADCASTQrZr GR64:$src)>;
942 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
943 (v16i32 immAllZerosV), (i16 GR16:$mask))),
944 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
945 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
946 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
947 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
949 // Provide aliases for broadcast from the same register class that
950 // automatically does the extract.
951 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
952 X86VectorVTInfo SrcInfo> {
953 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
954 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
955 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
958 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
959 AVX512VLVectorVTInfo _, Predicate prd> {
960 let Predicates = [prd] in {
961 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
962 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
964 // Defined separately to avoid redefinition.
965 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
967 let Predicates = [prd, HasVLX] in {
968 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
969 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
971 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
976 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
977 avx512vl_i8_info, HasBWI>;
978 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
979 avx512vl_i16_info, HasBWI>;
980 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
981 avx512vl_i32_info, HasAVX512>;
982 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
983 avx512vl_i64_info, HasAVX512>, VEX_W;
985 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
986 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
988 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
991 (_Dst.VT (X86SubVBroadcast
992 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
993 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
995 !strconcat(OpcodeStr,
996 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
998 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1000 !strconcat(OpcodeStr,
1001 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1006 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1007 v16i32_info, v4i32x_info>,
1008 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1009 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1010 v16f32_info, v4f32x_info>,
1011 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1012 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1013 v8i64_info, v4i64x_info>, VEX_W,
1014 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1015 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1016 v8f64_info, v4f64x_info>, VEX_W,
1017 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1019 let Predicates = [HasVLX] in {
1020 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1021 v8i32x_info, v4i32x_info>,
1022 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1023 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1024 v8f32x_info, v4f32x_info>,
1025 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1027 let Predicates = [HasVLX, HasDQI] in {
1028 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1029 v4i64x_info, v2i64x_info>, VEX_W,
1030 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1031 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1032 v4f64x_info, v2f64x_info>, VEX_W,
1033 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1035 let Predicates = [HasDQI] in {
1036 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1037 v8i64_info, v2i64x_info>, VEX_W,
1038 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1039 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1040 v16i32_info, v8i32x_info>,
1041 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1042 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1043 v8f64_info, v2f64x_info>, VEX_W,
1044 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1045 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1046 v16f32_info, v8f32x_info>,
1047 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1050 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1051 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1052 SDNode OpNode = X86SubVBroadcast> {
1054 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1055 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1056 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1059 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1062 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1063 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1066 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1067 AVX512VLVectorVTInfo _> {
1068 let Predicates = [HasDQI] in
1069 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1071 let Predicates = [HasDQI, HasVLX] in
1072 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1076 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1077 AVX512VLVectorVTInfo _> :
1078 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1080 let Predicates = [HasDQI, HasVLX] in
1081 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1082 X86SubV32x2Broadcast>, EVEX_V128;
1085 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1087 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1090 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1091 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1092 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1093 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1095 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1096 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1097 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1098 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1101 (VBROADCASTSSZr VR128X:$src)>;
1102 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1103 (VBROADCASTSDZr VR128X:$src)>;
1105 // Provide fallback in case the load node that is used in the patterns above
1106 // is used by additional users, which prevents the pattern selection.
1107 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1108 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1109 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1110 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1113 //===----------------------------------------------------------------------===//
1114 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1117 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1118 RegisterClass KRC> {
1119 let Predicates = [HasCDI] in
1120 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
1121 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1122 []>, EVEX, EVEX_V512;
1124 let Predicates = [HasCDI, HasVLX] in {
1125 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128X:$dst), (ins KRC:$src),
1126 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1127 []>, EVEX, EVEX_V128;
1128 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256X:$dst), (ins KRC:$src),
1129 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1130 []>, EVEX, EVEX_V256;
1134 let Predicates = [HasCDI] in {
1135 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1137 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1141 //===----------------------------------------------------------------------===//
1142 // -- VPERM2I - 3 source operands form --
1143 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1144 SDNode OpNode, X86VectorVTInfo _> {
1145 let Constraints = "$src1 = $dst" in {
1146 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1147 (ins _.RC:$src2, _.RC:$src3),
1148 OpcodeStr, "$src3, $src2", "$src2, $src3",
1149 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1153 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1154 (ins _.RC:$src2, _.MemOp:$src3),
1155 OpcodeStr, "$src3, $src2", "$src2, $src3",
1156 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1157 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1158 EVEX_4V, AVX5128IBase;
1161 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1162 SDNode OpNode, X86VectorVTInfo _> {
1163 let mayLoad = 1, Constraints = "$src1 = $dst" in
1164 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1165 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1166 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1167 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1168 (_.VT (OpNode _.RC:$src1,
1169 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1170 AVX5128IBase, EVEX_4V, EVEX_B;
1173 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1174 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1175 let Predicates = [HasAVX512] in
1176 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1177 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1178 let Predicates = [HasVLX] in {
1179 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1180 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1182 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1183 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1187 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1188 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1189 let Predicates = [HasBWI] in
1190 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1191 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1193 let Predicates = [HasBWI, HasVLX] in {
1194 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1195 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1197 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1198 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1202 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1203 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1204 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1205 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1206 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1207 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1208 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1209 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1211 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1212 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1213 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1214 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1215 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1216 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1217 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1218 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1220 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1221 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1222 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1223 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1225 //===----------------------------------------------------------------------===//
1226 // AVX-512 - BLEND using mask
1228 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1229 let ExeDomain = _.ExeDomain in {
1230 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1231 (ins _.RC:$src1, _.RC:$src2),
1232 !strconcat(OpcodeStr,
1233 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1235 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1236 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1237 !strconcat(OpcodeStr,
1238 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1239 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1240 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1241 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1242 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1243 !strconcat(OpcodeStr,
1244 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1245 []>, EVEX_4V, EVEX_KZ;
1246 let mayLoad = 1 in {
1247 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1248 (ins _.RC:$src1, _.MemOp:$src2),
1249 !strconcat(OpcodeStr,
1250 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1251 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1252 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1253 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1254 !strconcat(OpcodeStr,
1255 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1256 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1257 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1258 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1259 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1260 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1261 !strconcat(OpcodeStr,
1262 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1263 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1267 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1269 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1270 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1271 !strconcat(OpcodeStr,
1272 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1273 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1274 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1275 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1276 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1278 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1279 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1280 !strconcat(OpcodeStr,
1281 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1282 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1283 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1287 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1288 AVX512VLVectorVTInfo VTInfo> {
1289 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1290 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1292 let Predicates = [HasVLX] in {
1293 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1294 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1295 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1296 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1300 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1301 AVX512VLVectorVTInfo VTInfo> {
1302 let Predicates = [HasBWI] in
1303 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1305 let Predicates = [HasBWI, HasVLX] in {
1306 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1307 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1312 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1313 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1314 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1315 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1316 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1317 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1320 let Predicates = [HasAVX512] in {
1321 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1322 (v8f32 VR256X:$src2))),
1324 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1325 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1326 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1328 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1329 (v8i32 VR256X:$src2))),
1331 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1332 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1333 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1335 //===----------------------------------------------------------------------===//
1336 // Compare Instructions
1337 //===----------------------------------------------------------------------===//
1339 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1341 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1343 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1345 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1346 "vcmp${cc}"#_.Suffix,
1347 "$src2, $src1", "$src1, $src2",
1348 (OpNode (_.VT _.RC:$src1),
1352 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1354 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1355 "vcmp${cc}"#_.Suffix,
1356 "$src2, $src1", "$src1, $src2",
1357 (OpNode (_.VT _.RC:$src1),
1358 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1359 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1361 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1363 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1364 "vcmp${cc}"#_.Suffix,
1365 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1366 (OpNodeRnd (_.VT _.RC:$src1),
1369 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1370 // Accept explicit immediate argument form instead of comparison code.
1371 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1372 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1374 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1376 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1377 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1379 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1381 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1382 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1384 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1386 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1388 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1390 }// let isAsmParserOnly = 1, hasSideEffects = 0
1392 let isCodeGenOnly = 1 in {
1393 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1394 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1395 !strconcat("vcmp${cc}", _.Suffix,
1396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1397 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1400 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1402 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1404 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1405 !strconcat("vcmp${cc}", _.Suffix,
1406 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1407 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1408 (_.ScalarLdFrag addr:$src2),
1410 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1414 let Predicates = [HasAVX512] in {
1415 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1417 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1418 AVX512XDIi8Base, VEX_W;
1421 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1422 X86VectorVTInfo _> {
1423 def rr : AVX512BI<opc, MRMSrcReg,
1424 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1425 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1426 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1427 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1429 def rm : AVX512BI<opc, MRMSrcMem,
1430 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1431 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1432 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1433 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1434 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1435 def rrk : AVX512BI<opc, MRMSrcReg,
1436 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1437 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1438 "$dst {${mask}}, $src1, $src2}"),
1439 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1440 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1441 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1443 def rmk : AVX512BI<opc, MRMSrcMem,
1444 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1445 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1446 "$dst {${mask}}, $src1, $src2}"),
1447 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1448 (OpNode (_.VT _.RC:$src1),
1450 (_.LdFrag addr:$src2))))))],
1451 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1454 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1455 X86VectorVTInfo _> :
1456 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1457 let mayLoad = 1 in {
1458 def rmb : AVX512BI<opc, MRMSrcMem,
1459 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1460 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1461 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1462 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1463 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1464 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1465 def rmbk : AVX512BI<opc, MRMSrcMem,
1466 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1467 _.ScalarMemOp:$src2),
1468 !strconcat(OpcodeStr,
1469 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1470 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1471 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1472 (OpNode (_.VT _.RC:$src1),
1474 (_.ScalarLdFrag addr:$src2)))))],
1475 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1479 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1480 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1481 let Predicates = [prd] in
1482 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1485 let Predicates = [prd, HasVLX] in {
1486 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1488 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1493 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1494 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1496 let Predicates = [prd] in
1497 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1500 let Predicates = [prd, HasVLX] in {
1501 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1503 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1508 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1509 avx512vl_i8_info, HasBWI>,
1512 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1513 avx512vl_i16_info, HasBWI>,
1514 EVEX_CD8<16, CD8VF>;
1516 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1517 avx512vl_i32_info, HasAVX512>,
1518 EVEX_CD8<32, CD8VF>;
1520 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1521 avx512vl_i64_info, HasAVX512>,
1522 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1524 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1525 avx512vl_i8_info, HasBWI>,
1528 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1529 avx512vl_i16_info, HasBWI>,
1530 EVEX_CD8<16, CD8VF>;
1532 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1533 avx512vl_i32_info, HasAVX512>,
1534 EVEX_CD8<32, CD8VF>;
1536 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1537 avx512vl_i64_info, HasAVX512>,
1538 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1540 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1541 (COPY_TO_REGCLASS (VPCMPGTDZrr
1542 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1543 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1545 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1546 (COPY_TO_REGCLASS (VPCMPEQDZrr
1547 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1548 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1550 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1551 X86VectorVTInfo _> {
1552 def rri : AVX512AIi8<opc, MRMSrcReg,
1553 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1554 !strconcat("vpcmp${cc}", Suffix,
1555 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1556 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1558 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1560 def rmi : AVX512AIi8<opc, MRMSrcMem,
1561 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1562 !strconcat("vpcmp${cc}", Suffix,
1563 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1564 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1565 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1567 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1568 def rrik : AVX512AIi8<opc, MRMSrcReg,
1569 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1571 !strconcat("vpcmp${cc}", Suffix,
1572 "\t{$src2, $src1, $dst {${mask}}|",
1573 "$dst {${mask}}, $src1, $src2}"),
1574 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1575 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1577 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1579 def rmik : AVX512AIi8<opc, MRMSrcMem,
1580 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1582 !strconcat("vpcmp${cc}", Suffix,
1583 "\t{$src2, $src1, $dst {${mask}}|",
1584 "$dst {${mask}}, $src1, $src2}"),
1585 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1586 (OpNode (_.VT _.RC:$src1),
1587 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1589 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1591 // Accept explicit immediate argument form instead of comparison code.
1592 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1593 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1594 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1595 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1596 "$dst, $src1, $src2, $cc}"),
1597 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1599 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1600 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1601 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1602 "$dst, $src1, $src2, $cc}"),
1603 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1604 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1605 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1607 !strconcat("vpcmp", Suffix,
1608 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1609 "$dst {${mask}}, $src1, $src2, $cc}"),
1610 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1612 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1613 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1615 !strconcat("vpcmp", Suffix,
1616 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1617 "$dst {${mask}}, $src1, $src2, $cc}"),
1618 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1622 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1623 X86VectorVTInfo _> :
1624 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1625 def rmib : AVX512AIi8<opc, MRMSrcMem,
1626 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1628 !strconcat("vpcmp${cc}", Suffix,
1629 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1630 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1631 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1632 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1634 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1635 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1636 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1637 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1638 !strconcat("vpcmp${cc}", Suffix,
1639 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1640 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1641 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1642 (OpNode (_.VT _.RC:$src1),
1643 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1645 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1647 // Accept explicit immediate argument form instead of comparison code.
1648 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1649 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1650 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1652 !strconcat("vpcmp", Suffix,
1653 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1654 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1655 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1656 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1657 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1658 _.ScalarMemOp:$src2, u8imm:$cc),
1659 !strconcat("vpcmp", Suffix,
1660 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1661 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1662 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1666 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1667 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1668 let Predicates = [prd] in
1669 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1671 let Predicates = [prd, HasVLX] in {
1672 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1673 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1677 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1678 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1679 let Predicates = [prd] in
1680 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1683 let Predicates = [prd, HasVLX] in {
1684 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1686 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1691 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1692 HasBWI>, EVEX_CD8<8, CD8VF>;
1693 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1694 HasBWI>, EVEX_CD8<8, CD8VF>;
1696 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1697 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1698 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1699 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1701 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1702 HasAVX512>, EVEX_CD8<32, CD8VF>;
1703 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1704 HasAVX512>, EVEX_CD8<32, CD8VF>;
1706 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1707 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1708 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1709 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1711 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1713 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1714 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1715 "vcmp${cc}"#_.Suffix,
1716 "$src2, $src1", "$src1, $src2",
1717 (X86cmpm (_.VT _.RC:$src1),
1721 let mayLoad = 1 in {
1722 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1723 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1724 "vcmp${cc}"#_.Suffix,
1725 "$src2, $src1", "$src1, $src2",
1726 (X86cmpm (_.VT _.RC:$src1),
1727 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1730 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1732 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1733 "vcmp${cc}"#_.Suffix,
1734 "${src2}"##_.BroadcastStr##", $src1",
1735 "$src1, ${src2}"##_.BroadcastStr,
1736 (X86cmpm (_.VT _.RC:$src1),
1737 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1740 // Accept explicit immediate argument form instead of comparison code.
1741 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1742 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1744 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1746 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1748 let mayLoad = 1 in {
1749 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1751 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1753 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1755 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1757 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1759 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1760 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1765 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1766 // comparison code form (VCMP[EQ/LT/LE/...]
1767 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1768 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1769 "vcmp${cc}"#_.Suffix,
1770 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1771 (X86cmpmRnd (_.VT _.RC:$src1),
1774 (i32 FROUND_NO_EXC))>, EVEX_B;
1776 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1777 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1779 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1781 "$cc,{sae}, $src2, $src1",
1782 "$src1, $src2,{sae}, $cc">, EVEX_B;
1786 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1787 let Predicates = [HasAVX512] in {
1788 defm Z : avx512_vcmp_common<_.info512>,
1789 avx512_vcmp_sae<_.info512>, EVEX_V512;
1792 let Predicates = [HasAVX512,HasVLX] in {
1793 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1794 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1798 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1799 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1800 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1801 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1803 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1804 (COPY_TO_REGCLASS (VCMPPSZrri
1805 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1806 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1808 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1809 (COPY_TO_REGCLASS (VPCMPDZrri
1810 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1811 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1813 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1814 (COPY_TO_REGCLASS (VPCMPUDZrri
1815 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1816 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1819 // ----------------------------------------------------------------
1821 //handle fpclass instruction mask = op(reg_scalar,imm)
1822 // op(mem_scalar,imm)
1823 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1824 X86VectorVTInfo _, Predicate prd> {
1825 let Predicates = [prd] in {
1826 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1827 (ins _.RC:$src1, i32u8imm:$src2),
1828 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1829 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1830 (i32 imm:$src2)))], NoItinerary>;
1831 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1832 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1833 OpcodeStr##_.Suffix#
1834 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1835 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1836 (OpNode (_.VT _.RC:$src1),
1837 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1838 let mayLoad = 1, AddedComplexity = 20 in {
1839 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1840 (ins _.MemOp:$src1, i32u8imm:$src2),
1841 OpcodeStr##_.Suffix##
1842 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1844 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1845 (i32 imm:$src2)))], NoItinerary>;
1846 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1847 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1848 OpcodeStr##_.Suffix##
1849 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1850 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1851 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1852 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1857 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1858 // fpclass(reg_vec, mem_vec, imm)
1859 // fpclass(reg_vec, broadcast(eltVt), imm)
1860 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1861 X86VectorVTInfo _, string mem, string broadcast>{
1862 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1863 (ins _.RC:$src1, i32u8imm:$src2),
1864 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1865 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1866 (i32 imm:$src2)))], NoItinerary>;
1867 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1868 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1869 OpcodeStr##_.Suffix#
1870 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1871 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1872 (OpNode (_.VT _.RC:$src1),
1873 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1874 let mayLoad = 1 in {
1875 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1876 (ins _.MemOp:$src1, i32u8imm:$src2),
1877 OpcodeStr##_.Suffix##mem#
1878 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1879 [(set _.KRC:$dst,(OpNode
1880 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1881 (i32 imm:$src2)))], NoItinerary>;
1882 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1883 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1884 OpcodeStr##_.Suffix##mem#
1885 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1886 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1887 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1888 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1889 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1890 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1891 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1892 _.BroadcastStr##", $dst | $dst, ${src1}"
1893 ##_.BroadcastStr##", $src2}",
1894 [(set _.KRC:$dst,(OpNode
1895 (_.VT (X86VBroadcast
1896 (_.ScalarLdFrag addr:$src1))),
1897 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1898 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1899 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1900 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1901 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1902 _.BroadcastStr##", $src2}",
1903 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1904 (_.VT (X86VBroadcast
1905 (_.ScalarLdFrag addr:$src1))),
1906 (i32 imm:$src2))))], NoItinerary>,
1911 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1912 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1914 let Predicates = [prd] in {
1915 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1916 broadcast>, EVEX_V512;
1918 let Predicates = [prd, HasVLX] in {
1919 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1920 broadcast>, EVEX_V128;
1921 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1922 broadcast>, EVEX_V256;
1926 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1927 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1928 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1929 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1930 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1931 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1932 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1933 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1934 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1935 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
1938 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
1939 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
1941 //-----------------------------------------------------------------
1942 // Mask register copy, including
1943 // - copy between mask registers
1944 // - load/store mask registers
1945 // - copy from GPR to mask register and vice versa
1947 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1948 string OpcodeStr, RegisterClass KRC,
1949 ValueType vvt, X86MemOperand x86memop> {
1950 let hasSideEffects = 0 in {
1951 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1952 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1954 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1956 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1958 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1959 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1960 [(store KRC:$src, addr:$dst)]>;
1964 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1966 RegisterClass KRC, RegisterClass GRC> {
1967 let hasSideEffects = 0 in {
1968 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1969 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1970 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1971 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1975 let Predicates = [HasDQI] in
1976 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1977 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1980 let Predicates = [HasAVX512] in
1981 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1982 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1985 let Predicates = [HasBWI] in {
1986 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1988 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1992 let Predicates = [HasBWI] in {
1993 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1995 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1999 // GR from/to mask register
2000 let Predicates = [HasDQI] in {
2001 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2002 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2003 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2004 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2006 let Predicates = [HasAVX512] in {
2007 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2008 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2009 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2010 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2012 let Predicates = [HasBWI] in {
2013 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2014 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2016 let Predicates = [HasBWI] in {
2017 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2018 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2022 let Predicates = [HasDQI] in {
2023 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2024 (KMOVBmk addr:$dst, VK8:$src)>;
2025 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2026 (KMOVBkm addr:$src)>;
2028 def : Pat<(store VK4:$src, addr:$dst),
2029 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2030 def : Pat<(store VK2:$src, addr:$dst),
2031 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2033 let Predicates = [HasAVX512, NoDQI] in {
2034 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2035 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2036 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2037 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2039 let Predicates = [HasAVX512] in {
2040 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2041 (KMOVWmk addr:$dst, VK16:$src)>;
2042 def : Pat<(i1 (load addr:$src)),
2043 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2044 (MOV8rm addr:$src), sub_8bit)),
2046 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2047 (KMOVWkm addr:$src)>;
2049 let Predicates = [HasBWI] in {
2050 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2051 (KMOVDmk addr:$dst, VK32:$src)>;
2052 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2053 (KMOVDkm addr:$src)>;
2055 let Predicates = [HasBWI] in {
2056 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2057 (KMOVQmk addr:$dst, VK64:$src)>;
2058 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2059 (KMOVQkm addr:$src)>;
2062 let Predicates = [HasAVX512] in {
2063 def : Pat<(i1 (trunc (i64 GR64:$src))),
2064 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2067 def : Pat<(i1 (trunc (i32 GR32:$src))),
2068 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2070 def : Pat<(i1 (trunc (i8 GR8:$src))),
2072 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2074 def : Pat<(i1 (trunc (i16 GR16:$src))),
2076 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2079 def : Pat<(i32 (zext VK1:$src)),
2080 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2081 def : Pat<(i32 (anyext VK1:$src)),
2082 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2084 def : Pat<(i8 (zext VK1:$src)),
2087 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2088 def : Pat<(i8 (anyext VK1:$src)),
2090 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2092 def : Pat<(i64 (zext VK1:$src)),
2093 (AND64ri8 (SUBREG_TO_REG (i64 0),
2094 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2095 def : Pat<(i16 (zext VK1:$src)),
2097 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2099 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2100 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2101 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2102 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2104 let Predicates = [HasBWI] in {
2105 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2106 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2107 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2108 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2112 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2113 let Predicates = [HasAVX512, NoDQI] in {
2114 // GR from/to 8-bit mask without native support
2115 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2117 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2118 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2120 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2124 let Predicates = [HasAVX512] in {
2125 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2126 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2127 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2128 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2130 let Predicates = [HasBWI] in {
2131 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2132 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2133 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2134 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2137 // Mask unary operation
2139 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2140 RegisterClass KRC, SDPatternOperator OpNode,
2142 let Predicates = [prd] in
2143 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2144 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2145 [(set KRC:$dst, (OpNode KRC:$src))]>;
2148 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2149 SDPatternOperator OpNode> {
2150 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2152 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2153 HasAVX512>, VEX, PS;
2154 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2155 HasBWI>, VEX, PD, VEX_W;
2156 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2157 HasBWI>, VEX, PS, VEX_W;
2160 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2162 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2163 let Predicates = [HasAVX512] in
2164 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2166 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2167 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2169 defm : avx512_mask_unop_int<"knot", "KNOT">;
2171 let Predicates = [HasDQI] in
2172 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2173 let Predicates = [HasAVX512] in
2174 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2175 let Predicates = [HasBWI] in
2176 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2177 let Predicates = [HasBWI] in
2178 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2180 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2181 let Predicates = [HasAVX512, NoDQI] in {
2182 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2183 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2184 def : Pat<(not VK8:$src),
2186 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2188 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2189 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2190 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2191 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2193 // Mask binary operation
2194 // - KAND, KANDN, KOR, KXNOR, KXOR
2195 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2196 RegisterClass KRC, SDPatternOperator OpNode,
2197 Predicate prd, bit IsCommutable> {
2198 let Predicates = [prd], isCommutable = IsCommutable in
2199 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2200 !strconcat(OpcodeStr,
2201 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2202 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2205 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2206 SDPatternOperator OpNode, bit IsCommutable,
2207 Predicate prdW = HasAVX512> {
2208 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2209 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2210 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2211 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2212 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2213 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2214 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2215 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2218 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2219 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2221 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2222 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2223 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2224 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2225 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2226 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2228 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2229 let Predicates = [HasAVX512] in
2230 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2231 (i16 GR16:$src1), (i16 GR16:$src2)),
2232 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2233 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2234 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2237 defm : avx512_mask_binop_int<"kand", "KAND">;
2238 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2239 defm : avx512_mask_binop_int<"kor", "KOR">;
2240 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2241 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2243 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2244 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2245 // for the DQI set, this type is legal and KxxxB instruction is used
2246 let Predicates = [NoDQI] in
2247 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2249 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2250 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2252 // All types smaller than 8 bits require conversion anyway
2253 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2254 (COPY_TO_REGCLASS (Inst
2255 (COPY_TO_REGCLASS VK1:$src1, VK16),
2256 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2257 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2258 (COPY_TO_REGCLASS (Inst
2259 (COPY_TO_REGCLASS VK2:$src1, VK16),
2260 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2261 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2262 (COPY_TO_REGCLASS (Inst
2263 (COPY_TO_REGCLASS VK4:$src1, VK16),
2264 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2267 defm : avx512_binop_pat<and, KANDWrr>;
2268 defm : avx512_binop_pat<andn, KANDNWrr>;
2269 defm : avx512_binop_pat<or, KORWrr>;
2270 defm : avx512_binop_pat<xnor, KXNORWrr>;
2271 defm : avx512_binop_pat<xor, KXORWrr>;
2273 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2274 (KXNORWrr VK16:$src1, VK16:$src2)>;
2275 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2276 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2277 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2278 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2279 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2280 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2282 let Predicates = [NoDQI] in
2283 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2284 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2285 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2287 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2288 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2289 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2291 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2292 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2293 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2295 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2296 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2297 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2300 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2301 RegisterClass KRCSrc, Predicate prd> {
2302 let Predicates = [prd] in {
2303 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2304 (ins KRC:$src1, KRC:$src2),
2305 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2308 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2309 (!cast<Instruction>(NAME##rr)
2310 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2311 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2315 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2316 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2317 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2319 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2320 let Predicates = [HasAVX512] in
2321 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2322 (i16 GR16:$src1), (i16 GR16:$src2)),
2323 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2324 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2325 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2327 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2330 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2331 SDNode OpNode, Predicate prd> {
2332 let Predicates = [prd], Defs = [EFLAGS] in
2333 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2334 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2335 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2338 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2339 Predicate prdW = HasAVX512> {
2340 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2342 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2344 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2346 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2350 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2351 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2354 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2356 let Predicates = [HasAVX512] in
2357 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2358 !strconcat(OpcodeStr,
2359 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2360 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2363 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2365 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2367 let Predicates = [HasDQI] in
2368 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2370 let Predicates = [HasBWI] in {
2371 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2373 let Predicates = [HasDQI] in
2374 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2379 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2380 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2382 // Mask setting all 0s or 1s
2383 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2384 let Predicates = [HasAVX512] in
2385 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2386 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2387 [(set KRC:$dst, (VT Val))]>;
2390 multiclass avx512_mask_setop_w<PatFrag Val> {
2391 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2392 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2393 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2394 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2397 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2398 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2400 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2401 let Predicates = [HasAVX512] in {
2402 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2403 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2404 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2405 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2406 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2407 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2408 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2410 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2411 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2413 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2414 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2416 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2417 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2419 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2420 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2422 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2423 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2425 let Predicates = [HasVLX] in {
2426 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2427 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2428 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2429 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2430 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2431 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2432 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2433 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2434 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2435 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2438 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2439 (v8i1 (COPY_TO_REGCLASS
2440 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2441 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2443 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2444 (v8i1 (COPY_TO_REGCLASS
2445 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2446 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2448 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2449 (v4i1 (COPY_TO_REGCLASS
2450 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2451 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2453 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2454 (v4i1 (COPY_TO_REGCLASS
2455 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2456 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2458 //===----------------------------------------------------------------------===//
2459 // AVX-512 - Aligned and unaligned load and store
2463 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2464 PatFrag ld_frag, PatFrag mload,
2465 bit IsReMaterializable = 1> {
2466 let hasSideEffects = 0 in {
2467 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2468 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2470 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2471 (ins _.KRCWM:$mask, _.RC:$src),
2472 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2473 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2476 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2477 SchedRW = [WriteLoad] in
2478 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2479 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2480 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2483 let Constraints = "$src0 = $dst" in {
2484 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2485 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2486 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2487 "${dst} {${mask}}, $src1}"),
2488 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2490 (_.VT _.RC:$src0))))], _.ExeDomain>,
2492 let mayLoad = 1, SchedRW = [WriteLoad] in
2493 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2494 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2495 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2496 "${dst} {${mask}}, $src1}"),
2497 [(set _.RC:$dst, (_.VT
2498 (vselect _.KRCWM:$mask,
2499 (_.VT (bitconvert (ld_frag addr:$src1))),
2500 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2502 let mayLoad = 1, SchedRW = [WriteLoad] in
2503 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2504 (ins _.KRCWM:$mask, _.MemOp:$src),
2505 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2506 "${dst} {${mask}} {z}, $src}",
2507 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2508 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2509 _.ExeDomain>, EVEX, EVEX_KZ;
2511 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2512 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2514 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2515 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2517 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2518 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2519 _.KRCWM:$mask, addr:$ptr)>;
2522 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2523 AVX512VLVectorVTInfo _,
2525 bit IsReMaterializable = 1> {
2526 let Predicates = [prd] in
2527 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2528 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2530 let Predicates = [prd, HasVLX] in {
2531 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2532 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2533 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2534 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2538 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2539 AVX512VLVectorVTInfo _,
2541 bit IsReMaterializable = 1> {
2542 let Predicates = [prd] in
2543 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2544 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2546 let Predicates = [prd, HasVLX] in {
2547 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2548 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2549 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2550 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2554 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2555 PatFrag st_frag, PatFrag mstore> {
2556 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2557 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2558 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2560 let Constraints = "$src1 = $dst" in
2561 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2562 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2564 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2565 [], _.ExeDomain>, EVEX, EVEX_K;
2566 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2567 (ins _.KRCWM:$mask, _.RC:$src),
2569 "\t{$src, ${dst} {${mask}} {z}|" #
2570 "${dst} {${mask}} {z}, $src}",
2571 [], _.ExeDomain>, EVEX, EVEX_KZ;
2573 let mayStore = 1 in {
2574 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2576 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2577 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2578 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2579 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2580 [], _.ExeDomain>, EVEX, EVEX_K;
2583 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2584 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2585 _.KRCWM:$mask, _.RC:$src)>;
2589 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2590 AVX512VLVectorVTInfo _, Predicate prd> {
2591 let Predicates = [prd] in
2592 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2593 masked_store_unaligned>, EVEX_V512;
2595 let Predicates = [prd, HasVLX] in {
2596 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2597 masked_store_unaligned>, EVEX_V256;
2598 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2599 masked_store_unaligned>, EVEX_V128;
2603 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2604 AVX512VLVectorVTInfo _, Predicate prd> {
2605 let Predicates = [prd] in
2606 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2607 masked_store_aligned512>, EVEX_V512;
2609 let Predicates = [prd, HasVLX] in {
2610 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2611 masked_store_aligned256>, EVEX_V256;
2612 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2613 masked_store_aligned128>, EVEX_V128;
2617 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2619 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2620 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2622 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2624 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2625 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2627 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2628 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2629 PS, EVEX_CD8<32, CD8VF>;
2631 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2632 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2633 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2635 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2636 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2637 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2639 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2640 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2641 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2643 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2644 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2645 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2647 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2648 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2649 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2651 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2652 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2653 (VMOVAPDZrm addr:$ptr)>;
2655 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2656 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2657 (VMOVAPSZrm addr:$ptr)>;
2659 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2661 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2663 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2665 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2668 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2670 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2672 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2674 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2677 let Predicates = [HasAVX512, NoVLX] in {
2678 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2679 (VMOVUPSZmrk addr:$ptr,
2680 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2681 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2683 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2684 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2685 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2687 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2688 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2689 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2690 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2693 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2695 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2696 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2698 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2700 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2701 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2703 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2704 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2705 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2707 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2708 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2709 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2711 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2712 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2713 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2715 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2716 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2717 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2719 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2720 (v16i32 immAllZerosV), GR16:$mask)),
2721 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2723 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2724 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2725 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2727 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2729 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2731 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2733 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2736 let AddedComplexity = 20 in {
2737 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2738 (bc_v8i64 (v16i32 immAllZerosV)))),
2739 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2741 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2742 (v8i64 VR512:$src))),
2743 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2746 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2747 (v16i32 immAllZerosV))),
2748 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2750 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2751 (v16i32 VR512:$src))),
2752 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2755 let Predicates = [HasAVX512, NoVLX] in {
2756 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2757 (VMOVDQU32Zmrk addr:$ptr,
2758 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2759 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2761 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2762 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2763 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2766 // Move Int Doubleword to Packed Double Int
2768 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2769 "vmovd\t{$src, $dst|$dst, $src}",
2771 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2773 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2774 "vmovd\t{$src, $dst|$dst, $src}",
2776 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2777 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2778 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2779 "vmovq\t{$src, $dst|$dst, $src}",
2781 (v2i64 (scalar_to_vector GR64:$src)))],
2782 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2783 let isCodeGenOnly = 1 in {
2784 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2785 "vmovq\t{$src, $dst|$dst, $src}",
2786 [(set FR64:$dst, (bitconvert GR64:$src))],
2787 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2788 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2789 "vmovq\t{$src, $dst|$dst, $src}",
2790 [(set GR64:$dst, (bitconvert FR64:$src))],
2791 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2793 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2794 "vmovq\t{$src, $dst|$dst, $src}",
2795 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2796 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2797 EVEX_CD8<64, CD8VT1>;
2799 // Move Int Doubleword to Single Scalar
2801 let isCodeGenOnly = 1 in {
2802 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2803 "vmovd\t{$src, $dst|$dst, $src}",
2804 [(set FR32X:$dst, (bitconvert GR32:$src))],
2805 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2807 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2808 "vmovd\t{$src, $dst|$dst, $src}",
2809 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2810 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2813 // Move doubleword from xmm register to r/m32
2815 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2816 "vmovd\t{$src, $dst|$dst, $src}",
2817 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2818 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2820 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2821 (ins i32mem:$dst, VR128X:$src),
2822 "vmovd\t{$src, $dst|$dst, $src}",
2823 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2824 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2825 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2827 // Move quadword from xmm1 register to r/m64
2829 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2830 "vmovq\t{$src, $dst|$dst, $src}",
2831 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2833 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2834 Requires<[HasAVX512, In64BitMode]>;
2836 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2837 (ins i64mem:$dst, VR128X:$src),
2838 "vmovq\t{$src, $dst|$dst, $src}",
2839 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2840 addr:$dst)], IIC_SSE_MOVDQ>,
2841 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2842 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2844 // Move Scalar Single to Double Int
2846 let isCodeGenOnly = 1 in {
2847 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2849 "vmovd\t{$src, $dst|$dst, $src}",
2850 [(set GR32:$dst, (bitconvert FR32X:$src))],
2851 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2852 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2853 (ins i32mem:$dst, FR32X:$src),
2854 "vmovd\t{$src, $dst|$dst, $src}",
2855 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2856 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2859 // Move Quadword Int to Packed Quadword Int
2861 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2863 "vmovq\t{$src, $dst|$dst, $src}",
2865 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2866 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2868 //===----------------------------------------------------------------------===//
2869 // AVX-512 MOVSS, MOVSD
2870 //===----------------------------------------------------------------------===//
2872 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2873 SDNode OpNode, ValueType vt,
2874 X86MemOperand x86memop, PatFrag mem_pat> {
2875 let hasSideEffects = 0 in {
2876 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2877 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2878 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2879 (scalar_to_vector RC:$src2))))],
2880 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2881 let Constraints = "$src1 = $dst" in
2882 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2883 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2885 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2886 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2887 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2888 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2889 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2891 let mayStore = 1 in {
2892 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2893 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2894 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2896 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2897 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2898 [], IIC_SSE_MOV_S_MR>,
2899 EVEX, VEX_LIG, EVEX_K;
2901 } //hasSideEffects = 0
2904 let ExeDomain = SSEPackedSingle in
2905 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2906 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2908 let ExeDomain = SSEPackedDouble in
2909 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2910 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2912 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2913 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2914 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2916 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2917 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2918 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2920 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2921 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2922 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2924 // For the disassembler
2925 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2926 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2927 (ins VR128X:$src1, FR32X:$src2),
2928 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2930 XS, EVEX_4V, VEX_LIG;
2931 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2932 (ins VR128X:$src1, FR64X:$src2),
2933 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2935 XD, EVEX_4V, VEX_LIG, VEX_W;
2938 let Predicates = [HasAVX512] in {
2939 let AddedComplexity = 15 in {
2940 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2941 // MOVS{S,D} to the lower bits.
2942 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2943 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2944 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2945 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2946 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2947 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2948 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2949 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2951 // Move low f32 and clear high bits.
2952 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2953 (SUBREG_TO_REG (i32 0),
2954 (VMOVSSZrr (v4f32 (V_SET0)),
2955 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2956 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2957 (SUBREG_TO_REG (i32 0),
2958 (VMOVSSZrr (v4i32 (V_SET0)),
2959 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2962 let AddedComplexity = 20 in {
2963 // MOVSSrm zeros the high parts of the register; represent this
2964 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2965 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2966 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2967 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2968 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2969 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2970 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2972 // MOVSDrm zeros the high parts of the register; represent this
2973 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2974 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2975 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2976 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2977 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2978 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2979 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2980 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2981 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2982 def : Pat<(v2f64 (X86vzload addr:$src)),
2983 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2985 // Represent the same patterns above but in the form they appear for
2987 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2988 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2989 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2990 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2991 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2992 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2993 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2994 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2995 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2997 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2998 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2999 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3000 FR32X:$src)), sub_xmm)>;
3001 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3002 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3003 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3004 FR64X:$src)), sub_xmm)>;
3005 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3006 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3007 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3009 // Move low f64 and clear high bits.
3010 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3011 (SUBREG_TO_REG (i32 0),
3012 (VMOVSDZrr (v2f64 (V_SET0)),
3013 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3015 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3016 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3017 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3019 // Extract and store.
3020 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3022 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3023 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3025 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3027 // Shuffle with VMOVSS
3028 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3029 (VMOVSSZrr (v4i32 VR128X:$src1),
3030 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3031 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3032 (VMOVSSZrr (v4f32 VR128X:$src1),
3033 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3036 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3037 (SUBREG_TO_REG (i32 0),
3038 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3039 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3041 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3042 (SUBREG_TO_REG (i32 0),
3043 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3044 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3047 // Shuffle with VMOVSD
3048 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3049 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3050 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3051 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3052 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3053 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3054 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3055 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3058 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3059 (SUBREG_TO_REG (i32 0),
3060 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3061 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3063 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3064 (SUBREG_TO_REG (i32 0),
3065 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3066 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3069 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3070 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3071 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3072 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3073 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3074 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3075 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3076 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3079 let AddedComplexity = 15 in
3080 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3082 "vmovq\t{$src, $dst|$dst, $src}",
3083 [(set VR128X:$dst, (v2i64 (X86vzmovl
3084 (v2i64 VR128X:$src))))],
3085 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3087 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3088 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3090 "vmovq\t{$src, $dst|$dst, $src}",
3091 [(set VR128X:$dst, (v2i64 (X86vzmovl
3092 (loadv2i64 addr:$src))))],
3093 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3094 EVEX_CD8<8, CD8VT8>;
3096 let Predicates = [HasAVX512] in {
3097 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3098 let AddedComplexity = 20 in {
3099 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3100 (VMOVDI2PDIZrm addr:$src)>;
3101 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3102 (VMOV64toPQIZrr GR64:$src)>;
3103 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3104 (VMOVDI2PDIZrr GR32:$src)>;
3106 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3107 (VMOVDI2PDIZrm addr:$src)>;
3108 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3109 (VMOVDI2PDIZrm addr:$src)>;
3110 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3111 (VMOVZPQILo2PQIZrm addr:$src)>;
3112 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3113 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3114 def : Pat<(v2i64 (X86vzload addr:$src)),
3115 (VMOVZPQILo2PQIZrm addr:$src)>;
3118 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3119 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3120 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3121 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3122 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3123 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3124 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3127 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3128 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3130 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3131 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3133 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3134 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3136 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3137 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3139 //===----------------------------------------------------------------------===//
3140 // AVX-512 - Non-temporals
3141 //===----------------------------------------------------------------------===//
3142 let SchedRW = [WriteLoad] in {
3143 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3144 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3145 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3146 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3147 EVEX_CD8<64, CD8VF>;
3149 let Predicates = [HasAVX512, HasVLX] in {
3150 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3152 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3153 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3154 EVEX_CD8<64, CD8VF>;
3156 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3158 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3159 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3160 EVEX_CD8<64, CD8VF>;
3164 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3165 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3166 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3167 let SchedRW = [WriteStore], mayStore = 1,
3168 AddedComplexity = 400 in
3169 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3171 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3174 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3175 string elty, string elsz, string vsz512,
3176 string vsz256, string vsz128, Domain d,
3177 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3178 let Predicates = [prd] in
3179 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3180 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3181 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3184 let Predicates = [prd, HasVLX] in {
3185 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3186 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3187 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3190 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3191 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3192 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3197 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3198 "i", "64", "8", "4", "2", SSEPackedInt,
3199 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3201 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3202 "f", "64", "8", "4", "2", SSEPackedDouble,
3203 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3205 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3206 "f", "32", "16", "8", "4", SSEPackedSingle,
3207 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3209 //===----------------------------------------------------------------------===//
3210 // AVX-512 - Integer arithmetic
3212 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3213 X86VectorVTInfo _, OpndItins itins,
3214 bit IsCommutable = 0> {
3215 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3216 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3217 "$src2, $src1", "$src1, $src2",
3218 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3219 itins.rr, IsCommutable>,
3220 AVX512BIBase, EVEX_4V;
3223 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3224 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3225 "$src2, $src1", "$src1, $src2",
3226 (_.VT (OpNode _.RC:$src1,
3227 (bitconvert (_.LdFrag addr:$src2)))),
3229 AVX512BIBase, EVEX_4V;
3232 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3233 X86VectorVTInfo _, OpndItins itins,
3234 bit IsCommutable = 0> :
3235 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3237 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3238 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3239 "${src2}"##_.BroadcastStr##", $src1",
3240 "$src1, ${src2}"##_.BroadcastStr,
3241 (_.VT (OpNode _.RC:$src1,
3243 (_.ScalarLdFrag addr:$src2)))),
3245 AVX512BIBase, EVEX_4V, EVEX_B;
3248 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3249 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3250 Predicate prd, bit IsCommutable = 0> {
3251 let Predicates = [prd] in
3252 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3253 IsCommutable>, EVEX_V512;
3255 let Predicates = [prd, HasVLX] in {
3256 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3257 IsCommutable>, EVEX_V256;
3258 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3259 IsCommutable>, EVEX_V128;
3263 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3264 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3265 Predicate prd, bit IsCommutable = 0> {
3266 let Predicates = [prd] in
3267 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3268 IsCommutable>, EVEX_V512;
3270 let Predicates = [prd, HasVLX] in {
3271 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3272 IsCommutable>, EVEX_V256;
3273 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3274 IsCommutable>, EVEX_V128;
3278 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3279 OpndItins itins, Predicate prd,
3280 bit IsCommutable = 0> {
3281 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3282 itins, prd, IsCommutable>,
3283 VEX_W, EVEX_CD8<64, CD8VF>;
3286 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3287 OpndItins itins, Predicate prd,
3288 bit IsCommutable = 0> {
3289 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3290 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3293 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3294 OpndItins itins, Predicate prd,
3295 bit IsCommutable = 0> {
3296 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3297 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3300 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3301 OpndItins itins, Predicate prd,
3302 bit IsCommutable = 0> {
3303 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3304 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3307 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3308 SDNode OpNode, OpndItins itins, Predicate prd,
3309 bit IsCommutable = 0> {
3310 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3313 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3317 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3318 SDNode OpNode, OpndItins itins, Predicate prd,
3319 bit IsCommutable = 0> {
3320 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3323 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3327 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3328 bits<8> opc_d, bits<8> opc_q,
3329 string OpcodeStr, SDNode OpNode,
3330 OpndItins itins, bit IsCommutable = 0> {
3331 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3332 itins, HasAVX512, IsCommutable>,
3333 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3334 itins, HasBWI, IsCommutable>;
3337 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3338 SDNode OpNode,X86VectorVTInfo _Src,
3339 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3340 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3341 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3342 "$src2, $src1","$src1, $src2",
3344 (_Src.VT _Src.RC:$src1),
3345 (_Src.VT _Src.RC:$src2))),
3346 itins.rr, IsCommutable>,
3347 AVX512BIBase, EVEX_4V;
3348 let mayLoad = 1 in {
3349 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3350 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3351 "$src2, $src1", "$src1, $src2",
3352 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3353 (bitconvert (_Src.LdFrag addr:$src2)))),
3355 AVX512BIBase, EVEX_4V;
3357 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3358 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3360 "${src2}"##_Dst.BroadcastStr##", $src1",
3361 "$src1, ${src2}"##_Dst.BroadcastStr,
3362 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3363 (_Dst.VT (X86VBroadcast
3364 (_Dst.ScalarLdFrag addr:$src2)))))),
3366 AVX512BIBase, EVEX_4V, EVEX_B;
3370 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3371 SSE_INTALU_ITINS_P, 1>;
3372 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3373 SSE_INTALU_ITINS_P, 0>;
3374 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3375 SSE_INTALU_ITINS_P, HasBWI, 1>;
3376 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3377 SSE_INTALU_ITINS_P, HasBWI, 0>;
3378 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3379 SSE_INTALU_ITINS_P, HasBWI, 1>;
3380 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3381 SSE_INTALU_ITINS_P, HasBWI, 0>;
3382 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3383 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3384 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3385 SSE_INTALU_ITINS_P, HasBWI, 1>;
3386 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3387 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3388 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3390 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3392 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3394 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3395 SSE_INTALU_ITINS_P, HasBWI, 1>;
3397 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3398 SDNode OpNode, bit IsCommutable = 0> {
3400 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3401 v16i32_info, v8i64_info, IsCommutable>,
3402 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3403 let Predicates = [HasVLX] in {
3404 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3405 v8i32x_info, v4i64x_info, IsCommutable>,
3406 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3407 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3408 v4i32x_info, v2i64x_info, IsCommutable>,
3409 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3413 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3415 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3418 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3419 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3420 let mayLoad = 1 in {
3421 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3422 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3424 "${src2}"##_Src.BroadcastStr##", $src1",
3425 "$src1, ${src2}"##_Src.BroadcastStr,
3426 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3427 (_Src.VT (X86VBroadcast
3428 (_Src.ScalarLdFrag addr:$src2))))))>,
3429 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3433 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3434 SDNode OpNode,X86VectorVTInfo _Src,
3435 X86VectorVTInfo _Dst> {
3436 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3437 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3438 "$src2, $src1","$src1, $src2",
3440 (_Src.VT _Src.RC:$src1),
3441 (_Src.VT _Src.RC:$src2)))>,
3442 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3443 let mayLoad = 1 in {
3444 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3445 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3446 "$src2, $src1", "$src1, $src2",
3447 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3448 (bitconvert (_Src.LdFrag addr:$src2))))>,
3449 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3453 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3455 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3457 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3458 v32i16_info>, EVEX_V512;
3459 let Predicates = [HasVLX] in {
3460 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3462 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3463 v16i16x_info>, EVEX_V256;
3464 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3466 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3467 v8i16x_info>, EVEX_V128;
3470 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3472 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3473 v64i8_info>, EVEX_V512;
3474 let Predicates = [HasVLX] in {
3475 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3476 v32i8x_info>, EVEX_V256;
3477 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3478 v16i8x_info>, EVEX_V128;
3482 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3483 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3484 AVX512VLVectorVTInfo _Dst> {
3485 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3486 _Dst.info512>, EVEX_V512;
3487 let Predicates = [HasVLX] in {
3488 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3489 _Dst.info256>, EVEX_V256;
3490 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3491 _Dst.info128>, EVEX_V128;
3495 let Predicates = [HasBWI] in {
3496 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3497 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3498 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3499 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3501 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3502 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3503 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3504 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3507 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3508 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3509 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3510 SSE_INTALU_ITINS_P, HasBWI, 1>;
3511 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3512 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3514 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3515 SSE_INTALU_ITINS_P, HasBWI, 1>;
3516 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3517 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3518 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3519 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3521 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3522 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3523 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3524 SSE_INTALU_ITINS_P, HasBWI, 1>;
3525 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3526 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3528 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3529 SSE_INTALU_ITINS_P, HasBWI, 1>;
3530 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3531 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3532 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3533 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3534 //===----------------------------------------------------------------------===//
3535 // AVX-512 Logical Instructions
3536 //===----------------------------------------------------------------------===//
3538 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3539 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3540 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3541 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3542 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3543 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3544 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3545 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3547 //===----------------------------------------------------------------------===//
3548 // AVX-512 FP arithmetic
3549 //===----------------------------------------------------------------------===//
3550 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3551 SDNode OpNode, SDNode VecNode, OpndItins itins,
3554 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3555 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3556 "$src2, $src1", "$src1, $src2",
3557 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3558 (i32 FROUND_CURRENT)),
3559 itins.rr, IsCommutable>;
3561 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3562 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3563 "$src2, $src1", "$src1, $src2",
3564 (VecNode (_.VT _.RC:$src1),
3565 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3566 (i32 FROUND_CURRENT)),
3567 itins.rm, IsCommutable>;
3568 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3569 Predicates = [HasAVX512] in {
3570 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3571 (ins _.FRC:$src1, _.FRC:$src2),
3572 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3573 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3575 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3576 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3577 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3578 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3579 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3583 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3584 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3586 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3587 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3588 "$rc, $src2, $src1", "$src1, $src2, $rc",
3589 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3590 (i32 imm:$rc)), itins.rr, IsCommutable>,
3593 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3594 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3596 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3597 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3598 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3599 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3600 (i32 FROUND_NO_EXC))>, EVEX_B;
3603 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3605 SizeItins itins, bit IsCommutable> {
3606 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3607 itins.s, IsCommutable>,
3608 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3609 itins.s, IsCommutable>,
3610 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3611 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3612 itins.d, IsCommutable>,
3613 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3614 itins.d, IsCommutable>,
3615 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3618 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3620 SizeItins itins, bit IsCommutable> {
3621 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3622 itins.s, IsCommutable>,
3623 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3624 itins.s, IsCommutable>,
3625 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3626 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3627 itins.d, IsCommutable>,
3628 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3629 itins.d, IsCommutable>,
3630 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3632 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3633 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3634 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3635 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3636 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3637 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3639 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3640 X86VectorVTInfo _, bit IsCommutable> {
3641 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3642 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3643 "$src2, $src1", "$src1, $src2",
3644 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3645 let mayLoad = 1 in {
3646 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3647 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3648 "$src2, $src1", "$src1, $src2",
3649 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3650 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3651 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3652 "${src2}"##_.BroadcastStr##", $src1",
3653 "$src1, ${src2}"##_.BroadcastStr,
3654 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3655 (_.ScalarLdFrag addr:$src2))))>,
3660 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3661 X86VectorVTInfo _> {
3662 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3663 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3664 "$rc, $src2, $src1", "$src1, $src2, $rc",
3665 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3666 EVEX_4V, EVEX_B, EVEX_RC;
3670 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3671 X86VectorVTInfo _> {
3672 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3673 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3674 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3675 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3679 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3680 bit IsCommutable = 0> {
3681 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3682 IsCommutable>, EVEX_V512, PS,
3683 EVEX_CD8<32, CD8VF>;
3684 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3685 IsCommutable>, EVEX_V512, PD, VEX_W,
3686 EVEX_CD8<64, CD8VF>;
3688 // Define only if AVX512VL feature is present.
3689 let Predicates = [HasVLX] in {
3690 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3691 IsCommutable>, EVEX_V128, PS,
3692 EVEX_CD8<32, CD8VF>;
3693 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3694 IsCommutable>, EVEX_V256, PS,
3695 EVEX_CD8<32, CD8VF>;
3696 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3697 IsCommutable>, EVEX_V128, PD, VEX_W,
3698 EVEX_CD8<64, CD8VF>;
3699 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3700 IsCommutable>, EVEX_V256, PD, VEX_W,
3701 EVEX_CD8<64, CD8VF>;
3705 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3706 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3707 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3708 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3709 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3712 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3713 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3714 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3715 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3716 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3719 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3720 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3721 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3722 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3723 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3724 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3725 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3726 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3727 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3728 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3729 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3730 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3731 let Predicates = [HasDQI] in {
3732 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3733 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3734 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3735 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3738 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3739 X86VectorVTInfo _> {
3740 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3741 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3742 "$src2, $src1", "$src1, $src2",
3743 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3744 let mayLoad = 1 in {
3745 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3746 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3747 "$src2, $src1", "$src1, $src2",
3748 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3749 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3750 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3751 "${src2}"##_.BroadcastStr##", $src1",
3752 "$src1, ${src2}"##_.BroadcastStr,
3753 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3754 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3759 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3760 X86VectorVTInfo _> {
3761 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3762 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3763 "$src2, $src1", "$src1, $src2",
3764 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3765 let mayLoad = 1 in {
3766 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3767 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3768 "$src2, $src1", "$src1, $src2",
3769 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3773 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3774 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3775 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3776 EVEX_V512, EVEX_CD8<32, CD8VF>;
3777 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3778 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3779 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3780 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3781 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3782 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3783 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3784 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3785 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3787 // Define only if AVX512VL feature is present.
3788 let Predicates = [HasVLX] in {
3789 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3790 EVEX_V128, EVEX_CD8<32, CD8VF>;
3791 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3792 EVEX_V256, EVEX_CD8<32, CD8VF>;
3793 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3794 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3795 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3796 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3799 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3801 //===----------------------------------------------------------------------===//
3802 // AVX-512 VPTESTM instructions
3803 //===----------------------------------------------------------------------===//
3805 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3806 X86VectorVTInfo _> {
3807 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3808 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3809 "$src2, $src1", "$src1, $src2",
3810 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3813 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3814 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3815 "$src2, $src1", "$src1, $src2",
3816 (OpNode (_.VT _.RC:$src1),
3817 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3819 EVEX_CD8<_.EltSize, CD8VF>;
3822 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3823 X86VectorVTInfo _> {
3825 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3826 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3827 "${src2}"##_.BroadcastStr##", $src1",
3828 "$src1, ${src2}"##_.BroadcastStr,
3829 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3830 (_.ScalarLdFrag addr:$src2))))>,
3831 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3833 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3834 AVX512VLVectorVTInfo _> {
3835 let Predicates = [HasAVX512] in
3836 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3837 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3839 let Predicates = [HasAVX512, HasVLX] in {
3840 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3841 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3842 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3843 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3847 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3848 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3850 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3851 avx512vl_i64_info>, VEX_W;
3854 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3856 let Predicates = [HasBWI] in {
3857 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3859 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3862 let Predicates = [HasVLX, HasBWI] in {
3864 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3866 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3868 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3870 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3875 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3877 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3878 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3880 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3881 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3883 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3884 (v16i32 VR512:$src2), (i16 -1))),
3885 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3887 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3888 (v8i64 VR512:$src2), (i8 -1))),
3889 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3891 //===----------------------------------------------------------------------===//
3892 // AVX-512 Shift instructions
3893 //===----------------------------------------------------------------------===//
3894 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3895 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3896 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3897 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3898 "$src2, $src1", "$src1, $src2",
3899 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3900 SSE_INTSHIFT_ITINS_P.rr>;
3902 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3903 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3904 "$src2, $src1", "$src1, $src2",
3905 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3907 SSE_INTSHIFT_ITINS_P.rm>;
3910 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3911 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3913 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3914 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3915 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3916 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3917 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3920 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3921 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3922 // src2 is always 128-bit
3923 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3924 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3925 "$src2, $src1", "$src1, $src2",
3926 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3927 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3928 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3929 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3930 "$src2, $src1", "$src1, $src2",
3931 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3932 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3936 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3937 ValueType SrcVT, PatFrag bc_frag,
3938 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3939 let Predicates = [prd] in
3940 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3941 VTInfo.info512>, EVEX_V512,
3942 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3943 let Predicates = [prd, HasVLX] in {
3944 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3945 VTInfo.info256>, EVEX_V256,
3946 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3947 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3948 VTInfo.info128>, EVEX_V128,
3949 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3953 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3954 string OpcodeStr, SDNode OpNode> {
3955 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3956 avx512vl_i32_info, HasAVX512>;
3957 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3958 avx512vl_i64_info, HasAVX512>, VEX_W;
3959 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3960 avx512vl_i16_info, HasBWI>;
3963 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3964 string OpcodeStr, SDNode OpNode,
3965 AVX512VLVectorVTInfo VTInfo> {
3966 let Predicates = [HasAVX512] in
3967 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3969 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3970 VTInfo.info512>, EVEX_V512;
3971 let Predicates = [HasAVX512, HasVLX] in {
3972 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3974 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3975 VTInfo.info256>, EVEX_V256;
3976 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3978 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3979 VTInfo.info128>, EVEX_V128;
3983 multiclass avx512_shift_rmi_w<bits<8> opcw,
3984 Format ImmFormR, Format ImmFormM,
3985 string OpcodeStr, SDNode OpNode> {
3986 let Predicates = [HasBWI] in
3987 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3988 v32i16_info>, EVEX_V512;
3989 let Predicates = [HasVLX, HasBWI] in {
3990 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3991 v16i16x_info>, EVEX_V256;
3992 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3993 v8i16x_info>, EVEX_V128;
3997 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3998 Format ImmFormR, Format ImmFormM,
3999 string OpcodeStr, SDNode OpNode> {
4000 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4001 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4002 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4003 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4006 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4007 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4009 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4010 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4012 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4013 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4015 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4016 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4018 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4019 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4020 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4022 //===-------------------------------------------------------------------===//
4023 // Variable Bit Shifts
4024 //===-------------------------------------------------------------------===//
4025 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4026 X86VectorVTInfo _> {
4027 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4028 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4029 "$src2, $src1", "$src1, $src2",
4030 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4031 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4033 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4034 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4035 "$src2, $src1", "$src1, $src2",
4036 (_.VT (OpNode _.RC:$src1,
4037 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4038 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4039 EVEX_CD8<_.EltSize, CD8VF>;
4042 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4043 X86VectorVTInfo _> {
4045 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4046 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4047 "${src2}"##_.BroadcastStr##", $src1",
4048 "$src1, ${src2}"##_.BroadcastStr,
4049 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4050 (_.ScalarLdFrag addr:$src2))))),
4051 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4052 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4054 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4055 AVX512VLVectorVTInfo _> {
4056 let Predicates = [HasAVX512] in
4057 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4058 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4060 let Predicates = [HasAVX512, HasVLX] in {
4061 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4062 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4063 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4064 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4068 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4070 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4072 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4073 avx512vl_i64_info>, VEX_W;
4076 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4078 let Predicates = [HasBWI] in
4079 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4081 let Predicates = [HasVLX, HasBWI] in {
4083 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4085 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4090 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4091 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4092 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4093 avx512_var_shift_w<0x11, "vpsravw", sra>;
4094 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4095 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4096 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4097 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4099 //===-------------------------------------------------------------------===//
4100 // 1-src variable permutation VPERMW/D/Q
4101 //===-------------------------------------------------------------------===//
4102 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4103 AVX512VLVectorVTInfo _> {
4104 let Predicates = [HasAVX512] in
4105 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4106 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4108 let Predicates = [HasAVX512, HasVLX] in
4109 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4110 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4113 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4114 string OpcodeStr, SDNode OpNode,
4115 AVX512VLVectorVTInfo VTInfo> {
4116 let Predicates = [HasAVX512] in
4117 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4119 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4120 VTInfo.info512>, EVEX_V512;
4121 let Predicates = [HasAVX512, HasVLX] in
4122 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4124 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4125 VTInfo.info256>, EVEX_V256;
4129 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4131 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4133 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4134 avx512vl_i64_info>, VEX_W;
4135 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4137 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4138 avx512vl_f64_info>, VEX_W;
4140 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4141 X86VPermi, avx512vl_i64_info>,
4142 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4143 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4144 X86VPermi, avx512vl_f64_info>,
4145 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4146 //===----------------------------------------------------------------------===//
4147 // AVX-512 - VPERMIL
4148 //===----------------------------------------------------------------------===//
4150 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4151 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4152 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4153 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4154 "$src2, $src1", "$src1, $src2",
4155 (_.VT (OpNode _.RC:$src1,
4156 (Ctrl.VT Ctrl.RC:$src2)))>,
4158 let mayLoad = 1 in {
4159 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4160 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4161 "$src2, $src1", "$src1, $src2",
4164 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4165 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4166 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4167 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4168 "${src2}"##_.BroadcastStr##", $src1",
4169 "$src1, ${src2}"##_.BroadcastStr,
4172 (Ctrl.VT (X86VBroadcast
4173 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4174 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4178 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4179 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4180 let Predicates = [HasAVX512] in {
4181 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4182 Ctrl.info512>, EVEX_V512;
4184 let Predicates = [HasAVX512, HasVLX] in {
4185 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4186 Ctrl.info128>, EVEX_V128;
4187 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4188 Ctrl.info256>, EVEX_V256;
4192 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4193 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4195 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4196 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4198 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4200 let isCodeGenOnly = 1 in {
4201 // lowering implementation with the alternative types
4202 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4203 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4204 OpcodeStr, X86VPermilpi, Ctrl>,
4205 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4209 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4211 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4212 avx512vl_i64_info>, VEX_W;
4213 //===----------------------------------------------------------------------===//
4214 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4215 //===----------------------------------------------------------------------===//
4217 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4218 X86PShufd, avx512vl_i32_info>,
4219 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4220 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4221 X86PShufhw>, EVEX, AVX512XSIi8Base;
4222 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4223 X86PShuflw>, EVEX, AVX512XDIi8Base;
4225 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4226 let Predicates = [HasBWI] in
4227 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4229 let Predicates = [HasVLX, HasBWI] in {
4230 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4231 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4235 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4237 //===----------------------------------------------------------------------===//
4238 // AVX-512 - MOVDDUP
4239 //===----------------------------------------------------------------------===//
4241 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
4242 X86MemOperand x86memop, PatFrag memop_frag> {
4243 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4245 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
4246 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4247 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4249 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
4252 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
4253 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4254 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
4255 (VMOVDDUPZrm addr:$src)>;
4257 //===---------------------------------------------------------------------===//
4258 // Replicate Single FP - MOVSHDUP and MOVSLDUP
4259 //===---------------------------------------------------------------------===//
4260 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4261 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4262 X86MemOperand x86memop> {
4263 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4264 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4265 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
4267 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4268 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4269 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
4272 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4273 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4274 EVEX_CD8<32, CD8VF>;
4275 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4276 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4277 EVEX_CD8<32, CD8VF>;
4279 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
4280 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
4281 (VMOVSHDUPZrm addr:$src)>;
4282 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
4283 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
4284 (VMOVSLDUPZrm addr:$src)>;
4286 //===----------------------------------------------------------------------===//
4287 // Move Low to High and High to Low packed FP Instructions
4288 //===----------------------------------------------------------------------===//
4289 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4290 (ins VR128X:$src1, VR128X:$src2),
4291 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4292 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4293 IIC_SSE_MOV_LH>, EVEX_4V;
4294 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4295 (ins VR128X:$src1, VR128X:$src2),
4296 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4297 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4298 IIC_SSE_MOV_LH>, EVEX_4V;
4300 let Predicates = [HasAVX512] in {
4302 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4303 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4304 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4305 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4308 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4309 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4312 //===----------------------------------------------------------------------===//
4313 // FMA - Fused Multiply Operations
4316 let Constraints = "$src1 = $dst" in {
4317 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4318 X86VectorVTInfo _> {
4319 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4320 (ins _.RC:$src2, _.RC:$src3),
4321 OpcodeStr, "$src3, $src2", "$src2, $src3",
4322 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4325 let mayLoad = 1 in {
4326 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4327 (ins _.RC:$src2, _.MemOp:$src3),
4328 OpcodeStr, "$src3, $src2", "$src2, $src3",
4329 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4332 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4333 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4334 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4335 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4337 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4338 AVX512FMA3Base, EVEX_B;
4342 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4343 X86VectorVTInfo _> {
4344 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4345 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4346 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4347 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4348 AVX512FMA3Base, EVEX_B, EVEX_RC;
4350 } // Constraints = "$src1 = $dst"
4352 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4353 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4354 let Predicates = [HasAVX512] in {
4355 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4356 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4357 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4359 let Predicates = [HasVLX, HasAVX512] in {
4360 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4361 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4362 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4363 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4367 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4368 SDNode OpNodeRnd > {
4369 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4371 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4372 avx512vl_f64_info>, VEX_W;
4375 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4376 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4377 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4378 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4379 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4380 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4383 let Constraints = "$src1 = $dst" in {
4384 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4385 X86VectorVTInfo _> {
4386 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4387 (ins _.RC:$src2, _.RC:$src3),
4388 OpcodeStr, "$src3, $src2", "$src2, $src3",
4389 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4392 let mayLoad = 1 in {
4393 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4394 (ins _.RC:$src2, _.MemOp:$src3),
4395 OpcodeStr, "$src3, $src2", "$src2, $src3",
4396 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4399 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4400 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4401 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4402 "$src2, ${src3}"##_.BroadcastStr,
4403 (_.VT (OpNode _.RC:$src2,
4404 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4405 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4409 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4410 X86VectorVTInfo _> {
4411 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4412 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4413 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4414 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4415 AVX512FMA3Base, EVEX_B, EVEX_RC;
4417 } // Constraints = "$src1 = $dst"
4419 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4420 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4421 let Predicates = [HasAVX512] in {
4422 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4423 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4424 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4426 let Predicates = [HasVLX, HasAVX512] in {
4427 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4428 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4429 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4430 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4434 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4435 SDNode OpNodeRnd > {
4436 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4438 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4439 avx512vl_f64_info>, VEX_W;
4442 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4443 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4444 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4445 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4446 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4447 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4449 let Constraints = "$src1 = $dst" in {
4450 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4451 X86VectorVTInfo _> {
4452 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4453 (ins _.RC:$src3, _.RC:$src2),
4454 OpcodeStr, "$src2, $src3", "$src3, $src2",
4455 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4458 let mayLoad = 1 in {
4459 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4460 (ins _.RC:$src3, _.MemOp:$src2),
4461 OpcodeStr, "$src2, $src3", "$src3, $src2",
4462 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4465 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4466 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4467 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4468 "$src3, ${src2}"##_.BroadcastStr,
4469 (_.VT (OpNode _.RC:$src1,
4470 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4471 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4475 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4476 X86VectorVTInfo _> {
4477 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4478 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4479 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4480 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4481 AVX512FMA3Base, EVEX_B, EVEX_RC;
4483 } // Constraints = "$src1 = $dst"
4485 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4486 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4487 let Predicates = [HasAVX512] in {
4488 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4489 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4490 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4492 let Predicates = [HasVLX, HasAVX512] in {
4493 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4494 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4495 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4496 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4500 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4501 SDNode OpNodeRnd > {
4502 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4504 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4505 avx512vl_f64_info>, VEX_W;
4508 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4509 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4510 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4511 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4512 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4513 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4516 let Constraints = "$src1 = $dst" in {
4517 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4518 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4519 dag RHS_r, dag RHS_m > {
4520 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4521 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4522 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4525 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4526 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4527 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4529 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4530 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4531 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4532 AVX512FMA3Base, EVEX_B, EVEX_RC;
4534 let isCodeGenOnly = 1 in {
4535 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4536 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4537 !strconcat(OpcodeStr,
4538 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4541 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4542 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4543 !strconcat(OpcodeStr,
4544 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4546 }// isCodeGenOnly = 1
4548 }// Constraints = "$src1 = $dst"
4550 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4551 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4554 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4555 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4556 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4557 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4558 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4560 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4562 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4563 (_.ScalarLdFrag addr:$src3))))>;
4565 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4566 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4567 (_.VT (OpNode _.RC:$src2,
4568 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4570 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4572 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4574 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4575 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4577 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4578 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4579 (_.VT (OpNode _.RC:$src1,
4580 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4582 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4584 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4586 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4587 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4590 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4591 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4592 let Predicates = [HasAVX512] in {
4593 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4594 OpNodeRnd, f32x_info, "SS">,
4595 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4596 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4597 OpNodeRnd, f64x_info, "SD">,
4598 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4602 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4603 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4604 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4605 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4607 //===----------------------------------------------------------------------===//
4608 // AVX-512 Scalar convert from sign integer to float/double
4609 //===----------------------------------------------------------------------===//
4611 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4612 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4613 PatFrag ld_frag, string asm> {
4614 let hasSideEffects = 0 in {
4615 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4616 (ins DstVT.FRC:$src1, SrcRC:$src),
4617 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4620 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4621 (ins DstVT.FRC:$src1, x86memop:$src),
4622 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4624 } // hasSideEffects = 0
4625 let isCodeGenOnly = 1 in {
4626 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4627 (ins DstVT.RC:$src1, SrcRC:$src2),
4628 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4629 [(set DstVT.RC:$dst,
4630 (OpNode (DstVT.VT DstVT.RC:$src1),
4632 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4634 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4635 (ins DstVT.RC:$src1, x86memop:$src2),
4636 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4637 [(set DstVT.RC:$dst,
4638 (OpNode (DstVT.VT DstVT.RC:$src1),
4639 (ld_frag addr:$src2),
4640 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4641 }//isCodeGenOnly = 1
4644 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4645 X86VectorVTInfo DstVT, string asm> {
4646 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4647 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4649 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4650 [(set DstVT.RC:$dst,
4651 (OpNode (DstVT.VT DstVT.RC:$src1),
4653 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4656 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4657 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4658 PatFrag ld_frag, string asm> {
4659 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4660 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4664 let Predicates = [HasAVX512] in {
4665 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4666 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4667 XS, EVEX_CD8<32, CD8VT1>;
4668 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4669 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4670 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4671 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4672 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4673 XD, EVEX_CD8<32, CD8VT1>;
4674 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4675 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4676 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4678 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4679 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4680 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4681 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4682 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4683 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4684 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4685 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4687 def : Pat<(f32 (sint_to_fp GR32:$src)),
4688 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4689 def : Pat<(f32 (sint_to_fp GR64:$src)),
4690 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4691 def : Pat<(f64 (sint_to_fp GR32:$src)),
4692 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4693 def : Pat<(f64 (sint_to_fp GR64:$src)),
4694 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4696 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4697 v4f32x_info, i32mem, loadi32,
4698 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4699 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4700 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4701 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4702 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4703 i32mem, loadi32, "cvtusi2sd{l}">,
4704 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4705 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4706 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4707 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4709 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4710 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4711 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4712 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4713 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4714 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4715 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4716 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4718 def : Pat<(f32 (uint_to_fp GR32:$src)),
4719 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4720 def : Pat<(f32 (uint_to_fp GR64:$src)),
4721 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4722 def : Pat<(f64 (uint_to_fp GR32:$src)),
4723 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4724 def : Pat<(f64 (uint_to_fp GR64:$src)),
4725 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4728 //===----------------------------------------------------------------------===//
4729 // AVX-512 Scalar convert from float/double to integer
4730 //===----------------------------------------------------------------------===//
4731 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4732 RegisterClass DstRC, Intrinsic Int,
4733 Operand memop, ComplexPattern mem_cpat, string asm> {
4734 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4735 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4736 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4737 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4738 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4739 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4740 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4742 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4743 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4744 } // hasSideEffects = 0, Predicates = [HasAVX512]
4747 // Convert float/double to signed/unsigned int 32/64
4748 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4749 ssmem, sse_load_f32, "cvtss2si">,
4750 XS, EVEX_CD8<32, CD8VT1>;
4751 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4752 int_x86_sse_cvtss2si64,
4753 ssmem, sse_load_f32, "cvtss2si">,
4754 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4755 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4756 int_x86_avx512_cvtss2usi,
4757 ssmem, sse_load_f32, "cvtss2usi">,
4758 XS, EVEX_CD8<32, CD8VT1>;
4759 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4760 int_x86_avx512_cvtss2usi64, ssmem,
4761 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4762 EVEX_CD8<32, CD8VT1>;
4763 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4764 sdmem, sse_load_f64, "cvtsd2si">,
4765 XD, EVEX_CD8<64, CD8VT1>;
4766 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4767 int_x86_sse2_cvtsd2si64,
4768 sdmem, sse_load_f64, "cvtsd2si">,
4769 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4770 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4771 int_x86_avx512_cvtsd2usi,
4772 sdmem, sse_load_f64, "cvtsd2usi">,
4773 XD, EVEX_CD8<64, CD8VT1>;
4774 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4775 int_x86_avx512_cvtsd2usi64, sdmem,
4776 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4777 EVEX_CD8<64, CD8VT1>;
4779 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4780 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4781 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4782 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4783 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4784 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4785 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4786 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4787 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4788 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4789 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4790 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4791 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4793 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4794 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4795 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4796 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4798 // Convert float/double to signed/unsigned int 32/64 with truncation
4799 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4800 X86VectorVTInfo _DstRC, SDNode OpNode,
4802 let Predicates = [HasAVX512] in {
4803 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4804 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4805 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4806 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4807 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4809 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4810 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4811 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4814 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4815 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4816 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4817 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4818 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4819 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4820 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4821 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4822 (i32 FROUND_NO_EXC)))]>,
4823 EVEX,VEX_LIG , EVEX_B;
4825 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4826 (ins _SrcRC.MemOp:$src),
4827 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4830 } // isCodeGenOnly = 1, hasSideEffects = 0
4835 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4836 fp_to_sint,X86cvttss2IntRnd>,
4837 XS, EVEX_CD8<32, CD8VT1>;
4838 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4839 fp_to_sint,X86cvttss2IntRnd>,
4840 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4841 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4842 fp_to_sint,X86cvttsd2IntRnd>,
4843 XD, EVEX_CD8<64, CD8VT1>;
4844 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4845 fp_to_sint,X86cvttsd2IntRnd>,
4846 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4848 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4849 fp_to_uint,X86cvttss2UIntRnd>,
4850 XS, EVEX_CD8<32, CD8VT1>;
4851 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4852 fp_to_uint,X86cvttss2UIntRnd>,
4853 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4854 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4855 fp_to_uint,X86cvttsd2UIntRnd>,
4856 XD, EVEX_CD8<64, CD8VT1>;
4857 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4858 fp_to_uint,X86cvttsd2UIntRnd>,
4859 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4860 let Predicates = [HasAVX512] in {
4861 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4862 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4863 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4864 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4865 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4866 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4867 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4868 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4871 //===----------------------------------------------------------------------===//
4872 // AVX-512 Convert form float to double and back
4873 //===----------------------------------------------------------------------===//
4874 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4875 X86VectorVTInfo _Src, SDNode OpNode> {
4876 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4877 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4878 "$src2, $src1", "$src1, $src2",
4879 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4880 (_Src.VT _Src.RC:$src2)))>,
4881 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4882 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4883 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4884 "$src2, $src1", "$src1, $src2",
4885 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4886 (_Src.VT (scalar_to_vector
4887 (_Src.ScalarLdFrag addr:$src2)))))>,
4888 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4891 // Scalar Coversion with SAE - suppress all exceptions
4892 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4893 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4894 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4895 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4896 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4897 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4898 (_Src.VT _Src.RC:$src2),
4899 (i32 FROUND_NO_EXC)))>,
4900 EVEX_4V, VEX_LIG, EVEX_B;
4903 // Scalar Conversion with rounding control (RC)
4904 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4905 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4906 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4907 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4908 "$rc, $src2, $src1", "$src1, $src2, $rc",
4909 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4910 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4911 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4914 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4915 SDNode OpNodeRnd, X86VectorVTInfo _src,
4916 X86VectorVTInfo _dst> {
4917 let Predicates = [HasAVX512] in {
4918 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4919 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4920 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
4925 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4926 SDNode OpNodeRnd, X86VectorVTInfo _src,
4927 X86VectorVTInfo _dst> {
4928 let Predicates = [HasAVX512] in {
4929 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4930 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
4931 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
4934 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
4935 X86froundRnd, f64x_info, f32x_info>;
4936 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
4937 X86fpextRnd,f32x_info, f64x_info >;
4939 def : Pat<(f64 (fextend FR32X:$src)),
4940 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
4941 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
4942 Requires<[HasAVX512]>;
4943 def : Pat<(f64 (fextend (loadf32 addr:$src))),
4944 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4945 Requires<[HasAVX512]>;
4947 def : Pat<(f64 (extloadf32 addr:$src)),
4948 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4949 Requires<[HasAVX512, OptForSize]>;
4951 def : Pat<(f64 (extloadf32 addr:$src)),
4952 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
4953 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
4954 Requires<[HasAVX512, OptForSpeed]>;
4956 def : Pat<(f32 (fround FR64X:$src)),
4957 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
4958 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
4959 Requires<[HasAVX512]>;
4960 //===----------------------------------------------------------------------===//
4961 // AVX-512 Vector convert from signed/unsigned integer to float/double
4962 // and from float/double to signed/unsigned integer
4963 //===----------------------------------------------------------------------===//
4965 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4966 X86VectorVTInfo _Src, SDNode OpNode,
4967 string Broadcast = _.BroadcastStr,
4968 string Alias = ""> {
4970 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4971 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4972 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4974 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4975 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4976 (_.VT (OpNode (_Src.VT
4977 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4979 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4980 (ins _Src.MemOp:$src), OpcodeStr,
4981 "${src}"##Broadcast, "${src}"##Broadcast,
4982 (_.VT (OpNode (_Src.VT
4983 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4986 // Coversion with SAE - suppress all exceptions
4987 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4988 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4989 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4990 (ins _Src.RC:$src), OpcodeStr,
4991 "{sae}, $src", "$src, {sae}",
4992 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4993 (i32 FROUND_NO_EXC)))>,
4997 // Conversion with rounding control (RC)
4998 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4999 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5000 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5001 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5002 "$rc, $src", "$src, $rc",
5003 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5004 EVEX, EVEX_B, EVEX_RC;
5007 // Extend Float to Double
5008 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5009 let Predicates = [HasAVX512] in {
5010 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5011 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5012 X86vfpextRnd>, EVEX_V512;
5014 let Predicates = [HasVLX] in {
5015 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5016 X86vfpext, "{1to2}">, EVEX_V128;
5017 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5022 // Truncate Double to Float
5023 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5024 let Predicates = [HasAVX512] in {
5025 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5026 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5027 X86vfproundRnd>, EVEX_V512;
5029 let Predicates = [HasVLX] in {
5030 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5031 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5032 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5033 "{1to4}", "{y}">, EVEX_V256;
5037 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5038 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5039 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5040 PS, EVEX_CD8<32, CD8VH>;
5042 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5043 (VCVTPS2PDZrm addr:$src)>;
5045 let Predicates = [HasVLX] in {
5046 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5047 (VCVTPS2PDZ256rm addr:$src)>;
5050 // Convert Signed/Unsigned Doubleword to Double
5051 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5053 // No rounding in this op
5054 let Predicates = [HasAVX512] in
5055 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5058 let Predicates = [HasVLX] in {
5059 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5060 OpNode128, "{1to2}">, EVEX_V128;
5061 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5066 // Convert Signed/Unsigned Doubleword to Float
5067 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5069 let Predicates = [HasAVX512] in
5070 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5071 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5072 OpNodeRnd>, EVEX_V512;
5074 let Predicates = [HasVLX] in {
5075 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5077 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5082 // Convert Float to Signed/Unsigned Doubleword with truncation
5083 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5084 SDNode OpNode, SDNode OpNodeRnd> {
5085 let Predicates = [HasAVX512] in {
5086 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5087 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5088 OpNodeRnd>, EVEX_V512;
5090 let Predicates = [HasVLX] in {
5091 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5093 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5098 // Convert Float to Signed/Unsigned Doubleword
5099 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5100 SDNode OpNode, SDNode OpNodeRnd> {
5101 let Predicates = [HasAVX512] in {
5102 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5103 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5104 OpNodeRnd>, EVEX_V512;
5106 let Predicates = [HasVLX] in {
5107 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5109 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5114 // Convert Double to Signed/Unsigned Doubleword with truncation
5115 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5116 SDNode OpNode, SDNode OpNodeRnd> {
5117 let Predicates = [HasAVX512] in {
5118 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5119 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5120 OpNodeRnd>, EVEX_V512;
5122 let Predicates = [HasVLX] in {
5123 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5124 // memory forms of these instructions in Asm Parcer. They have the same
5125 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5126 // due to the same reason.
5127 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5128 "{1to2}", "{x}">, EVEX_V128;
5129 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5130 "{1to4}", "{y}">, EVEX_V256;
5134 // Convert Double to Signed/Unsigned Doubleword
5135 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5136 SDNode OpNode, SDNode OpNodeRnd> {
5137 let Predicates = [HasAVX512] in {
5138 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5139 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5140 OpNodeRnd>, EVEX_V512;
5142 let Predicates = [HasVLX] in {
5143 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5144 // memory forms of these instructions in Asm Parcer. They have the same
5145 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5146 // due to the same reason.
5147 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5148 "{1to2}", "{x}">, EVEX_V128;
5149 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5150 "{1to4}", "{y}">, EVEX_V256;
5154 // Convert Double to Signed/Unsigned Quardword
5155 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5156 SDNode OpNode, SDNode OpNodeRnd> {
5157 let Predicates = [HasDQI] in {
5158 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5159 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5160 OpNodeRnd>, EVEX_V512;
5162 let Predicates = [HasDQI, HasVLX] in {
5163 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5165 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5170 // Convert Double to Signed/Unsigned Quardword with truncation
5171 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5172 SDNode OpNode, SDNode OpNodeRnd> {
5173 let Predicates = [HasDQI] in {
5174 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5175 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5176 OpNodeRnd>, EVEX_V512;
5178 let Predicates = [HasDQI, HasVLX] in {
5179 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5181 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5186 // Convert Signed/Unsigned Quardword to Double
5187 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5188 SDNode OpNode, SDNode OpNodeRnd> {
5189 let Predicates = [HasDQI] in {
5190 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5191 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5192 OpNodeRnd>, EVEX_V512;
5194 let Predicates = [HasDQI, HasVLX] in {
5195 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5197 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5202 // Convert Float to Signed/Unsigned Quardword
5203 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5204 SDNode OpNode, SDNode OpNodeRnd> {
5205 let Predicates = [HasDQI] in {
5206 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5207 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5208 OpNodeRnd>, EVEX_V512;
5210 let Predicates = [HasDQI, HasVLX] in {
5211 // Explicitly specified broadcast string, since we take only 2 elements
5212 // from v4f32x_info source
5213 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5214 "{1to2}">, EVEX_V128;
5215 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5220 // Convert Float to Signed/Unsigned Quardword with truncation
5221 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5222 SDNode OpNode, SDNode OpNodeRnd> {
5223 let Predicates = [HasDQI] in {
5224 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5225 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5226 OpNodeRnd>, EVEX_V512;
5228 let Predicates = [HasDQI, HasVLX] in {
5229 // Explicitly specified broadcast string, since we take only 2 elements
5230 // from v4f32x_info source
5231 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5232 "{1to2}">, EVEX_V128;
5233 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5238 // Convert Signed/Unsigned Quardword to Float
5239 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5240 SDNode OpNode, SDNode OpNodeRnd> {
5241 let Predicates = [HasDQI] in {
5242 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5243 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5244 OpNodeRnd>, EVEX_V512;
5246 let Predicates = [HasDQI, HasVLX] in {
5247 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5248 // memory forms of these instructions in Asm Parcer. They have the same
5249 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5250 // due to the same reason.
5251 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5252 "{1to2}", "{x}">, EVEX_V128;
5253 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5254 "{1to4}", "{y}">, EVEX_V256;
5258 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5259 EVEX_CD8<32, CD8VH>;
5261 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5263 PS, EVEX_CD8<32, CD8VF>;
5265 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5267 XS, EVEX_CD8<32, CD8VF>;
5269 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5271 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5273 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5274 X86VFpToUintRnd>, PS,
5275 EVEX_CD8<32, CD8VF>;
5277 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5278 X86VFpToUintRnd>, PS, VEX_W,
5279 EVEX_CD8<64, CD8VF>;
5281 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5282 XS, EVEX_CD8<32, CD8VH>;
5284 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5285 X86VUintToFpRnd>, XD,
5286 EVEX_CD8<32, CD8VF>;
5288 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5289 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5291 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5292 X86cvtpd2IntRnd>, XD, VEX_W,
5293 EVEX_CD8<64, CD8VF>;
5295 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5297 PS, EVEX_CD8<32, CD8VF>;
5298 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5299 X86cvtpd2UIntRnd>, VEX_W,
5300 PS, EVEX_CD8<64, CD8VF>;
5302 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5303 X86cvtpd2IntRnd>, VEX_W,
5304 PD, EVEX_CD8<64, CD8VF>;
5306 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5307 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5309 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5310 X86cvtpd2UIntRnd>, VEX_W,
5311 PD, EVEX_CD8<64, CD8VF>;
5313 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5314 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5316 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5317 X86VFpToSlongRnd>, VEX_W,
5318 PD, EVEX_CD8<64, CD8VF>;
5320 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5321 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5323 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5324 X86VFpToUlongRnd>, VEX_W,
5325 PD, EVEX_CD8<64, CD8VF>;
5327 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5328 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5330 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5331 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5333 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5334 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5336 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5337 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5339 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5340 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5342 let Predicates = [NoVLX] in {
5343 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5344 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5345 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5347 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5348 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5349 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5351 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5352 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5353 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5355 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5356 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5357 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5359 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5360 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5361 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5364 let Predicates = [HasAVX512] in {
5365 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5366 (VCVTPD2PSZrm addr:$src)>;
5367 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5368 (VCVTPS2PDZrm addr:$src)>;
5371 //===----------------------------------------------------------------------===//
5372 // Half precision conversion instructions
5373 //===----------------------------------------------------------------------===//
5374 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5375 X86MemOperand x86memop, PatFrag ld_frag> {
5376 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5377 "vcvtph2ps", "$src", "$src",
5378 (X86cvtph2ps (_src.VT _src.RC:$src),
5379 (i32 FROUND_CURRENT))>, T8PD;
5380 let hasSideEffects = 0, mayLoad = 1 in {
5381 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5382 "vcvtph2ps", "$src", "$src",
5383 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5384 (i32 FROUND_CURRENT))>, T8PD;
5388 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5389 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5390 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5391 (X86cvtph2ps (_src.VT _src.RC:$src),
5392 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5396 let Predicates = [HasAVX512] in {
5397 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5398 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5399 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5400 let Predicates = [HasVLX] in {
5401 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5402 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5403 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5404 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5408 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5409 X86MemOperand x86memop> {
5410 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5411 (ins _src.RC:$src1, i32u8imm:$src2),
5412 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5413 (X86cvtps2ph (_src.VT _src.RC:$src1),
5415 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5416 let hasSideEffects = 0, mayStore = 1 in {
5417 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5418 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5419 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5420 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5421 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5423 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5424 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5425 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5429 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5430 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5431 (ins _src.RC:$src1, i32u8imm:$src2),
5432 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5433 (X86cvtps2ph (_src.VT _src.RC:$src1),
5435 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5437 let Predicates = [HasAVX512] in {
5438 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5439 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5440 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5441 let Predicates = [HasVLX] in {
5442 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5443 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5444 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5445 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5448 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5449 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5450 "ucomiss">, PS, EVEX, VEX_LIG,
5451 EVEX_CD8<32, CD8VT1>;
5452 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5453 "ucomisd">, PD, EVEX,
5454 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5455 let Pattern = []<dag> in {
5456 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5457 "comiss">, PS, EVEX, VEX_LIG,
5458 EVEX_CD8<32, CD8VT1>;
5459 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5460 "comisd">, PD, EVEX,
5461 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5463 let isCodeGenOnly = 1 in {
5464 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5465 load, "ucomiss">, PS, EVEX, VEX_LIG,
5466 EVEX_CD8<32, CD8VT1>;
5467 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5468 load, "ucomisd">, PD, EVEX,
5469 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5471 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5472 load, "comiss">, PS, EVEX, VEX_LIG,
5473 EVEX_CD8<32, CD8VT1>;
5474 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5475 load, "comisd">, PD, EVEX,
5476 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5480 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5481 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5482 X86VectorVTInfo _> {
5483 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5484 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5485 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5486 "$src2, $src1", "$src1, $src2",
5487 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5488 let mayLoad = 1 in {
5489 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5490 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5491 "$src2, $src1", "$src1, $src2",
5492 (OpNode (_.VT _.RC:$src1),
5493 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5498 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5499 EVEX_CD8<32, CD8VT1>, T8PD;
5500 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5501 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5502 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5503 EVEX_CD8<32, CD8VT1>, T8PD;
5504 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5505 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5507 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5508 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5509 X86VectorVTInfo _> {
5510 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5511 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5512 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5513 let mayLoad = 1 in {
5514 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5515 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5517 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5518 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5519 (ins _.ScalarMemOp:$src), OpcodeStr,
5520 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5522 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5527 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5528 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5529 EVEX_V512, EVEX_CD8<32, CD8VF>;
5530 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5531 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5533 // Define only if AVX512VL feature is present.
5534 let Predicates = [HasVLX] in {
5535 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5536 OpNode, v4f32x_info>,
5537 EVEX_V128, EVEX_CD8<32, CD8VF>;
5538 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5539 OpNode, v8f32x_info>,
5540 EVEX_V256, EVEX_CD8<32, CD8VF>;
5541 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5542 OpNode, v2f64x_info>,
5543 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5544 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5545 OpNode, v4f64x_info>,
5546 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5550 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5551 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5553 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5554 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5555 (VRSQRT14PSZr VR512:$src)>;
5556 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5557 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5558 (VRSQRT14PDZr VR512:$src)>;
5560 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5561 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5562 (VRCP14PSZr VR512:$src)>;
5563 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5564 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5565 (VRCP14PDZr VR512:$src)>;
5567 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5568 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5571 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5572 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5573 "$src2, $src1", "$src1, $src2",
5574 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5575 (i32 FROUND_CURRENT))>;
5577 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5578 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5579 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5580 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5581 (i32 FROUND_NO_EXC))>, EVEX_B;
5583 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5584 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5585 "$src2, $src1", "$src1, $src2",
5586 (OpNode (_.VT _.RC:$src1),
5587 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5588 (i32 FROUND_CURRENT))>;
5591 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5592 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5593 EVEX_CD8<32, CD8VT1>;
5594 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5595 EVEX_CD8<64, CD8VT1>, VEX_W;
5598 let hasSideEffects = 0, Predicates = [HasERI] in {
5599 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5600 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5603 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5604 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5606 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5609 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5610 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5611 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5613 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5614 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5616 (bitconvert (_.LdFrag addr:$src))),
5617 (i32 FROUND_CURRENT))>;
5619 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5620 (ins _.MemOp:$src), OpcodeStr,
5621 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5623 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5624 (i32 FROUND_CURRENT))>, EVEX_B;
5626 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5628 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5629 (ins _.RC:$src), OpcodeStr,
5630 "{sae}, $src", "$src, {sae}",
5631 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5634 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5635 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5636 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5637 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5638 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5639 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5640 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5643 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5645 // Define only if AVX512VL feature is present.
5646 let Predicates = [HasVLX] in {
5647 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5648 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5649 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5650 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5651 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5652 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5653 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5654 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5657 let Predicates = [HasERI], hasSideEffects = 0 in {
5659 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5660 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5661 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5663 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5664 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5666 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5667 SDNode OpNodeRnd, X86VectorVTInfo _>{
5668 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5669 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5670 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5671 EVEX, EVEX_B, EVEX_RC;
5674 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5675 SDNode OpNode, X86VectorVTInfo _>{
5676 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5677 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5678 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5679 let mayLoad = 1 in {
5680 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5681 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5683 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5685 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5686 (ins _.ScalarMemOp:$src), OpcodeStr,
5687 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5689 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5694 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5696 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5698 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5699 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5701 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5702 // Define only if AVX512VL feature is present.
5703 let Predicates = [HasVLX] in {
5704 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5705 OpNode, v4f32x_info>,
5706 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5707 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5708 OpNode, v8f32x_info>,
5709 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5710 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5711 OpNode, v2f64x_info>,
5712 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5713 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5714 OpNode, v4f64x_info>,
5715 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5719 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5721 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5722 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5723 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5724 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5727 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5728 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5730 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5731 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5732 "$src2, $src1", "$src1, $src2",
5733 (OpNodeRnd (_.VT _.RC:$src1),
5735 (i32 FROUND_CURRENT))>;
5737 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5738 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5739 "$src2, $src1", "$src1, $src2",
5740 (OpNodeRnd (_.VT _.RC:$src1),
5741 (_.VT (scalar_to_vector
5742 (_.ScalarLdFrag addr:$src2))),
5743 (i32 FROUND_CURRENT))>;
5745 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5746 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5747 "$rc, $src2, $src1", "$src1, $src2, $rc",
5748 (OpNodeRnd (_.VT _.RC:$src1),
5753 let isCodeGenOnly = 1 in {
5754 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5755 (ins _.FRC:$src1, _.FRC:$src2),
5756 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5759 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5760 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5761 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5764 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5765 (!cast<Instruction>(NAME#SUFF#Zr)
5766 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5768 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5769 (!cast<Instruction>(NAME#SUFF#Zm)
5770 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5773 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5774 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5775 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5776 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5777 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5780 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5781 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5783 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5785 let Predicates = [HasAVX512] in {
5786 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5787 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5788 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5789 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5790 Requires<[OptForSize]>;
5791 def : Pat<(f32 (X86frcp FR32X:$src)),
5792 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5793 def : Pat<(f32 (X86frcp (load addr:$src))),
5794 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5795 Requires<[OptForSize]>;
5799 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5801 let ExeDomain = _.ExeDomain in {
5802 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5803 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5804 "$src3, $src2, $src1", "$src1, $src2, $src3",
5805 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5806 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5808 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5809 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5810 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5811 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5812 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5815 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5816 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5817 "$src3, $src2, $src1", "$src1, $src2, $src3",
5818 (_.VT (X86RndScales (_.VT _.RC:$src1),
5819 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5820 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5822 let Predicates = [HasAVX512] in {
5823 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5824 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5825 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5826 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5827 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5828 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5829 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5830 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5831 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5832 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5833 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5834 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5835 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5836 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5837 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5839 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5840 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5841 addr:$src, (i32 0x1))), _.FRC)>;
5842 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5843 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5844 addr:$src, (i32 0x2))), _.FRC)>;
5845 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5846 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5847 addr:$src, (i32 0x3))), _.FRC)>;
5848 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5849 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5850 addr:$src, (i32 0x4))), _.FRC)>;
5851 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5852 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5853 addr:$src, (i32 0xc))), _.FRC)>;
5857 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5858 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5860 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5861 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5863 //-------------------------------------------------
5864 // Integer truncate and extend operations
5865 //-------------------------------------------------
5867 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5868 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5869 X86MemOperand x86memop> {
5871 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5872 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5873 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5876 // for intrinsic patter match
5877 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5878 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5880 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5883 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5884 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5885 DestInfo.ImmAllZerosV)),
5886 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5889 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5890 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5891 DestInfo.RC:$src0)),
5892 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5893 DestInfo.KRCWM:$mask ,
5896 let mayStore = 1 in {
5897 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5898 (ins x86memop:$dst, SrcInfo.RC:$src),
5899 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5902 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5903 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5904 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5909 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5910 X86VectorVTInfo DestInfo,
5911 PatFrag truncFrag, PatFrag mtruncFrag > {
5913 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5914 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5915 addr:$dst, SrcInfo.RC:$src)>;
5917 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5918 (SrcInfo.VT SrcInfo.RC:$src)),
5919 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5920 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5923 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5924 X86VectorVTInfo DestInfo, string sat > {
5926 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5927 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5928 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5929 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5930 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5931 (SrcInfo.VT SrcInfo.RC:$src))>;
5933 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5934 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5935 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5936 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5937 (SrcInfo.VT SrcInfo.RC:$src))>;
5940 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5941 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5942 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5943 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5944 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5945 Predicate prd = HasAVX512>{
5947 let Predicates = [HasVLX, prd] in {
5948 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5949 DestInfoZ128, x86memopZ128>,
5950 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5951 truncFrag, mtruncFrag>, EVEX_V128;
5953 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5954 DestInfoZ256, x86memopZ256>,
5955 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5956 truncFrag, mtruncFrag>, EVEX_V256;
5958 let Predicates = [prd] in
5959 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5960 DestInfoZ, x86memopZ>,
5961 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5962 truncFrag, mtruncFrag>, EVEX_V512;
5965 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5966 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5967 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5968 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5969 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5971 let Predicates = [HasVLX, prd] in {
5972 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5973 DestInfoZ128, x86memopZ128>,
5974 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5977 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5978 DestInfoZ256, x86memopZ256>,
5979 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5982 let Predicates = [prd] in
5983 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5984 DestInfoZ, x86memopZ>,
5985 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5989 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5990 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5991 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5992 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5994 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5995 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5996 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5997 sat>, EVEX_CD8<8, CD8VO>;
6000 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6001 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6002 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6003 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6005 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6006 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6007 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6008 sat>, EVEX_CD8<16, CD8VQ>;
6011 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6012 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6013 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6014 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6016 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6017 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6018 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6019 sat>, EVEX_CD8<32, CD8VH>;
6022 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6023 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6024 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6025 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6027 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6028 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6029 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6030 sat>, EVEX_CD8<8, CD8VQ>;
6033 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6034 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6035 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6036 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6038 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6039 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6040 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6041 sat>, EVEX_CD8<16, CD8VH>;
6044 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6045 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6046 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6047 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6049 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6050 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6051 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6052 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6055 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6056 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6057 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6059 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6060 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6061 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6063 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6064 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6065 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6067 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6068 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6069 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6071 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6072 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6073 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6075 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6076 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6077 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6079 let Predicates = [HasAVX512, NoVLX] in {
6080 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6081 (v8i16 (EXTRACT_SUBREG
6082 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6083 VR256X:$src, sub_ymm)))), sub_xmm))>;
6084 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6085 (v4i32 (EXTRACT_SUBREG
6086 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6087 VR256X:$src, sub_ymm)))), sub_xmm))>;
6090 let Predicates = [HasBWI, NoVLX] in {
6091 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6092 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6093 VR256X:$src, sub_ymm))), sub_xmm))>;
6096 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6097 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6098 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6100 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6101 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6102 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6105 let mayLoad = 1 in {
6106 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6107 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6108 (DestInfo.VT (LdFrag addr:$src))>,
6113 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6114 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6115 let Predicates = [HasVLX, HasBWI] in {
6116 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6117 v16i8x_info, i64mem, LdFrag, OpNode>,
6118 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6120 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6121 v16i8x_info, i128mem, LdFrag, OpNode>,
6122 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6124 let Predicates = [HasBWI] in {
6125 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6126 v32i8x_info, i256mem, LdFrag, OpNode>,
6127 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6131 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6132 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6133 let Predicates = [HasVLX, HasAVX512] in {
6134 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6135 v16i8x_info, i32mem, LdFrag, OpNode>,
6136 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6138 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6139 v16i8x_info, i64mem, LdFrag, OpNode>,
6140 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6142 let Predicates = [HasAVX512] in {
6143 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6144 v16i8x_info, i128mem, LdFrag, OpNode>,
6145 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6149 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6150 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6151 let Predicates = [HasVLX, HasAVX512] in {
6152 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6153 v16i8x_info, i16mem, LdFrag, OpNode>,
6154 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6156 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6157 v16i8x_info, i32mem, LdFrag, OpNode>,
6158 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6160 let Predicates = [HasAVX512] in {
6161 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6162 v16i8x_info, i64mem, LdFrag, OpNode>,
6163 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6167 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6168 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6169 let Predicates = [HasVLX, HasAVX512] in {
6170 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6171 v8i16x_info, i64mem, LdFrag, OpNode>,
6172 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6174 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6175 v8i16x_info, i128mem, LdFrag, OpNode>,
6176 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6178 let Predicates = [HasAVX512] in {
6179 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6180 v16i16x_info, i256mem, LdFrag, OpNode>,
6181 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6185 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6186 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6187 let Predicates = [HasVLX, HasAVX512] in {
6188 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6189 v8i16x_info, i32mem, LdFrag, OpNode>,
6190 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6192 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6193 v8i16x_info, i64mem, LdFrag, OpNode>,
6194 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6196 let Predicates = [HasAVX512] in {
6197 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6198 v8i16x_info, i128mem, LdFrag, OpNode>,
6199 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6203 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6204 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6206 let Predicates = [HasVLX, HasAVX512] in {
6207 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6208 v4i32x_info, i64mem, LdFrag, OpNode>,
6209 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6211 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6212 v4i32x_info, i128mem, LdFrag, OpNode>,
6213 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6215 let Predicates = [HasAVX512] in {
6216 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6217 v8i32x_info, i256mem, LdFrag, OpNode>,
6218 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6222 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6223 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6224 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6225 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6226 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6227 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6230 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6231 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6232 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6233 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6234 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6235 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6237 //===----------------------------------------------------------------------===//
6238 // GATHER - SCATTER Operations
6240 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6241 X86MemOperand memop, PatFrag GatherNode> {
6242 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6243 ExeDomain = _.ExeDomain in
6244 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6245 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6246 !strconcat(OpcodeStr#_.Suffix,
6247 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6248 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6249 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6250 vectoraddr:$src2))]>, EVEX, EVEX_K,
6251 EVEX_CD8<_.EltSize, CD8VT1>;
6254 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6255 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6256 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6257 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6258 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6259 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6260 let Predicates = [HasVLX] in {
6261 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6262 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6263 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6264 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6265 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6266 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6267 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6268 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6272 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6273 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6274 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6275 mgatherv16i32>, EVEX_V512;
6276 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6277 mgatherv8i64>, EVEX_V512;
6278 let Predicates = [HasVLX] in {
6279 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6280 vy32xmem, mgatherv8i32>, EVEX_V256;
6281 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6282 vy64xmem, mgatherv4i64>, EVEX_V256;
6283 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6284 vx32xmem, mgatherv4i32>, EVEX_V128;
6285 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6286 vx64xmem, mgatherv2i64>, EVEX_V128;
6291 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6292 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6294 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6295 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6297 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6298 X86MemOperand memop, PatFrag ScatterNode> {
6300 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6302 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6303 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6304 !strconcat(OpcodeStr#_.Suffix,
6305 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6306 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6307 _.KRCWM:$mask, vectoraddr:$dst))]>,
6308 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6311 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6312 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6313 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6314 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6315 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6316 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6317 let Predicates = [HasVLX] in {
6318 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6319 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6320 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6321 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6322 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6323 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6324 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6325 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6329 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6330 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6331 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6332 mscatterv16i32>, EVEX_V512;
6333 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6334 mscatterv8i64>, EVEX_V512;
6335 let Predicates = [HasVLX] in {
6336 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6337 vy32xmem, mscatterv8i32>, EVEX_V256;
6338 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6339 vy64xmem, mscatterv4i64>, EVEX_V256;
6340 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6341 vx32xmem, mscatterv4i32>, EVEX_V128;
6342 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6343 vx64xmem, mscatterv2i64>, EVEX_V128;
6347 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6348 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6350 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6351 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6354 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6355 RegisterClass KRC, X86MemOperand memop> {
6356 let Predicates = [HasPFI], hasSideEffects = 1 in
6357 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6358 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6362 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6363 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6365 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6366 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6368 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6369 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6371 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6372 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6374 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6375 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6377 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6378 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6380 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6381 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6383 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6384 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6386 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6387 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6389 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6390 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6392 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6393 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6395 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6396 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6398 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6399 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6401 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6402 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6404 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6405 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6407 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6408 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6410 // Helper fragments to match sext vXi1 to vXiY.
6411 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6412 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6414 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6415 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6416 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6418 def : Pat<(store VK1:$src, addr:$dst),
6420 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6421 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6423 def : Pat<(store VK8:$src, addr:$dst),
6425 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6426 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6428 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6429 (truncstore node:$val, node:$ptr), [{
6430 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6433 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6434 (MOV8mr addr:$dst, GR8:$src)>;
6436 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6437 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6438 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6439 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6442 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6443 string OpcodeStr, Predicate prd> {
6444 let Predicates = [prd] in
6445 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6447 let Predicates = [prd, HasVLX] in {
6448 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6449 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6453 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6454 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6456 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6458 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6460 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6464 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6466 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6467 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6468 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6469 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6472 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6473 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6474 let Predicates = [prd] in
6475 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6478 let Predicates = [prd, HasVLX] in {
6479 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6481 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6486 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6487 avx512vl_i8_info, HasBWI>;
6488 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6489 avx512vl_i16_info, HasBWI>, VEX_W;
6490 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6491 avx512vl_i32_info, HasDQI>;
6492 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6493 avx512vl_i64_info, HasDQI>, VEX_W;
6495 //===----------------------------------------------------------------------===//
6496 // AVX-512 - COMPRESS and EXPAND
6499 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6501 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6502 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6503 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6505 let mayStore = 1 in {
6506 def mr : AVX5128I<opc, MRMDestMem, (outs),
6507 (ins _.MemOp:$dst, _.RC:$src),
6508 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6509 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6511 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6512 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6513 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6514 [(store (_.VT (vselect _.KRCWM:$mask,
6515 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6517 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6521 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6522 AVX512VLVectorVTInfo VTInfo> {
6523 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6525 let Predicates = [HasVLX] in {
6526 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6527 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6531 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6533 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6535 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6537 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6541 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6543 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6544 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6545 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6548 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6549 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6550 (_.VT (X86expand (_.VT (bitconvert
6551 (_.LdFrag addr:$src1)))))>,
6552 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6555 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6556 AVX512VLVectorVTInfo VTInfo> {
6557 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6559 let Predicates = [HasVLX] in {
6560 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6561 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6565 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6567 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6569 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6571 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6574 //handle instruction reg_vec1 = op(reg_vec,imm)
6576 // op(broadcast(eltVt),imm)
6577 //all instruction created with FROUND_CURRENT
6578 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6580 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6581 (ins _.RC:$src1, i32u8imm:$src2),
6582 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6583 (OpNode (_.VT _.RC:$src1),
6585 (i32 FROUND_CURRENT))>;
6586 let mayLoad = 1 in {
6587 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6588 (ins _.MemOp:$src1, i32u8imm:$src2),
6589 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6590 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6592 (i32 FROUND_CURRENT))>;
6593 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6594 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6595 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6596 "${src1}"##_.BroadcastStr##", $src2",
6597 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6599 (i32 FROUND_CURRENT))>, EVEX_B;
6603 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6604 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6605 SDNode OpNode, X86VectorVTInfo _>{
6606 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6607 (ins _.RC:$src1, i32u8imm:$src2),
6608 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6609 "$src1, {sae}, $src2",
6610 (OpNode (_.VT _.RC:$src1),
6612 (i32 FROUND_NO_EXC))>, EVEX_B;
6615 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6616 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6617 let Predicates = [prd] in {
6618 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6619 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6622 let Predicates = [prd, HasVLX] in {
6623 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6625 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6630 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6631 // op(reg_vec2,mem_vec,imm)
6632 // op(reg_vec2,broadcast(eltVt),imm)
6633 //all instruction created with FROUND_CURRENT
6634 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6636 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6637 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6638 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6639 (OpNode (_.VT _.RC:$src1),
6642 (i32 FROUND_CURRENT))>;
6643 let mayLoad = 1 in {
6644 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6645 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6646 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6647 (OpNode (_.VT _.RC:$src1),
6648 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6650 (i32 FROUND_CURRENT))>;
6651 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6652 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6653 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6654 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6655 (OpNode (_.VT _.RC:$src1),
6656 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6658 (i32 FROUND_CURRENT))>, EVEX_B;
6662 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6663 // op(reg_vec2,mem_vec,imm)
6664 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6665 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6667 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6668 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6669 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6670 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6671 (SrcInfo.VT SrcInfo.RC:$src2),
6674 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6675 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6676 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6677 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6678 (SrcInfo.VT (bitconvert
6679 (SrcInfo.LdFrag addr:$src2))),
6683 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6684 // op(reg_vec2,mem_vec,imm)
6685 // op(reg_vec2,broadcast(eltVt),imm)
6686 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6688 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6691 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6692 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6693 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6694 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6695 (OpNode (_.VT _.RC:$src1),
6696 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6697 (i8 imm:$src3))>, EVEX_B;
6700 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6701 // op(reg_vec2,mem_scalar,imm)
6702 //all instruction created with FROUND_CURRENT
6703 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6704 X86VectorVTInfo _> {
6706 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6707 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6708 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6709 (OpNode (_.VT _.RC:$src1),
6712 (i32 FROUND_CURRENT))>;
6713 let mayLoad = 1 in {
6714 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6715 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6716 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6717 (OpNode (_.VT _.RC:$src1),
6718 (_.VT (scalar_to_vector
6719 (_.ScalarLdFrag addr:$src2))),
6721 (i32 FROUND_CURRENT))>;
6723 let isAsmParserOnly = 1 in {
6724 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6725 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6726 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6732 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6733 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6734 SDNode OpNode, X86VectorVTInfo _>{
6735 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6736 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6737 OpcodeStr, "$src3,{sae}, $src2, $src1",
6738 "$src1, $src2,{sae}, $src3",
6739 (OpNode (_.VT _.RC:$src1),
6742 (i32 FROUND_NO_EXC))>, EVEX_B;
6744 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6745 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6746 SDNode OpNode, X86VectorVTInfo _> {
6747 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6748 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6749 OpcodeStr, "$src3,{sae}, $src2, $src1",
6750 "$src1, $src2,{sae}, $src3",
6751 (OpNode (_.VT _.RC:$src1),
6754 (i32 FROUND_NO_EXC))>, EVEX_B;
6757 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6758 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6759 let Predicates = [prd] in {
6760 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6761 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6765 let Predicates = [prd, HasVLX] in {
6766 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6768 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6773 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6774 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6775 let Predicates = [HasBWI] in {
6776 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6777 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6779 let Predicates = [HasBWI, HasVLX] in {
6780 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6781 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6782 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6783 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6787 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6788 bits<8> opc, SDNode OpNode>{
6789 let Predicates = [HasAVX512] in {
6790 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6792 let Predicates = [HasAVX512, HasVLX] in {
6793 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6794 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6798 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6799 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6800 let Predicates = [prd] in {
6801 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6802 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6806 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6807 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6808 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6809 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6810 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6811 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6814 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6815 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6816 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6817 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6818 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6819 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6821 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6822 0x55, X86VFixupimm, HasAVX512>,
6823 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6824 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6825 0x55, X86VFixupimm, HasAVX512>,
6826 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6828 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6829 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6830 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6831 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6832 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6833 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6836 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6837 0x50, X86VRange, HasDQI>,
6838 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6839 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6840 0x50, X86VRange, HasDQI>,
6841 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6843 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6844 0x51, X86VRange, HasDQI>,
6845 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6846 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6847 0x51, X86VRange, HasDQI>,
6848 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6850 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6851 0x57, X86Reduces, HasDQI>,
6852 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6853 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6854 0x57, X86Reduces, HasDQI>,
6855 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6857 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6858 0x27, X86GetMants, HasAVX512>,
6859 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6860 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6861 0x27, X86GetMants, HasAVX512>,
6862 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6864 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6865 bits<8> opc, SDNode OpNode = X86Shuf128>{
6866 let Predicates = [HasAVX512] in {
6867 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6870 let Predicates = [HasAVX512, HasVLX] in {
6871 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6874 let Predicates = [HasAVX512] in {
6875 def : Pat<(v16f32 (ffloor VR512:$src)),
6876 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6877 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6878 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6879 def : Pat<(v16f32 (fceil VR512:$src)),
6880 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6881 def : Pat<(v16f32 (frint VR512:$src)),
6882 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6883 def : Pat<(v16f32 (ftrunc VR512:$src)),
6884 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6886 def : Pat<(v8f64 (ffloor VR512:$src)),
6887 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6888 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6889 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6890 def : Pat<(v8f64 (fceil VR512:$src)),
6891 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6892 def : Pat<(v8f64 (frint VR512:$src)),
6893 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6894 def : Pat<(v8f64 (ftrunc VR512:$src)),
6895 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6898 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6899 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6900 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6901 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6902 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6903 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6904 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6905 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6907 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6908 AVX512VLVectorVTInfo VTInfo_FP>{
6909 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6910 AVX512AIi8Base, EVEX_4V;
6911 let isCodeGenOnly = 1 in {
6912 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6913 AVX512AIi8Base, EVEX_4V;
6917 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6918 EVEX_CD8<32, CD8VF>;
6919 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6920 EVEX_CD8<64, CD8VF>, VEX_W;
6922 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6923 let Predicates = p in
6924 def NAME#_.VTName#rri:
6925 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6926 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6927 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6930 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6931 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6932 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6933 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6935 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6936 avx512vl_i8_info, avx512vl_i8_info>,
6937 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6938 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6939 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6940 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6941 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6944 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
6945 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
6947 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6948 X86VectorVTInfo _> {
6949 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6950 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6952 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6955 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6956 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6958 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6959 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6962 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6963 X86VectorVTInfo _> :
6964 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6966 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6967 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6968 "${src1}"##_.BroadcastStr,
6969 "${src1}"##_.BroadcastStr,
6970 (_.VT (OpNode (X86VBroadcast
6971 (_.ScalarLdFrag addr:$src1))))>,
6972 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6975 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6976 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6977 let Predicates = [prd] in
6978 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6980 let Predicates = [prd, HasVLX] in {
6981 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6983 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6988 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6989 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6990 let Predicates = [prd] in
6991 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6994 let Predicates = [prd, HasVLX] in {
6995 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6997 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7002 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7003 SDNode OpNode, Predicate prd> {
7004 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
7006 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
7009 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7010 SDNode OpNode, Predicate prd> {
7011 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
7012 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
7015 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7016 bits<8> opc_d, bits<8> opc_q,
7017 string OpcodeStr, SDNode OpNode> {
7018 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7020 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7024 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7027 (bc_v16i32 (v16i1sextv16i32)),
7028 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7029 (VPABSDZrr VR512:$src)>;
7031 (bc_v8i64 (v8i1sextv8i64)),
7032 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7033 (VPABSQZrr VR512:$src)>;
7035 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7037 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7038 let isCodeGenOnly = 1 in
7039 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
7040 ctlz_zero_undef, prd>;
7043 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7044 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7046 //===----------------------------------------------------------------------===//
7047 // AVX-512 - Unpack Instructions
7048 //===----------------------------------------------------------------------===//
7049 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7050 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7052 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7053 SSE_INTALU_ITINS_P, HasBWI>;
7054 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7055 SSE_INTALU_ITINS_P, HasBWI>;
7056 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7057 SSE_INTALU_ITINS_P, HasBWI>;
7058 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7059 SSE_INTALU_ITINS_P, HasBWI>;
7061 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7062 SSE_INTALU_ITINS_P, HasAVX512>;
7063 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7064 SSE_INTALU_ITINS_P, HasAVX512>;
7065 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7066 SSE_INTALU_ITINS_P, HasAVX512>;
7067 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7068 SSE_INTALU_ITINS_P, HasAVX512>;
7070 //===----------------------------------------------------------------------===//
7071 // AVX-512 - Extract & Insert Integer Instructions
7072 //===----------------------------------------------------------------------===//
7074 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7075 X86VectorVTInfo _> {
7077 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7078 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7079 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7080 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7083 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7086 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7087 let Predicates = [HasBWI] in {
7088 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7089 (ins _.RC:$src1, u8imm:$src2),
7090 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7091 [(set GR32orGR64:$dst,
7092 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7095 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7099 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7100 let Predicates = [HasBWI] in {
7101 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7102 (ins _.RC:$src1, u8imm:$src2),
7103 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7104 [(set GR32orGR64:$dst,
7105 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7108 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7112 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7113 RegisterClass GRC> {
7114 let Predicates = [HasDQI] in {
7115 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7116 (ins _.RC:$src1, u8imm:$src2),
7117 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7119 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7123 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7124 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7125 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7126 [(store (extractelt (_.VT _.RC:$src1),
7127 imm:$src2),addr:$dst)]>,
7128 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7132 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7133 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7134 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7135 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7137 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7138 X86VectorVTInfo _, PatFrag LdFrag> {
7139 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7140 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7141 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7143 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7144 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7147 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7148 X86VectorVTInfo _, PatFrag LdFrag> {
7149 let Predicates = [HasBWI] in {
7150 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7151 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7152 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7154 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7156 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7160 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7161 X86VectorVTInfo _, RegisterClass GRC> {
7162 let Predicates = [HasDQI] in {
7163 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7164 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7165 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7167 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7170 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7171 _.ScalarLdFrag>, TAPD;
7175 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7177 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7179 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7180 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7181 //===----------------------------------------------------------------------===//
7182 // VSHUFPS - VSHUFPD Operations
7183 //===----------------------------------------------------------------------===//
7184 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7185 AVX512VLVectorVTInfo VTInfo_FP>{
7186 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7187 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7188 AVX512AIi8Base, EVEX_4V;
7189 let isCodeGenOnly = 1 in {
7190 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7191 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7192 AVX512AIi8Base, EVEX_4V;
7196 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7197 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7198 //===----------------------------------------------------------------------===//
7199 // AVX-512 - Byte shift Left/Right
7200 //===----------------------------------------------------------------------===//
7202 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7203 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7204 def rr : AVX512<opc, MRMr,
7205 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7206 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7207 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7209 def rm : AVX512<opc, MRMm,
7210 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7211 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7212 [(set _.RC:$dst,(_.VT (OpNode
7213 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7216 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7217 Format MRMm, string OpcodeStr, Predicate prd>{
7218 let Predicates = [prd] in
7219 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7220 OpcodeStr, v8i64_info>, EVEX_V512;
7221 let Predicates = [prd, HasVLX] in {
7222 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7223 OpcodeStr, v4i64x_info>, EVEX_V256;
7224 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7225 OpcodeStr, v2i64x_info>, EVEX_V128;
7228 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7229 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7230 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7231 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7234 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7235 string OpcodeStr, X86VectorVTInfo _src>{
7236 def rr : AVX512BI<opc, MRMSrcReg,
7237 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7238 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7239 [(set _src.RC:$dst,(_src.VT
7240 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
7242 def rm : AVX512BI<opc, MRMSrcMem,
7243 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7245 [(set _src.RC:$dst,(_src.VT
7246 (OpNode _src.RC:$src1,
7247 (_src.VT (bitconvert
7248 (_src.LdFrag addr:$src2))))))]>;
7251 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7252 string OpcodeStr, Predicate prd> {
7253 let Predicates = [prd] in
7254 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
7256 let Predicates = [prd, HasVLX] in {
7257 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
7259 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
7264 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7267 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7269 let Constraints = "$src1 = $dst" in {
7270 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7271 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7272 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7273 (OpNode (_.VT _.RC:$src1),
7276 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7277 let mayLoad = 1 in {
7278 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7279 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7280 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7281 (OpNode (_.VT _.RC:$src1),
7283 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7285 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7286 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7287 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7288 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7289 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7290 (OpNode (_.VT _.RC:$src1),
7292 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7293 (i8 imm:$src4))>, EVEX_B,
7294 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7296 }// Constraints = "$src1 = $dst"
7299 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7300 let Predicates = [HasAVX512] in
7301 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7302 let Predicates = [HasAVX512, HasVLX] in {
7303 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7304 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7308 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7309 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;