1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
8 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
11 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
12 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
13 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
14 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
15 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
16 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
17 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
18 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
19 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
20 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
21 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
22 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
23 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
24 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
25 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
26 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
27 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
28 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
29 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
30 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
31 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
32 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
33 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
35 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
36 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
37 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
38 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
39 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
40 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
41 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
42 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
43 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
44 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
45 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
46 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
47 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
48 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
49 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
50 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
51 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
52 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
53 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
54 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
55 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
56 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
57 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
58 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
59 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
60 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
61 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
62 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
63 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
64 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
66 // Bitcasts between 256-bit vector types. Return the original type since
67 // no instruction is needed for the conversion
68 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
69 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
70 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
71 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
72 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
73 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
74 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
75 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
76 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
77 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
78 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
79 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
80 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
81 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
82 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
83 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
84 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
85 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
86 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
87 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
88 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
89 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
90 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
91 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
92 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
93 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
94 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
95 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
96 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
97 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
101 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
104 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
105 isPseudo = 1, Predicates = [HasAVX512] in {
106 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
107 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
110 let Predicates = [HasAVX512] in {
111 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
112 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
113 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
116 //===----------------------------------------------------------------------===//
117 // AVX-512 - VECTOR INSERT
120 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
121 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
122 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
123 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512;
126 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
127 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
128 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
129 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
132 // -- 64x4 fp form --
133 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
134 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
135 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
136 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, VEX_W;
139 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
140 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
141 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
142 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
144 // -- 32x4 integer form --
145 let hasSideEffects = 0 in {
146 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
147 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
148 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
149 []>, EVEX_4V, EVEX_V512;
151 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
152 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
153 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
154 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
157 let hasSideEffects = 0 in {
159 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
160 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
161 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
162 []>, EVEX_4V, EVEX_V512, VEX_W;
164 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
165 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
166 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
167 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
170 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
171 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
174 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
177 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
180 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
181 (INSERT_get_vinsert128_imm VR512:$ins))>;
183 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
184 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
185 (INSERT_get_vinsert128_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
187 (bc_v4i32 (loadv2i64 addr:$src2)),
188 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
189 (INSERT_get_vinsert128_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
191 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
192 (INSERT_get_vinsert128_imm VR512:$ins))>;
193 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
194 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert128_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
198 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
201 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
204 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
207 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
208 (INSERT_get_vinsert256_imm VR512:$ins))>;
210 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
211 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
212 (INSERT_get_vinsert256_imm VR512:$ins))>;
213 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
214 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
215 (INSERT_get_vinsert256_imm VR512:$ins))>;
216 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
217 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
218 (INSERT_get_vinsert256_imm VR512:$ins))>;
219 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
220 (bc_v8i32 (loadv4i64 addr:$src2)),
221 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
222 (INSERT_get_vinsert256_imm VR512:$ins))>;
224 // vinsertps - insert f32 to XMM
225 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
226 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
227 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
228 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
230 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
231 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
232 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
233 [(set VR128X:$dst, (X86insertps VR128X:$src1,
234 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
235 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
237 //===----------------------------------------------------------------------===//
238 // AVX-512 VECTOR EXTRACT
240 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
242 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
243 (ins VR512:$src1, i8imm:$src2),
244 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
245 []>, EVEX, EVEX_V512;
246 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
247 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
248 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
249 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
252 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
253 (ins VR512:$src1, i8imm:$src2),
254 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, VEX_W;
257 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
258 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
259 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
260 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
263 let hasSideEffects = 0 in {
265 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
266 (ins VR512:$src1, i8imm:$src2),
267 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
268 []>, EVEX, EVEX_V512;
269 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
270 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
271 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
272 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
275 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
276 (ins VR512:$src1, i8imm:$src2),
277 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
278 []>, EVEX, EVEX_V512, VEX_W;
280 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
281 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
282 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
283 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
286 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
288 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
290 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
291 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
292 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
294 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
296 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
298 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
300 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
303 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
304 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
305 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
307 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
308 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
309 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
311 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
312 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
313 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
315 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
316 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
317 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
319 // A 256-bit subvector extract from the first 512-bit vector position
320 // is a subregister copy that needs no instruction.
321 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
322 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
323 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
324 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
325 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
326 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
327 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
328 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
331 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
332 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
333 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
334 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
335 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
336 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
337 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
338 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
341 // A 128-bit subvector insert to the first 512-bit vector position
342 // is a subregister copy that needs no instruction.
343 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
345 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
347 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
349 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
351 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
352 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
353 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
355 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
356 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
357 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
360 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
361 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
362 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
364 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
365 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
366 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
369 // vextractps - extract 32 bits from XMM
370 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
371 (ins VR128X:$src1, u32u8imm:$src2),
372 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
373 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
376 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
377 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
378 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
379 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
380 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
382 //===---------------------------------------------------------------------===//
385 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
386 RegisterClass DestRC,
387 RegisterClass SrcRC, X86MemOperand x86memop> {
388 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
389 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
391 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
392 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
394 let ExeDomain = SSEPackedSingle in {
395 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
397 EVEX_V512, EVEX_CD8<32, CD8VT1>;
400 let ExeDomain = SSEPackedDouble in {
401 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
403 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
406 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
407 (VBROADCASTSSZrm addr:$src)>;
408 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
409 (VBROADCASTSDZrm addr:$src)>;
411 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
412 (VBROADCASTSSZrm addr:$src)>;
413 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
414 (VBROADCASTSDZrm addr:$src)>;
416 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
417 RegisterClass SrcRC, RegisterClass KRC> {
418 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
419 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
420 []>, EVEX, EVEX_V512;
421 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
422 (ins KRC:$mask, SrcRC:$src),
423 !strconcat(OpcodeStr,
424 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
425 []>, EVEX, EVEX_V512, EVEX_KZ;
428 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
429 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
432 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
433 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
435 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
436 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
438 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
439 (VPBROADCASTDrZrr GR32:$src)>;
440 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
441 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
442 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
443 (VPBROADCASTQrZrr GR64:$src)>;
444 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
445 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
447 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
448 (VPBROADCASTDrZrr GR32:$src)>;
449 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
450 (VPBROADCASTQrZrr GR64:$src)>;
452 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
453 (v16i32 immAllZerosV), (i16 GR16:$mask))),
454 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
455 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
456 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
457 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
459 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
460 X86MemOperand x86memop, PatFrag ld_frag,
461 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
463 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
464 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
466 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
467 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
469 !strconcat(OpcodeStr,
470 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
472 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
475 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
476 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
478 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
479 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
481 !strconcat(OpcodeStr,
482 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
483 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
484 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
488 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
489 loadi32, VR512, v16i32, v4i32, VK16WM>,
490 EVEX_V512, EVEX_CD8<32, CD8VT1>;
491 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
492 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
493 EVEX_CD8<64, CD8VT1>;
495 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
496 X86MemOperand x86memop, PatFrag ld_frag,
499 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
500 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
502 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
504 !strconcat(OpcodeStr,
505 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
510 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
511 i128mem, loadv2i64, VK16WM>,
512 EVEX_V512, EVEX_CD8<32, CD8VT4>;
513 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
514 i256mem, loadv4i64, VK16WM>, VEX_W,
515 EVEX_V512, EVEX_CD8<64, CD8VT4>;
517 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
518 (VPBROADCASTDZrr VR128X:$src)>;
519 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
520 (VPBROADCASTQZrr VR128X:$src)>;
522 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
523 (VBROADCASTSSZrr VR128X:$src)>;
524 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
525 (VBROADCASTSDZrr VR128X:$src)>;
527 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
528 (VBROADCASTSSZrr VR128X:$src)>;
529 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
530 (VBROADCASTSDZrr VR128X:$src)>;
532 // Provide fallback in case the load node that is used in the patterns above
533 // is used by additional users, which prevents the pattern selection.
534 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
535 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
536 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
537 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
540 let Predicates = [HasAVX512] in {
541 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
543 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
544 addr:$src)), sub_ymm)>;
546 //===----------------------------------------------------------------------===//
547 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
550 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
551 RegisterClass DstRC, RegisterClass KRC,
552 ValueType OpVT, ValueType SrcVT> {
553 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
554 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
558 let Predicates = [HasCDI] in {
559 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
560 VK16, v16i32, v16i1>, EVEX_V512;
561 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
562 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
565 //===----------------------------------------------------------------------===//
568 // -- immediate form --
569 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
570 SDNode OpNode, PatFrag mem_frag,
571 X86MemOperand x86memop, ValueType OpVT> {
572 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
573 (ins RC:$src1, i8imm:$src2),
574 !strconcat(OpcodeStr,
575 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
577 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
579 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
580 (ins x86memop:$src1, i8imm:$src2),
581 !strconcat(OpcodeStr,
582 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
584 (OpVT (OpNode (mem_frag addr:$src1),
585 (i8 imm:$src2))))]>, EVEX;
588 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
589 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
590 let ExeDomain = SSEPackedDouble in
591 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
592 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
594 // -- VPERM - register form --
595 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
596 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
598 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2),
600 !strconcat(OpcodeStr,
601 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
603 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
605 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
606 (ins RC:$src1, x86memop:$src2),
607 !strconcat(OpcodeStr,
608 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
610 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
614 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
615 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
616 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
617 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
618 let ExeDomain = SSEPackedSingle in
619 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
620 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
621 let ExeDomain = SSEPackedDouble in
622 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
623 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
625 // -- VPERM2I - 3 source operands form --
626 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
627 PatFrag mem_frag, X86MemOperand x86memop,
628 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
629 let Constraints = "$src1 = $dst" in {
630 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
631 (ins RC:$src1, RC:$src2, RC:$src3),
632 !strconcat(OpcodeStr,
633 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
635 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
638 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
639 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
640 !strconcat(OpcodeStr,
641 " \t{$src3, $src2, $dst {${mask}}|"
642 "$dst {${mask}}, $src2, $src3}"),
643 [(set RC:$dst, (OpVT (vselect KRC:$mask,
644 (OpNode RC:$src1, RC:$src2,
649 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
650 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
651 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
652 !strconcat(OpcodeStr,
653 " \t{$src3, $src2, $dst {${mask}} {z} |",
654 "$dst {${mask}} {z}, $src2, $src3}"),
655 [(set RC:$dst, (OpVT (vselect KRC:$mask,
656 (OpNode RC:$src1, RC:$src2,
659 (v16i32 immAllZerosV))))))]>,
662 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
663 (ins RC:$src1, RC:$src2, x86memop:$src3),
664 !strconcat(OpcodeStr,
665 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
667 (OpVT (OpNode RC:$src1, RC:$src2,
668 (mem_frag addr:$src3))))]>, EVEX_4V;
670 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
671 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
672 !strconcat(OpcodeStr,
673 " \t{$src3, $src2, $dst {${mask}}|"
674 "$dst {${mask}}, $src2, $src3}"),
676 (OpVT (vselect KRC:$mask,
677 (OpNode RC:$src1, RC:$src2,
678 (mem_frag addr:$src3)),
682 let AddedComplexity = 10 in // Prefer over the rrkz variant
683 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
684 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
685 !strconcat(OpcodeStr,
686 " \t{$src3, $src2, $dst {${mask}} {z}|"
687 "$dst {${mask}} {z}, $src2, $src3}"),
689 (OpVT (vselect KRC:$mask,
690 (OpNode RC:$src1, RC:$src2,
691 (mem_frag addr:$src3)),
693 (v16i32 immAllZerosV))))))]>,
697 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
698 i512mem, X86VPermiv3, v16i32, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VF>;
700 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
701 i512mem, X86VPermiv3, v8i64, VK8WM>,
702 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
703 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
704 i512mem, X86VPermiv3, v16f32, VK16WM>,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
706 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
707 i512mem, X86VPermiv3, v8f64, VK8WM>,
708 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
710 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
711 PatFrag mem_frag, X86MemOperand x86memop,
712 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
713 ValueType MaskVT, RegisterClass MRC> :
714 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
716 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
717 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
718 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
720 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
721 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
722 (!cast<Instruction>(NAME#rrk) VR512:$src1,
723 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
726 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
727 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
728 EVEX_V512, EVEX_CD8<32, CD8VF>;
729 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
730 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
731 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
732 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
733 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
734 EVEX_V512, EVEX_CD8<32, CD8VF>;
735 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
736 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
737 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
739 //===----------------------------------------------------------------------===//
740 // AVX-512 - BLEND using mask
742 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
743 RegisterClass KRC, RegisterClass RC,
744 X86MemOperand x86memop, PatFrag mem_frag,
745 SDNode OpNode, ValueType vt> {
746 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
747 (ins KRC:$mask, RC:$src1, RC:$src2),
748 !strconcat(OpcodeStr,
749 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
750 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
751 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
753 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
754 (ins KRC:$mask, RC:$src1, x86memop:$src2),
755 !strconcat(OpcodeStr,
756 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
757 []>, EVEX_4V, EVEX_K;
760 let ExeDomain = SSEPackedSingle in
761 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
762 VK16WM, VR512, f512mem,
763 memopv16f32, vselect, v16f32>,
764 EVEX_CD8<32, CD8VF>, EVEX_V512;
765 let ExeDomain = SSEPackedDouble in
766 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
767 VK8WM, VR512, f512mem,
768 memopv8f64, vselect, v8f64>,
769 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
771 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
772 (v16f32 VR512:$src2), (i16 GR16:$mask))),
773 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
774 VR512:$src1, VR512:$src2)>;
776 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
777 (v8f64 VR512:$src2), (i8 GR8:$mask))),
778 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
779 VR512:$src1, VR512:$src2)>;
781 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
782 VK16WM, VR512, f512mem,
783 memopv16i32, vselect, v16i32>,
784 EVEX_CD8<32, CD8VF>, EVEX_V512;
786 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
787 VK8WM, VR512, f512mem,
788 memopv8i64, vselect, v8i64>,
789 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
791 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
792 (v16i32 VR512:$src2), (i16 GR16:$mask))),
793 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
794 VR512:$src1, VR512:$src2)>;
796 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
797 (v8i64 VR512:$src2), (i8 GR8:$mask))),
798 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
799 VR512:$src1, VR512:$src2)>;
801 let Predicates = [HasAVX512] in {
802 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
803 (v8f32 VR256X:$src2))),
805 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
806 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
807 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
809 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
810 (v8i32 VR256X:$src2))),
812 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
814 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
816 //===----------------------------------------------------------------------===//
817 // Compare Instructions
818 //===----------------------------------------------------------------------===//
820 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
821 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
822 Operand CC, SDNode OpNode, ValueType VT,
823 PatFrag ld_frag, string asm, string asm_alt> {
824 def rr : AVX512Ii8<0xC2, MRMSrcReg,
825 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
826 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
827 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
828 def rm : AVX512Ii8<0xC2, MRMSrcMem,
829 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
830 [(set VK1:$dst, (OpNode (VT RC:$src1),
831 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
832 let isAsmParserOnly = 1, hasSideEffects = 0 in {
833 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
834 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
835 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
836 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
837 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
838 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
842 let Predicates = [HasAVX512] in {
843 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
844 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
845 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
847 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
848 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
849 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
853 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
854 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
855 SDNode OpNode, ValueType vt> {
856 def rr : AVX512BI<opc, MRMSrcReg,
857 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
858 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
859 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
860 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
861 def rm : AVX512BI<opc, MRMSrcMem,
862 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
863 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
864 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
865 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
868 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
869 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
871 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
872 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
873 VEX_W, EVEX_CD8<64, CD8VF>;
875 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
876 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
878 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
879 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
880 VEX_W, EVEX_CD8<64, CD8VF>;
882 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
883 (COPY_TO_REGCLASS (VPCMPGTDZrr
884 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
885 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
887 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
888 (COPY_TO_REGCLASS (VPCMPEQDZrr
889 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
890 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
892 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
893 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
894 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
895 def rri : AVX512AIi8<opc, MRMSrcReg,
896 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
897 !strconcat("vpcmp${cc}", Suffix,
898 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
899 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
900 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
901 def rmi : AVX512AIi8<opc, MRMSrcMem,
902 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
903 !strconcat("vpcmp${cc}", Suffix,
904 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
905 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
906 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
907 // Accept explicit immediate argument form instead of comparison code.
908 let isAsmParserOnly = 1, hasSideEffects = 0 in {
909 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
910 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
911 !strconcat("vpcmp", Suffix,
912 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
913 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
914 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
915 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
916 !strconcat("vpcmp", Suffix,
917 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
918 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
919 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
920 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
921 !strconcat("vpcmp", Suffix,
922 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
923 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
924 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
925 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
926 !strconcat("vpcmp", Suffix,
927 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
928 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
932 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
933 X86cmpm, v16i32, AVXCC, "d">,
934 EVEX_V512, EVEX_CD8<32, CD8VF>;
935 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
936 X86cmpmu, v16i32, AVXCC, "ud">,
937 EVEX_V512, EVEX_CD8<32, CD8VF>;
939 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
940 X86cmpm, v8i64, AVXCC, "q">,
941 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
942 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
943 X86cmpmu, v8i64, AVXCC, "uq">,
944 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
946 // avx512_cmp_packed - compare packed instructions
947 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
948 X86MemOperand x86memop, ValueType vt,
949 string suffix, Domain d> {
950 def rri : AVX512PIi8<0xC2, MRMSrcReg,
951 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
952 !strconcat("vcmp${cc}", suffix,
953 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
955 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
956 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
957 !strconcat("vcmp${cc}", suffix,
958 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
960 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
961 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
962 !strconcat("vcmp${cc}", suffix,
963 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
965 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
967 // Accept explicit immediate argument form instead of comparison code.
968 let isAsmParserOnly = 1, hasSideEffects = 0 in {
969 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
970 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
971 !strconcat("vcmp", suffix,
972 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
973 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
974 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
975 !strconcat("vcmp", suffix,
976 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
980 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
981 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
983 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
984 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
987 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
988 (COPY_TO_REGCLASS (VCMPPSZrri
989 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
990 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
992 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
993 (COPY_TO_REGCLASS (VPCMPDZrri
994 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
995 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
997 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
998 (COPY_TO_REGCLASS (VPCMPUDZrri
999 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1000 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1003 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1004 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1006 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1007 (I8Imm imm:$cc)), GR16)>;
1009 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1010 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1012 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1013 (I8Imm imm:$cc)), GR8)>;
1015 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1016 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1018 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1019 (I8Imm imm:$cc)), GR16)>;
1021 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1022 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1024 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1025 (I8Imm imm:$cc)), GR8)>;
1027 // Mask register copy, including
1028 // - copy between mask registers
1029 // - load/store mask registers
1030 // - copy from GPR to mask register and vice versa
1032 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1033 string OpcodeStr, RegisterClass KRC,
1034 ValueType vt, X86MemOperand x86memop> {
1035 let hasSideEffects = 0 in {
1036 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1037 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1039 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1040 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1041 [(set KRC:$dst, (vt (load addr:$src)))]>;
1043 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1044 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1048 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1050 RegisterClass KRC, RegisterClass GRC> {
1051 let hasSideEffects = 0 in {
1052 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1053 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1054 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1055 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1059 let Predicates = [HasAVX512] in {
1060 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1062 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1066 let Predicates = [HasAVX512] in {
1067 // GR16 from/to 16-bit mask
1068 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1069 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1070 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1071 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1073 // Store kreg in memory
1074 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
1075 (KMOVWmk addr:$dst, VK16:$src)>;
1077 def : Pat<(store VK8:$src, addr:$dst),
1078 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1080 def : Pat<(i1 (load addr:$src)),
1081 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1083 def : Pat<(v8i1 (load addr:$src)),
1084 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1086 def : Pat<(i1 (trunc (i32 GR32:$src))),
1087 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1089 def : Pat<(i1 (trunc (i8 GR8:$src))),
1091 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1093 def : Pat<(i1 (trunc (i16 GR16:$src))),
1095 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1098 def : Pat<(i32 (zext VK1:$src)),
1099 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1100 def : Pat<(i8 (zext VK1:$src)),
1103 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1104 def : Pat<(i64 (zext VK1:$src)),
1105 (AND64ri8 (SUBREG_TO_REG (i64 0),
1106 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1107 def : Pat<(i16 (zext VK1:$src)),
1109 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1111 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1112 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1113 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1114 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1116 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1117 let Predicates = [HasAVX512] in {
1118 // GR from/to 8-bit mask without native support
1119 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1121 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1123 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1125 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1128 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1129 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1130 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1131 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1135 // Mask unary operation
1137 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1138 RegisterClass KRC, SDPatternOperator OpNode> {
1139 let Predicates = [HasAVX512] in
1140 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1141 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1142 [(set KRC:$dst, (OpNode KRC:$src))]>;
1145 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1146 SDPatternOperator OpNode> {
1147 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1151 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1153 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1154 let Predicates = [HasAVX512] in
1155 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1157 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1158 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1160 defm : avx512_mask_unop_int<"knot", "KNOT">;
1162 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1163 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1164 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1166 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1167 def : Pat<(not VK8:$src),
1169 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1171 // Mask binary operation
1172 // - KAND, KANDN, KOR, KXNOR, KXOR
1173 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1174 RegisterClass KRC, SDPatternOperator OpNode> {
1175 let Predicates = [HasAVX512] in
1176 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1177 !strconcat(OpcodeStr,
1178 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1179 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1182 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1183 SDPatternOperator OpNode> {
1184 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1188 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1189 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1191 let isCommutable = 1 in {
1192 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1193 let isCommutable = 0 in
1194 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1195 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1196 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1197 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1200 def : Pat<(xor VK1:$src1, VK1:$src2),
1201 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1202 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1204 def : Pat<(or VK1:$src1, VK1:$src2),
1205 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1206 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1208 def : Pat<(and VK1:$src1, VK1:$src2),
1209 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1210 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1212 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1213 let Predicates = [HasAVX512] in
1214 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1215 (i16 GR16:$src1), (i16 GR16:$src2)),
1216 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1217 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1218 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1221 defm : avx512_mask_binop_int<"kand", "KAND">;
1222 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1223 defm : avx512_mask_binop_int<"kor", "KOR">;
1224 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1225 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1227 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1228 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1229 let Predicates = [HasAVX512] in
1230 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1232 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1233 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1236 defm : avx512_binop_pat<and, KANDWrr>;
1237 defm : avx512_binop_pat<andn, KANDNWrr>;
1238 defm : avx512_binop_pat<or, KORWrr>;
1239 defm : avx512_binop_pat<xnor, KXNORWrr>;
1240 defm : avx512_binop_pat<xor, KXORWrr>;
1243 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1244 RegisterClass KRC> {
1245 let Predicates = [HasAVX512] in
1246 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1247 !strconcat(OpcodeStr,
1248 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1251 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1252 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1256 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1257 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1258 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1259 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1262 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1263 let Predicates = [HasAVX512] in
1264 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1265 (i16 GR16:$src1), (i16 GR16:$src2)),
1266 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1267 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1268 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1270 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1273 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1275 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1276 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1277 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1278 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1281 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1282 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1286 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1288 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1289 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1290 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1293 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1295 let Predicates = [HasAVX512] in
1296 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1297 !strconcat(OpcodeStr,
1298 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1299 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1302 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1304 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1308 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1309 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1311 // Mask setting all 0s or 1s
1312 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1313 let Predicates = [HasAVX512] in
1314 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1315 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1316 [(set KRC:$dst, (VT Val))]>;
1319 multiclass avx512_mask_setop_w<PatFrag Val> {
1320 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1321 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1324 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1325 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1327 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1328 let Predicates = [HasAVX512] in {
1329 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1330 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1331 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1332 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1333 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1335 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1336 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1338 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1339 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1341 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1342 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1344 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1345 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1347 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1348 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1349 //===----------------------------------------------------------------------===//
1350 // AVX-512 - Aligned and unaligned load and store
1353 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1354 X86MemOperand x86memop, PatFrag ld_frag,
1355 string asm, Domain d,
1356 ValueType vt, bit IsReMaterializable = 1> {
1357 let hasSideEffects = 0 in {
1358 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1359 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1361 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1363 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1364 [], d>, EVEX, EVEX_KZ;
1366 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1367 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1368 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1369 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1370 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1371 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1372 (ins RC:$src1, KRC:$mask, RC:$src2),
1374 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1377 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1378 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1380 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1381 [], d>, EVEX, EVEX_K;
1384 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1385 (ins KRC:$mask, x86memop:$src2),
1387 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1388 [], d>, EVEX, EVEX_KZ;
1391 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1392 X86MemOperand x86memop, PatFrag store_frag,
1393 string asm, Domain d, ValueType vt> {
1394 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1395 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1396 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1398 let Constraints = "$src1 = $dst" in
1399 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1400 (ins RC:$src1, KRC:$mask, RC:$src2),
1402 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1404 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1405 (ins KRC:$mask, RC:$src),
1407 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1408 [], d>, EVEX, EVEX_KZ;
1410 let mayStore = 1 in {
1411 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1412 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1413 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1414 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1415 (ins x86memop:$dst, KRC:$mask, RC:$src),
1417 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1418 [], d>, EVEX, EVEX_K;
1419 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1420 (ins x86memop:$dst, KRC:$mask, RC:$src),
1422 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1423 [], d>, EVEX, EVEX_KZ;
1427 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1428 "vmovaps", SSEPackedSingle, v16f32>,
1429 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1430 "vmovaps", SSEPackedSingle, v16f32>,
1431 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1432 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1433 "vmovapd", SSEPackedDouble, v8f64>,
1434 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1435 "vmovapd", SSEPackedDouble, v8f64>,
1436 PD, EVEX_V512, VEX_W,
1437 EVEX_CD8<64, CD8VF>;
1438 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1439 "vmovups", SSEPackedSingle, v16f32>,
1440 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1441 "vmovups", SSEPackedSingle, v16f32>,
1442 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1443 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1444 "vmovupd", SSEPackedDouble, v8f64, 0>,
1445 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1446 "vmovupd", SSEPackedDouble, v8f64>,
1447 PD, EVEX_V512, VEX_W,
1448 EVEX_CD8<64, CD8VF>;
1449 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1450 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1451 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1453 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1454 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1455 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1457 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1459 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1461 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1463 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1466 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1467 "vmovdqa32", SSEPackedInt, v16i32>,
1468 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1469 "vmovdqa32", SSEPackedInt, v16i32>,
1470 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1471 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1472 "vmovdqa64", SSEPackedInt, v8i64>,
1473 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1474 "vmovdqa64", SSEPackedInt, v8i64>,
1475 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1476 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1477 "vmovdqu32", SSEPackedInt, v16i32>,
1478 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1479 "vmovdqu32", SSEPackedInt, v16i32>,
1480 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1481 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1482 "vmovdqu64", SSEPackedInt, v8i64>,
1483 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1484 "vmovdqu64", SSEPackedInt, v8i64>,
1485 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1487 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1488 (v16i32 immAllZerosV), GR16:$mask)),
1489 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1491 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1492 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1493 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1495 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1497 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1499 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1501 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1504 let AddedComplexity = 20 in {
1505 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1506 (bc_v8i64 (v16i32 immAllZerosV)))),
1507 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1509 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1510 (v8i64 VR512:$src))),
1511 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1514 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1515 (v16i32 immAllZerosV))),
1516 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1518 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1519 (v16i32 VR512:$src))),
1520 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1522 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1523 (v16f32 VR512:$src2))),
1524 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1525 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1526 (v8f64 VR512:$src2))),
1527 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1528 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1529 (v16i32 VR512:$src2))),
1530 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1531 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1532 (v8i64 VR512:$src2))),
1533 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1535 // Move Int Doubleword to Packed Double Int
1537 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1538 "vmovd\t{$src, $dst|$dst, $src}",
1540 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1542 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1543 "vmovd\t{$src, $dst|$dst, $src}",
1545 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1546 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1547 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1548 "vmovq\t{$src, $dst|$dst, $src}",
1550 (v2i64 (scalar_to_vector GR64:$src)))],
1551 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1552 let isCodeGenOnly = 1 in {
1553 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1554 "vmovq\t{$src, $dst|$dst, $src}",
1555 [(set FR64:$dst, (bitconvert GR64:$src))],
1556 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1557 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1558 "vmovq\t{$src, $dst|$dst, $src}",
1559 [(set GR64:$dst, (bitconvert FR64:$src))],
1560 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1562 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1563 "vmovq\t{$src, $dst|$dst, $src}",
1564 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1565 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1566 EVEX_CD8<64, CD8VT1>;
1568 // Move Int Doubleword to Single Scalar
1570 let isCodeGenOnly = 1 in {
1571 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1572 "vmovd\t{$src, $dst|$dst, $src}",
1573 [(set FR32X:$dst, (bitconvert GR32:$src))],
1574 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1576 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1577 "vmovd\t{$src, $dst|$dst, $src}",
1578 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1579 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1582 // Move doubleword from xmm register to r/m32
1584 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1585 "vmovd\t{$src, $dst|$dst, $src}",
1586 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1587 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1589 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1590 (ins i32mem:$dst, VR128X:$src),
1591 "vmovd\t{$src, $dst|$dst, $src}",
1592 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1593 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1594 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1596 // Move quadword from xmm1 register to r/m64
1598 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1599 "vmovq\t{$src, $dst|$dst, $src}",
1600 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1602 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1603 Requires<[HasAVX512, In64BitMode]>;
1605 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1606 (ins i64mem:$dst, VR128X:$src),
1607 "vmovq\t{$src, $dst|$dst, $src}",
1608 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1609 addr:$dst)], IIC_SSE_MOVDQ>,
1610 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1611 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1613 // Move Scalar Single to Double Int
1615 let isCodeGenOnly = 1 in {
1616 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1618 "vmovd\t{$src, $dst|$dst, $src}",
1619 [(set GR32:$dst, (bitconvert FR32X:$src))],
1620 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1621 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1622 (ins i32mem:$dst, FR32X:$src),
1623 "vmovd\t{$src, $dst|$dst, $src}",
1624 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1625 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1628 // Move Quadword Int to Packed Quadword Int
1630 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1632 "vmovq\t{$src, $dst|$dst, $src}",
1634 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1635 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1637 //===----------------------------------------------------------------------===//
1638 // AVX-512 MOVSS, MOVSD
1639 //===----------------------------------------------------------------------===//
1641 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1642 SDNode OpNode, ValueType vt,
1643 X86MemOperand x86memop, PatFrag mem_pat> {
1644 let hasSideEffects = 0 in {
1645 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1646 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1647 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1648 (scalar_to_vector RC:$src2))))],
1649 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1650 let Constraints = "$src1 = $dst" in
1651 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1652 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1654 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1655 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1656 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1657 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1658 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1660 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1661 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1662 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1664 } //hasSideEffects = 0
1667 let ExeDomain = SSEPackedSingle in
1668 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1669 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1671 let ExeDomain = SSEPackedDouble in
1672 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1673 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1675 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1676 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1677 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1679 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1680 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1681 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1683 // For the disassembler
1684 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1685 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1686 (ins VR128X:$src1, FR32X:$src2),
1687 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1689 XS, EVEX_4V, VEX_LIG;
1690 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1691 (ins VR128X:$src1, FR64X:$src2),
1692 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1694 XD, EVEX_4V, VEX_LIG, VEX_W;
1697 let Predicates = [HasAVX512] in {
1698 let AddedComplexity = 15 in {
1699 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1700 // MOVS{S,D} to the lower bits.
1701 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1702 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1703 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1704 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1705 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1706 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1707 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1708 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1710 // Move low f32 and clear high bits.
1711 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1712 (SUBREG_TO_REG (i32 0),
1713 (VMOVSSZrr (v4f32 (V_SET0)),
1714 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1715 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1716 (SUBREG_TO_REG (i32 0),
1717 (VMOVSSZrr (v4i32 (V_SET0)),
1718 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1721 let AddedComplexity = 20 in {
1722 // MOVSSrm zeros the high parts of the register; represent this
1723 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1724 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1725 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1726 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1727 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1728 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1729 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1731 // MOVSDrm zeros the high parts of the register; represent this
1732 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1733 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1734 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1735 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1736 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1737 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1738 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1739 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1740 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1741 def : Pat<(v2f64 (X86vzload addr:$src)),
1742 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1744 // Represent the same patterns above but in the form they appear for
1746 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1747 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1748 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1749 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1750 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1751 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1752 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1753 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1754 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1756 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1757 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1758 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1759 FR32X:$src)), sub_xmm)>;
1760 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1761 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1762 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1763 FR64X:$src)), sub_xmm)>;
1764 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1765 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1766 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1768 // Move low f64 and clear high bits.
1769 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1770 (SUBREG_TO_REG (i32 0),
1771 (VMOVSDZrr (v2f64 (V_SET0)),
1772 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1774 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1775 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1776 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1778 // Extract and store.
1779 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1781 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1782 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1784 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1786 // Shuffle with VMOVSS
1787 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1788 (VMOVSSZrr (v4i32 VR128X:$src1),
1789 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1790 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1791 (VMOVSSZrr (v4f32 VR128X:$src1),
1792 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1795 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1796 (SUBREG_TO_REG (i32 0),
1797 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1798 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1800 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1801 (SUBREG_TO_REG (i32 0),
1802 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1803 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1806 // Shuffle with VMOVSD
1807 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1808 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1809 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1810 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1811 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1812 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1813 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1814 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1817 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1818 (SUBREG_TO_REG (i32 0),
1819 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1820 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1822 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1823 (SUBREG_TO_REG (i32 0),
1824 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1825 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1828 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1829 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1830 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1831 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1832 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1833 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1834 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1835 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1838 let AddedComplexity = 15 in
1839 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1841 "vmovq\t{$src, $dst|$dst, $src}",
1842 [(set VR128X:$dst, (v2i64 (X86vzmovl
1843 (v2i64 VR128X:$src))))],
1844 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1846 let AddedComplexity = 20 in
1847 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1849 "vmovq\t{$src, $dst|$dst, $src}",
1850 [(set VR128X:$dst, (v2i64 (X86vzmovl
1851 (loadv2i64 addr:$src))))],
1852 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1853 EVEX_CD8<8, CD8VT8>;
1855 let Predicates = [HasAVX512] in {
1856 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1857 let AddedComplexity = 20 in {
1858 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1859 (VMOVDI2PDIZrm addr:$src)>;
1860 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1861 (VMOV64toPQIZrr GR64:$src)>;
1862 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1863 (VMOVDI2PDIZrr GR32:$src)>;
1865 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1866 (VMOVDI2PDIZrm addr:$src)>;
1867 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1868 (VMOVDI2PDIZrm addr:$src)>;
1869 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1870 (VMOVZPQILo2PQIZrm addr:$src)>;
1871 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1872 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1873 def : Pat<(v2i64 (X86vzload addr:$src)),
1874 (VMOVZPQILo2PQIZrm addr:$src)>;
1877 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1878 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1879 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1880 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1881 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1882 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1883 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1886 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1887 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1889 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1890 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1892 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1893 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1895 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1896 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1898 //===----------------------------------------------------------------------===//
1899 // AVX-512 - Non-temporals
1900 //===----------------------------------------------------------------------===//
1902 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1904 "vmovntdqa\t{$src, $dst|$dst, $src}",
1906 (int_x86_avx512_movntdqa addr:$src))]>,
1907 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1909 // Prefer non-temporal over temporal versions
1910 let AddedComplexity = 400, SchedRW = [WriteStore] in {
1912 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
1913 (ins f512mem:$dst, VR512:$src),
1914 "vmovntps\t{$src, $dst|$dst, $src}",
1915 [(alignednontemporalstore (v16f32 VR512:$src),
1918 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1920 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
1921 (ins f512mem:$dst, VR512:$src),
1922 "vmovntpd\t{$src, $dst|$dst, $src}",
1923 [(alignednontemporalstore (v8f64 VR512:$src),
1926 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1929 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
1930 (ins i512mem:$dst, VR512:$src),
1931 "vmovntdq\t{$src, $dst|$dst, $src}",
1932 [(alignednontemporalstore (v8i64 VR512:$src),
1935 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1938 //===----------------------------------------------------------------------===//
1939 // AVX-512 - Integer arithmetic
1941 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1942 ValueType OpVT, RegisterClass KRC,
1943 RegisterClass RC, PatFrag memop_frag,
1944 X86MemOperand x86memop, PatFrag scalar_mfrag,
1945 X86MemOperand x86scalar_mop, string BrdcstStr,
1946 OpndItins itins, bit IsCommutable = 0> {
1947 let isCommutable = IsCommutable in
1948 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1949 (ins RC:$src1, RC:$src2),
1950 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1951 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1953 let AddedComplexity = 30 in {
1954 let Constraints = "$src0 = $dst" in
1955 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1956 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1957 !strconcat(OpcodeStr,
1958 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1959 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1960 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1962 itins.rr>, EVEX_4V, EVEX_K;
1963 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1964 (ins KRC:$mask, RC:$src1, RC:$src2),
1965 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1966 "|$dst {${mask}} {z}, $src1, $src2}"),
1967 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1968 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1969 (OpVT immAllZerosV))))],
1970 itins.rr>, EVEX_4V, EVEX_KZ;
1973 let mayLoad = 1 in {
1974 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1975 (ins RC:$src1, x86memop:$src2),
1976 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1977 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1979 let AddedComplexity = 30 in {
1980 let Constraints = "$src0 = $dst" in
1981 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1982 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1983 !strconcat(OpcodeStr,
1984 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1985 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1986 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1988 itins.rm>, EVEX_4V, EVEX_K;
1989 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1990 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1991 !strconcat(OpcodeStr,
1992 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1993 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1994 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1995 (OpVT immAllZerosV))))],
1996 itins.rm>, EVEX_4V, EVEX_KZ;
1998 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1999 (ins RC:$src1, x86scalar_mop:$src2),
2000 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2001 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2002 [(set RC:$dst, (OpNode RC:$src1,
2003 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2004 itins.rm>, EVEX_4V, EVEX_B;
2005 let AddedComplexity = 30 in {
2006 let Constraints = "$src0 = $dst" in
2007 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2008 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2009 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2010 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2012 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2013 (OpNode (OpVT RC:$src1),
2014 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2016 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2017 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2018 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2019 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2020 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2022 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2023 (OpNode (OpVT RC:$src1),
2024 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2025 (OpVT immAllZerosV))))],
2026 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2031 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2032 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2033 PatFrag memop_frag, X86MemOperand x86memop,
2034 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2035 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2036 let isCommutable = IsCommutable in
2038 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2039 (ins RC:$src1, RC:$src2),
2040 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2042 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2043 (ins KRC:$mask, RC:$src1, RC:$src2),
2044 !strconcat(OpcodeStr,
2045 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2046 [], itins.rr>, EVEX_4V, EVEX_K;
2047 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2048 (ins KRC:$mask, RC:$src1, RC:$src2),
2049 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2050 "|$dst {${mask}} {z}, $src1, $src2}"),
2051 [], itins.rr>, EVEX_4V, EVEX_KZ;
2053 let mayLoad = 1 in {
2054 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2055 (ins RC:$src1, x86memop:$src2),
2056 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2058 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2059 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2060 !strconcat(OpcodeStr,
2061 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2062 [], itins.rm>, EVEX_4V, EVEX_K;
2063 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2064 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2065 !strconcat(OpcodeStr,
2066 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2067 [], itins.rm>, EVEX_4V, EVEX_KZ;
2068 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2069 (ins RC:$src1, x86scalar_mop:$src2),
2070 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2071 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2072 [], itins.rm>, EVEX_4V, EVEX_B;
2073 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2074 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2075 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2076 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2078 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2079 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2080 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2081 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2082 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2084 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2088 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2089 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2090 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2092 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2093 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2094 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2096 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2097 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2098 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2100 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2101 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2102 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2104 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2105 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2106 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2108 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2109 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2110 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2111 EVEX_CD8<64, CD8VF>, VEX_W;
2113 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2114 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2115 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2117 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2118 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2120 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2121 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2122 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2123 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2124 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2125 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2127 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2128 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2129 SSE_INTALU_ITINS_P, 1>,
2130 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2131 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2132 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2133 SSE_INTALU_ITINS_P, 0>,
2134 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2136 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2137 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2138 SSE_INTALU_ITINS_P, 1>,
2139 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2140 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2141 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2142 SSE_INTALU_ITINS_P, 0>,
2143 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2145 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2146 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2147 SSE_INTALU_ITINS_P, 1>,
2148 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2149 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2150 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2151 SSE_INTALU_ITINS_P, 0>,
2152 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2154 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2155 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2156 SSE_INTALU_ITINS_P, 1>,
2157 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2158 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2159 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2160 SSE_INTALU_ITINS_P, 0>,
2161 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2163 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2164 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2165 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2166 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2167 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2168 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2169 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2170 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2171 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2172 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2173 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2174 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2175 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2176 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2177 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2178 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2179 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2180 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2181 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2182 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2183 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2184 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2185 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2186 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2187 //===----------------------------------------------------------------------===//
2188 // AVX-512 - Unpack Instructions
2189 //===----------------------------------------------------------------------===//
2191 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2192 PatFrag mem_frag, RegisterClass RC,
2193 X86MemOperand x86memop, string asm,
2195 def rr : AVX512PI<opc, MRMSrcReg,
2196 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2198 (vt (OpNode RC:$src1, RC:$src2)))],
2200 def rm : AVX512PI<opc, MRMSrcMem,
2201 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2203 (vt (OpNode RC:$src1,
2204 (bitconvert (mem_frag addr:$src2)))))],
2208 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2209 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2210 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2211 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2212 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2213 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2214 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2215 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2216 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2217 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2218 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2219 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2221 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2222 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2223 X86MemOperand x86memop> {
2224 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2225 (ins RC:$src1, RC:$src2),
2226 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2227 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2228 IIC_SSE_UNPCK>, EVEX_4V;
2229 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2230 (ins RC:$src1, x86memop:$src2),
2231 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2232 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2233 (bitconvert (memop_frag addr:$src2)))))],
2234 IIC_SSE_UNPCK>, EVEX_4V;
2236 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2237 VR512, memopv16i32, i512mem>, EVEX_V512,
2238 EVEX_CD8<32, CD8VF>;
2239 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2240 VR512, memopv8i64, i512mem>, EVEX_V512,
2241 VEX_W, EVEX_CD8<64, CD8VF>;
2242 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2243 VR512, memopv16i32, i512mem>, EVEX_V512,
2244 EVEX_CD8<32, CD8VF>;
2245 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2246 VR512, memopv8i64, i512mem>, EVEX_V512,
2247 VEX_W, EVEX_CD8<64, CD8VF>;
2248 //===----------------------------------------------------------------------===//
2252 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2253 SDNode OpNode, PatFrag mem_frag,
2254 X86MemOperand x86memop, ValueType OpVT> {
2255 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2256 (ins RC:$src1, i8imm:$src2),
2257 !strconcat(OpcodeStr,
2258 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2260 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2262 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2263 (ins x86memop:$src1, i8imm:$src2),
2264 !strconcat(OpcodeStr,
2265 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2267 (OpVT (OpNode (mem_frag addr:$src1),
2268 (i8 imm:$src2))))]>, EVEX;
2271 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2272 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2274 let ExeDomain = SSEPackedSingle in
2275 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2276 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2277 EVEX_CD8<32, CD8VF>;
2278 let ExeDomain = SSEPackedDouble in
2279 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2280 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2281 VEX_W, EVEX_CD8<32, CD8VF>;
2283 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2284 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2285 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2286 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2288 //===----------------------------------------------------------------------===//
2289 // AVX-512 Logical Instructions
2290 //===----------------------------------------------------------------------===//
2292 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2293 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2294 EVEX_V512, EVEX_CD8<32, CD8VF>;
2295 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2296 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2297 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2298 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2299 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2300 EVEX_V512, EVEX_CD8<32, CD8VF>;
2301 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2302 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2303 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2304 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2305 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2306 EVEX_V512, EVEX_CD8<32, CD8VF>;
2307 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2308 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2309 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2310 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2311 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2312 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2313 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2314 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2315 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2317 //===----------------------------------------------------------------------===//
2318 // AVX-512 FP arithmetic
2319 //===----------------------------------------------------------------------===//
2321 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2323 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2324 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2325 EVEX_CD8<32, CD8VT1>;
2326 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2327 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2328 EVEX_CD8<64, CD8VT1>;
2331 let isCommutable = 1 in {
2332 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2333 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2334 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2335 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2337 let isCommutable = 0 in {
2338 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2339 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2342 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2344 RegisterClass RC, ValueType vt,
2345 X86MemOperand x86memop, PatFrag mem_frag,
2346 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2348 Domain d, OpndItins itins, bit commutable> {
2349 let isCommutable = commutable in {
2350 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2351 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2352 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2355 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2356 !strconcat(OpcodeStr,
2357 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2358 [], itins.rr, d>, EVEX_4V, EVEX_K;
2360 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2361 !strconcat(OpcodeStr,
2362 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2363 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2366 let mayLoad = 1 in {
2367 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2368 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2369 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2370 itins.rm, d>, EVEX_4V;
2372 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2373 (ins RC:$src1, x86scalar_mop:$src2),
2374 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2375 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2376 [(set RC:$dst, (OpNode RC:$src1,
2377 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2378 itins.rm, d>, EVEX_4V, EVEX_B;
2380 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2381 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2382 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2383 [], itins.rm, d>, EVEX_4V, EVEX_K;
2385 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2386 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2387 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2388 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2390 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2391 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2392 " \t{${src2}", BrdcstStr,
2393 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2394 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2396 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2397 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2398 " \t{${src2}", BrdcstStr,
2399 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2401 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2405 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2406 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2407 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2409 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2410 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2411 SSE_ALU_ITINS_P.d, 1>,
2412 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2414 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2415 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2416 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2417 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2418 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2419 SSE_ALU_ITINS_P.d, 1>,
2420 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2422 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2423 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2424 SSE_ALU_ITINS_P.s, 1>,
2425 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2426 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2427 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2428 SSE_ALU_ITINS_P.s, 1>,
2429 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2431 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2432 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2433 SSE_ALU_ITINS_P.d, 1>,
2434 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2435 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2436 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2437 SSE_ALU_ITINS_P.d, 1>,
2438 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2440 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2441 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2442 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2443 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2444 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2445 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2447 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2448 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2449 SSE_ALU_ITINS_P.d, 0>,
2450 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2451 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2452 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2453 SSE_ALU_ITINS_P.d, 0>,
2454 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2456 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2457 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2458 (i16 -1), FROUND_CURRENT)),
2459 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2461 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2462 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2463 (i8 -1), FROUND_CURRENT)),
2464 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2466 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2467 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2468 (i16 -1), FROUND_CURRENT)),
2469 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2471 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2472 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2473 (i8 -1), FROUND_CURRENT)),
2474 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2475 //===----------------------------------------------------------------------===//
2476 // AVX-512 VPTESTM instructions
2477 //===----------------------------------------------------------------------===//
2479 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2480 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2481 SDNode OpNode, ValueType vt> {
2482 def rr : AVX512PI<opc, MRMSrcReg,
2483 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2484 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2485 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2486 SSEPackedInt>, EVEX_4V;
2487 def rm : AVX512PI<opc, MRMSrcMem,
2488 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2489 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2490 [(set KRC:$dst, (OpNode (vt RC:$src1),
2491 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2494 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2495 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2496 EVEX_CD8<32, CD8VF>;
2497 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2498 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2499 EVEX_CD8<64, CD8VF>;
2501 let Predicates = [HasCDI] in {
2502 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2503 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2504 EVEX_CD8<32, CD8VF>;
2505 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2506 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2507 EVEX_CD8<64, CD8VF>;
2510 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2511 (v16i32 VR512:$src2), (i16 -1))),
2512 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2514 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2515 (v8i64 VR512:$src2), (i8 -1))),
2516 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2517 //===----------------------------------------------------------------------===//
2518 // AVX-512 Shift instructions
2519 //===----------------------------------------------------------------------===//
2520 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2521 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2522 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2523 RegisterClass KRC> {
2524 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2525 (ins RC:$src1, i8imm:$src2),
2526 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2527 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2528 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2529 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2530 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2531 !strconcat(OpcodeStr,
2532 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2533 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2534 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2535 (ins x86memop:$src1, i8imm:$src2),
2536 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2537 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2538 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2539 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2540 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2541 !strconcat(OpcodeStr,
2542 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2543 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2546 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2547 RegisterClass RC, ValueType vt, ValueType SrcVT,
2548 PatFrag bc_frag, RegisterClass KRC> {
2549 // src2 is always 128-bit
2550 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2551 (ins RC:$src1, VR128X:$src2),
2552 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2553 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2554 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2555 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2556 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2557 !strconcat(OpcodeStr,
2558 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2559 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2560 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2561 (ins RC:$src1, i128mem:$src2),
2562 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2563 [(set RC:$dst, (vt (OpNode RC:$src1,
2564 (bc_frag (memopv2i64 addr:$src2)))))],
2565 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2566 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2567 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2568 !strconcat(OpcodeStr,
2569 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2570 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2573 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2574 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2575 EVEX_V512, EVEX_CD8<32, CD8VF>;
2576 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2577 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2578 EVEX_CD8<32, CD8VQ>;
2580 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2581 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2582 EVEX_CD8<64, CD8VF>, VEX_W;
2583 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2584 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2585 EVEX_CD8<64, CD8VQ>, VEX_W;
2587 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2588 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2589 EVEX_CD8<32, CD8VF>;
2590 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2591 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2592 EVEX_CD8<32, CD8VQ>;
2594 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2595 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2596 EVEX_CD8<64, CD8VF>, VEX_W;
2597 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2598 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2599 EVEX_CD8<64, CD8VQ>, VEX_W;
2601 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2602 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2603 EVEX_V512, EVEX_CD8<32, CD8VF>;
2604 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2605 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2606 EVEX_CD8<32, CD8VQ>;
2608 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2609 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2610 EVEX_CD8<64, CD8VF>, VEX_W;
2611 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2612 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2613 EVEX_CD8<64, CD8VQ>, VEX_W;
2615 //===-------------------------------------------------------------------===//
2616 // Variable Bit Shifts
2617 //===-------------------------------------------------------------------===//
2618 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2619 RegisterClass RC, ValueType vt,
2620 X86MemOperand x86memop, PatFrag mem_frag> {
2621 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2622 (ins RC:$src1, RC:$src2),
2623 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2625 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2627 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2628 (ins RC:$src1, x86memop:$src2),
2629 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2631 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2635 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2636 i512mem, memopv16i32>, EVEX_V512,
2637 EVEX_CD8<32, CD8VF>;
2638 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2639 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2640 EVEX_CD8<64, CD8VF>;
2641 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2642 i512mem, memopv16i32>, EVEX_V512,
2643 EVEX_CD8<32, CD8VF>;
2644 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2645 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2646 EVEX_CD8<64, CD8VF>;
2647 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2648 i512mem, memopv16i32>, EVEX_V512,
2649 EVEX_CD8<32, CD8VF>;
2650 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2651 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2652 EVEX_CD8<64, CD8VF>;
2654 //===----------------------------------------------------------------------===//
2655 // AVX-512 - MOVDDUP
2656 //===----------------------------------------------------------------------===//
2658 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2659 X86MemOperand x86memop, PatFrag memop_frag> {
2660 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2661 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2662 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2663 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2664 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2666 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2669 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2670 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2671 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2672 (VMOVDDUPZrm addr:$src)>;
2674 //===---------------------------------------------------------------------===//
2675 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2676 //===---------------------------------------------------------------------===//
2677 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2678 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2679 X86MemOperand x86memop> {
2680 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2681 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2682 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2684 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2685 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2686 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2689 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2690 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2691 EVEX_CD8<32, CD8VF>;
2692 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2693 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2694 EVEX_CD8<32, CD8VF>;
2696 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2697 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2698 (VMOVSHDUPZrm addr:$src)>;
2699 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2700 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2701 (VMOVSLDUPZrm addr:$src)>;
2703 //===----------------------------------------------------------------------===//
2704 // Move Low to High and High to Low packed FP Instructions
2705 //===----------------------------------------------------------------------===//
2706 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2707 (ins VR128X:$src1, VR128X:$src2),
2708 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2710 IIC_SSE_MOV_LH>, EVEX_4V;
2711 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2712 (ins VR128X:$src1, VR128X:$src2),
2713 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2714 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2715 IIC_SSE_MOV_LH>, EVEX_4V;
2717 let Predicates = [HasAVX512] in {
2719 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2720 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2721 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2722 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2725 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2726 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2729 //===----------------------------------------------------------------------===//
2730 // FMA - Fused Multiply Operations
2732 let Constraints = "$src1 = $dst" in {
2733 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2734 RegisterClass RC, X86MemOperand x86memop,
2735 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2736 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2737 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2738 (ins RC:$src1, RC:$src2, RC:$src3),
2739 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2740 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2743 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2744 (ins RC:$src1, RC:$src2, x86memop:$src3),
2745 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2746 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2747 (mem_frag addr:$src3))))]>;
2748 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2749 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2750 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2751 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2752 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2753 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2755 } // Constraints = "$src1 = $dst"
2757 let ExeDomain = SSEPackedSingle in {
2758 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2759 memopv16f32, f32mem, loadf32, "{1to16}",
2760 X86Fmadd, v16f32>, EVEX_V512,
2761 EVEX_CD8<32, CD8VF>;
2762 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2763 memopv16f32, f32mem, loadf32, "{1to16}",
2764 X86Fmsub, v16f32>, EVEX_V512,
2765 EVEX_CD8<32, CD8VF>;
2766 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2767 memopv16f32, f32mem, loadf32, "{1to16}",
2768 X86Fmaddsub, v16f32>,
2769 EVEX_V512, EVEX_CD8<32, CD8VF>;
2770 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2771 memopv16f32, f32mem, loadf32, "{1to16}",
2772 X86Fmsubadd, v16f32>,
2773 EVEX_V512, EVEX_CD8<32, CD8VF>;
2774 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2775 memopv16f32, f32mem, loadf32, "{1to16}",
2776 X86Fnmadd, v16f32>, EVEX_V512,
2777 EVEX_CD8<32, CD8VF>;
2778 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2779 memopv16f32, f32mem, loadf32, "{1to16}",
2780 X86Fnmsub, v16f32>, EVEX_V512,
2781 EVEX_CD8<32, CD8VF>;
2783 let ExeDomain = SSEPackedDouble in {
2784 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2785 memopv8f64, f64mem, loadf64, "{1to8}",
2786 X86Fmadd, v8f64>, EVEX_V512,
2787 VEX_W, EVEX_CD8<64, CD8VF>;
2788 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2789 memopv8f64, f64mem, loadf64, "{1to8}",
2790 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2791 EVEX_CD8<64, CD8VF>;
2792 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2793 memopv8f64, f64mem, loadf64, "{1to8}",
2794 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2795 EVEX_CD8<64, CD8VF>;
2796 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2797 memopv8f64, f64mem, loadf64, "{1to8}",
2798 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2799 EVEX_CD8<64, CD8VF>;
2800 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2801 memopv8f64, f64mem, loadf64, "{1to8}",
2802 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2803 EVEX_CD8<64, CD8VF>;
2804 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2805 memopv8f64, f64mem, loadf64, "{1to8}",
2806 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2807 EVEX_CD8<64, CD8VF>;
2810 let Constraints = "$src1 = $dst" in {
2811 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2812 RegisterClass RC, X86MemOperand x86memop,
2813 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2814 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2816 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2817 (ins RC:$src1, RC:$src3, x86memop:$src2),
2818 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2819 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2820 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2821 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2822 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2823 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2824 [(set RC:$dst, (OpNode RC:$src1,
2825 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2827 } // Constraints = "$src1 = $dst"
2830 let ExeDomain = SSEPackedSingle in {
2831 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2832 memopv16f32, f32mem, loadf32, "{1to16}",
2833 X86Fmadd, v16f32>, EVEX_V512,
2834 EVEX_CD8<32, CD8VF>;
2835 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2836 memopv16f32, f32mem, loadf32, "{1to16}",
2837 X86Fmsub, v16f32>, EVEX_V512,
2838 EVEX_CD8<32, CD8VF>;
2839 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2840 memopv16f32, f32mem, loadf32, "{1to16}",
2841 X86Fmaddsub, v16f32>,
2842 EVEX_V512, EVEX_CD8<32, CD8VF>;
2843 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2844 memopv16f32, f32mem, loadf32, "{1to16}",
2845 X86Fmsubadd, v16f32>,
2846 EVEX_V512, EVEX_CD8<32, CD8VF>;
2847 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2848 memopv16f32, f32mem, loadf32, "{1to16}",
2849 X86Fnmadd, v16f32>, EVEX_V512,
2850 EVEX_CD8<32, CD8VF>;
2851 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2852 memopv16f32, f32mem, loadf32, "{1to16}",
2853 X86Fnmsub, v16f32>, EVEX_V512,
2854 EVEX_CD8<32, CD8VF>;
2856 let ExeDomain = SSEPackedDouble in {
2857 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2858 memopv8f64, f64mem, loadf64, "{1to8}",
2859 X86Fmadd, v8f64>, EVEX_V512,
2860 VEX_W, EVEX_CD8<64, CD8VF>;
2861 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2862 memopv8f64, f64mem, loadf64, "{1to8}",
2863 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2864 EVEX_CD8<64, CD8VF>;
2865 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2866 memopv8f64, f64mem, loadf64, "{1to8}",
2867 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2868 EVEX_CD8<64, CD8VF>;
2869 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2870 memopv8f64, f64mem, loadf64, "{1to8}",
2871 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2872 EVEX_CD8<64, CD8VF>;
2873 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2874 memopv8f64, f64mem, loadf64, "{1to8}",
2875 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2876 EVEX_CD8<64, CD8VF>;
2877 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2878 memopv8f64, f64mem, loadf64, "{1to8}",
2879 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2880 EVEX_CD8<64, CD8VF>;
2884 let Constraints = "$src1 = $dst" in {
2885 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2886 RegisterClass RC, ValueType OpVT,
2887 X86MemOperand x86memop, Operand memop,
2889 let isCommutable = 1 in
2890 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2891 (ins RC:$src1, RC:$src2, RC:$src3),
2892 !strconcat(OpcodeStr,
2893 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2895 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2897 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2898 (ins RC:$src1, RC:$src2, f128mem:$src3),
2899 !strconcat(OpcodeStr,
2900 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2902 (OpVT (OpNode RC:$src2, RC:$src1,
2903 (mem_frag addr:$src3))))]>;
2906 } // Constraints = "$src1 = $dst"
2908 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2909 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2910 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2911 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2912 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2913 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2914 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2915 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2916 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2917 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2918 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2919 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2920 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2921 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2922 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2923 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2925 //===----------------------------------------------------------------------===//
2926 // AVX-512 Scalar convert from sign integer to float/double
2927 //===----------------------------------------------------------------------===//
2929 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2930 X86MemOperand x86memop, string asm> {
2931 let hasSideEffects = 0 in {
2932 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2933 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2936 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2937 (ins DstRC:$src1, x86memop:$src),
2938 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2940 } // hasSideEffects = 0
2942 let Predicates = [HasAVX512] in {
2943 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2944 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2945 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2946 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2947 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2948 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2949 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2950 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2952 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2953 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2954 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2955 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2956 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2957 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2958 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2959 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2961 def : Pat<(f32 (sint_to_fp GR32:$src)),
2962 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2963 def : Pat<(f32 (sint_to_fp GR64:$src)),
2964 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2965 def : Pat<(f64 (sint_to_fp GR32:$src)),
2966 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2967 def : Pat<(f64 (sint_to_fp GR64:$src)),
2968 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2970 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2971 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2972 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2973 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2974 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2975 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2976 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2977 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2979 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2980 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2981 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2982 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2983 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2984 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2985 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2986 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2988 def : Pat<(f32 (uint_to_fp GR32:$src)),
2989 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2990 def : Pat<(f32 (uint_to_fp GR64:$src)),
2991 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2992 def : Pat<(f64 (uint_to_fp GR32:$src)),
2993 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2994 def : Pat<(f64 (uint_to_fp GR64:$src)),
2995 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2998 //===----------------------------------------------------------------------===//
2999 // AVX-512 Scalar convert from float/double to integer
3000 //===----------------------------------------------------------------------===//
3001 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3002 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3004 let hasSideEffects = 0 in {
3005 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3006 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3007 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3008 Requires<[HasAVX512]>;
3010 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3011 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3012 Requires<[HasAVX512]>;
3013 } // hasSideEffects = 0
3015 let Predicates = [HasAVX512] in {
3016 // Convert float/double to signed/unsigned int 32/64
3017 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3018 ssmem, sse_load_f32, "cvtss2si">,
3019 XS, EVEX_CD8<32, CD8VT1>;
3020 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3021 ssmem, sse_load_f32, "cvtss2si">,
3022 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3023 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3024 ssmem, sse_load_f32, "cvtss2usi">,
3025 XS, EVEX_CD8<32, CD8VT1>;
3026 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3027 int_x86_avx512_cvtss2usi64, ssmem,
3028 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3029 EVEX_CD8<32, CD8VT1>;
3030 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3031 sdmem, sse_load_f64, "cvtsd2si">,
3032 XD, EVEX_CD8<64, CD8VT1>;
3033 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3034 sdmem, sse_load_f64, "cvtsd2si">,
3035 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3036 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3037 sdmem, sse_load_f64, "cvtsd2usi">,
3038 XD, EVEX_CD8<64, CD8VT1>;
3039 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3040 int_x86_avx512_cvtsd2usi64, sdmem,
3041 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3042 EVEX_CD8<64, CD8VT1>;
3044 let isCodeGenOnly = 1 in {
3045 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3046 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3047 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3048 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3049 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3050 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3051 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3052 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3053 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3054 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3055 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3056 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3058 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3059 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3060 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3061 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3062 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3063 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3064 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3065 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3066 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3067 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3068 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3069 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3070 } // isCodeGenOnly = 1
3072 // Convert float/double to signed/unsigned int 32/64 with truncation
3073 let isCodeGenOnly = 1 in {
3074 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3075 ssmem, sse_load_f32, "cvttss2si">,
3076 XS, EVEX_CD8<32, CD8VT1>;
3077 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3078 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3079 "cvttss2si">, XS, VEX_W,
3080 EVEX_CD8<32, CD8VT1>;
3081 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3082 sdmem, sse_load_f64, "cvttsd2si">, XD,
3083 EVEX_CD8<64, CD8VT1>;
3084 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3085 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3086 "cvttsd2si">, XD, VEX_W,
3087 EVEX_CD8<64, CD8VT1>;
3088 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3089 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3090 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3091 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3092 int_x86_avx512_cvttss2usi64, ssmem,
3093 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3094 EVEX_CD8<32, CD8VT1>;
3095 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3096 int_x86_avx512_cvttsd2usi,
3097 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3098 EVEX_CD8<64, CD8VT1>;
3099 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3100 int_x86_avx512_cvttsd2usi64, sdmem,
3101 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3102 EVEX_CD8<64, CD8VT1>;
3103 } // isCodeGenOnly = 1
3105 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3106 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3108 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3109 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3110 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3111 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3112 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3113 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3116 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3117 loadf32, "cvttss2si">, XS,
3118 EVEX_CD8<32, CD8VT1>;
3119 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3120 loadf32, "cvttss2usi">, XS,
3121 EVEX_CD8<32, CD8VT1>;
3122 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3123 loadf32, "cvttss2si">, XS, VEX_W,
3124 EVEX_CD8<32, CD8VT1>;
3125 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3126 loadf32, "cvttss2usi">, XS, VEX_W,
3127 EVEX_CD8<32, CD8VT1>;
3128 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3129 loadf64, "cvttsd2si">, XD,
3130 EVEX_CD8<64, CD8VT1>;
3131 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3132 loadf64, "cvttsd2usi">, XD,
3133 EVEX_CD8<64, CD8VT1>;
3134 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3135 loadf64, "cvttsd2si">, XD, VEX_W,
3136 EVEX_CD8<64, CD8VT1>;
3137 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3138 loadf64, "cvttsd2usi">, XD, VEX_W,
3139 EVEX_CD8<64, CD8VT1>;
3141 //===----------------------------------------------------------------------===//
3142 // AVX-512 Convert form float to double and back
3143 //===----------------------------------------------------------------------===//
3144 let hasSideEffects = 0 in {
3145 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3146 (ins FR32X:$src1, FR32X:$src2),
3147 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3148 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3150 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3151 (ins FR32X:$src1, f32mem:$src2),
3152 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3153 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3154 EVEX_CD8<32, CD8VT1>;
3156 // Convert scalar double to scalar single
3157 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3158 (ins FR64X:$src1, FR64X:$src2),
3159 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3160 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3162 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3163 (ins FR64X:$src1, f64mem:$src2),
3164 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3165 []>, EVEX_4V, VEX_LIG, VEX_W,
3166 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3169 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3170 Requires<[HasAVX512]>;
3171 def : Pat<(fextend (loadf32 addr:$src)),
3172 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3174 def : Pat<(extloadf32 addr:$src),
3175 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3176 Requires<[HasAVX512, OptForSize]>;
3178 def : Pat<(extloadf32 addr:$src),
3179 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3180 Requires<[HasAVX512, OptForSpeed]>;
3182 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3183 Requires<[HasAVX512]>;
3185 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3186 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3187 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3189 let hasSideEffects = 0 in {
3190 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3191 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3193 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3194 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3195 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3196 [], d>, EVEX, EVEX_B, EVEX_RC;
3198 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3199 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3201 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3202 } // hasSideEffects = 0
3205 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3206 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3207 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3209 let hasSideEffects = 0 in {
3210 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3211 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3213 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3215 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3216 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3218 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3219 } // hasSideEffects = 0
3222 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3223 memopv8f64, f512mem, v8f32, v8f64,
3224 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3225 EVEX_CD8<64, CD8VF>;
3227 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3228 memopv4f64, f256mem, v8f64, v8f32,
3229 SSEPackedDouble>, EVEX_V512, PS,
3230 EVEX_CD8<32, CD8VH>;
3231 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3232 (VCVTPS2PDZrm addr:$src)>;
3234 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3235 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3236 (VCVTPD2PSZrr VR512:$src)>;
3238 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3239 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3240 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3242 //===----------------------------------------------------------------------===//
3243 // AVX-512 Vector convert from sign integer to float/double
3244 //===----------------------------------------------------------------------===//
3246 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3247 memopv8i64, i512mem, v16f32, v16i32,
3248 SSEPackedSingle>, EVEX_V512, PS,
3249 EVEX_CD8<32, CD8VF>;
3251 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3252 memopv4i64, i256mem, v8f64, v8i32,
3253 SSEPackedDouble>, EVEX_V512, XS,
3254 EVEX_CD8<32, CD8VH>;
3256 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3257 memopv16f32, f512mem, v16i32, v16f32,
3258 SSEPackedSingle>, EVEX_V512, XS,
3259 EVEX_CD8<32, CD8VF>;
3261 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3262 memopv8f64, f512mem, v8i32, v8f64,
3263 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3264 EVEX_CD8<64, CD8VF>;
3266 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3267 memopv16f32, f512mem, v16i32, v16f32,
3268 SSEPackedSingle>, EVEX_V512, PS,
3269 EVEX_CD8<32, CD8VF>;
3271 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3272 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3273 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3274 (VCVTTPS2UDQZrr VR512:$src)>;
3276 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3277 memopv8f64, f512mem, v8i32, v8f64,
3278 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3279 EVEX_CD8<64, CD8VF>;
3281 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3282 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3283 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3284 (VCVTTPD2UDQZrr VR512:$src)>;
3286 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3287 memopv4i64, f256mem, v8f64, v8i32,
3288 SSEPackedDouble>, EVEX_V512, XS,
3289 EVEX_CD8<32, CD8VH>;
3291 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3292 memopv16i32, f512mem, v16f32, v16i32,
3293 SSEPackedSingle>, EVEX_V512, XD,
3294 EVEX_CD8<32, CD8VF>;
3296 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3297 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3298 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3300 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3301 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3302 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3304 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3305 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3306 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3308 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3309 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3310 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3312 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3313 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3314 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3316 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3317 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3318 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3319 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3320 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3321 (VCVTDQ2PDZrr VR256X:$src)>;
3322 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3323 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3324 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3325 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3326 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3327 (VCVTUDQ2PDZrr VR256X:$src)>;
3329 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3330 RegisterClass DstRC, PatFrag mem_frag,
3331 X86MemOperand x86memop, Domain d> {
3332 let hasSideEffects = 0 in {
3333 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3334 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3336 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3337 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3338 [], d>, EVEX, EVEX_B, EVEX_RC;
3340 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3341 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3343 } // hasSideEffects = 0
3346 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3347 memopv16f32, f512mem, SSEPackedSingle>, PD,
3348 EVEX_V512, EVEX_CD8<32, CD8VF>;
3349 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3350 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3351 EVEX_V512, EVEX_CD8<64, CD8VF>;
3353 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3354 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3355 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3357 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3358 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3359 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3361 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3362 memopv16f32, f512mem, SSEPackedSingle>,
3363 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3364 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3365 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3366 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3368 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3369 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3370 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3372 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3373 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3374 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3376 let Predicates = [HasAVX512] in {
3377 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3378 (VCVTPD2PSZrm addr:$src)>;
3379 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3380 (VCVTPS2PDZrm addr:$src)>;
3383 //===----------------------------------------------------------------------===//
3384 // Half precision conversion instructions
3385 //===----------------------------------------------------------------------===//
3386 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3387 X86MemOperand x86memop> {
3388 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3389 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3391 let hasSideEffects = 0, mayLoad = 1 in
3392 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3393 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3396 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3397 X86MemOperand x86memop> {
3398 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3399 (ins srcRC:$src1, i32i8imm:$src2),
3400 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3402 let hasSideEffects = 0, mayStore = 1 in
3403 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3404 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3405 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3408 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3409 EVEX_CD8<32, CD8VH>;
3410 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3411 EVEX_CD8<32, CD8VH>;
3413 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3414 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3415 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3417 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3418 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3419 (VCVTPH2PSZrr VR256X:$src)>;
3421 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3422 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3423 "ucomiss">, PS, EVEX, VEX_LIG,
3424 EVEX_CD8<32, CD8VT1>;
3425 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3426 "ucomisd">, PD, EVEX,
3427 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3428 let Pattern = []<dag> in {
3429 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3430 "comiss">, PS, EVEX, VEX_LIG,
3431 EVEX_CD8<32, CD8VT1>;
3432 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3433 "comisd">, PD, EVEX,
3434 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3436 let isCodeGenOnly = 1 in {
3437 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3438 load, "ucomiss">, PS, EVEX, VEX_LIG,
3439 EVEX_CD8<32, CD8VT1>;
3440 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3441 load, "ucomisd">, PD, EVEX,
3442 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3444 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3445 load, "comiss">, PS, EVEX, VEX_LIG,
3446 EVEX_CD8<32, CD8VT1>;
3447 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3448 load, "comisd">, PD, EVEX,
3449 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3453 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3454 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3455 X86MemOperand x86memop> {
3456 let hasSideEffects = 0 in {
3457 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3458 (ins RC:$src1, RC:$src2),
3459 !strconcat(OpcodeStr,
3460 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3461 let mayLoad = 1 in {
3462 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3463 (ins RC:$src1, x86memop:$src2),
3464 !strconcat(OpcodeStr,
3465 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3470 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3471 EVEX_CD8<32, CD8VT1>;
3472 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3473 VEX_W, EVEX_CD8<64, CD8VT1>;
3474 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3475 EVEX_CD8<32, CD8VT1>;
3476 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3477 VEX_W, EVEX_CD8<64, CD8VT1>;
3479 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3480 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3481 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3482 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3484 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3485 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3486 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3487 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3489 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3490 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3491 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3492 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3494 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3495 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3496 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3497 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3499 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3500 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3501 RegisterClass RC, X86MemOperand x86memop,
3502 PatFrag mem_frag, ValueType OpVt> {
3503 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3504 !strconcat(OpcodeStr,
3505 " \t{$src, $dst|$dst, $src}"),
3506 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3508 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3509 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3510 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3513 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3514 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3515 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3516 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3517 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3518 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3519 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3520 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3522 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3523 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3524 (VRSQRT14PSZr VR512:$src)>;
3525 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3526 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3527 (VRSQRT14PDZr VR512:$src)>;
3529 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3530 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3531 (VRCP14PSZr VR512:$src)>;
3532 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3533 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3534 (VRCP14PDZr VR512:$src)>;
3536 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3537 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3538 X86MemOperand x86memop> {
3539 let hasSideEffects = 0, Predicates = [HasERI] in {
3540 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3541 (ins RC:$src1, RC:$src2),
3542 !strconcat(OpcodeStr,
3543 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3544 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3545 (ins RC:$src1, RC:$src2),
3546 !strconcat(OpcodeStr,
3547 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3548 []>, EVEX_4V, EVEX_B;
3549 let mayLoad = 1 in {
3550 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3551 (ins RC:$src1, x86memop:$src2),
3552 !strconcat(OpcodeStr,
3553 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3558 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3559 EVEX_CD8<32, CD8VT1>;
3560 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3561 VEX_W, EVEX_CD8<64, CD8VT1>;
3562 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3563 EVEX_CD8<32, CD8VT1>;
3564 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3565 VEX_W, EVEX_CD8<64, CD8VT1>;
3567 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3568 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3570 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3571 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3573 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3574 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3576 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3577 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3579 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3580 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3582 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3583 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3585 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3586 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3588 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3589 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3591 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3592 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3593 RegisterClass RC, X86MemOperand x86memop> {
3594 let hasSideEffects = 0, Predicates = [HasERI] in {
3595 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3596 !strconcat(OpcodeStr,
3597 " \t{$src, $dst|$dst, $src}"),
3599 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3600 !strconcat(OpcodeStr,
3601 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3603 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3604 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3608 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3609 EVEX_V512, EVEX_CD8<32, CD8VF>;
3610 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3611 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3612 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3613 EVEX_V512, EVEX_CD8<32, CD8VF>;
3614 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3615 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3617 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3618 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3619 (VRSQRT28PSZrb VR512:$src)>;
3620 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3621 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3622 (VRSQRT28PDZrb VR512:$src)>;
3624 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3625 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3626 (VRCP28PSZrb VR512:$src)>;
3627 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3628 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3629 (VRCP28PDZrb VR512:$src)>;
3631 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3632 OpndItins itins_s, OpndItins itins_d> {
3633 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3634 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3635 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3639 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3640 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3642 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3643 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3645 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3646 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3647 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3651 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3652 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3653 [(set VR512:$dst, (OpNode
3654 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3655 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3659 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3660 Intrinsic F32Int, Intrinsic F64Int,
3661 OpndItins itins_s, OpndItins itins_d> {
3662 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3663 (ins FR32X:$src1, FR32X:$src2),
3664 !strconcat(OpcodeStr,
3665 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3666 [], itins_s.rr>, XS, EVEX_4V;
3667 let isCodeGenOnly = 1 in
3668 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3669 (ins VR128X:$src1, VR128X:$src2),
3670 !strconcat(OpcodeStr,
3671 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3673 (F32Int VR128X:$src1, VR128X:$src2))],
3674 itins_s.rr>, XS, EVEX_4V;
3675 let mayLoad = 1 in {
3676 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3677 (ins FR32X:$src1, f32mem:$src2),
3678 !strconcat(OpcodeStr,
3679 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3680 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3681 let isCodeGenOnly = 1 in
3682 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3683 (ins VR128X:$src1, ssmem:$src2),
3684 !strconcat(OpcodeStr,
3685 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3687 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3688 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3690 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3691 (ins FR64X:$src1, FR64X:$src2),
3692 !strconcat(OpcodeStr,
3693 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3695 let isCodeGenOnly = 1 in
3696 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3697 (ins VR128X:$src1, VR128X:$src2),
3698 !strconcat(OpcodeStr,
3699 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3701 (F64Int VR128X:$src1, VR128X:$src2))],
3702 itins_s.rr>, XD, EVEX_4V, VEX_W;
3703 let mayLoad = 1 in {
3704 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3705 (ins FR64X:$src1, f64mem:$src2),
3706 !strconcat(OpcodeStr,
3707 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3708 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3709 let isCodeGenOnly = 1 in
3710 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3711 (ins VR128X:$src1, sdmem:$src2),
3712 !strconcat(OpcodeStr,
3713 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3715 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3716 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3721 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3722 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3723 SSE_SQRTSS, SSE_SQRTSD>,
3724 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3725 SSE_SQRTPS, SSE_SQRTPD>;
3727 let Predicates = [HasAVX512] in {
3728 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3729 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3730 (VSQRTPSZrr VR512:$src1)>;
3731 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3732 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3733 (VSQRTPDZrr VR512:$src1)>;
3735 def : Pat<(f32 (fsqrt FR32X:$src)),
3736 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3737 def : Pat<(f32 (fsqrt (load addr:$src))),
3738 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3739 Requires<[OptForSize]>;
3740 def : Pat<(f64 (fsqrt FR64X:$src)),
3741 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3742 def : Pat<(f64 (fsqrt (load addr:$src))),
3743 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3744 Requires<[OptForSize]>;
3746 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3747 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3748 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3749 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3750 Requires<[OptForSize]>;
3752 def : Pat<(f32 (X86frcp FR32X:$src)),
3753 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3754 def : Pat<(f32 (X86frcp (load addr:$src))),
3755 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3756 Requires<[OptForSize]>;
3758 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3759 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3760 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3762 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3763 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3765 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3766 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3767 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3769 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3770 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3774 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3775 X86MemOperand x86memop, RegisterClass RC,
3776 PatFrag mem_frag32, PatFrag mem_frag64,
3777 Intrinsic V4F32Int, Intrinsic V2F64Int,
3779 let ExeDomain = SSEPackedSingle in {
3780 // Intrinsic operation, reg.
3781 // Vector intrinsic operation, reg
3782 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3783 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3784 !strconcat(OpcodeStr,
3785 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3786 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3788 // Vector intrinsic operation, mem
3789 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3790 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3791 !strconcat(OpcodeStr,
3792 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3794 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3795 EVEX_CD8<32, VForm>;
3796 } // ExeDomain = SSEPackedSingle
3798 let ExeDomain = SSEPackedDouble in {
3799 // Vector intrinsic operation, reg
3800 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3801 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3802 !strconcat(OpcodeStr,
3803 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3804 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3806 // Vector intrinsic operation, mem
3807 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3808 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3809 !strconcat(OpcodeStr,
3810 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3812 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3813 EVEX_CD8<64, VForm>;
3814 } // ExeDomain = SSEPackedDouble
3817 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3821 let ExeDomain = GenericDomain in {
3823 let hasSideEffects = 0 in
3824 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3825 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3826 !strconcat(OpcodeStr,
3827 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3830 // Intrinsic operation, reg.
3831 let isCodeGenOnly = 1 in
3832 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3833 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3834 !strconcat(OpcodeStr,
3835 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3836 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3838 // Intrinsic operation, mem.
3839 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3840 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3841 !strconcat(OpcodeStr,
3842 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3843 [(set VR128X:$dst, (F32Int VR128X:$src1,
3844 sse_load_f32:$src2, imm:$src3))]>,
3845 EVEX_CD8<32, CD8VT1>;
3848 let hasSideEffects = 0 in
3849 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3850 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3851 !strconcat(OpcodeStr,
3852 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3855 // Intrinsic operation, reg.
3856 let isCodeGenOnly = 1 in
3857 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3858 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3859 !strconcat(OpcodeStr,
3860 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3861 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3864 // Intrinsic operation, mem.
3865 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3866 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3867 !strconcat(OpcodeStr,
3868 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3870 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3871 VEX_W, EVEX_CD8<64, CD8VT1>;
3872 } // ExeDomain = GenericDomain
3875 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3876 X86MemOperand x86memop, RegisterClass RC,
3877 PatFrag mem_frag, Domain d> {
3878 let ExeDomain = d in {
3879 // Intrinsic operation, reg.
3880 // Vector intrinsic operation, reg
3881 def r : AVX512AIi8<opc, MRMSrcReg,
3882 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3883 !strconcat(OpcodeStr,
3884 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3887 // Vector intrinsic operation, mem
3888 def m : AVX512AIi8<opc, MRMSrcMem,
3889 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3890 !strconcat(OpcodeStr,
3891 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3897 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3898 memopv16f32, SSEPackedSingle>, EVEX_V512,
3899 EVEX_CD8<32, CD8VF>;
3901 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3902 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3904 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3907 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3908 memopv8f64, SSEPackedDouble>, EVEX_V512,
3909 VEX_W, EVEX_CD8<64, CD8VF>;
3911 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3912 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3914 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3916 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3917 Operand x86memop, RegisterClass RC, Domain d> {
3918 let ExeDomain = d in {
3919 def r : AVX512AIi8<opc, MRMSrcReg,
3920 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3921 !strconcat(OpcodeStr,
3922 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3925 def m : AVX512AIi8<opc, MRMSrcMem,
3926 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3927 !strconcat(OpcodeStr,
3928 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3933 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3934 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3936 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3937 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3939 def : Pat<(ffloor FR32X:$src),
3940 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3941 def : Pat<(f64 (ffloor FR64X:$src)),
3942 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3943 def : Pat<(f32 (fnearbyint FR32X:$src)),
3944 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3945 def : Pat<(f64 (fnearbyint FR64X:$src)),
3946 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3947 def : Pat<(f32 (fceil FR32X:$src)),
3948 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3949 def : Pat<(f64 (fceil FR64X:$src)),
3950 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3951 def : Pat<(f32 (frint FR32X:$src)),
3952 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3953 def : Pat<(f64 (frint FR64X:$src)),
3954 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3955 def : Pat<(f32 (ftrunc FR32X:$src)),
3956 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3957 def : Pat<(f64 (ftrunc FR64X:$src)),
3958 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3960 def : Pat<(v16f32 (ffloor VR512:$src)),
3961 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3962 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3963 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3964 def : Pat<(v16f32 (fceil VR512:$src)),
3965 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3966 def : Pat<(v16f32 (frint VR512:$src)),
3967 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3968 def : Pat<(v16f32 (ftrunc VR512:$src)),
3969 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3971 def : Pat<(v8f64 (ffloor VR512:$src)),
3972 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3973 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3974 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3975 def : Pat<(v8f64 (fceil VR512:$src)),
3976 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3977 def : Pat<(v8f64 (frint VR512:$src)),
3978 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3979 def : Pat<(v8f64 (ftrunc VR512:$src)),
3980 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3982 //-------------------------------------------------
3983 // Integer truncate and extend operations
3984 //-------------------------------------------------
3986 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3987 RegisterClass dstRC, RegisterClass srcRC,
3988 RegisterClass KRC, X86MemOperand x86memop> {
3989 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3991 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3994 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3995 (ins KRC:$mask, srcRC:$src),
3996 !strconcat(OpcodeStr,
3997 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4000 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4001 (ins KRC:$mask, srcRC:$src),
4002 !strconcat(OpcodeStr,
4003 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4006 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4007 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4010 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4011 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4012 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4016 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4017 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4018 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4019 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4020 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4021 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4022 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4023 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4024 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4025 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4026 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4027 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4028 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4029 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4030 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4031 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4032 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4033 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4034 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4035 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4036 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4037 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4038 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4039 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4040 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4041 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4042 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4043 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4044 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4045 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4047 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4048 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4049 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4050 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4051 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4053 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4054 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4055 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4056 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4057 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4058 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4059 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4060 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4063 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4064 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4065 PatFrag mem_frag, X86MemOperand x86memop,
4066 ValueType OpVT, ValueType InVT> {
4068 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4070 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4071 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4073 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4074 (ins KRC:$mask, SrcRC:$src),
4075 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4078 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4079 (ins KRC:$mask, SrcRC:$src),
4080 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4083 let mayLoad = 1 in {
4084 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4085 (ins x86memop:$src),
4086 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4088 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4091 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4092 (ins KRC:$mask, x86memop:$src),
4093 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4097 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4098 (ins KRC:$mask, x86memop:$src),
4099 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4105 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4106 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4108 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4109 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4111 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4112 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4113 EVEX_CD8<16, CD8VH>;
4114 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4115 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4116 EVEX_CD8<16, CD8VQ>;
4117 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4118 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4119 EVEX_CD8<32, CD8VH>;
4121 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4122 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4124 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4125 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4127 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4128 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4129 EVEX_CD8<16, CD8VH>;
4130 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4131 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4132 EVEX_CD8<16, CD8VQ>;
4133 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4134 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4135 EVEX_CD8<32, CD8VH>;
4137 //===----------------------------------------------------------------------===//
4138 // GATHER - SCATTER Operations
4140 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4141 RegisterClass RC, X86MemOperand memop> {
4143 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4144 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4145 (ins RC:$src1, KRC:$mask, memop:$src2),
4146 !strconcat(OpcodeStr,
4147 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4151 let ExeDomain = SSEPackedDouble in {
4152 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4153 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4154 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4155 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4158 let ExeDomain = SSEPackedSingle in {
4159 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4160 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4161 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4162 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4165 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4166 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4167 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4168 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4170 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4171 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4172 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4173 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4175 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4176 RegisterClass RC, X86MemOperand memop> {
4177 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4178 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4179 (ins memop:$dst, KRC:$mask, RC:$src2),
4180 !strconcat(OpcodeStr,
4181 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4185 let ExeDomain = SSEPackedDouble in {
4186 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4187 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4188 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4189 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4192 let ExeDomain = SSEPackedSingle in {
4193 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4194 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4195 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4196 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4199 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4200 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4201 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4202 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4204 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4205 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4206 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4207 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4210 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4211 RegisterClass KRC, X86MemOperand memop> {
4212 let Predicates = [HasPFI], hasSideEffects = 1 in
4213 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4214 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4218 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4219 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4221 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4222 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4224 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4225 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4227 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4228 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4230 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4231 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4233 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4234 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4236 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4237 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4239 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4240 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4242 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4243 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4245 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4246 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4248 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4249 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4251 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4252 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4254 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4255 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4257 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4258 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4260 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4261 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4263 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4264 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4265 //===----------------------------------------------------------------------===//
4266 // VSHUFPS - VSHUFPD Operations
4268 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4269 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4271 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4272 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4273 !strconcat(OpcodeStr,
4274 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4275 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4276 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4277 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4278 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4279 (ins RC:$src1, RC:$src2, i8imm:$src3),
4280 !strconcat(OpcodeStr,
4281 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4282 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4283 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4284 EVEX_4V, Sched<[WriteShuffle]>;
4287 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4288 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4289 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4290 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4292 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4293 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4294 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4295 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4296 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4298 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4299 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4300 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4301 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4302 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4304 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4305 X86MemOperand x86memop> {
4306 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4307 (ins RC:$src1, RC:$src2, i8imm:$src3),
4308 !strconcat(OpcodeStr,
4309 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4312 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4313 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4314 !strconcat(OpcodeStr,
4315 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4318 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4319 EVEX_V512, EVEX_CD8<32, CD8VF>;
4320 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4321 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4323 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4324 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4325 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4326 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4327 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4328 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4329 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4330 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4332 // Helper fragments to match sext vXi1 to vXiY.
4333 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4334 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4336 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4337 RegisterClass KRC, RegisterClass RC,
4338 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4340 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4341 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4343 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4344 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4346 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4347 !strconcat(OpcodeStr,
4348 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4350 let mayLoad = 1 in {
4351 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4352 (ins x86memop:$src),
4353 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4355 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4356 (ins KRC:$mask, x86memop:$src),
4357 !strconcat(OpcodeStr,
4358 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4360 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4361 (ins KRC:$mask, x86memop:$src),
4362 !strconcat(OpcodeStr,
4363 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4365 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4366 (ins x86scalar_mop:$src),
4367 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4368 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4370 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4371 (ins KRC:$mask, x86scalar_mop:$src),
4372 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4373 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4374 []>, EVEX, EVEX_B, EVEX_K;
4375 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4376 (ins KRC:$mask, x86scalar_mop:$src),
4377 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4378 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4380 []>, EVEX, EVEX_B, EVEX_KZ;
4384 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4385 i512mem, i32mem, "{1to16}">, EVEX_V512,
4386 EVEX_CD8<32, CD8VF>;
4387 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4388 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4389 EVEX_CD8<64, CD8VF>;
4392 (bc_v16i32 (v16i1sextv16i32)),
4393 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4394 (VPABSDZrr VR512:$src)>;
4396 (bc_v8i64 (v8i1sextv8i64)),
4397 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4398 (VPABSQZrr VR512:$src)>;
4400 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4401 (v16i32 immAllZerosV), (i16 -1))),
4402 (VPABSDZrr VR512:$src)>;
4403 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4404 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4405 (VPABSQZrr VR512:$src)>;
4407 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4408 RegisterClass RC, RegisterClass KRC,
4409 X86MemOperand x86memop,
4410 X86MemOperand x86scalar_mop, string BrdcstStr> {
4411 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4413 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4415 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4416 (ins x86memop:$src),
4417 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4419 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4420 (ins x86scalar_mop:$src),
4421 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4422 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4424 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4425 (ins KRC:$mask, RC:$src),
4426 !strconcat(OpcodeStr,
4427 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4429 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4430 (ins KRC:$mask, x86memop:$src),
4431 !strconcat(OpcodeStr,
4432 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4434 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4435 (ins KRC:$mask, x86scalar_mop:$src),
4436 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4437 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4439 []>, EVEX, EVEX_KZ, EVEX_B;
4441 let Constraints = "$src1 = $dst" in {
4442 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4443 (ins RC:$src1, KRC:$mask, RC:$src2),
4444 !strconcat(OpcodeStr,
4445 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4447 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4448 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4449 !strconcat(OpcodeStr,
4450 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4452 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4453 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4454 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4455 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4456 []>, EVEX, EVEX_K, EVEX_B;
4460 let Predicates = [HasCDI] in {
4461 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4462 i512mem, i32mem, "{1to16}">,
4463 EVEX_V512, EVEX_CD8<32, CD8VF>;
4466 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4467 i512mem, i64mem, "{1to8}">,
4468 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4472 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4474 (VPCONFLICTDrrk VR512:$src1,
4475 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4477 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4479 (VPCONFLICTQrrk VR512:$src1,
4480 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4482 let Predicates = [HasCDI] in {
4483 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4484 i512mem, i32mem, "{1to16}">,
4485 EVEX_V512, EVEX_CD8<32, CD8VF>;
4488 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4489 i512mem, i64mem, "{1to8}">,
4490 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4494 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4496 (VPLZCNTDrrk VR512:$src1,
4497 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4499 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4501 (VPLZCNTQrrk VR512:$src1,
4502 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4504 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4505 (VPLZCNTDrm addr:$src)>;
4506 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4507 (VPLZCNTDrr VR512:$src)>;
4508 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4509 (VPLZCNTQrm addr:$src)>;
4510 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4511 (VPLZCNTQrr VR512:$src)>;
4513 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4514 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4515 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4517 def : Pat<(store VK1:$src, addr:$dst),
4518 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4520 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4521 (truncstore node:$val, node:$ptr), [{
4522 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4525 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4526 (MOV8mr addr:$dst, GR8:$src)>;