1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
25 string VTName = "v" # NumElts # EltVT;
28 ValueType VT = !cast<ValueType>(VTName);
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
35 // "i" for integer types and "f" for floating-point types
36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
38 // Size of RC in bits, e.g. 512 for VR512.
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
63 // The corresponding float type, e.g. v16f32 for v16i32
64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
83 // A vector type of the same width with element type i32. This is used to
84 // create the canonical constant zero node ImmAllZerosV.
85 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
86 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
89 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
90 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
91 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
92 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
93 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
94 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
96 // "x" in v32i8x_info means RC = VR256X
97 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
98 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
99 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
100 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
102 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
103 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
104 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
105 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
107 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
108 X86VectorVTInfo i128> {
109 X86VectorVTInfo info512 = i512;
110 X86VectorVTInfo info256 = i256;
111 X86VectorVTInfo info128 = i128;
114 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
116 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
118 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
120 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
123 // This multiclass generates the masking variants from the non-masking
124 // variant. It only provides the assembly pieces for the masking variants.
125 // It assumes custom ISel patterns for masking which can be provided as
126 // template arguments.
127 multiclass AVX512_maskable_custom<bits<8> O, Format F,
129 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
131 string AttSrcAsm, string IntelSrcAsm,
133 list<dag> MaskingPattern,
134 list<dag> ZeroMaskingPattern,
135 string MaskingConstraint = "",
136 InstrItinClass itin = NoItinerary,
137 bit IsCommutable = 0> {
138 let isCommutable = IsCommutable in
139 def NAME: AVX512<O, F, Outs, Ins,
140 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
141 "$dst, "#IntelSrcAsm#"}",
144 // Prefer over VMOV*rrk Pat<>
145 let AddedComplexity = 20 in
146 def NAME#k: AVX512<O, F, Outs, MaskingIns,
147 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
148 "$dst {${mask}}, "#IntelSrcAsm#"}",
149 MaskingPattern, itin>,
151 // In case of the 3src subclass this is overridden with a let.
152 string Constraints = MaskingConstraint;
154 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
155 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
156 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
157 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
164 // Common base class of AVX512_maskable and AVX512_maskable_3src.
165 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
167 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
169 string AttSrcAsm, string IntelSrcAsm,
170 dag RHS, dag MaskingRHS,
171 string MaskingConstraint = "",
172 InstrItinClass itin = NoItinerary,
173 bit IsCommutable = 0> :
174 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
175 AttSrcAsm, IntelSrcAsm,
176 [(set _.RC:$dst, RHS)],
177 [(set _.RC:$dst, MaskingRHS)],
179 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
180 MaskingConstraint, NoItinerary, IsCommutable>;
182 // This multiclass generates the unconditional/non-masking, the masking and
183 // the zero-masking variant of the instruction. In the masking case, the
184 // perserved vector elements come from a new dummy input operand tied to $dst.
185 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
186 dag Outs, dag Ins, string OpcodeStr,
187 string AttSrcAsm, string IntelSrcAsm,
188 dag RHS, InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
190 AVX512_maskable_common<O, F, _, Outs, Ins,
191 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
192 !con((ins _.KRCWM:$mask), Ins),
193 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
194 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
195 "$src0 = $dst", itin, IsCommutable>;
197 // Similar to AVX512_maskable but in this case one of the source operands
198 // ($src1) is already tied to $dst so we just use that for the preserved
199 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
201 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag NonTiedIns, string OpcodeStr,
203 string AttSrcAsm, string IntelSrcAsm,
205 AVX512_maskable_common<O, F, _, Outs,
206 !con((ins _.RC:$src1), NonTiedIns),
207 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
208 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
209 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
210 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
213 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
216 string AttSrcAsm, string IntelSrcAsm,
218 AVX512_maskable_custom<O, F, Outs, Ins,
219 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
220 !con((ins _.KRCWM:$mask), Ins),
221 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
224 // Bitcasts between 512-bit vector types. Return the original type since
225 // no instruction is needed for the conversion
226 let Predicates = [HasAVX512] in {
227 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
228 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
229 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
230 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
231 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
232 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
233 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
234 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
235 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
236 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
237 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
238 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
239 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
240 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
241 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
242 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
243 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
244 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
245 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
246 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
247 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
248 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
249 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
250 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
251 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
252 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
253 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
254 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
255 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
256 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
257 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
259 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
260 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
261 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
262 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
263 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
264 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
265 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
266 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
267 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
268 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
269 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
270 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
271 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
272 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
273 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
274 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
275 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
276 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
277 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
278 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
279 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
280 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
281 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
282 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
283 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
284 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
285 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
286 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
287 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
288 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
290 // Bitcasts between 256-bit vector types. Return the original type since
291 // no instruction is needed for the conversion
292 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
293 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
294 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
295 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
296 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
297 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
298 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
299 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
300 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
301 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
302 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
303 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
304 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
305 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
306 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
307 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
308 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
309 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
310 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
311 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
312 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
313 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
314 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
315 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
316 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
317 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
318 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
319 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
320 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
321 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
325 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
328 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
329 isPseudo = 1, Predicates = [HasAVX512] in {
330 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
331 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
334 let Predicates = [HasAVX512] in {
335 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
336 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
337 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
340 //===----------------------------------------------------------------------===//
341 // AVX-512 - VECTOR INSERT
344 multiclass vinsert_for_size<int Opcode,
345 X86VectorVTInfo From, X86VectorVTInfo To,
346 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
347 PatFrag vinsert_insert,
348 SDNodeXForm INSERT_get_vinsert_imm> {
349 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
350 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
351 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
352 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
353 "$dst, $src1, $src2, $src3}",
354 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
355 (From.VT From.RC:$src2),
360 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
361 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
362 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
363 "$dst, $src1, $src2, $src3}",
364 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
367 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
369 def : Pat<(vinsert_insert:$ins
370 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
371 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
372 VR512:$src1, From.RC:$src2,
373 (INSERT_get_vinsert_imm VR512:$ins)))>;
376 multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
377 ValueType EltVT64, int Opcode64> {
378 defm NAME # "32x4" : vinsert_for_size<Opcode32,
379 X86VectorVTInfo< 4, EltVT32, VR128X>,
380 X86VectorVTInfo<16, EltVT32, VR512>,
381 X86VectorVTInfo< 2, EltVT64, VR128X>,
382 X86VectorVTInfo< 8, EltVT64, VR512>,
384 INSERT_get_vinsert128_imm>;
385 defm NAME # "64x4" : vinsert_for_size<Opcode64,
386 X86VectorVTInfo< 4, EltVT64, VR256X>,
387 X86VectorVTInfo< 8, EltVT64, VR512>,
388 X86VectorVTInfo< 8, EltVT32, VR256>,
389 X86VectorVTInfo<16, EltVT32, VR512>,
391 INSERT_get_vinsert256_imm>, VEX_W;
394 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
395 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
397 // vinsertps - insert f32 to XMM
398 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
399 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
400 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
401 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
403 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
404 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
405 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
406 [(set VR128X:$dst, (X86insertps VR128X:$src1,
407 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
408 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
410 //===----------------------------------------------------------------------===//
411 // AVX-512 VECTOR EXTRACT
414 multiclass vextract_for_size<int Opcode,
415 X86VectorVTInfo From, X86VectorVTInfo To,
416 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
417 PatFrag vextract_extract,
418 SDNodeXForm EXTRACT_get_vextract_imm> {
419 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
420 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
421 (ins VR512:$src1, i8imm:$idx),
422 "vextract" # To.EltTypeName # "x4",
423 "$idx, $src1", "$src1, $idx",
424 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
426 AVX512AIi8Base, EVEX, EVEX_V512;
428 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
429 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
430 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
431 "$dst, $src1, $src2}",
432 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
435 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
437 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
438 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
440 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
442 // A 128/256-bit subvector extract from the first 512-bit vector position is
443 // a subregister copy that needs no instruction.
444 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
446 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
448 // And for the alternative types.
449 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
451 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
453 // Intrinsic call with masking.
454 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
456 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
457 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
458 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
459 VR512:$src1, imm:$idx)>;
461 // Intrinsic call with zero-masking.
462 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
464 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
465 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
466 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
467 VR512:$src1, imm:$idx)>;
469 // Intrinsic call without masking.
470 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
472 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
473 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
474 VR512:$src1, imm:$idx)>;
477 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
478 ValueType EltVT64, int Opcode64> {
479 defm NAME # "32x4" : vextract_for_size<Opcode32,
480 X86VectorVTInfo<16, EltVT32, VR512>,
481 X86VectorVTInfo< 4, EltVT32, VR128X>,
482 X86VectorVTInfo< 8, EltVT64, VR512>,
483 X86VectorVTInfo< 2, EltVT64, VR128X>,
485 EXTRACT_get_vextract128_imm>;
486 defm NAME # "64x4" : vextract_for_size<Opcode64,
487 X86VectorVTInfo< 8, EltVT64, VR512>,
488 X86VectorVTInfo< 4, EltVT64, VR256X>,
489 X86VectorVTInfo<16, EltVT32, VR512>,
490 X86VectorVTInfo< 8, EltVT32, VR256>,
492 EXTRACT_get_vextract256_imm>, VEX_W;
495 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
496 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
498 // A 128-bit subvector insert to the first 512-bit vector position
499 // is a subregister copy that needs no instruction.
500 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
501 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
502 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
504 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
505 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
506 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
508 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
509 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
510 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
512 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
513 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
514 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
517 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
518 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
519 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
520 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
521 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
522 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
523 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
524 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
526 // vextractps - extract 32 bits from XMM
527 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
528 (ins VR128X:$src1, i32i8imm:$src2),
529 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
530 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
533 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
534 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
535 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
536 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
537 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
539 //===---------------------------------------------------------------------===//
542 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
543 RegisterClass DestRC,
544 RegisterClass SrcRC, X86MemOperand x86memop> {
545 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
546 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
548 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
549 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
551 let ExeDomain = SSEPackedSingle in {
552 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
554 EVEX_V512, EVEX_CD8<32, CD8VT1>;
557 let ExeDomain = SSEPackedDouble in {
558 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
560 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
563 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
564 (VBROADCASTSSZrm addr:$src)>;
565 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
566 (VBROADCASTSDZrm addr:$src)>;
568 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
569 (VBROADCASTSSZrm addr:$src)>;
570 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
571 (VBROADCASTSDZrm addr:$src)>;
573 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
574 RegisterClass SrcRC, RegisterClass KRC> {
575 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
577 []>, EVEX, EVEX_V512;
578 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
579 (ins KRC:$mask, SrcRC:$src),
580 !strconcat(OpcodeStr,
581 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
582 []>, EVEX, EVEX_V512, EVEX_KZ;
585 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
586 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
589 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
590 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
592 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
593 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
595 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
596 (VPBROADCASTDrZrr GR32:$src)>;
597 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
598 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
599 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
600 (VPBROADCASTQrZrr GR64:$src)>;
601 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
602 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
604 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
605 (VPBROADCASTDrZrr GR32:$src)>;
606 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
607 (VPBROADCASTQrZrr GR64:$src)>;
609 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
610 (v16i32 immAllZerosV), (i16 GR16:$mask))),
611 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
612 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
613 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
614 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
616 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
617 X86MemOperand x86memop, PatFrag ld_frag,
618 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
620 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
621 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
623 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
624 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
626 !strconcat(OpcodeStr,
627 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
629 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
632 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
633 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
635 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
636 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
638 !strconcat(OpcodeStr,
639 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
640 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
641 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
645 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
646 loadi32, VR512, v16i32, v4i32, VK16WM>,
647 EVEX_V512, EVEX_CD8<32, CD8VT1>;
648 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
649 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
650 EVEX_CD8<64, CD8VT1>;
652 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
653 X86MemOperand x86memop, PatFrag ld_frag,
656 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
657 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
659 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
661 !strconcat(OpcodeStr,
662 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
667 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
668 i128mem, loadv2i64, VK16WM>,
669 EVEX_V512, EVEX_CD8<32, CD8VT4>;
670 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
671 i256mem, loadv4i64, VK16WM>, VEX_W,
672 EVEX_V512, EVEX_CD8<64, CD8VT4>;
674 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
675 (VPBROADCASTDZrr VR128X:$src)>;
676 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
677 (VPBROADCASTQZrr VR128X:$src)>;
679 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
680 (VBROADCASTSSZrr VR128X:$src)>;
681 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
682 (VBROADCASTSDZrr VR128X:$src)>;
684 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
685 (VBROADCASTSSZrr VR128X:$src)>;
686 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
687 (VBROADCASTSDZrr VR128X:$src)>;
689 // Provide fallback in case the load node that is used in the patterns above
690 // is used by additional users, which prevents the pattern selection.
691 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
692 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
693 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
694 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
697 let Predicates = [HasAVX512] in {
698 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
700 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
701 addr:$src)), sub_ymm)>;
703 //===----------------------------------------------------------------------===//
704 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
707 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
708 RegisterClass DstRC, RegisterClass KRC,
709 ValueType OpVT, ValueType SrcVT> {
710 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
711 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
715 let Predicates = [HasCDI] in {
716 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
717 VK16, v16i32, v16i1>, EVEX_V512;
718 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
719 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
722 //===----------------------------------------------------------------------===//
725 // -- immediate form --
726 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
727 SDNode OpNode, PatFrag mem_frag,
728 X86MemOperand x86memop, ValueType OpVT> {
729 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
730 (ins RC:$src1, i8imm:$src2),
731 !strconcat(OpcodeStr,
732 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
734 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
736 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
737 (ins x86memop:$src1, i8imm:$src2),
738 !strconcat(OpcodeStr,
739 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
741 (OpVT (OpNode (mem_frag addr:$src1),
742 (i8 imm:$src2))))]>, EVEX;
745 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
746 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
747 let ExeDomain = SSEPackedDouble in
748 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
749 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
751 // -- VPERM - register form --
752 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
753 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
755 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
756 (ins RC:$src1, RC:$src2),
757 !strconcat(OpcodeStr,
758 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
760 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
762 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
763 (ins RC:$src1, x86memop:$src2),
764 !strconcat(OpcodeStr,
765 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
767 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
771 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
772 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
773 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
774 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
775 let ExeDomain = SSEPackedSingle in
776 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
777 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
778 let ExeDomain = SSEPackedDouble in
779 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
780 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
782 // -- VPERM2I - 3 source operands form --
783 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
784 PatFrag mem_frag, X86MemOperand x86memop,
785 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
786 let Constraints = "$src1 = $dst" in {
787 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
788 (ins RC:$src1, RC:$src2, RC:$src3),
789 !strconcat(OpcodeStr,
790 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
792 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
795 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
796 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
797 !strconcat(OpcodeStr,
798 " \t{$src3, $src2, $dst {${mask}}|"
799 "$dst {${mask}}, $src2, $src3}"),
800 [(set RC:$dst, (OpVT (vselect KRC:$mask,
801 (OpNode RC:$src1, RC:$src2,
806 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
807 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
808 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
809 !strconcat(OpcodeStr,
810 " \t{$src3, $src2, $dst {${mask}} {z} |",
811 "$dst {${mask}} {z}, $src2, $src3}"),
812 [(set RC:$dst, (OpVT (vselect KRC:$mask,
813 (OpNode RC:$src1, RC:$src2,
816 (v16i32 immAllZerosV))))))]>,
819 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
820 (ins RC:$src1, RC:$src2, x86memop:$src3),
821 !strconcat(OpcodeStr,
822 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
824 (OpVT (OpNode RC:$src1, RC:$src2,
825 (mem_frag addr:$src3))))]>, EVEX_4V;
827 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
828 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
829 !strconcat(OpcodeStr,
830 " \t{$src3, $src2, $dst {${mask}}|"
831 "$dst {${mask}}, $src2, $src3}"),
833 (OpVT (vselect KRC:$mask,
834 (OpNode RC:$src1, RC:$src2,
835 (mem_frag addr:$src3)),
839 let AddedComplexity = 10 in // Prefer over the rrkz variant
840 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
841 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
842 !strconcat(OpcodeStr,
843 " \t{$src3, $src2, $dst {${mask}} {z}|"
844 "$dst {${mask}} {z}, $src2, $src3}"),
846 (OpVT (vselect KRC:$mask,
847 (OpNode RC:$src1, RC:$src2,
848 (mem_frag addr:$src3)),
850 (v16i32 immAllZerosV))))))]>,
854 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
855 i512mem, X86VPermiv3, v16i32, VK16WM>,
856 EVEX_V512, EVEX_CD8<32, CD8VF>;
857 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
858 i512mem, X86VPermiv3, v8i64, VK8WM>,
859 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
860 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
861 i512mem, X86VPermiv3, v16f32, VK16WM>,
862 EVEX_V512, EVEX_CD8<32, CD8VF>;
863 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
864 i512mem, X86VPermiv3, v8f64, VK8WM>,
865 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
867 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
868 PatFrag mem_frag, X86MemOperand x86memop,
869 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
870 ValueType MaskVT, RegisterClass MRC> :
871 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
873 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
874 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
875 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
877 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
878 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
879 (!cast<Instruction>(NAME#rrk) VR512:$src1,
880 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
883 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
884 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
885 EVEX_V512, EVEX_CD8<32, CD8VF>;
886 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
887 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
888 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
889 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
890 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
891 EVEX_V512, EVEX_CD8<32, CD8VF>;
892 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
893 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
894 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
896 //===----------------------------------------------------------------------===//
897 // AVX-512 - BLEND using mask
899 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
900 RegisterClass KRC, RegisterClass RC,
901 X86MemOperand x86memop, PatFrag mem_frag,
902 SDNode OpNode, ValueType vt> {
903 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
904 (ins KRC:$mask, RC:$src1, RC:$src2),
905 !strconcat(OpcodeStr,
906 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
907 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
908 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
910 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
911 (ins KRC:$mask, RC:$src1, x86memop:$src2),
912 !strconcat(OpcodeStr,
913 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
914 []>, EVEX_4V, EVEX_K;
917 let ExeDomain = SSEPackedSingle in
918 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
919 VK16WM, VR512, f512mem,
920 memopv16f32, vselect, v16f32>,
921 EVEX_CD8<32, CD8VF>, EVEX_V512;
922 let ExeDomain = SSEPackedDouble in
923 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
924 VK8WM, VR512, f512mem,
925 memopv8f64, vselect, v8f64>,
926 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
928 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
929 (v16f32 VR512:$src2), (i16 GR16:$mask))),
930 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
931 VR512:$src1, VR512:$src2)>;
933 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
934 (v8f64 VR512:$src2), (i8 GR8:$mask))),
935 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
936 VR512:$src1, VR512:$src2)>;
938 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
939 VK16WM, VR512, f512mem,
940 memopv16i32, vselect, v16i32>,
941 EVEX_CD8<32, CD8VF>, EVEX_V512;
943 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
944 VK8WM, VR512, f512mem,
945 memopv8i64, vselect, v8i64>,
946 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
948 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
949 (v16i32 VR512:$src2), (i16 GR16:$mask))),
950 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
951 VR512:$src1, VR512:$src2)>;
953 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
954 (v8i64 VR512:$src2), (i8 GR8:$mask))),
955 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
956 VR512:$src1, VR512:$src2)>;
958 let Predicates = [HasAVX512] in {
959 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
960 (v8f32 VR256X:$src2))),
962 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
963 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
964 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
966 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
967 (v8i32 VR256X:$src2))),
969 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
970 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
971 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
973 //===----------------------------------------------------------------------===//
974 // Compare Instructions
975 //===----------------------------------------------------------------------===//
977 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
978 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
979 Operand CC, SDNode OpNode, ValueType VT,
980 PatFrag ld_frag, string asm, string asm_alt> {
981 def rr : AVX512Ii8<0xC2, MRMSrcReg,
982 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
983 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
984 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
985 def rm : AVX512Ii8<0xC2, MRMSrcMem,
986 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
987 [(set VK1:$dst, (OpNode (VT RC:$src1),
988 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
989 let isAsmParserOnly = 1, hasSideEffects = 0 in {
990 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
991 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
992 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
993 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
994 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
995 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
999 let Predicates = [HasAVX512] in {
1000 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1001 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1002 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1004 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1005 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1006 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1010 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1011 X86VectorVTInfo _> {
1012 def rr : AVX512BI<opc, MRMSrcReg,
1013 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1014 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1015 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1016 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1018 def rm : AVX512BI<opc, MRMSrcMem,
1019 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1021 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1022 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1023 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1024 def rrk : AVX512BI<opc, MRMSrcReg,
1025 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1027 "$dst {${mask}}, $src1, $src2}"),
1028 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1029 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1030 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1032 def rmk : AVX512BI<opc, MRMSrcMem,
1033 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1034 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1035 "$dst {${mask}}, $src1, $src2}"),
1036 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1037 (OpNode (_.VT _.RC:$src1),
1039 (_.LdFrag addr:$src2))))))],
1040 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1043 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1044 X86VectorVTInfo _> :
1045 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1046 let mayLoad = 1 in {
1047 def rmb : AVX512BI<opc, MRMSrcMem,
1048 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1049 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1050 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1051 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1052 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1053 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1054 def rmbk : AVX512BI<opc, MRMSrcMem,
1055 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1056 _.ScalarMemOp:$src2),
1057 !strconcat(OpcodeStr,
1058 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1059 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1060 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1061 (OpNode (_.VT _.RC:$src1),
1063 (_.ScalarLdFrag addr:$src2)))))],
1064 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1068 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1069 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1070 let Predicates = [prd] in
1071 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1074 let Predicates = [prd, HasVLX] in {
1075 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1077 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1082 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1083 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1085 let Predicates = [prd] in
1086 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1089 let Predicates = [prd, HasVLX] in {
1090 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1092 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1097 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1098 avx512vl_i8_info, HasBWI>,
1101 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1102 avx512vl_i16_info, HasBWI>,
1103 EVEX_CD8<16, CD8VF>;
1105 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1106 avx512vl_i32_info, HasAVX512>,
1107 EVEX_CD8<32, CD8VF>;
1109 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1110 avx512vl_i64_info, HasAVX512>,
1111 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1113 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1114 avx512vl_i8_info, HasBWI>,
1117 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1118 avx512vl_i16_info, HasBWI>,
1119 EVEX_CD8<16, CD8VF>;
1121 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1122 avx512vl_i32_info, HasAVX512>,
1123 EVEX_CD8<32, CD8VF>;
1125 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1126 avx512vl_i64_info, HasAVX512>,
1127 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1129 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1130 (COPY_TO_REGCLASS (VPCMPGTDZrr
1131 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1132 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1134 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1135 (COPY_TO_REGCLASS (VPCMPEQDZrr
1136 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1137 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1139 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1140 X86VectorVTInfo _> {
1141 def rri : AVX512AIi8<opc, MRMSrcReg,
1142 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1143 !strconcat("vpcmp${cc}", Suffix,
1144 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1145 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1147 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1149 def rmi : AVX512AIi8<opc, MRMSrcMem,
1150 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1151 !strconcat("vpcmp${cc}", Suffix,
1152 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1153 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1154 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1156 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1157 def rrik : AVX512AIi8<opc, MRMSrcReg,
1158 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1160 !strconcat("vpcmp${cc}", Suffix,
1161 "\t{$src2, $src1, $dst {${mask}}|",
1162 "$dst {${mask}}, $src1, $src2}"),
1163 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1164 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1166 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1168 def rmik : AVX512AIi8<opc, MRMSrcMem,
1169 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1171 !strconcat("vpcmp${cc}", Suffix,
1172 "\t{$src2, $src1, $dst {${mask}}|",
1173 "$dst {${mask}}, $src1, $src2}"),
1174 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1175 (OpNode (_.VT _.RC:$src1),
1176 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1178 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1180 // Accept explicit immediate argument form instead of comparison code.
1181 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1182 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1183 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1184 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1185 "$dst, $src1, $src2, $cc}"),
1186 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1187 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1188 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1189 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1190 "$dst, $src1, $src2, $cc}"),
1191 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1192 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1193 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1195 !strconcat("vpcmp", Suffix,
1196 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1197 "$dst {${mask}}, $src1, $src2, $cc}"),
1198 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1199 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1200 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1202 !strconcat("vpcmp", Suffix,
1203 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1204 "$dst {${mask}}, $src1, $src2, $cc}"),
1205 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1209 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1210 X86VectorVTInfo _> :
1211 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1212 let mayLoad = 1 in {
1213 def rmib : AVX512AIi8<opc, MRMSrcMem,
1214 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1216 !strconcat("vpcmp${cc}", Suffix,
1217 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1218 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1219 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1220 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1222 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1223 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1224 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1225 _.ScalarMemOp:$src2, AVXCC:$cc),
1226 !strconcat("vpcmp${cc}", Suffix,
1227 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1228 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1229 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1230 (OpNode (_.VT _.RC:$src1),
1231 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1233 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1236 // Accept explicit immediate argument form instead of comparison code.
1237 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1238 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1239 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1241 !strconcat("vpcmp", Suffix,
1242 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1243 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1244 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1245 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1246 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1247 _.ScalarMemOp:$src2, i8imm:$cc),
1248 !strconcat("vpcmp", Suffix,
1249 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1250 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1251 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1255 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1256 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1257 let Predicates = [prd] in
1258 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1260 let Predicates = [prd, HasVLX] in {
1261 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1262 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1266 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1267 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1268 let Predicates = [prd] in
1269 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1272 let Predicates = [prd, HasVLX] in {
1273 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1275 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1280 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1281 HasBWI>, EVEX_CD8<8, CD8VF>;
1282 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1283 HasBWI>, EVEX_CD8<8, CD8VF>;
1285 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1286 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1287 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1288 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1290 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1291 HasAVX512>, EVEX_CD8<32, CD8VF>;
1292 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1293 HasAVX512>, EVEX_CD8<32, CD8VF>;
1295 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1296 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1297 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1298 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1300 // avx512_cmp_packed - compare packed instructions
1301 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1302 X86MemOperand x86memop, ValueType vt,
1303 string suffix, Domain d> {
1304 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1305 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1306 !strconcat("vcmp${cc}", suffix,
1307 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1308 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1309 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1310 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1311 !strconcat("vcmp${cc}", suffix,
1312 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1314 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1315 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1316 !strconcat("vcmp${cc}", suffix,
1317 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1319 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1321 // Accept explicit immediate argument form instead of comparison code.
1322 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1323 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1324 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1325 !strconcat("vcmp", suffix,
1326 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1327 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1328 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1329 !strconcat("vcmp", suffix,
1330 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1334 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1335 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1336 EVEX_CD8<32, CD8VF>;
1337 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1338 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1339 EVEX_CD8<64, CD8VF>;
1341 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1342 (COPY_TO_REGCLASS (VCMPPSZrri
1343 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1344 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1346 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1347 (COPY_TO_REGCLASS (VPCMPDZrri
1348 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1349 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1351 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1352 (COPY_TO_REGCLASS (VPCMPUDZrri
1353 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1354 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1357 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1358 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1360 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1361 (I8Imm imm:$cc)), GR16)>;
1363 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1364 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1366 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1367 (I8Imm imm:$cc)), GR8)>;
1369 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1370 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1372 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1373 (I8Imm imm:$cc)), GR16)>;
1375 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1376 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1378 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1379 (I8Imm imm:$cc)), GR8)>;
1381 // Mask register copy, including
1382 // - copy between mask registers
1383 // - load/store mask registers
1384 // - copy from GPR to mask register and vice versa
1386 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1387 string OpcodeStr, RegisterClass KRC,
1388 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1389 let hasSideEffects = 0 in {
1390 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1391 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1393 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1394 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1395 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1397 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1398 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1402 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1404 RegisterClass KRC, RegisterClass GRC> {
1405 let hasSideEffects = 0 in {
1406 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1407 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1408 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1409 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1413 let Predicates = [HasDQI] in
1414 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1416 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1419 let Predicates = [HasAVX512] in
1420 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1422 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1425 let Predicates = [HasBWI] in {
1426 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1427 i32mem>, VEX, PD, VEX_W;
1428 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1432 let Predicates = [HasBWI] in {
1433 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1434 i64mem>, VEX, PS, VEX_W;
1435 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1439 // GR from/to mask register
1440 let Predicates = [HasDQI] in {
1441 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1442 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1443 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1444 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1446 let Predicates = [HasAVX512] in {
1447 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1448 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1449 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1450 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1452 let Predicates = [HasBWI] in {
1453 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1454 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1456 let Predicates = [HasBWI] in {
1457 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1458 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1462 let Predicates = [HasDQI] in {
1463 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1464 (KMOVBmk addr:$dst, VK8:$src)>;
1466 let Predicates = [HasAVX512] in {
1467 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1468 (KMOVWmk addr:$dst, VK16:$src)>;
1469 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1470 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1471 def : Pat<(i1 (load addr:$src)),
1472 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1473 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1474 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1476 let Predicates = [HasBWI] in {
1477 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1478 (KMOVDmk addr:$dst, VK32:$src)>;
1480 let Predicates = [HasBWI] in {
1481 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1482 (KMOVQmk addr:$dst, VK64:$src)>;
1485 let Predicates = [HasAVX512] in {
1486 def : Pat<(i1 (trunc (i64 GR64:$src))),
1487 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1490 def : Pat<(i1 (trunc (i32 GR32:$src))),
1491 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1493 def : Pat<(i1 (trunc (i8 GR8:$src))),
1495 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1497 def : Pat<(i1 (trunc (i16 GR16:$src))),
1499 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1502 def : Pat<(i32 (zext VK1:$src)),
1503 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1504 def : Pat<(i8 (zext VK1:$src)),
1507 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1508 def : Pat<(i64 (zext VK1:$src)),
1509 (AND64ri8 (SUBREG_TO_REG (i64 0),
1510 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1511 def : Pat<(i16 (zext VK1:$src)),
1513 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1515 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1516 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1517 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1518 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1520 let Predicates = [HasBWI] in {
1521 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1522 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1523 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1524 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1528 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1529 let Predicates = [HasAVX512] in {
1530 // GR from/to 8-bit mask without native support
1531 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1533 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1535 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1537 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1540 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1541 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1542 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1543 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1545 let Predicates = [HasBWI] in {
1546 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1547 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1548 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1549 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1552 // Mask unary operation
1554 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1555 RegisterClass KRC, SDPatternOperator OpNode,
1557 let Predicates = [prd] in
1558 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1559 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1560 [(set KRC:$dst, (OpNode KRC:$src))]>;
1563 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1564 SDPatternOperator OpNode> {
1565 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1567 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1568 HasAVX512>, VEX, PS;
1569 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1570 HasBWI>, VEX, PD, VEX_W;
1571 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1572 HasBWI>, VEX, PS, VEX_W;
1575 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1577 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1578 let Predicates = [HasAVX512] in
1579 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1581 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1582 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1584 defm : avx512_mask_unop_int<"knot", "KNOT">;
1586 let Predicates = [HasDQI] in
1587 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1588 let Predicates = [HasAVX512] in
1589 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1590 let Predicates = [HasBWI] in
1591 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1592 let Predicates = [HasBWI] in
1593 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1595 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1596 let Predicates = [HasAVX512] in {
1597 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1598 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1600 def : Pat<(not VK8:$src),
1602 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1605 // Mask binary operation
1606 // - KAND, KANDN, KOR, KXNOR, KXOR
1607 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1608 RegisterClass KRC, SDPatternOperator OpNode,
1610 let Predicates = [prd] in
1611 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1612 !strconcat(OpcodeStr,
1613 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1614 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1617 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1618 SDPatternOperator OpNode> {
1619 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1620 HasDQI>, VEX_4V, VEX_L, PD;
1621 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1622 HasAVX512>, VEX_4V, VEX_L, PS;
1623 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1624 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1625 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1626 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1629 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1630 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1632 let isCommutable = 1 in {
1633 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1634 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1635 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1636 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1638 let isCommutable = 0 in
1639 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1641 def : Pat<(xor VK1:$src1, VK1:$src2),
1642 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1643 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1645 def : Pat<(or VK1:$src1, VK1:$src2),
1646 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1647 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1649 def : Pat<(and VK1:$src1, VK1:$src2),
1650 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1651 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1653 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1654 let Predicates = [HasAVX512] in
1655 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1656 (i16 GR16:$src1), (i16 GR16:$src2)),
1657 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1658 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1659 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1662 defm : avx512_mask_binop_int<"kand", "KAND">;
1663 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1664 defm : avx512_mask_binop_int<"kor", "KOR">;
1665 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1666 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1668 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1669 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1670 let Predicates = [HasAVX512] in
1671 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1673 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1674 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1677 defm : avx512_binop_pat<and, KANDWrr>;
1678 defm : avx512_binop_pat<andn, KANDNWrr>;
1679 defm : avx512_binop_pat<or, KORWrr>;
1680 defm : avx512_binop_pat<xnor, KXNORWrr>;
1681 defm : avx512_binop_pat<xor, KXORWrr>;
1684 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1685 RegisterClass KRC> {
1686 let Predicates = [HasAVX512] in
1687 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1688 !strconcat(OpcodeStr,
1689 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1692 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1693 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1697 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1698 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1699 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1700 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1703 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1704 let Predicates = [HasAVX512] in
1705 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1706 (i16 GR16:$src1), (i16 GR16:$src2)),
1707 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1708 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1709 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1711 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1714 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1716 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1717 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1718 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1719 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1722 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1723 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1727 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1729 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1730 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1731 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1734 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1736 let Predicates = [HasAVX512] in
1737 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1738 !strconcat(OpcodeStr,
1739 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1740 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1743 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1745 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1749 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1750 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1752 // Mask setting all 0s or 1s
1753 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1754 let Predicates = [HasAVX512] in
1755 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1756 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1757 [(set KRC:$dst, (VT Val))]>;
1760 multiclass avx512_mask_setop_w<PatFrag Val> {
1761 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1762 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1765 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1766 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1768 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1769 let Predicates = [HasAVX512] in {
1770 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1771 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1772 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1773 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1774 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1776 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1777 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1779 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1780 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1782 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1783 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1785 let Predicates = [HasVLX] in {
1786 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1787 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1788 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1789 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1790 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1791 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1792 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1793 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1796 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1797 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1799 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1800 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1801 //===----------------------------------------------------------------------===//
1802 // AVX-512 - Aligned and unaligned load and store
1805 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1806 RegisterClass KRC, RegisterClass RC,
1807 ValueType vt, ValueType zvt, X86MemOperand memop,
1808 Domain d, bit IsReMaterializable = 1> {
1809 let hasSideEffects = 0 in {
1810 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1811 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1813 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1814 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1815 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1817 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1818 SchedRW = [WriteLoad] in
1819 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1820 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1821 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1824 let AddedComplexity = 20 in {
1825 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1826 let hasSideEffects = 0 in
1827 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1828 (ins RC:$src0, KRC:$mask, RC:$src1),
1829 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1830 "${dst} {${mask}}, $src1}"),
1831 [(set RC:$dst, (vt (vselect KRC:$mask,
1835 let mayLoad = 1, SchedRW = [WriteLoad] in
1836 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1837 (ins RC:$src0, KRC:$mask, memop:$src1),
1838 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1839 "${dst} {${mask}}, $src1}"),
1842 (vt (bitconvert (ld_frag addr:$src1))),
1846 let mayLoad = 1, SchedRW = [WriteLoad] in
1847 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1848 (ins KRC:$mask, memop:$src),
1849 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1850 "${dst} {${mask}} {z}, $src}"),
1853 (vt (bitconvert (ld_frag addr:$src))),
1854 (vt (bitconvert (zvt immAllZerosV))))))],
1859 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1860 string elty, string elsz, string vsz512,
1861 string vsz256, string vsz128, Domain d,
1862 Predicate prd, bit IsReMaterializable = 1> {
1863 let Predicates = [prd] in
1864 defm Z : avx512_load<opc, OpcodeStr,
1865 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1866 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1867 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1868 !cast<X86MemOperand>(elty##"512mem"), d,
1869 IsReMaterializable>, EVEX_V512;
1871 let Predicates = [prd, HasVLX] in {
1872 defm Z256 : avx512_load<opc, OpcodeStr,
1873 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1874 "v"##vsz256##elty##elsz, "v4i64")),
1875 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1876 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1877 !cast<X86MemOperand>(elty##"256mem"), d,
1878 IsReMaterializable>, EVEX_V256;
1880 defm Z128 : avx512_load<opc, OpcodeStr,
1881 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1882 "v"##vsz128##elty##elsz, "v2i64")),
1883 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1884 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1885 !cast<X86MemOperand>(elty##"128mem"), d,
1886 IsReMaterializable>, EVEX_V128;
1891 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1892 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1893 X86MemOperand memop, Domain d> {
1894 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1895 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1898 let Constraints = "$src1 = $dst" in
1899 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1900 (ins RC:$src1, KRC:$mask, RC:$src2),
1901 !strconcat(OpcodeStr,
1902 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1904 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1905 (ins KRC:$mask, RC:$src),
1906 !strconcat(OpcodeStr,
1907 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1908 [], d>, EVEX, EVEX_KZ;
1910 let mayStore = 1 in {
1911 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1912 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1913 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1914 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1915 (ins memop:$dst, KRC:$mask, RC:$src),
1916 !strconcat(OpcodeStr,
1917 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1918 [], d>, EVEX, EVEX_K;
1923 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1924 string st_suff_512, string st_suff_256,
1925 string st_suff_128, string elty, string elsz,
1926 string vsz512, string vsz256, string vsz128,
1927 Domain d, Predicate prd> {
1928 let Predicates = [prd] in
1929 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1930 !cast<ValueType>("v"##vsz512##elty##elsz),
1931 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1932 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1934 let Predicates = [prd, HasVLX] in {
1935 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1936 !cast<ValueType>("v"##vsz256##elty##elsz),
1937 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1938 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1940 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1941 !cast<ValueType>("v"##vsz128##elty##elsz),
1942 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1943 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1947 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1948 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1949 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1950 "512", "256", "", "f", "32", "16", "8", "4",
1951 SSEPackedSingle, HasAVX512>,
1952 PS, EVEX_CD8<32, CD8VF>;
1954 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1955 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1956 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1957 "512", "256", "", "f", "64", "8", "4", "2",
1958 SSEPackedDouble, HasAVX512>,
1959 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1961 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1962 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1963 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1964 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1965 PS, EVEX_CD8<32, CD8VF>;
1967 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1968 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1969 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1970 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1971 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1973 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1974 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1975 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1977 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1978 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1979 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1981 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1983 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1985 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1987 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1990 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1991 "16", "8", "4", SSEPackedInt, HasAVX512>,
1992 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1993 "512", "256", "", "i", "32", "16", "8", "4",
1994 SSEPackedInt, HasAVX512>,
1995 PD, EVEX_CD8<32, CD8VF>;
1997 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1998 "8", "4", "2", SSEPackedInt, HasAVX512>,
1999 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2000 "512", "256", "", "i", "64", "8", "4", "2",
2001 SSEPackedInt, HasAVX512>,
2002 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2004 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2005 "64", "32", "16", SSEPackedInt, HasBWI>,
2006 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2007 "i", "8", "64", "32", "16", SSEPackedInt,
2008 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2010 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2011 "32", "16", "8", SSEPackedInt, HasBWI>,
2012 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2013 "i", "16", "32", "16", "8", SSEPackedInt,
2014 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2016 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2017 "16", "8", "4", SSEPackedInt, HasAVX512>,
2018 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2019 "i", "32", "16", "8", "4", SSEPackedInt,
2020 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2022 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2023 "8", "4", "2", SSEPackedInt, HasAVX512>,
2024 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2025 "i", "64", "8", "4", "2", SSEPackedInt,
2026 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2028 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2029 (v16i32 immAllZerosV), GR16:$mask)),
2030 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2032 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2033 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2034 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2036 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2038 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2040 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2042 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2045 let AddedComplexity = 20 in {
2046 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2047 (bc_v8i64 (v16i32 immAllZerosV)))),
2048 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2050 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2051 (v8i64 VR512:$src))),
2052 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2055 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2056 (v16i32 immAllZerosV))),
2057 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2059 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2060 (v16i32 VR512:$src))),
2061 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2064 // Move Int Doubleword to Packed Double Int
2066 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2067 "vmovd\t{$src, $dst|$dst, $src}",
2069 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2071 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2072 "vmovd\t{$src, $dst|$dst, $src}",
2074 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2075 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2076 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2077 "vmovq\t{$src, $dst|$dst, $src}",
2079 (v2i64 (scalar_to_vector GR64:$src)))],
2080 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2081 let isCodeGenOnly = 1 in {
2082 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2083 "vmovq\t{$src, $dst|$dst, $src}",
2084 [(set FR64:$dst, (bitconvert GR64:$src))],
2085 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2086 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2087 "vmovq\t{$src, $dst|$dst, $src}",
2088 [(set GR64:$dst, (bitconvert FR64:$src))],
2089 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2091 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2092 "vmovq\t{$src, $dst|$dst, $src}",
2093 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2094 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2095 EVEX_CD8<64, CD8VT1>;
2097 // Move Int Doubleword to Single Scalar
2099 let isCodeGenOnly = 1 in {
2100 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2101 "vmovd\t{$src, $dst|$dst, $src}",
2102 [(set FR32X:$dst, (bitconvert GR32:$src))],
2103 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2105 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2106 "vmovd\t{$src, $dst|$dst, $src}",
2107 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2108 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2111 // Move doubleword from xmm register to r/m32
2113 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2114 "vmovd\t{$src, $dst|$dst, $src}",
2115 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2116 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2118 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2119 (ins i32mem:$dst, VR128X:$src),
2120 "vmovd\t{$src, $dst|$dst, $src}",
2121 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2122 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2123 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2125 // Move quadword from xmm1 register to r/m64
2127 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2128 "vmovq\t{$src, $dst|$dst, $src}",
2129 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2131 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2132 Requires<[HasAVX512, In64BitMode]>;
2134 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2135 (ins i64mem:$dst, VR128X:$src),
2136 "vmovq\t{$src, $dst|$dst, $src}",
2137 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2138 addr:$dst)], IIC_SSE_MOVDQ>,
2139 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2140 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2142 // Move Scalar Single to Double Int
2144 let isCodeGenOnly = 1 in {
2145 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2147 "vmovd\t{$src, $dst|$dst, $src}",
2148 [(set GR32:$dst, (bitconvert FR32X:$src))],
2149 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2150 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2151 (ins i32mem:$dst, FR32X:$src),
2152 "vmovd\t{$src, $dst|$dst, $src}",
2153 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2154 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2157 // Move Quadword Int to Packed Quadword Int
2159 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2161 "vmovq\t{$src, $dst|$dst, $src}",
2163 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2164 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2166 //===----------------------------------------------------------------------===//
2167 // AVX-512 MOVSS, MOVSD
2168 //===----------------------------------------------------------------------===//
2170 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2171 SDNode OpNode, ValueType vt,
2172 X86MemOperand x86memop, PatFrag mem_pat> {
2173 let hasSideEffects = 0 in {
2174 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2175 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2176 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2177 (scalar_to_vector RC:$src2))))],
2178 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2179 let Constraints = "$src1 = $dst" in
2180 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2181 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2183 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2184 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2185 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2186 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2187 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2189 let mayStore = 1 in {
2190 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2191 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2192 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2194 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2195 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2196 [], IIC_SSE_MOV_S_MR>,
2197 EVEX, VEX_LIG, EVEX_K;
2199 } //hasSideEffects = 0
2202 let ExeDomain = SSEPackedSingle in
2203 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2204 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2206 let ExeDomain = SSEPackedDouble in
2207 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2208 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2210 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2211 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2212 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2214 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2215 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2216 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2218 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2219 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2220 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2222 // For the disassembler
2223 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2224 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2225 (ins VR128X:$src1, FR32X:$src2),
2226 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2228 XS, EVEX_4V, VEX_LIG;
2229 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2230 (ins VR128X:$src1, FR64X:$src2),
2231 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2233 XD, EVEX_4V, VEX_LIG, VEX_W;
2236 let Predicates = [HasAVX512] in {
2237 let AddedComplexity = 15 in {
2238 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2239 // MOVS{S,D} to the lower bits.
2240 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2241 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2242 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2243 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2244 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2245 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2246 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2247 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2249 // Move low f32 and clear high bits.
2250 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2251 (SUBREG_TO_REG (i32 0),
2252 (VMOVSSZrr (v4f32 (V_SET0)),
2253 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2254 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2255 (SUBREG_TO_REG (i32 0),
2256 (VMOVSSZrr (v4i32 (V_SET0)),
2257 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2260 let AddedComplexity = 20 in {
2261 // MOVSSrm zeros the high parts of the register; represent this
2262 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2263 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2264 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2265 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2266 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2267 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2268 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2270 // MOVSDrm zeros the high parts of the register; represent this
2271 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2272 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2273 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2274 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2275 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2276 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2277 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2278 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2279 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2280 def : Pat<(v2f64 (X86vzload addr:$src)),
2281 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2283 // Represent the same patterns above but in the form they appear for
2285 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2286 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2287 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2288 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2289 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2290 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2291 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2292 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2293 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2295 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2296 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2297 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2298 FR32X:$src)), sub_xmm)>;
2299 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2300 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2301 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2302 FR64X:$src)), sub_xmm)>;
2303 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2304 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2305 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2307 // Move low f64 and clear high bits.
2308 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2309 (SUBREG_TO_REG (i32 0),
2310 (VMOVSDZrr (v2f64 (V_SET0)),
2311 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2313 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2314 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2315 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2317 // Extract and store.
2318 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2320 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2321 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2323 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2325 // Shuffle with VMOVSS
2326 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2327 (VMOVSSZrr (v4i32 VR128X:$src1),
2328 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2329 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2330 (VMOVSSZrr (v4f32 VR128X:$src1),
2331 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2334 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2335 (SUBREG_TO_REG (i32 0),
2336 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2337 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2339 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2340 (SUBREG_TO_REG (i32 0),
2341 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2342 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2345 // Shuffle with VMOVSD
2346 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2347 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2348 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2349 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2350 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2351 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2352 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2353 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2356 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2357 (SUBREG_TO_REG (i32 0),
2358 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2359 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2361 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2362 (SUBREG_TO_REG (i32 0),
2363 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2364 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2367 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2368 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2369 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2370 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2371 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2372 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2373 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2374 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2377 let AddedComplexity = 15 in
2378 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2380 "vmovq\t{$src, $dst|$dst, $src}",
2381 [(set VR128X:$dst, (v2i64 (X86vzmovl
2382 (v2i64 VR128X:$src))))],
2383 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2385 let AddedComplexity = 20 in
2386 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2388 "vmovq\t{$src, $dst|$dst, $src}",
2389 [(set VR128X:$dst, (v2i64 (X86vzmovl
2390 (loadv2i64 addr:$src))))],
2391 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2392 EVEX_CD8<8, CD8VT8>;
2394 let Predicates = [HasAVX512] in {
2395 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2396 let AddedComplexity = 20 in {
2397 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2398 (VMOVDI2PDIZrm addr:$src)>;
2399 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2400 (VMOV64toPQIZrr GR64:$src)>;
2401 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2402 (VMOVDI2PDIZrr GR32:$src)>;
2404 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2405 (VMOVDI2PDIZrm addr:$src)>;
2406 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2407 (VMOVDI2PDIZrm addr:$src)>;
2408 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2409 (VMOVZPQILo2PQIZrm addr:$src)>;
2410 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2411 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2412 def : Pat<(v2i64 (X86vzload addr:$src)),
2413 (VMOVZPQILo2PQIZrm addr:$src)>;
2416 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2417 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2418 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2419 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2420 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2421 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2422 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2425 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2426 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2428 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2429 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2431 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2432 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2434 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2435 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2437 //===----------------------------------------------------------------------===//
2438 // AVX-512 - Non-temporals
2439 //===----------------------------------------------------------------------===//
2440 let SchedRW = [WriteLoad] in {
2441 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2442 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2443 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2444 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2445 EVEX_CD8<64, CD8VF>;
2447 let Predicates = [HasAVX512, HasVLX] in {
2448 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2450 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2451 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2452 EVEX_CD8<64, CD8VF>;
2454 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2456 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2457 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2458 EVEX_CD8<64, CD8VF>;
2462 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2463 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2464 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2465 let SchedRW = [WriteStore], mayStore = 1,
2466 AddedComplexity = 400 in
2467 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2468 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2469 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2472 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2473 string elty, string elsz, string vsz512,
2474 string vsz256, string vsz128, Domain d,
2475 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2476 let Predicates = [prd] in
2477 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2478 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2479 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2482 let Predicates = [prd, HasVLX] in {
2483 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2484 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2485 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2488 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2489 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2490 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2495 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2496 "i", "64", "8", "4", "2", SSEPackedInt,
2497 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2499 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2500 "f", "64", "8", "4", "2", SSEPackedDouble,
2501 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2503 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2504 "f", "32", "16", "8", "4", SSEPackedSingle,
2505 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2507 //===----------------------------------------------------------------------===//
2508 // AVX-512 - Integer arithmetic
2510 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2511 X86VectorVTInfo _, OpndItins itins,
2512 bit IsCommutable = 0> {
2513 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2514 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2515 "$src2, $src1", "$src1, $src2",
2516 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2517 itins.rr, IsCommutable>,
2518 AVX512BIBase, EVEX_4V;
2520 let mayLoad = 1 in {
2521 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2522 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2523 "$src2, $src1", "$src1, $src2",
2524 (_.VT (OpNode _.RC:$src1,
2525 (bitconvert (_.LdFrag addr:$src2)))),
2527 AVX512BIBase, EVEX_4V;
2528 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2529 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2530 "${src2}"##_.BroadcastStr##", $src1",
2531 "$src1, ${src2}"##_.BroadcastStr,
2532 (_.VT (OpNode _.RC:$src1,
2534 (_.ScalarLdFrag addr:$src2)))),
2536 AVX512BIBase, EVEX_4V, EVEX_B;
2540 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2541 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2542 PatFrag memop_frag, X86MemOperand x86memop,
2543 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2544 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2545 let isCommutable = IsCommutable in
2547 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2548 (ins RC:$src1, RC:$src2),
2549 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2551 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2552 (ins KRC:$mask, RC:$src1, RC:$src2),
2553 !strconcat(OpcodeStr,
2554 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2555 [], itins.rr>, EVEX_4V, EVEX_K;
2556 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2557 (ins KRC:$mask, RC:$src1, RC:$src2),
2558 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2559 "|$dst {${mask}} {z}, $src1, $src2}"),
2560 [], itins.rr>, EVEX_4V, EVEX_KZ;
2562 let mayLoad = 1 in {
2563 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2564 (ins RC:$src1, x86memop:$src2),
2565 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2567 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2568 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2569 !strconcat(OpcodeStr,
2570 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2571 [], itins.rm>, EVEX_4V, EVEX_K;
2572 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2573 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2574 !strconcat(OpcodeStr,
2575 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2576 [], itins.rm>, EVEX_4V, EVEX_KZ;
2577 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2578 (ins RC:$src1, x86scalar_mop:$src2),
2579 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2580 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2581 [], itins.rm>, EVEX_4V, EVEX_B;
2582 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2583 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2584 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2585 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2587 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2588 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2589 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2590 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2591 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2593 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2597 defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
2598 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2600 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
2601 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2603 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
2604 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2606 defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
2607 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2609 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
2610 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2612 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2613 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2614 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2615 EVEX_CD8<64, CD8VF>, VEX_W;
2617 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2618 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2619 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2621 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2622 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2624 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2625 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2626 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2627 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2628 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2629 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2631 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
2632 SSE_INTALU_ITINS_P, 1>,
2633 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2634 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
2635 SSE_INTALU_ITINS_P, 0>,
2636 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2638 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
2639 SSE_INTALU_ITINS_P, 1>,
2640 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2641 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
2642 SSE_INTALU_ITINS_P, 0>,
2643 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2645 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
2646 SSE_INTALU_ITINS_P, 1>,
2647 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2648 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
2649 SSE_INTALU_ITINS_P, 0>,
2650 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2652 defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
2653 SSE_INTALU_ITINS_P, 1>,
2654 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2655 defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
2656 SSE_INTALU_ITINS_P, 0>,
2657 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2659 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2660 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2661 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2662 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2663 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2664 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2665 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2666 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2667 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2668 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2669 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2670 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2671 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2672 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2673 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2674 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2675 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2676 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2677 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2678 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2679 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2680 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2681 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2682 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2683 //===----------------------------------------------------------------------===//
2684 // AVX-512 - Unpack Instructions
2685 //===----------------------------------------------------------------------===//
2687 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2688 PatFrag mem_frag, RegisterClass RC,
2689 X86MemOperand x86memop, string asm,
2691 def rr : AVX512PI<opc, MRMSrcReg,
2692 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2694 (vt (OpNode RC:$src1, RC:$src2)))],
2696 def rm : AVX512PI<opc, MRMSrcMem,
2697 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2699 (vt (OpNode RC:$src1,
2700 (bitconvert (mem_frag addr:$src2)))))],
2704 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2705 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2707 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2708 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2710 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2711 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2712 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2713 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2714 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2715 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2717 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2718 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2719 X86MemOperand x86memop> {
2720 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2721 (ins RC:$src1, RC:$src2),
2722 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2723 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2724 IIC_SSE_UNPCK>, EVEX_4V;
2725 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2726 (ins RC:$src1, x86memop:$src2),
2727 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2728 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2729 (bitconvert (memop_frag addr:$src2)))))],
2730 IIC_SSE_UNPCK>, EVEX_4V;
2732 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2733 VR512, memopv16i32, i512mem>, EVEX_V512,
2734 EVEX_CD8<32, CD8VF>;
2735 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2736 VR512, memopv8i64, i512mem>, EVEX_V512,
2737 VEX_W, EVEX_CD8<64, CD8VF>;
2738 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2739 VR512, memopv16i32, i512mem>, EVEX_V512,
2740 EVEX_CD8<32, CD8VF>;
2741 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2742 VR512, memopv8i64, i512mem>, EVEX_V512,
2743 VEX_W, EVEX_CD8<64, CD8VF>;
2744 //===----------------------------------------------------------------------===//
2748 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2749 SDNode OpNode, PatFrag mem_frag,
2750 X86MemOperand x86memop, ValueType OpVT> {
2751 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2752 (ins RC:$src1, i8imm:$src2),
2753 !strconcat(OpcodeStr,
2754 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2756 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2758 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2759 (ins x86memop:$src1, i8imm:$src2),
2760 !strconcat(OpcodeStr,
2761 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2763 (OpVT (OpNode (mem_frag addr:$src1),
2764 (i8 imm:$src2))))]>, EVEX;
2767 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2768 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2770 let ExeDomain = SSEPackedSingle in
2771 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
2772 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2773 EVEX_CD8<32, CD8VF>;
2774 let ExeDomain = SSEPackedDouble in
2775 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
2776 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2777 VEX_W, EVEX_CD8<32, CD8VF>;
2779 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2780 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2781 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2782 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2784 //===----------------------------------------------------------------------===//
2785 // AVX-512 Logical Instructions
2786 //===----------------------------------------------------------------------===//
2788 defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
2789 EVEX_V512, EVEX_CD8<32, CD8VF>;
2790 defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
2791 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2792 defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
2793 EVEX_V512, EVEX_CD8<32, CD8VF>;
2794 defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
2795 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2796 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
2797 EVEX_V512, EVEX_CD8<32, CD8VF>;
2798 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
2799 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2800 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
2801 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2802 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
2803 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2805 //===----------------------------------------------------------------------===//
2806 // AVX-512 FP arithmetic
2807 //===----------------------------------------------------------------------===//
2809 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2811 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2812 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2813 EVEX_CD8<32, CD8VT1>;
2814 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2815 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2816 EVEX_CD8<64, CD8VT1>;
2819 let isCommutable = 1 in {
2820 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2821 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2822 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2823 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2825 let isCommutable = 0 in {
2826 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2827 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2830 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2832 RegisterClass RC, ValueType vt,
2833 X86MemOperand x86memop, PatFrag mem_frag,
2834 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2836 Domain d, OpndItins itins, bit commutable> {
2837 let isCommutable = commutable in {
2838 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2839 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2840 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2843 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2844 !strconcat(OpcodeStr,
2845 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2846 [], itins.rr, d>, EVEX_4V, EVEX_K;
2848 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2849 !strconcat(OpcodeStr,
2850 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2851 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2854 let mayLoad = 1 in {
2855 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2856 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2857 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2858 itins.rm, d>, EVEX_4V;
2860 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2861 (ins RC:$src1, x86scalar_mop:$src2),
2862 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2863 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2864 [(set RC:$dst, (OpNode RC:$src1,
2865 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2866 itins.rm, d>, EVEX_4V, EVEX_B;
2868 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2869 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2870 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2871 [], itins.rm, d>, EVEX_4V, EVEX_K;
2873 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2874 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2875 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2876 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2878 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2879 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2880 " \t{${src2}", BrdcstStr,
2881 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2882 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2884 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2885 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2886 " \t{${src2}", BrdcstStr,
2887 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2889 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2893 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2894 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2895 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2897 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2898 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2899 SSE_ALU_ITINS_P.d, 1>,
2900 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2902 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2903 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2904 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2905 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2906 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2907 SSE_ALU_ITINS_P.d, 1>,
2908 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2910 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2911 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2912 SSE_ALU_ITINS_P.s, 1>,
2913 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2914 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2915 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2916 SSE_ALU_ITINS_P.s, 1>,
2917 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2919 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2920 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2921 SSE_ALU_ITINS_P.d, 1>,
2922 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2923 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2924 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2925 SSE_ALU_ITINS_P.d, 1>,
2926 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2928 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2929 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2930 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2931 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2932 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2933 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2935 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2936 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2937 SSE_ALU_ITINS_P.d, 0>,
2938 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2939 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2940 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2941 SSE_ALU_ITINS_P.d, 0>,
2942 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2944 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2945 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2946 (i16 -1), FROUND_CURRENT)),
2947 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2949 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2950 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2951 (i8 -1), FROUND_CURRENT)),
2952 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2954 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2955 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2956 (i16 -1), FROUND_CURRENT)),
2957 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2959 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2960 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2961 (i8 -1), FROUND_CURRENT)),
2962 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2963 //===----------------------------------------------------------------------===//
2964 // AVX-512 VPTESTM instructions
2965 //===----------------------------------------------------------------------===//
2967 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2968 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2969 SDNode OpNode, ValueType vt> {
2970 def rr : AVX512PI<opc, MRMSrcReg,
2971 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2972 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2973 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2974 SSEPackedInt>, EVEX_4V;
2975 def rm : AVX512PI<opc, MRMSrcMem,
2976 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2977 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2978 [(set KRC:$dst, (OpNode (vt RC:$src1),
2979 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2982 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2983 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2984 EVEX_CD8<32, CD8VF>;
2985 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2986 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2987 EVEX_CD8<64, CD8VF>;
2989 let Predicates = [HasCDI] in {
2990 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2991 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2992 EVEX_CD8<32, CD8VF>;
2993 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2994 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2995 EVEX_CD8<64, CD8VF>;
2998 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2999 (v16i32 VR512:$src2), (i16 -1))),
3000 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3002 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3003 (v8i64 VR512:$src2), (i8 -1))),
3004 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3005 //===----------------------------------------------------------------------===//
3006 // AVX-512 Shift instructions
3007 //===----------------------------------------------------------------------===//
3008 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3009 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3010 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3011 RegisterClass KRC> {
3012 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3013 (ins RC:$src1, i8imm:$src2),
3014 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3015 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
3016 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3017 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3018 (ins KRC:$mask, RC:$src1, i8imm:$src2),
3019 !strconcat(OpcodeStr,
3020 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3021 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3022 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3023 (ins x86memop:$src1, i8imm:$src2),
3024 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3025 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
3026 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3027 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3028 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
3029 !strconcat(OpcodeStr,
3030 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3031 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3034 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3035 RegisterClass RC, ValueType vt, ValueType SrcVT,
3036 PatFrag bc_frag, RegisterClass KRC> {
3037 // src2 is always 128-bit
3038 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3039 (ins RC:$src1, VR128X:$src2),
3040 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3041 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3042 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3043 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3044 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3045 !strconcat(OpcodeStr,
3046 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3047 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3048 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3049 (ins RC:$src1, i128mem:$src2),
3050 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3051 [(set RC:$dst, (vt (OpNode RC:$src1,
3052 (bc_frag (memopv2i64 addr:$src2)))))],
3053 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3054 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3055 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3056 !strconcat(OpcodeStr,
3057 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3058 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3061 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3062 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3063 EVEX_V512, EVEX_CD8<32, CD8VF>;
3064 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3065 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3066 EVEX_CD8<32, CD8VQ>;
3068 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3069 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3070 EVEX_CD8<64, CD8VF>, VEX_W;
3071 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3072 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3073 EVEX_CD8<64, CD8VQ>, VEX_W;
3075 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3076 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3077 EVEX_CD8<32, CD8VF>;
3078 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3079 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3080 EVEX_CD8<32, CD8VQ>;
3082 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3083 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3084 EVEX_CD8<64, CD8VF>, VEX_W;
3085 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3086 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3087 EVEX_CD8<64, CD8VQ>, VEX_W;
3089 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3090 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3091 EVEX_V512, EVEX_CD8<32, CD8VF>;
3092 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3093 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3094 EVEX_CD8<32, CD8VQ>;
3096 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3097 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3098 EVEX_CD8<64, CD8VF>, VEX_W;
3099 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3100 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3101 EVEX_CD8<64, CD8VQ>, VEX_W;
3103 //===-------------------------------------------------------------------===//
3104 // Variable Bit Shifts
3105 //===-------------------------------------------------------------------===//
3106 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3107 RegisterClass RC, ValueType vt,
3108 X86MemOperand x86memop, PatFrag mem_frag> {
3109 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3110 (ins RC:$src1, RC:$src2),
3111 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3113 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3115 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3116 (ins RC:$src1, x86memop:$src2),
3117 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3119 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3123 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3124 i512mem, memopv16i32>, EVEX_V512,
3125 EVEX_CD8<32, CD8VF>;
3126 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3127 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3128 EVEX_CD8<64, CD8VF>;
3129 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3130 i512mem, memopv16i32>, EVEX_V512,
3131 EVEX_CD8<32, CD8VF>;
3132 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3133 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3134 EVEX_CD8<64, CD8VF>;
3135 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3136 i512mem, memopv16i32>, EVEX_V512,
3137 EVEX_CD8<32, CD8VF>;
3138 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3139 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3140 EVEX_CD8<64, CD8VF>;
3142 //===----------------------------------------------------------------------===//
3143 // AVX-512 - MOVDDUP
3144 //===----------------------------------------------------------------------===//
3146 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3147 X86MemOperand x86memop, PatFrag memop_frag> {
3148 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3149 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3150 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3151 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3152 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3154 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3157 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3158 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3159 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3160 (VMOVDDUPZrm addr:$src)>;
3162 //===---------------------------------------------------------------------===//
3163 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3164 //===---------------------------------------------------------------------===//
3165 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3166 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3167 X86MemOperand x86memop> {
3168 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3169 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3170 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3172 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3173 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3174 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3177 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3178 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3179 EVEX_CD8<32, CD8VF>;
3180 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3181 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3182 EVEX_CD8<32, CD8VF>;
3184 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3185 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3186 (VMOVSHDUPZrm addr:$src)>;
3187 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3188 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3189 (VMOVSLDUPZrm addr:$src)>;
3191 //===----------------------------------------------------------------------===//
3192 // Move Low to High and High to Low packed FP Instructions
3193 //===----------------------------------------------------------------------===//
3194 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3195 (ins VR128X:$src1, VR128X:$src2),
3196 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3197 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3198 IIC_SSE_MOV_LH>, EVEX_4V;
3199 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3200 (ins VR128X:$src1, VR128X:$src2),
3201 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3202 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3203 IIC_SSE_MOV_LH>, EVEX_4V;
3205 let Predicates = [HasAVX512] in {
3207 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3208 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3209 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3210 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3213 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3214 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3217 //===----------------------------------------------------------------------===//
3218 // FMA - Fused Multiply Operations
3220 let Constraints = "$src1 = $dst" in {
3221 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3222 X86VectorVTInfo _> {
3223 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3224 (ins _.RC:$src2, _.RC:$src3),
3225 OpcodeStr, "$src3, $src2", "$src2, $src3",
3226 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3230 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3231 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3232 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3233 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3234 (_.MemOpFrag addr:$src3))))]>;
3235 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3236 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3237 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3238 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3239 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3240 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3242 } // Constraints = "$src1 = $dst"
3244 let ExeDomain = SSEPackedSingle in {
3245 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3247 EVEX_V512, EVEX_CD8<32, CD8VF>;
3248 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3250 EVEX_V512, EVEX_CD8<32, CD8VF>;
3251 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3253 EVEX_V512, EVEX_CD8<32, CD8VF>;
3254 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3256 EVEX_V512, EVEX_CD8<32, CD8VF>;
3257 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3259 EVEX_V512, EVEX_CD8<32, CD8VF>;
3260 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3262 EVEX_V512, EVEX_CD8<32, CD8VF>;
3264 let ExeDomain = SSEPackedDouble in {
3265 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3267 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3268 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3270 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3271 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3273 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3274 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3276 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3277 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3279 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3280 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3282 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3285 let Constraints = "$src1 = $dst" in {
3286 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3287 X86VectorVTInfo _> {
3289 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3290 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3291 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3292 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3294 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3295 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3296 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3297 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3299 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3300 (_.ScalarLdFrag addr:$src2))),
3301 _.RC:$src3))]>, EVEX_B;
3303 } // Constraints = "$src1 = $dst"
3306 let ExeDomain = SSEPackedSingle in {
3307 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3309 EVEX_V512, EVEX_CD8<32, CD8VF>;
3310 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3312 EVEX_V512, EVEX_CD8<32, CD8VF>;
3313 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3315 EVEX_V512, EVEX_CD8<32, CD8VF>;
3316 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3318 EVEX_V512, EVEX_CD8<32, CD8VF>;
3319 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3321 EVEX_V512, EVEX_CD8<32, CD8VF>;
3322 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3324 EVEX_V512, EVEX_CD8<32, CD8VF>;
3326 let ExeDomain = SSEPackedDouble in {
3327 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3329 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3330 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3332 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3333 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3335 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3336 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3338 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3339 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3341 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3342 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3344 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3348 let Constraints = "$src1 = $dst" in {
3349 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3350 RegisterClass RC, ValueType OpVT,
3351 X86MemOperand x86memop, Operand memop,
3353 let isCommutable = 1 in
3354 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3355 (ins RC:$src1, RC:$src2, RC:$src3),
3356 !strconcat(OpcodeStr,
3357 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3359 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3361 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3362 (ins RC:$src1, RC:$src2, f128mem:$src3),
3363 !strconcat(OpcodeStr,
3364 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3366 (OpVT (OpNode RC:$src2, RC:$src1,
3367 (mem_frag addr:$src3))))]>;
3370 } // Constraints = "$src1 = $dst"
3372 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3373 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3374 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3375 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3376 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3377 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3378 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3379 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3380 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3381 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3382 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3383 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3384 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3385 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3386 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3387 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3389 //===----------------------------------------------------------------------===//
3390 // AVX-512 Scalar convert from sign integer to float/double
3391 //===----------------------------------------------------------------------===//
3393 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3394 X86MemOperand x86memop, string asm> {
3395 let hasSideEffects = 0 in {
3396 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3397 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3400 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3401 (ins DstRC:$src1, x86memop:$src),
3402 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3404 } // hasSideEffects = 0
3406 let Predicates = [HasAVX512] in {
3407 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3408 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3409 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3410 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3411 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3412 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3413 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3414 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3416 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3417 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3418 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3419 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3420 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3421 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3422 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3423 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3425 def : Pat<(f32 (sint_to_fp GR32:$src)),
3426 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3427 def : Pat<(f32 (sint_to_fp GR64:$src)),
3428 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3429 def : Pat<(f64 (sint_to_fp GR32:$src)),
3430 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3431 def : Pat<(f64 (sint_to_fp GR64:$src)),
3432 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3434 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3435 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3436 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3437 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3438 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3439 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3440 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3441 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3443 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3444 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3445 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3446 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3447 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3448 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3449 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3450 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3452 def : Pat<(f32 (uint_to_fp GR32:$src)),
3453 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3454 def : Pat<(f32 (uint_to_fp GR64:$src)),
3455 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3456 def : Pat<(f64 (uint_to_fp GR32:$src)),
3457 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3458 def : Pat<(f64 (uint_to_fp GR64:$src)),
3459 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3462 //===----------------------------------------------------------------------===//
3463 // AVX-512 Scalar convert from float/double to integer
3464 //===----------------------------------------------------------------------===//
3465 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3466 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3468 let hasSideEffects = 0 in {
3469 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3470 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3471 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3472 Requires<[HasAVX512]>;
3474 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3475 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3476 Requires<[HasAVX512]>;
3477 } // hasSideEffects = 0
3479 let Predicates = [HasAVX512] in {
3480 // Convert float/double to signed/unsigned int 32/64
3481 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3482 ssmem, sse_load_f32, "cvtss2si">,
3483 XS, EVEX_CD8<32, CD8VT1>;
3484 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3485 ssmem, sse_load_f32, "cvtss2si">,
3486 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3487 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3488 ssmem, sse_load_f32, "cvtss2usi">,
3489 XS, EVEX_CD8<32, CD8VT1>;
3490 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3491 int_x86_avx512_cvtss2usi64, ssmem,
3492 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3493 EVEX_CD8<32, CD8VT1>;
3494 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3495 sdmem, sse_load_f64, "cvtsd2si">,
3496 XD, EVEX_CD8<64, CD8VT1>;
3497 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3498 sdmem, sse_load_f64, "cvtsd2si">,
3499 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3500 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3501 sdmem, sse_load_f64, "cvtsd2usi">,
3502 XD, EVEX_CD8<64, CD8VT1>;
3503 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3504 int_x86_avx512_cvtsd2usi64, sdmem,
3505 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3506 EVEX_CD8<64, CD8VT1>;
3508 let isCodeGenOnly = 1 in {
3509 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3510 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3511 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3512 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3513 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3514 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3515 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3516 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3517 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3518 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3519 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3520 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3522 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3523 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3524 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3525 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3526 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3527 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3528 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3529 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3530 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3531 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3532 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3533 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3534 } // isCodeGenOnly = 1
3536 // Convert float/double to signed/unsigned int 32/64 with truncation
3537 let isCodeGenOnly = 1 in {
3538 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3539 ssmem, sse_load_f32, "cvttss2si">,
3540 XS, EVEX_CD8<32, CD8VT1>;
3541 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3542 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3543 "cvttss2si">, XS, VEX_W,
3544 EVEX_CD8<32, CD8VT1>;
3545 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3546 sdmem, sse_load_f64, "cvttsd2si">, XD,
3547 EVEX_CD8<64, CD8VT1>;
3548 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3549 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3550 "cvttsd2si">, XD, VEX_W,
3551 EVEX_CD8<64, CD8VT1>;
3552 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3553 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3554 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3555 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3556 int_x86_avx512_cvttss2usi64, ssmem,
3557 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3558 EVEX_CD8<32, CD8VT1>;
3559 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3560 int_x86_avx512_cvttsd2usi,
3561 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3562 EVEX_CD8<64, CD8VT1>;
3563 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3564 int_x86_avx512_cvttsd2usi64, sdmem,
3565 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3566 EVEX_CD8<64, CD8VT1>;
3567 } // isCodeGenOnly = 1
3569 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3570 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3572 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3573 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3574 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3575 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3576 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3577 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3580 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3581 loadf32, "cvttss2si">, XS,
3582 EVEX_CD8<32, CD8VT1>;
3583 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3584 loadf32, "cvttss2usi">, XS,
3585 EVEX_CD8<32, CD8VT1>;
3586 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3587 loadf32, "cvttss2si">, XS, VEX_W,
3588 EVEX_CD8<32, CD8VT1>;
3589 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3590 loadf32, "cvttss2usi">, XS, VEX_W,
3591 EVEX_CD8<32, CD8VT1>;
3592 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3593 loadf64, "cvttsd2si">, XD,
3594 EVEX_CD8<64, CD8VT1>;
3595 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3596 loadf64, "cvttsd2usi">, XD,
3597 EVEX_CD8<64, CD8VT1>;
3598 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3599 loadf64, "cvttsd2si">, XD, VEX_W,
3600 EVEX_CD8<64, CD8VT1>;
3601 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3602 loadf64, "cvttsd2usi">, XD, VEX_W,
3603 EVEX_CD8<64, CD8VT1>;
3605 //===----------------------------------------------------------------------===//
3606 // AVX-512 Convert form float to double and back
3607 //===----------------------------------------------------------------------===//
3608 let hasSideEffects = 0 in {
3609 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3610 (ins FR32X:$src1, FR32X:$src2),
3611 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3612 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3614 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3615 (ins FR32X:$src1, f32mem:$src2),
3616 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3617 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3618 EVEX_CD8<32, CD8VT1>;
3620 // Convert scalar double to scalar single
3621 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3622 (ins FR64X:$src1, FR64X:$src2),
3623 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3624 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3626 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3627 (ins FR64X:$src1, f64mem:$src2),
3628 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3629 []>, EVEX_4V, VEX_LIG, VEX_W,
3630 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3633 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3634 Requires<[HasAVX512]>;
3635 def : Pat<(fextend (loadf32 addr:$src)),
3636 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3638 def : Pat<(extloadf32 addr:$src),
3639 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3640 Requires<[HasAVX512, OptForSize]>;
3642 def : Pat<(extloadf32 addr:$src),
3643 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3644 Requires<[HasAVX512, OptForSpeed]>;
3646 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3647 Requires<[HasAVX512]>;
3649 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3650 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3651 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3653 let hasSideEffects = 0 in {
3654 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3655 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3657 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3658 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3659 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3660 [], d>, EVEX, EVEX_B, EVEX_RC;
3662 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3663 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3665 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3666 } // hasSideEffects = 0
3669 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3670 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3671 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3673 let hasSideEffects = 0 in {
3674 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3675 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3677 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3679 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3680 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3682 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3683 } // hasSideEffects = 0
3686 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3687 memopv8f64, f512mem, v8f32, v8f64,
3688 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3689 EVEX_CD8<64, CD8VF>;
3691 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3692 memopv4f64, f256mem, v8f64, v8f32,
3693 SSEPackedDouble>, EVEX_V512, PS,
3694 EVEX_CD8<32, CD8VH>;
3695 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3696 (VCVTPS2PDZrm addr:$src)>;
3698 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3699 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3700 (VCVTPD2PSZrr VR512:$src)>;
3702 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3703 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3704 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3706 //===----------------------------------------------------------------------===//
3707 // AVX-512 Vector convert from sign integer to float/double
3708 //===----------------------------------------------------------------------===//
3710 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3711 memopv8i64, i512mem, v16f32, v16i32,
3712 SSEPackedSingle>, EVEX_V512, PS,
3713 EVEX_CD8<32, CD8VF>;
3715 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3716 memopv4i64, i256mem, v8f64, v8i32,
3717 SSEPackedDouble>, EVEX_V512, XS,
3718 EVEX_CD8<32, CD8VH>;
3720 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3721 memopv16f32, f512mem, v16i32, v16f32,
3722 SSEPackedSingle>, EVEX_V512, XS,
3723 EVEX_CD8<32, CD8VF>;
3725 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3726 memopv8f64, f512mem, v8i32, v8f64,
3727 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3728 EVEX_CD8<64, CD8VF>;
3730 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3731 memopv16f32, f512mem, v16i32, v16f32,
3732 SSEPackedSingle>, EVEX_V512, PS,
3733 EVEX_CD8<32, CD8VF>;
3735 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3736 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3737 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3738 (VCVTTPS2UDQZrr VR512:$src)>;
3740 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3741 memopv8f64, f512mem, v8i32, v8f64,
3742 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3743 EVEX_CD8<64, CD8VF>;
3745 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3746 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3747 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3748 (VCVTTPD2UDQZrr VR512:$src)>;
3750 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3751 memopv4i64, f256mem, v8f64, v8i32,
3752 SSEPackedDouble>, EVEX_V512, XS,
3753 EVEX_CD8<32, CD8VH>;
3755 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3756 memopv16i32, f512mem, v16f32, v16i32,
3757 SSEPackedSingle>, EVEX_V512, XD,
3758 EVEX_CD8<32, CD8VF>;
3760 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3761 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3762 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3764 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3765 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3766 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3768 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3769 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3772 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3773 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3774 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3776 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3777 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3778 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3780 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3781 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3782 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3783 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3784 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3785 (VCVTDQ2PDZrr VR256X:$src)>;
3786 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3787 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3788 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3789 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3790 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3791 (VCVTUDQ2PDZrr VR256X:$src)>;
3793 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3794 RegisterClass DstRC, PatFrag mem_frag,
3795 X86MemOperand x86memop, Domain d> {
3796 let hasSideEffects = 0 in {
3797 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3798 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3800 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3801 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3802 [], d>, EVEX, EVEX_B, EVEX_RC;
3804 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3805 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3807 } // hasSideEffects = 0
3810 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3811 memopv16f32, f512mem, SSEPackedSingle>, PD,
3812 EVEX_V512, EVEX_CD8<32, CD8VF>;
3813 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3814 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3815 EVEX_V512, EVEX_CD8<64, CD8VF>;
3817 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3818 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3819 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3821 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3822 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3823 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3825 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3826 memopv16f32, f512mem, SSEPackedSingle>,
3827 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3828 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3829 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3830 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3832 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3833 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3834 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3836 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3837 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3838 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3840 let Predicates = [HasAVX512] in {
3841 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3842 (VCVTPD2PSZrm addr:$src)>;
3843 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3844 (VCVTPS2PDZrm addr:$src)>;
3847 //===----------------------------------------------------------------------===//
3848 // Half precision conversion instructions
3849 //===----------------------------------------------------------------------===//
3850 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3851 X86MemOperand x86memop> {
3852 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3853 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3855 let hasSideEffects = 0, mayLoad = 1 in
3856 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3857 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3860 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3861 X86MemOperand x86memop> {
3862 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3863 (ins srcRC:$src1, i32i8imm:$src2),
3864 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3866 let hasSideEffects = 0, mayStore = 1 in
3867 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3868 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3869 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3872 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3873 EVEX_CD8<32, CD8VH>;
3874 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3875 EVEX_CD8<32, CD8VH>;
3877 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3878 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3879 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3881 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3882 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3883 (VCVTPH2PSZrr VR256X:$src)>;
3885 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3886 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3887 "ucomiss">, PS, EVEX, VEX_LIG,
3888 EVEX_CD8<32, CD8VT1>;
3889 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3890 "ucomisd">, PD, EVEX,
3891 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3892 let Pattern = []<dag> in {
3893 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3894 "comiss">, PS, EVEX, VEX_LIG,
3895 EVEX_CD8<32, CD8VT1>;
3896 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3897 "comisd">, PD, EVEX,
3898 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3900 let isCodeGenOnly = 1 in {
3901 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3902 load, "ucomiss">, PS, EVEX, VEX_LIG,
3903 EVEX_CD8<32, CD8VT1>;
3904 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3905 load, "ucomisd">, PD, EVEX,
3906 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3908 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3909 load, "comiss">, PS, EVEX, VEX_LIG,
3910 EVEX_CD8<32, CD8VT1>;
3911 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3912 load, "comisd">, PD, EVEX,
3913 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3917 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3918 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3919 X86MemOperand x86memop> {
3920 let hasSideEffects = 0 in {
3921 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3922 (ins RC:$src1, RC:$src2),
3923 !strconcat(OpcodeStr,
3924 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3925 let mayLoad = 1 in {
3926 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3927 (ins RC:$src1, x86memop:$src2),
3928 !strconcat(OpcodeStr,
3929 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3934 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3935 EVEX_CD8<32, CD8VT1>;
3936 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3937 VEX_W, EVEX_CD8<64, CD8VT1>;
3938 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3939 EVEX_CD8<32, CD8VT1>;
3940 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3941 VEX_W, EVEX_CD8<64, CD8VT1>;
3943 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3944 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3945 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3946 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3948 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3949 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3950 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3951 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3953 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3954 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3955 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3956 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3958 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3959 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3960 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3961 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3963 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3964 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3965 RegisterClass RC, X86MemOperand x86memop,
3966 PatFrag mem_frag, ValueType OpVt> {
3967 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3968 !strconcat(OpcodeStr,
3969 " \t{$src, $dst|$dst, $src}"),
3970 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3972 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3973 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3974 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3977 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3978 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3979 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3980 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3981 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3982 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3983 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3984 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3986 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3987 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3988 (VRSQRT14PSZr VR512:$src)>;
3989 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3990 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3991 (VRSQRT14PDZr VR512:$src)>;
3993 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3994 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3995 (VRCP14PSZr VR512:$src)>;
3996 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3997 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3998 (VRCP14PDZr VR512:$src)>;
4000 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4001 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4002 X86MemOperand x86memop> {
4003 let hasSideEffects = 0, Predicates = [HasERI] in {
4004 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4005 (ins RC:$src1, RC:$src2),
4006 !strconcat(OpcodeStr,
4007 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4008 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4009 (ins RC:$src1, RC:$src2),
4010 !strconcat(OpcodeStr,
4011 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4012 []>, EVEX_4V, EVEX_B;
4013 let mayLoad = 1 in {
4014 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4015 (ins RC:$src1, x86memop:$src2),
4016 !strconcat(OpcodeStr,
4017 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4022 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4023 EVEX_CD8<32, CD8VT1>;
4024 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4025 VEX_W, EVEX_CD8<64, CD8VT1>;
4026 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4027 EVEX_CD8<32, CD8VT1>;
4028 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4029 VEX_W, EVEX_CD8<64, CD8VT1>;
4031 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4032 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4034 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4035 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4037 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4038 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4040 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4041 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4043 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4044 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4046 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4047 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4049 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4050 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4052 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4053 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4055 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4056 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4057 RegisterClass RC, X86MemOperand x86memop> {
4058 let hasSideEffects = 0, Predicates = [HasERI] in {
4059 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4060 !strconcat(OpcodeStr,
4061 " \t{$src, $dst|$dst, $src}"),
4063 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4064 !strconcat(OpcodeStr,
4065 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4067 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4068 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4072 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4073 EVEX_V512, EVEX_CD8<32, CD8VF>;
4074 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4075 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4076 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4077 EVEX_V512, EVEX_CD8<32, CD8VF>;
4078 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4079 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4081 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4082 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4083 (VRSQRT28PSZrb VR512:$src)>;
4084 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4085 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4086 (VRSQRT28PDZrb VR512:$src)>;
4088 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4089 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4090 (VRCP28PSZrb VR512:$src)>;
4091 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4092 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4093 (VRCP28PDZrb VR512:$src)>;
4095 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4096 OpndItins itins_s, OpndItins itins_d> {
4097 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4098 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4099 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4103 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4104 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4106 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4107 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4109 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4110 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4111 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4115 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4116 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4117 [(set VR512:$dst, (OpNode
4118 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4119 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4123 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4124 Intrinsic F32Int, Intrinsic F64Int,
4125 OpndItins itins_s, OpndItins itins_d> {
4126 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4127 (ins FR32X:$src1, FR32X:$src2),
4128 !strconcat(OpcodeStr,
4129 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4130 [], itins_s.rr>, XS, EVEX_4V;
4131 let isCodeGenOnly = 1 in
4132 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4133 (ins VR128X:$src1, VR128X:$src2),
4134 !strconcat(OpcodeStr,
4135 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4137 (F32Int VR128X:$src1, VR128X:$src2))],
4138 itins_s.rr>, XS, EVEX_4V;
4139 let mayLoad = 1 in {
4140 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4141 (ins FR32X:$src1, f32mem:$src2),
4142 !strconcat(OpcodeStr,
4143 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4144 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4145 let isCodeGenOnly = 1 in
4146 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4147 (ins VR128X:$src1, ssmem:$src2),
4148 !strconcat(OpcodeStr,
4149 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4151 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4152 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4154 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4155 (ins FR64X:$src1, FR64X:$src2),
4156 !strconcat(OpcodeStr,
4157 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4159 let isCodeGenOnly = 1 in
4160 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4161 (ins VR128X:$src1, VR128X:$src2),
4162 !strconcat(OpcodeStr,
4163 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4165 (F64Int VR128X:$src1, VR128X:$src2))],
4166 itins_s.rr>, XD, EVEX_4V, VEX_W;
4167 let mayLoad = 1 in {
4168 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4169 (ins FR64X:$src1, f64mem:$src2),
4170 !strconcat(OpcodeStr,
4171 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4172 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4173 let isCodeGenOnly = 1 in
4174 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4175 (ins VR128X:$src1, sdmem:$src2),
4176 !strconcat(OpcodeStr,
4177 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4179 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4180 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4185 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4186 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4187 SSE_SQRTSS, SSE_SQRTSD>,
4188 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
4189 SSE_SQRTPS, SSE_SQRTPD>;
4191 let Predicates = [HasAVX512] in {
4192 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4193 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4194 (VSQRTPSZrr VR512:$src1)>;
4195 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4196 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4197 (VSQRTPDZrr VR512:$src1)>;
4199 def : Pat<(f32 (fsqrt FR32X:$src)),
4200 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4201 def : Pat<(f32 (fsqrt (load addr:$src))),
4202 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4203 Requires<[OptForSize]>;
4204 def : Pat<(f64 (fsqrt FR64X:$src)),
4205 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4206 def : Pat<(f64 (fsqrt (load addr:$src))),
4207 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4208 Requires<[OptForSize]>;
4210 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4211 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4212 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4213 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4214 Requires<[OptForSize]>;
4216 def : Pat<(f32 (X86frcp FR32X:$src)),
4217 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4218 def : Pat<(f32 (X86frcp (load addr:$src))),
4219 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4220 Requires<[OptForSize]>;
4222 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4223 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4224 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4226 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4227 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4229 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4230 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4231 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4233 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4234 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4238 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4239 X86MemOperand x86memop, RegisterClass RC,
4240 PatFrag mem_frag32, PatFrag mem_frag64,
4241 Intrinsic V4F32Int, Intrinsic V2F64Int,
4243 let ExeDomain = SSEPackedSingle in {
4244 // Intrinsic operation, reg.
4245 // Vector intrinsic operation, reg
4246 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4247 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4248 !strconcat(OpcodeStr,
4249 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4250 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4252 // Vector intrinsic operation, mem
4253 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4254 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4255 !strconcat(OpcodeStr,
4256 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4258 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4259 EVEX_CD8<32, VForm>;
4260 } // ExeDomain = SSEPackedSingle
4262 let ExeDomain = SSEPackedDouble in {
4263 // Vector intrinsic operation, reg
4264 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4265 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4266 !strconcat(OpcodeStr,
4267 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4268 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4270 // Vector intrinsic operation, mem
4271 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4272 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4273 !strconcat(OpcodeStr,
4274 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4276 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4277 EVEX_CD8<64, VForm>;
4278 } // ExeDomain = SSEPackedDouble
4281 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4285 let ExeDomain = GenericDomain in {
4287 let hasSideEffects = 0 in
4288 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4289 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4290 !strconcat(OpcodeStr,
4291 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4294 // Intrinsic operation, reg.
4295 let isCodeGenOnly = 1 in
4296 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4297 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4298 !strconcat(OpcodeStr,
4299 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4300 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4302 // Intrinsic operation, mem.
4303 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4304 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4305 !strconcat(OpcodeStr,
4306 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4307 [(set VR128X:$dst, (F32Int VR128X:$src1,
4308 sse_load_f32:$src2, imm:$src3))]>,
4309 EVEX_CD8<32, CD8VT1>;
4312 let hasSideEffects = 0 in
4313 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4314 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4315 !strconcat(OpcodeStr,
4316 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4319 // Intrinsic operation, reg.
4320 let isCodeGenOnly = 1 in
4321 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4322 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4323 !strconcat(OpcodeStr,
4324 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4325 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4328 // Intrinsic operation, mem.
4329 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4330 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4331 !strconcat(OpcodeStr,
4332 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4334 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4335 VEX_W, EVEX_CD8<64, CD8VT1>;
4336 } // ExeDomain = GenericDomain
4339 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4340 X86MemOperand x86memop, RegisterClass RC,
4341 PatFrag mem_frag, Domain d> {
4342 let ExeDomain = d in {
4343 // Intrinsic operation, reg.
4344 // Vector intrinsic operation, reg
4345 def r : AVX512AIi8<opc, MRMSrcReg,
4346 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4347 !strconcat(OpcodeStr,
4348 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4351 // Vector intrinsic operation, mem
4352 def m : AVX512AIi8<opc, MRMSrcMem,
4353 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4354 !strconcat(OpcodeStr,
4355 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4361 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4362 memopv16f32, SSEPackedSingle>, EVEX_V512,
4363 EVEX_CD8<32, CD8VF>;
4365 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4366 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4368 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4371 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4372 memopv8f64, SSEPackedDouble>, EVEX_V512,
4373 VEX_W, EVEX_CD8<64, CD8VF>;
4375 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4376 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4378 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4380 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4381 Operand x86memop, RegisterClass RC, Domain d> {
4382 let ExeDomain = d in {
4383 def r : AVX512AIi8<opc, MRMSrcReg,
4384 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4385 !strconcat(OpcodeStr,
4386 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4389 def m : AVX512AIi8<opc, MRMSrcMem,
4390 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4391 !strconcat(OpcodeStr,
4392 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4397 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4398 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4400 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4401 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4403 def : Pat<(ffloor FR32X:$src),
4404 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4405 def : Pat<(f64 (ffloor FR64X:$src)),
4406 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4407 def : Pat<(f32 (fnearbyint FR32X:$src)),
4408 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4409 def : Pat<(f64 (fnearbyint FR64X:$src)),
4410 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4411 def : Pat<(f32 (fceil FR32X:$src)),
4412 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4413 def : Pat<(f64 (fceil FR64X:$src)),
4414 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4415 def : Pat<(f32 (frint FR32X:$src)),
4416 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4417 def : Pat<(f64 (frint FR64X:$src)),
4418 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4419 def : Pat<(f32 (ftrunc FR32X:$src)),
4420 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4421 def : Pat<(f64 (ftrunc FR64X:$src)),
4422 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4424 def : Pat<(v16f32 (ffloor VR512:$src)),
4425 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4426 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4427 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4428 def : Pat<(v16f32 (fceil VR512:$src)),
4429 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4430 def : Pat<(v16f32 (frint VR512:$src)),
4431 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4432 def : Pat<(v16f32 (ftrunc VR512:$src)),
4433 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4435 def : Pat<(v8f64 (ffloor VR512:$src)),
4436 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4437 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4438 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4439 def : Pat<(v8f64 (fceil VR512:$src)),
4440 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4441 def : Pat<(v8f64 (frint VR512:$src)),
4442 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4443 def : Pat<(v8f64 (ftrunc VR512:$src)),
4444 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4446 //-------------------------------------------------
4447 // Integer truncate and extend operations
4448 //-------------------------------------------------
4450 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4451 RegisterClass dstRC, RegisterClass srcRC,
4452 RegisterClass KRC, X86MemOperand x86memop> {
4453 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4455 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4458 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4459 (ins KRC:$mask, srcRC:$src),
4460 !strconcat(OpcodeStr,
4461 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4464 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4465 (ins KRC:$mask, srcRC:$src),
4466 !strconcat(OpcodeStr,
4467 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4470 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4471 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4474 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4475 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4476 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4480 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4481 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4482 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4483 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4484 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4485 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4486 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4487 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4488 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4489 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4490 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4491 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4492 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4493 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4494 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4495 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4496 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4497 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4498 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4499 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4500 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4501 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4502 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4503 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4504 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4505 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4506 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4507 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4508 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4509 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4511 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4512 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4513 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4514 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4515 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4517 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4518 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4519 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4520 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4521 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4522 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4523 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4524 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4527 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4528 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4529 PatFrag mem_frag, X86MemOperand x86memop,
4530 ValueType OpVT, ValueType InVT> {
4532 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4534 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4535 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4537 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4538 (ins KRC:$mask, SrcRC:$src),
4539 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4542 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4543 (ins KRC:$mask, SrcRC:$src),
4544 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4547 let mayLoad = 1 in {
4548 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4549 (ins x86memop:$src),
4550 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4552 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4555 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4556 (ins KRC:$mask, x86memop:$src),
4557 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4561 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4562 (ins KRC:$mask, x86memop:$src),
4563 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4569 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4570 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4572 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4573 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4575 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4576 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4577 EVEX_CD8<16, CD8VH>;
4578 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4579 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4580 EVEX_CD8<16, CD8VQ>;
4581 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4582 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4583 EVEX_CD8<32, CD8VH>;
4585 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4586 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4588 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4589 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4591 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4592 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4593 EVEX_CD8<16, CD8VH>;
4594 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4595 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4596 EVEX_CD8<16, CD8VQ>;
4597 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4598 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4599 EVEX_CD8<32, CD8VH>;
4601 //===----------------------------------------------------------------------===//
4602 // GATHER - SCATTER Operations
4604 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4605 RegisterClass RC, X86MemOperand memop> {
4607 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4608 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4609 (ins RC:$src1, KRC:$mask, memop:$src2),
4610 !strconcat(OpcodeStr,
4611 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4615 let ExeDomain = SSEPackedDouble in {
4616 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4617 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4618 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4619 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4622 let ExeDomain = SSEPackedSingle in {
4623 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4624 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4625 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4626 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4629 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4630 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4631 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4632 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4634 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4635 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4636 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4637 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4639 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4640 RegisterClass RC, X86MemOperand memop> {
4641 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4642 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4643 (ins memop:$dst, KRC:$mask, RC:$src2),
4644 !strconcat(OpcodeStr,
4645 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4649 let ExeDomain = SSEPackedDouble in {
4650 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4651 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4652 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4653 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4656 let ExeDomain = SSEPackedSingle in {
4657 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4658 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4659 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4660 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4663 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4664 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4665 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4666 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4668 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4669 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4670 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4671 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4674 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4675 RegisterClass KRC, X86MemOperand memop> {
4676 let Predicates = [HasPFI], hasSideEffects = 1 in
4677 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4678 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4682 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4683 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4685 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4686 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4688 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4689 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4691 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4692 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4694 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4695 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4697 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4698 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4700 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4701 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4703 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4704 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4706 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4707 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4709 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4710 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4712 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4713 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4715 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4716 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4718 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4719 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4721 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4722 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4724 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4725 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4727 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4728 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4729 //===----------------------------------------------------------------------===//
4730 // VSHUFPS - VSHUFPD Operations
4732 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4733 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4735 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4736 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4737 !strconcat(OpcodeStr,
4738 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4739 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4740 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4741 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4742 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4743 (ins RC:$src1, RC:$src2, i8imm:$src3),
4744 !strconcat(OpcodeStr,
4745 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4746 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4747 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4748 EVEX_4V, Sched<[WriteShuffle]>;
4751 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4752 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4753 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4754 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4756 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4757 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4758 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4759 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4760 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4762 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4763 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4764 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4765 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4766 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4768 multiclass avx512_valign<X86VectorVTInfo _> {
4769 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4770 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4772 "$src3, $src2, $src1", "$src1, $src2, $src3",
4773 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4775 AVX512AIi8Base, EVEX_4V;
4777 // Also match valign of packed floats.
4778 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4779 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4782 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4783 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4784 !strconcat("valign"##_.Suffix,
4785 " \t{$src3, $src2, $src1, $dst|"
4786 "$dst, $src1, $src2, $src3}"),
4789 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4790 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4792 // Helper fragments to match sext vXi1 to vXiY.
4793 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4794 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4796 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4797 RegisterClass KRC, RegisterClass RC,
4798 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4800 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4801 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4803 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4804 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4806 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4807 !strconcat(OpcodeStr,
4808 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4810 let mayLoad = 1 in {
4811 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4812 (ins x86memop:$src),
4813 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4815 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4816 (ins KRC:$mask, x86memop:$src),
4817 !strconcat(OpcodeStr,
4818 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4820 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4821 (ins KRC:$mask, x86memop:$src),
4822 !strconcat(OpcodeStr,
4823 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4825 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4826 (ins x86scalar_mop:$src),
4827 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4828 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4830 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4831 (ins KRC:$mask, x86scalar_mop:$src),
4832 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4833 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4834 []>, EVEX, EVEX_B, EVEX_K;
4835 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4836 (ins KRC:$mask, x86scalar_mop:$src),
4837 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4838 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4840 []>, EVEX, EVEX_B, EVEX_KZ;
4844 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4845 i512mem, i32mem, "{1to16}">, EVEX_V512,
4846 EVEX_CD8<32, CD8VF>;
4847 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4848 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4849 EVEX_CD8<64, CD8VF>;
4852 (bc_v16i32 (v16i1sextv16i32)),
4853 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4854 (VPABSDZrr VR512:$src)>;
4856 (bc_v8i64 (v8i1sextv8i64)),
4857 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4858 (VPABSQZrr VR512:$src)>;
4860 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4861 (v16i32 immAllZerosV), (i16 -1))),
4862 (VPABSDZrr VR512:$src)>;
4863 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4864 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4865 (VPABSQZrr VR512:$src)>;
4867 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4868 RegisterClass RC, RegisterClass KRC,
4869 X86MemOperand x86memop,
4870 X86MemOperand x86scalar_mop, string BrdcstStr> {
4871 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4873 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4875 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4876 (ins x86memop:$src),
4877 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4879 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4880 (ins x86scalar_mop:$src),
4881 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4882 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4884 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4885 (ins KRC:$mask, RC:$src),
4886 !strconcat(OpcodeStr,
4887 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4889 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4890 (ins KRC:$mask, x86memop:$src),
4891 !strconcat(OpcodeStr,
4892 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4894 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4895 (ins KRC:$mask, x86scalar_mop:$src),
4896 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4897 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4899 []>, EVEX, EVEX_KZ, EVEX_B;
4901 let Constraints = "$src1 = $dst" in {
4902 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4903 (ins RC:$src1, KRC:$mask, RC:$src2),
4904 !strconcat(OpcodeStr,
4905 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4907 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4908 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4909 !strconcat(OpcodeStr,
4910 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4912 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4913 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4914 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4915 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4916 []>, EVEX, EVEX_K, EVEX_B;
4920 let Predicates = [HasCDI] in {
4921 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4922 i512mem, i32mem, "{1to16}">,
4923 EVEX_V512, EVEX_CD8<32, CD8VF>;
4926 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4927 i512mem, i64mem, "{1to8}">,
4928 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4932 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4934 (VPCONFLICTDrrk VR512:$src1,
4935 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4937 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4939 (VPCONFLICTQrrk VR512:$src1,
4940 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4942 let Predicates = [HasCDI] in {
4943 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4944 i512mem, i32mem, "{1to16}">,
4945 EVEX_V512, EVEX_CD8<32, CD8VF>;
4948 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4949 i512mem, i64mem, "{1to8}">,
4950 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4954 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4956 (VPLZCNTDrrk VR512:$src1,
4957 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4959 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4961 (VPLZCNTQrrk VR512:$src1,
4962 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4964 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4965 (VPLZCNTDrm addr:$src)>;
4966 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4967 (VPLZCNTDrr VR512:$src)>;
4968 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4969 (VPLZCNTQrm addr:$src)>;
4970 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4971 (VPLZCNTQrr VR512:$src)>;
4973 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4974 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4975 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4977 def : Pat<(store VK1:$src, addr:$dst),
4978 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4980 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4981 (truncstore node:$val, node:$ptr), [{
4982 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4985 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4986 (MOV8mr addr:$dst, GR8:$src)>;
4988 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
4989 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
4990 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
4991 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
4994 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
4995 string OpcodeStr, Predicate prd> {
4996 let Predicates = [prd] in
4997 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
4999 let Predicates = [prd, HasVLX] in {
5000 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5001 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5005 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5006 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5008 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5010 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5012 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5016 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;