1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
277 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
278 dag Outs, dag NonTiedIns, string OpcodeStr,
279 string AttSrcAsm, string IntelSrcAsm,
281 AVX512_maskable_common<O, F, _, Outs,
282 !con((ins _.RC:$src1), NonTiedIns),
283 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
284 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
285 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
286 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
288 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
291 string AttSrcAsm, string IntelSrcAsm,
293 AVX512_maskable_custom<O, F, Outs, Ins,
294 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
295 !con((ins _.KRCWM:$mask), Ins),
296 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
300 // Instruction with mask that puts result in mask register,
301 // like "compare" and "vptest"
302 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
304 dag Ins, dag MaskingIns,
306 string AttSrcAsm, string IntelSrcAsm,
308 list<dag> MaskingPattern,
310 InstrItinClass itin = NoItinerary> {
311 def NAME: AVX512<O, F, Outs, Ins,
312 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
313 "$dst "#Round#", "#IntelSrcAsm#"}",
316 def NAME#k: AVX512<O, F, Outs, MaskingIns,
317 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
318 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
319 MaskingPattern, itin>, EVEX_K;
322 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
324 dag Ins, dag MaskingIns,
326 string AttSrcAsm, string IntelSrcAsm,
327 dag RHS, dag MaskingRHS,
329 InstrItinClass itin = NoItinerary> :
330 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
331 AttSrcAsm, IntelSrcAsm,
332 [(set _.KRC:$dst, RHS)],
333 [(set _.KRC:$dst, MaskingRHS)],
336 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
337 dag Outs, dag Ins, string OpcodeStr,
338 string AttSrcAsm, string IntelSrcAsm,
339 dag RHS, string Round = "",
340 InstrItinClass itin = NoItinerary> :
341 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
342 !con((ins _.KRCWM:$mask), Ins),
343 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
344 (and _.KRCWM:$mask, RHS),
347 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
348 dag Outs, dag Ins, string OpcodeStr,
349 string AttSrcAsm, string IntelSrcAsm> :
350 AVX512_maskable_custom_cmp<O, F, Outs,
351 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
352 AttSrcAsm, IntelSrcAsm,
353 [],[],"", NoItinerary>;
355 // Bitcasts between 512-bit vector types. Return the original type since
356 // no instruction is needed for the conversion
357 let Predicates = [HasAVX512] in {
358 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
359 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
360 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
364 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
369 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
374 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
379 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
385 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
391 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
392 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
396 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
401 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
406 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
411 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
416 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
421 // Bitcasts between 256-bit vector types. Return the original type since
422 // no instruction is needed for the conversion
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
456 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
459 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
460 isPseudo = 1, Predicates = [HasAVX512] in {
461 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
462 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
465 let Predicates = [HasAVX512] in {
466 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
467 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
468 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
471 //===----------------------------------------------------------------------===//
472 // AVX-512 - VECTOR INSERT
475 multiclass vinsert_for_size_no_alt<int Opcode,
476 X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert,
478 SDNodeXForm INSERT_get_vinsert_imm> {
479 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
480 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
481 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
482 "vinsert" # From.EltTypeName # "x" # From.NumElts #
483 "\t{$src3, $src2, $src1, $dst|"
484 "$dst, $src1, $src2, $src3}",
485 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
486 (From.VT From.RC:$src2),
491 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
492 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
493 "vinsert" # From.EltTypeName # "x" # From.NumElts #
494 "\t{$src3, $src2, $src1, $dst|"
495 "$dst, $src1, $src2, $src3}",
497 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
501 multiclass vinsert_for_size<int Opcode,
502 X86VectorVTInfo From, X86VectorVTInfo To,
503 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
504 PatFrag vinsert_insert,
505 SDNodeXForm INSERT_get_vinsert_imm> :
506 vinsert_for_size_no_alt<Opcode, From, To,
507 vinsert_insert, INSERT_get_vinsert_imm> {
508 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
509 // vinserti32x4. Only add this if 64x2 and friends are not supported
510 // natively via AVX512DQ.
511 let Predicates = [NoDQI] in
512 def : Pat<(vinsert_insert:$ins
513 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
514 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
515 VR512:$src1, From.RC:$src2,
516 (INSERT_get_vinsert_imm VR512:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
521 defm NAME # "32x4" : vinsert_for_size<Opcode128,
522 X86VectorVTInfo< 4, EltVT32, VR128X>,
523 X86VectorVTInfo<16, EltVT32, VR512>,
524 X86VectorVTInfo< 2, EltVT64, VR128X>,
525 X86VectorVTInfo< 8, EltVT64, VR512>,
527 INSERT_get_vinsert128_imm>;
528 let Predicates = [HasDQI] in
529 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
530 X86VectorVTInfo< 2, EltVT64, VR128X>,
531 X86VectorVTInfo< 8, EltVT64, VR512>,
533 INSERT_get_vinsert128_imm>, VEX_W;
534 defm NAME # "64x4" : vinsert_for_size<Opcode256,
535 X86VectorVTInfo< 4, EltVT64, VR256X>,
536 X86VectorVTInfo< 8, EltVT64, VR512>,
537 X86VectorVTInfo< 8, EltVT32, VR256>,
538 X86VectorVTInfo<16, EltVT32, VR512>,
540 INSERT_get_vinsert256_imm>, VEX_W;
541 let Predicates = [HasDQI] in
542 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
543 X86VectorVTInfo< 8, EltVT32, VR256X>,
544 X86VectorVTInfo<16, EltVT32, VR512>,
546 INSERT_get_vinsert256_imm>;
549 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
550 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
552 // vinsertps - insert f32 to XMM
553 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
554 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
555 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
556 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
558 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
559 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
560 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
561 [(set VR128X:$dst, (X86insertps VR128X:$src1,
562 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
563 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
565 //===----------------------------------------------------------------------===//
566 // AVX-512 VECTOR EXTRACT
569 multiclass vextract_for_size<int Opcode,
570 X86VectorVTInfo From, X86VectorVTInfo To,
571 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
572 PatFrag vextract_extract,
573 SDNodeXForm EXTRACT_get_vextract_imm> {
574 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
575 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
576 (ins VR512:$src1, u8imm:$idx),
577 "vextract" # To.EltTypeName # "x4",
578 "$idx, $src1", "$src1, $idx",
579 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
581 AVX512AIi8Base, EVEX, EVEX_V512;
583 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
584 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
585 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
586 "$dst, $src1, $src2}",
587 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
590 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
592 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
593 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
595 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
597 // A 128/256-bit subvector extract from the first 512-bit vector position is
598 // a subregister copy that needs no instruction.
599 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
601 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
603 // And for the alternative types.
604 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
606 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
608 // Intrinsic call with masking.
609 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
611 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
612 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
613 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
614 VR512:$src1, imm:$idx)>;
616 // Intrinsic call with zero-masking.
617 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
619 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
620 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
621 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
622 VR512:$src1, imm:$idx)>;
624 // Intrinsic call without masking.
625 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
627 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
628 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
629 VR512:$src1, imm:$idx)>;
632 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
633 ValueType EltVT64, int Opcode64> {
634 defm NAME # "32x4" : vextract_for_size<Opcode32,
635 X86VectorVTInfo<16, EltVT32, VR512>,
636 X86VectorVTInfo< 4, EltVT32, VR128X>,
637 X86VectorVTInfo< 8, EltVT64, VR512>,
638 X86VectorVTInfo< 2, EltVT64, VR128X>,
640 EXTRACT_get_vextract128_imm>;
641 defm NAME # "64x4" : vextract_for_size<Opcode64,
642 X86VectorVTInfo< 8, EltVT64, VR512>,
643 X86VectorVTInfo< 4, EltVT64, VR256X>,
644 X86VectorVTInfo<16, EltVT32, VR512>,
645 X86VectorVTInfo< 8, EltVT32, VR256>,
647 EXTRACT_get_vextract256_imm>, VEX_W;
650 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
651 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
653 // A 128-bit subvector insert to the first 512-bit vector position
654 // is a subregister copy that needs no instruction.
655 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
656 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
657 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
659 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
660 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
661 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
663 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
664 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
665 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
667 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
668 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
669 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
672 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
673 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
674 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
675 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
676 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
677 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
678 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
679 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
681 // vextractps - extract 32 bits from XMM
682 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
683 (ins VR128X:$src1, u8imm:$src2),
684 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
685 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
688 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
689 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
690 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
691 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
692 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
694 //===---------------------------------------------------------------------===//
697 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
698 ValueType svt, X86VectorVTInfo _> {
699 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
700 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
701 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
705 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
706 (ins _.ScalarMemOp:$src),
707 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
708 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
713 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
714 AVX512VLVectorVTInfo _> {
715 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
718 let Predicates = [HasVLX] in {
719 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
724 let ExeDomain = SSEPackedSingle in {
725 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
726 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
727 let Predicates = [HasVLX] in {
728 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
729 v4f32, v4f32x_info>, EVEX_V128,
730 EVEX_CD8<32, CD8VT1>;
734 let ExeDomain = SSEPackedDouble in {
735 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
736 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
739 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
740 // Later, we can canonize broadcast instructions before ISel phase and
741 // eliminate additional patterns on ISel.
742 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
743 // representations of source
744 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
745 X86VectorVTInfo _, RegisterClass SrcRC_v,
746 RegisterClass SrcRC_s> {
747 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
748 (!cast<Instruction>(InstName##"r")
749 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
751 let AddedComplexity = 30 in {
752 def : Pat<(_.VT (vselect _.KRCWM:$mask,
753 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
754 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
755 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
757 def : Pat<(_.VT(vselect _.KRCWM:$mask,
758 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
759 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
760 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
764 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
766 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
769 let Predicates = [HasVLX] in {
770 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
771 v8f32x_info, VR128X, FR32X>;
772 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
773 v4f32x_info, VR128X, FR32X>;
774 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
775 v4f64x_info, VR128X, FR64X>;
778 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
779 (VBROADCASTSSZm addr:$src)>;
780 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
781 (VBROADCASTSDZm addr:$src)>;
783 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
784 (VBROADCASTSSZm addr:$src)>;
785 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
786 (VBROADCASTSDZm addr:$src)>;
788 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
789 RegisterClass SrcRC> {
790 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
791 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
792 "$src", "$src", []>, T8PD, EVEX;
795 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
796 RegisterClass SrcRC, Predicate prd> {
797 let Predicates = [prd] in
798 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
799 let Predicates = [prd, HasVLX] in {
800 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
801 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
805 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
807 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
809 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
811 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
814 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
815 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
817 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
818 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
820 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
821 (VPBROADCASTDrZr GR32:$src)>;
822 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
823 (VPBROADCASTQrZr GR64:$src)>;
825 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
826 (VPBROADCASTDrZr GR32:$src)>;
827 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
828 (VPBROADCASTQrZr GR64:$src)>;
830 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
831 (v16i32 immAllZerosV), (i16 GR16:$mask))),
832 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
833 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
834 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
835 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
837 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
838 X86MemOperand x86memop, PatFrag ld_frag,
839 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
841 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
842 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
844 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
845 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
847 !strconcat(OpcodeStr,
848 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
850 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
856 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
859 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
860 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
862 !strconcat(OpcodeStr,
863 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
865 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
867 !strconcat(OpcodeStr,
868 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
869 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
870 (X86VBroadcast (ld_frag addr:$src)),
871 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
875 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
876 loadi32, VR512, v16i32, v4i32, VK16WM>,
877 EVEX_V512, EVEX_CD8<32, CD8VT1>;
878 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
879 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
880 EVEX_CD8<64, CD8VT1>;
882 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
883 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
885 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
886 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
888 (_Dst.VT (X86SubVBroadcast
889 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
890 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
892 !strconcat(OpcodeStr,
893 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
895 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
897 !strconcat(OpcodeStr,
898 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
903 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
904 v16i32_info, v4i32x_info>,
905 EVEX_V512, EVEX_CD8<32, CD8VT4>;
906 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
907 v16f32_info, v4f32x_info>,
908 EVEX_V512, EVEX_CD8<32, CD8VT4>;
909 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
910 v8i64_info, v4i64x_info>, VEX_W,
911 EVEX_V512, EVEX_CD8<64, CD8VT4>;
912 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
913 v8f64_info, v4f64x_info>, VEX_W,
914 EVEX_V512, EVEX_CD8<64, CD8VT4>;
916 let Predicates = [HasVLX] in {
917 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
918 v8i32x_info, v4i32x_info>,
919 EVEX_V256, EVEX_CD8<32, CD8VT4>;
920 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
921 v8f32x_info, v4f32x_info>,
922 EVEX_V256, EVEX_CD8<32, CD8VT4>;
924 let Predicates = [HasVLX, HasDQI] in {
925 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
926 v4i64x_info, v2i64x_info>, VEX_W,
927 EVEX_V256, EVEX_CD8<64, CD8VT2>;
928 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
929 v4f64x_info, v2f64x_info>, VEX_W,
930 EVEX_V256, EVEX_CD8<64, CD8VT2>;
932 let Predicates = [HasDQI] in {
933 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
934 v8i64_info, v2i64x_info>, VEX_W,
935 EVEX_V512, EVEX_CD8<64, CD8VT2>;
936 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
937 v16i32_info, v8i32x_info>,
938 EVEX_V512, EVEX_CD8<32, CD8VT8>;
939 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
940 v8f64_info, v2f64x_info>, VEX_W,
941 EVEX_V512, EVEX_CD8<64, CD8VT2>;
942 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
943 v16f32_info, v8f32x_info>,
944 EVEX_V512, EVEX_CD8<32, CD8VT8>;
947 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
948 (VPBROADCASTDZrr VR128X:$src)>;
949 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
950 (VPBROADCASTQZrr VR128X:$src)>;
952 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
953 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
954 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
955 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
957 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
958 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
959 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
960 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
962 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
963 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
964 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
965 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
967 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
968 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
969 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
970 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
972 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
973 (VBROADCASTSSZr VR128X:$src)>;
974 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
975 (VBROADCASTSDZr VR128X:$src)>;
977 // Provide fallback in case the load node that is used in the patterns above
978 // is used by additional users, which prevents the pattern selection.
979 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
980 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
981 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
982 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
985 //===----------------------------------------------------------------------===//
986 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
989 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
991 let Predicates = [HasCDI] in
992 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
993 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
994 []>, EVEX, EVEX_V512;
996 let Predicates = [HasCDI, HasVLX] in {
997 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
998 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
999 []>, EVEX, EVEX_V128;
1000 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
1001 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1002 []>, EVEX, EVEX_V256;
1006 let Predicates = [HasCDI] in {
1007 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1009 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1013 //===----------------------------------------------------------------------===//
1016 // -- immediate form --
1017 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1018 X86VectorVTInfo _> {
1019 let ExeDomain = _.ExeDomain in {
1020 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1021 (ins _.RC:$src1, u8imm:$src2),
1022 !strconcat(OpcodeStr,
1023 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1025 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1027 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1028 (ins _.MemOp:$src1, u8imm:$src2),
1029 !strconcat(OpcodeStr,
1030 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1032 (_.VT (OpNode (_.LdFrag addr:$src1),
1033 (i8 imm:$src2))))]>,
1034 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1038 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1039 X86VectorVTInfo Ctrl> :
1040 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1041 let ExeDomain = _.ExeDomain in {
1042 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1043 (ins _.RC:$src1, _.RC:$src2),
1044 !strconcat("vpermil" # _.Suffix,
1045 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1047 (_.VT (X86VPermilpv _.RC:$src1,
1048 (Ctrl.VT Ctrl.RC:$src2))))]>,
1050 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1051 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1052 !strconcat("vpermil" # _.Suffix,
1053 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1055 (_.VT (X86VPermilpv _.RC:$src1,
1056 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1060 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1062 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1065 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1066 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1067 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1068 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1070 // -- VPERM2I - 3 source operands form --
1071 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1072 SDNode OpNode, X86VectorVTInfo _> {
1073 let Constraints = "$src1 = $dst" in {
1074 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1075 (ins _.RC:$src2, _.RC:$src3),
1076 OpcodeStr, "$src3, $src2", "$src2, $src3",
1077 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1081 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1082 (ins _.RC:$src2, _.MemOp:$src3),
1083 OpcodeStr, "$src3, $src2", "$src2, $src3",
1084 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1085 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1086 EVEX_4V, AVX5128IBase;
1089 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1090 SDNode OpNode, X86VectorVTInfo _> {
1091 let mayLoad = 1, Constraints = "$src1 = $dst" in
1092 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1093 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1094 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1095 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1096 (_.VT (OpNode _.RC:$src1,
1097 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1098 AVX5128IBase, EVEX_4V, EVEX_B;
1101 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1102 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1103 let Predicates = [HasAVX512] in
1104 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1105 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1106 let Predicates = [HasVLX] in {
1107 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1108 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1110 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1111 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1115 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1116 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1117 let Predicates = [HasBWI] in
1118 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1119 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1121 let Predicates = [HasBWI, HasVLX] in {
1122 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1123 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1125 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1126 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1130 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1131 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1132 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1133 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1134 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1135 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1136 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1137 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1139 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1140 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1141 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1142 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1143 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1144 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1145 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1146 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1148 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1149 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1150 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1151 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1153 //===----------------------------------------------------------------------===//
1154 // AVX-512 - BLEND using mask
1156 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1157 let ExeDomain = _.ExeDomain in {
1158 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1159 (ins _.RC:$src1, _.RC:$src2),
1160 !strconcat(OpcodeStr,
1161 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1163 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1164 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1165 !strconcat(OpcodeStr,
1166 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1167 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1168 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1169 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1170 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1171 !strconcat(OpcodeStr,
1172 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1173 []>, EVEX_4V, EVEX_KZ;
1174 let mayLoad = 1 in {
1175 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1176 (ins _.RC:$src1, _.MemOp:$src2),
1177 !strconcat(OpcodeStr,
1178 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1179 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1180 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1181 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1182 !strconcat(OpcodeStr,
1183 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1184 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1185 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1186 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1187 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1188 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1189 !strconcat(OpcodeStr,
1190 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1191 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1195 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1197 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1198 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1199 !strconcat(OpcodeStr,
1200 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1201 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1202 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1203 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1204 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1206 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1207 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1208 !strconcat(OpcodeStr,
1209 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1210 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1211 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1215 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1216 AVX512VLVectorVTInfo VTInfo> {
1217 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1218 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1220 let Predicates = [HasVLX] in {
1221 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1222 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1223 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1224 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1228 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1229 AVX512VLVectorVTInfo VTInfo> {
1230 let Predicates = [HasBWI] in
1231 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1233 let Predicates = [HasBWI, HasVLX] in {
1234 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1235 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1240 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1241 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1242 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1243 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1244 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1245 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1248 let Predicates = [HasAVX512] in {
1249 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1250 (v8f32 VR256X:$src2))),
1252 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1253 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1254 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1256 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1257 (v8i32 VR256X:$src2))),
1259 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1260 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1261 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1263 //===----------------------------------------------------------------------===//
1264 // Compare Instructions
1265 //===----------------------------------------------------------------------===//
1267 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1268 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1269 SDNode OpNode, ValueType VT,
1270 PatFrag ld_frag, string Suffix> {
1271 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1272 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1273 !strconcat("vcmp${cc}", Suffix,
1274 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1275 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1276 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1277 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1278 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1279 !strconcat("vcmp${cc}", Suffix,
1280 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1281 [(set VK1:$dst, (OpNode (VT RC:$src1),
1282 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1283 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1284 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1285 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1286 !strconcat("vcmp", Suffix,
1287 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1288 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1290 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1291 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1292 !strconcat("vcmp", Suffix,
1293 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1294 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1298 let Predicates = [HasAVX512] in {
1299 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1301 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1305 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1306 X86VectorVTInfo _> {
1307 def rr : AVX512BI<opc, MRMSrcReg,
1308 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1310 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1311 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1313 def rm : AVX512BI<opc, MRMSrcMem,
1314 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1316 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1317 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1318 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1319 def rrk : AVX512BI<opc, MRMSrcReg,
1320 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1322 "$dst {${mask}}, $src1, $src2}"),
1323 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1324 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1325 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1327 def rmk : AVX512BI<opc, MRMSrcMem,
1328 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1329 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1330 "$dst {${mask}}, $src1, $src2}"),
1331 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1332 (OpNode (_.VT _.RC:$src1),
1334 (_.LdFrag addr:$src2))))))],
1335 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1338 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1339 X86VectorVTInfo _> :
1340 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1341 let mayLoad = 1 in {
1342 def rmb : AVX512BI<opc, MRMSrcMem,
1343 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1344 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1345 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1346 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1347 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1348 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1349 def rmbk : AVX512BI<opc, MRMSrcMem,
1350 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1351 _.ScalarMemOp:$src2),
1352 !strconcat(OpcodeStr,
1353 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1354 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1355 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1356 (OpNode (_.VT _.RC:$src1),
1358 (_.ScalarLdFrag addr:$src2)))))],
1359 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1363 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1364 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1365 let Predicates = [prd] in
1366 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1369 let Predicates = [prd, HasVLX] in {
1370 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1372 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1377 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1378 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1380 let Predicates = [prd] in
1381 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1384 let Predicates = [prd, HasVLX] in {
1385 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1387 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1392 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1393 avx512vl_i8_info, HasBWI>,
1396 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1397 avx512vl_i16_info, HasBWI>,
1398 EVEX_CD8<16, CD8VF>;
1400 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1401 avx512vl_i32_info, HasAVX512>,
1402 EVEX_CD8<32, CD8VF>;
1404 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1405 avx512vl_i64_info, HasAVX512>,
1406 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1408 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1409 avx512vl_i8_info, HasBWI>,
1412 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1413 avx512vl_i16_info, HasBWI>,
1414 EVEX_CD8<16, CD8VF>;
1416 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1417 avx512vl_i32_info, HasAVX512>,
1418 EVEX_CD8<32, CD8VF>;
1420 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1421 avx512vl_i64_info, HasAVX512>,
1422 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1424 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1425 (COPY_TO_REGCLASS (VPCMPGTDZrr
1426 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1427 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1429 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1430 (COPY_TO_REGCLASS (VPCMPEQDZrr
1431 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1432 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1434 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1435 X86VectorVTInfo _> {
1436 def rri : AVX512AIi8<opc, MRMSrcReg,
1437 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1438 !strconcat("vpcmp${cc}", Suffix,
1439 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1440 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1442 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1444 def rmi : AVX512AIi8<opc, MRMSrcMem,
1445 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1446 !strconcat("vpcmp${cc}", Suffix,
1447 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1448 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1449 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1451 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1452 def rrik : AVX512AIi8<opc, MRMSrcReg,
1453 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1455 !strconcat("vpcmp${cc}", Suffix,
1456 "\t{$src2, $src1, $dst {${mask}}|",
1457 "$dst {${mask}}, $src1, $src2}"),
1458 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1459 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1461 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1463 def rmik : AVX512AIi8<opc, MRMSrcMem,
1464 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1466 !strconcat("vpcmp${cc}", Suffix,
1467 "\t{$src2, $src1, $dst {${mask}}|",
1468 "$dst {${mask}}, $src1, $src2}"),
1469 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1470 (OpNode (_.VT _.RC:$src1),
1471 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1473 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1475 // Accept explicit immediate argument form instead of comparison code.
1476 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1477 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1478 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1479 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1480 "$dst, $src1, $src2, $cc}"),
1481 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1483 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1484 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1485 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1486 "$dst, $src1, $src2, $cc}"),
1487 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1488 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1489 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1491 !strconcat("vpcmp", Suffix,
1492 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1493 "$dst {${mask}}, $src1, $src2, $cc}"),
1494 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1496 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1497 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1499 !strconcat("vpcmp", Suffix,
1500 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1501 "$dst {${mask}}, $src1, $src2, $cc}"),
1502 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1506 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1507 X86VectorVTInfo _> :
1508 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1509 def rmib : AVX512AIi8<opc, MRMSrcMem,
1510 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1512 !strconcat("vpcmp${cc}", Suffix,
1513 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1514 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1515 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1516 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1518 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1519 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1520 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1521 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1522 !strconcat("vpcmp${cc}", Suffix,
1523 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1524 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1525 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1526 (OpNode (_.VT _.RC:$src1),
1527 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1529 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1531 // Accept explicit immediate argument form instead of comparison code.
1532 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1533 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1534 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1536 !strconcat("vpcmp", Suffix,
1537 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1538 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1539 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1540 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1541 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1542 _.ScalarMemOp:$src2, u8imm:$cc),
1543 !strconcat("vpcmp", Suffix,
1544 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1545 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1546 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1550 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1551 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1552 let Predicates = [prd] in
1553 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1555 let Predicates = [prd, HasVLX] in {
1556 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1557 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1561 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1562 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1563 let Predicates = [prd] in
1564 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1567 let Predicates = [prd, HasVLX] in {
1568 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1570 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1575 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1576 HasBWI>, EVEX_CD8<8, CD8VF>;
1577 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1578 HasBWI>, EVEX_CD8<8, CD8VF>;
1580 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1581 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1582 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1583 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1585 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1586 HasAVX512>, EVEX_CD8<32, CD8VF>;
1587 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1588 HasAVX512>, EVEX_CD8<32, CD8VF>;
1590 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1591 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1592 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1593 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1595 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1597 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1598 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1599 "vcmp${cc}"#_.Suffix,
1600 "$src2, $src1", "$src1, $src2",
1601 (X86cmpm (_.VT _.RC:$src1),
1605 let mayLoad = 1 in {
1606 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1607 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1608 "vcmp${cc}"#_.Suffix,
1609 "$src2, $src1", "$src1, $src2",
1610 (X86cmpm (_.VT _.RC:$src1),
1611 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1614 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1616 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1617 "vcmp${cc}"#_.Suffix,
1618 "${src2}"##_.BroadcastStr##", $src1",
1619 "$src1, ${src2}"##_.BroadcastStr,
1620 (X86cmpm (_.VT _.RC:$src1),
1621 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1624 // Accept explicit immediate argument form instead of comparison code.
1625 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1626 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1628 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1630 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1632 let mayLoad = 1 in {
1633 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1635 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1637 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1639 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1641 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1643 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1644 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1649 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1650 // comparison code form (VCMP[EQ/LT/LE/...]
1651 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1652 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1653 "vcmp${cc}"#_.Suffix,
1654 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1655 (X86cmpmRnd (_.VT _.RC:$src1),
1658 (i32 FROUND_NO_EXC))>, EVEX_B;
1660 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1661 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1663 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1665 "$cc,{sae}, $src2, $src1",
1666 "$src1, $src2,{sae}, $cc">, EVEX_B;
1670 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1671 let Predicates = [HasAVX512] in {
1672 defm Z : avx512_vcmp_common<_.info512>,
1673 avx512_vcmp_sae<_.info512>, EVEX_V512;
1676 let Predicates = [HasAVX512,HasVLX] in {
1677 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1678 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1682 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1683 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1684 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1685 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1687 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1688 (COPY_TO_REGCLASS (VCMPPSZrri
1689 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1690 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1692 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1693 (COPY_TO_REGCLASS (VPCMPDZrri
1694 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1695 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1697 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1698 (COPY_TO_REGCLASS (VPCMPUDZrri
1699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1700 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1703 //-----------------------------------------------------------------
1704 // Mask register copy, including
1705 // - copy between mask registers
1706 // - load/store mask registers
1707 // - copy from GPR to mask register and vice versa
1709 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1710 string OpcodeStr, RegisterClass KRC,
1711 ValueType vvt, X86MemOperand x86memop> {
1712 let hasSideEffects = 0 in {
1713 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1714 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1716 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1717 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1718 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1720 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1721 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1722 [(store KRC:$src, addr:$dst)]>;
1726 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1728 RegisterClass KRC, RegisterClass GRC> {
1729 let hasSideEffects = 0 in {
1730 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1731 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1732 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1733 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1737 let Predicates = [HasDQI] in
1738 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1739 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1742 let Predicates = [HasAVX512] in
1743 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1744 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1747 let Predicates = [HasBWI] in {
1748 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1750 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1754 let Predicates = [HasBWI] in {
1755 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1757 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1761 // GR from/to mask register
1762 let Predicates = [HasDQI] in {
1763 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1764 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1765 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1766 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1768 let Predicates = [HasAVX512] in {
1769 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1770 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1771 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1772 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1774 let Predicates = [HasBWI] in {
1775 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1776 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1778 let Predicates = [HasBWI] in {
1779 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1780 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1784 let Predicates = [HasDQI] in {
1785 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1786 (KMOVBmk addr:$dst, VK8:$src)>;
1787 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1788 (KMOVBkm addr:$src)>;
1790 let Predicates = [HasAVX512, NoDQI] in {
1791 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1792 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1793 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1794 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1796 let Predicates = [HasAVX512] in {
1797 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1798 (KMOVWmk addr:$dst, VK16:$src)>;
1799 def : Pat<(i1 (load addr:$src)),
1800 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1801 (MOV8rm addr:$src), sub_8bit)),
1803 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1804 (KMOVWkm addr:$src)>;
1806 let Predicates = [HasBWI] in {
1807 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1808 (KMOVDmk addr:$dst, VK32:$src)>;
1809 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1810 (KMOVDkm addr:$src)>;
1812 let Predicates = [HasBWI] in {
1813 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1814 (KMOVQmk addr:$dst, VK64:$src)>;
1815 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1816 (KMOVQkm addr:$src)>;
1819 let Predicates = [HasAVX512] in {
1820 def : Pat<(i1 (trunc (i64 GR64:$src))),
1821 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1824 def : Pat<(i1 (trunc (i32 GR32:$src))),
1825 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1827 def : Pat<(i1 (trunc (i8 GR8:$src))),
1829 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1831 def : Pat<(i1 (trunc (i16 GR16:$src))),
1833 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1836 def : Pat<(i32 (zext VK1:$src)),
1837 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1838 def : Pat<(i32 (anyext VK1:$src)),
1839 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
1840 def : Pat<(i8 (zext VK1:$src)),
1843 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1844 def : Pat<(i64 (zext VK1:$src)),
1845 (AND64ri8 (SUBREG_TO_REG (i64 0),
1846 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1847 def : Pat<(i16 (zext VK1:$src)),
1849 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1851 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1852 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1853 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1854 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1856 let Predicates = [HasBWI] in {
1857 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1858 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1859 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1860 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1864 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1865 let Predicates = [HasAVX512, NoDQI] in {
1866 // GR from/to 8-bit mask without native support
1867 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1869 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1870 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1872 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1876 let Predicates = [HasAVX512] in {
1877 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1878 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1879 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1880 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1882 let Predicates = [HasBWI] in {
1883 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1884 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1885 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1886 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1889 // Mask unary operation
1891 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1892 RegisterClass KRC, SDPatternOperator OpNode,
1894 let Predicates = [prd] in
1895 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1897 [(set KRC:$dst, (OpNode KRC:$src))]>;
1900 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1901 SDPatternOperator OpNode> {
1902 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1904 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1905 HasAVX512>, VEX, PS;
1906 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1907 HasBWI>, VEX, PD, VEX_W;
1908 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1909 HasBWI>, VEX, PS, VEX_W;
1912 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1914 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1915 let Predicates = [HasAVX512] in
1916 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1918 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1919 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1921 defm : avx512_mask_unop_int<"knot", "KNOT">;
1923 let Predicates = [HasDQI] in
1924 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1925 let Predicates = [HasAVX512] in
1926 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1927 let Predicates = [HasBWI] in
1928 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1929 let Predicates = [HasBWI] in
1930 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1932 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1933 let Predicates = [HasAVX512, NoDQI] in {
1934 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1935 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1936 def : Pat<(not VK8:$src),
1938 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1940 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1941 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1942 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1943 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
1945 // Mask binary operation
1946 // - KAND, KANDN, KOR, KXNOR, KXOR
1947 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1948 RegisterClass KRC, SDPatternOperator OpNode,
1949 Predicate prd, bit IsCommutable> {
1950 let Predicates = [prd], isCommutable = IsCommutable in
1951 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1952 !strconcat(OpcodeStr,
1953 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1954 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1957 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1958 SDPatternOperator OpNode, bit IsCommutable> {
1959 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1960 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
1961 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1962 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
1963 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1964 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
1965 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1966 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
1969 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1970 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1972 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
1973 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
1974 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
1975 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
1976 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
1978 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1979 let Predicates = [HasAVX512] in
1980 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1981 (i16 GR16:$src1), (i16 GR16:$src2)),
1982 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1983 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1984 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1987 defm : avx512_mask_binop_int<"kand", "KAND">;
1988 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1989 defm : avx512_mask_binop_int<"kor", "KOR">;
1990 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1991 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1993 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1994 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
1995 // for the DQI set, this type is legal and KxxxB instruction is used
1996 let Predicates = [NoDQI] in
1997 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1999 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2000 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2002 // All types smaller than 8 bits require conversion anyway
2003 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2004 (COPY_TO_REGCLASS (Inst
2005 (COPY_TO_REGCLASS VK1:$src1, VK16),
2006 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2007 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2008 (COPY_TO_REGCLASS (Inst
2009 (COPY_TO_REGCLASS VK2:$src1, VK16),
2010 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2011 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2012 (COPY_TO_REGCLASS (Inst
2013 (COPY_TO_REGCLASS VK4:$src1, VK16),
2014 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2017 defm : avx512_binop_pat<and, KANDWrr>;
2018 defm : avx512_binop_pat<andn, KANDNWrr>;
2019 defm : avx512_binop_pat<or, KORWrr>;
2020 defm : avx512_binop_pat<xnor, KXNORWrr>;
2021 defm : avx512_binop_pat<xor, KXORWrr>;
2023 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2024 (KXNORWrr VK16:$src1, VK16:$src2)>;
2025 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2026 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2027 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2028 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2029 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2030 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2032 let Predicates = [NoDQI] in
2033 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2034 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2035 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2037 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2038 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2039 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2041 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2042 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2043 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2045 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2046 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2047 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2050 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2051 RegisterClass KRC> {
2052 let Predicates = [HasAVX512] in
2053 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2054 !strconcat(OpcodeStr,
2055 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2058 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2059 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2063 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2064 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2065 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2066 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2069 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2070 let Predicates = [HasAVX512] in
2071 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2072 (i16 GR16:$src1), (i16 GR16:$src2)),
2073 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2074 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2075 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2077 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2080 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2082 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2083 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2084 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2085 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2088 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2089 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2091 let Predicates = [HasDQI] in
2092 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2094 let Predicates = [HasBWI] in {
2095 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2097 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2102 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2105 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2107 let Predicates = [HasAVX512] in
2108 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2109 !strconcat(OpcodeStr,
2110 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2111 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2114 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2116 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2118 let Predicates = [HasDQI] in
2119 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2121 let Predicates = [HasBWI] in {
2122 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2124 let Predicates = [HasDQI] in
2125 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2130 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2131 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2133 // Mask setting all 0s or 1s
2134 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2135 let Predicates = [HasAVX512] in
2136 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2137 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2138 [(set KRC:$dst, (VT Val))]>;
2141 multiclass avx512_mask_setop_w<PatFrag Val> {
2142 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2143 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2144 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2145 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2148 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2149 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2151 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2152 let Predicates = [HasAVX512] in {
2153 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2154 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2155 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2156 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2157 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2158 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2159 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2161 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2162 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2164 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2165 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2167 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2168 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2170 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2171 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2173 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2174 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2176 let Predicates = [HasVLX] in {
2177 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2178 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2179 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2180 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2181 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2182 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2183 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2184 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2185 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2186 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2189 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2190 (v8i1 (COPY_TO_REGCLASS
2191 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2192 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2194 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2195 (v8i1 (COPY_TO_REGCLASS
2196 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2197 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2199 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2200 (v4i1 (COPY_TO_REGCLASS
2201 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2202 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2204 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2205 (v4i1 (COPY_TO_REGCLASS
2206 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2207 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2209 //===----------------------------------------------------------------------===//
2210 // AVX-512 - Aligned and unaligned load and store
2214 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2215 PatFrag ld_frag, PatFrag mload,
2216 bit IsReMaterializable = 1> {
2217 let hasSideEffects = 0 in {
2218 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2219 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2221 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2222 (ins _.KRCWM:$mask, _.RC:$src),
2223 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2224 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2227 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2228 SchedRW = [WriteLoad] in
2229 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2230 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2231 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2234 let Constraints = "$src0 = $dst" in {
2235 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2236 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2237 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2238 "${dst} {${mask}}, $src1}"),
2239 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2241 (_.VT _.RC:$src0))))], _.ExeDomain>,
2243 let mayLoad = 1, SchedRW = [WriteLoad] in
2244 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2245 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2246 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2247 "${dst} {${mask}}, $src1}"),
2248 [(set _.RC:$dst, (_.VT
2249 (vselect _.KRCWM:$mask,
2250 (_.VT (bitconvert (ld_frag addr:$src1))),
2251 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2253 let mayLoad = 1, SchedRW = [WriteLoad] in
2254 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2255 (ins _.KRCWM:$mask, _.MemOp:$src),
2256 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2257 "${dst} {${mask}} {z}, $src}",
2258 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2259 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2260 _.ExeDomain>, EVEX, EVEX_KZ;
2262 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2263 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2265 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2266 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2268 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2269 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2270 _.KRCWM:$mask, addr:$ptr)>;
2273 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2274 AVX512VLVectorVTInfo _,
2276 bit IsReMaterializable = 1> {
2277 let Predicates = [prd] in
2278 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2279 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2281 let Predicates = [prd, HasVLX] in {
2282 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2283 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2284 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2285 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2289 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2290 AVX512VLVectorVTInfo _,
2292 bit IsReMaterializable = 1> {
2293 let Predicates = [prd] in
2294 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2295 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2297 let Predicates = [prd, HasVLX] in {
2298 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2299 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2300 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2301 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2305 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2306 PatFrag st_frag, PatFrag mstore> {
2307 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2308 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2309 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2311 let Constraints = "$src1 = $dst" in
2312 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2313 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2315 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2316 [], _.ExeDomain>, EVEX, EVEX_K;
2317 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2318 (ins _.KRCWM:$mask, _.RC:$src),
2320 "\t{$src, ${dst} {${mask}} {z}|" #
2321 "${dst} {${mask}} {z}, $src}",
2322 [], _.ExeDomain>, EVEX, EVEX_KZ;
2324 let mayStore = 1 in {
2325 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2326 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2327 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2328 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2329 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2330 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2331 [], _.ExeDomain>, EVEX, EVEX_K;
2334 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2335 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2336 _.KRCWM:$mask, _.RC:$src)>;
2340 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2341 AVX512VLVectorVTInfo _, Predicate prd> {
2342 let Predicates = [prd] in
2343 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2344 masked_store_unaligned>, EVEX_V512;
2346 let Predicates = [prd, HasVLX] in {
2347 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2348 masked_store_unaligned>, EVEX_V256;
2349 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2350 masked_store_unaligned>, EVEX_V128;
2354 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2355 AVX512VLVectorVTInfo _, Predicate prd> {
2356 let Predicates = [prd] in
2357 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2358 masked_store_aligned512>, EVEX_V512;
2360 let Predicates = [prd, HasVLX] in {
2361 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2362 masked_store_aligned256>, EVEX_V256;
2363 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2364 masked_store_aligned128>, EVEX_V128;
2368 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2370 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2371 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2373 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2375 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2376 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2378 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2379 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2380 PS, EVEX_CD8<32, CD8VF>;
2382 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2383 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2384 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2386 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2387 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2388 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2390 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2391 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2392 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2394 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2395 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2396 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2398 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2399 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2400 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2402 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2403 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2404 (VMOVAPDZrm addr:$ptr)>;
2406 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2407 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2408 (VMOVAPSZrm addr:$ptr)>;
2410 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2412 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2414 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2416 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2419 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2421 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2423 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2425 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2428 let Predicates = [HasAVX512, NoVLX] in {
2429 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2430 (VMOVUPSZmrk addr:$ptr,
2431 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2432 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2434 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2435 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2436 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2438 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2439 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2440 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2441 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2444 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2446 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2447 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2449 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2451 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2452 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2454 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2455 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2456 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2458 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2459 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2460 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2462 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2463 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2464 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2466 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2467 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2468 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2470 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2471 (v16i32 immAllZerosV), GR16:$mask)),
2472 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2474 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2475 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2476 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2478 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2480 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2482 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2484 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2487 let AddedComplexity = 20 in {
2488 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2489 (bc_v8i64 (v16i32 immAllZerosV)))),
2490 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2492 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2493 (v8i64 VR512:$src))),
2494 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2497 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2498 (v16i32 immAllZerosV))),
2499 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2501 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2502 (v16i32 VR512:$src))),
2503 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2506 let Predicates = [HasAVX512, NoVLX] in {
2507 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2508 (VMOVDQU32Zmrk addr:$ptr,
2509 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2510 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2512 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2513 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2514 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2517 // Move Int Doubleword to Packed Double Int
2519 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2520 "vmovd\t{$src, $dst|$dst, $src}",
2522 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2524 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2525 "vmovd\t{$src, $dst|$dst, $src}",
2527 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2528 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2529 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2530 "vmovq\t{$src, $dst|$dst, $src}",
2532 (v2i64 (scalar_to_vector GR64:$src)))],
2533 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2534 let isCodeGenOnly = 1 in {
2535 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2536 "vmovq\t{$src, $dst|$dst, $src}",
2537 [(set FR64:$dst, (bitconvert GR64:$src))],
2538 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2539 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2540 "vmovq\t{$src, $dst|$dst, $src}",
2541 [(set GR64:$dst, (bitconvert FR64:$src))],
2542 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2544 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2545 "vmovq\t{$src, $dst|$dst, $src}",
2546 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2547 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2548 EVEX_CD8<64, CD8VT1>;
2550 // Move Int Doubleword to Single Scalar
2552 let isCodeGenOnly = 1 in {
2553 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2554 "vmovd\t{$src, $dst|$dst, $src}",
2555 [(set FR32X:$dst, (bitconvert GR32:$src))],
2556 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2558 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2559 "vmovd\t{$src, $dst|$dst, $src}",
2560 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2561 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2564 // Move doubleword from xmm register to r/m32
2566 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2567 "vmovd\t{$src, $dst|$dst, $src}",
2568 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2569 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2571 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2572 (ins i32mem:$dst, VR128X:$src),
2573 "vmovd\t{$src, $dst|$dst, $src}",
2574 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2575 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2576 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2578 // Move quadword from xmm1 register to r/m64
2580 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2581 "vmovq\t{$src, $dst|$dst, $src}",
2582 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2584 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2585 Requires<[HasAVX512, In64BitMode]>;
2587 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2588 (ins i64mem:$dst, VR128X:$src),
2589 "vmovq\t{$src, $dst|$dst, $src}",
2590 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2591 addr:$dst)], IIC_SSE_MOVDQ>,
2592 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2593 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2595 // Move Scalar Single to Double Int
2597 let isCodeGenOnly = 1 in {
2598 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2600 "vmovd\t{$src, $dst|$dst, $src}",
2601 [(set GR32:$dst, (bitconvert FR32X:$src))],
2602 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2603 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2604 (ins i32mem:$dst, FR32X:$src),
2605 "vmovd\t{$src, $dst|$dst, $src}",
2606 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2607 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2610 // Move Quadword Int to Packed Quadword Int
2612 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2614 "vmovq\t{$src, $dst|$dst, $src}",
2616 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2617 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2619 //===----------------------------------------------------------------------===//
2620 // AVX-512 MOVSS, MOVSD
2621 //===----------------------------------------------------------------------===//
2623 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2624 SDNode OpNode, ValueType vt,
2625 X86MemOperand x86memop, PatFrag mem_pat> {
2626 let hasSideEffects = 0 in {
2627 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2628 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2629 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2630 (scalar_to_vector RC:$src2))))],
2631 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2632 let Constraints = "$src1 = $dst" in
2633 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2634 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2636 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2637 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2638 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2639 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2640 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2642 let mayStore = 1 in {
2643 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2644 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2645 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2647 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2648 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2649 [], IIC_SSE_MOV_S_MR>,
2650 EVEX, VEX_LIG, EVEX_K;
2652 } //hasSideEffects = 0
2655 let ExeDomain = SSEPackedSingle in
2656 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2657 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2659 let ExeDomain = SSEPackedDouble in
2660 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2661 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2663 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2664 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2665 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2667 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2668 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2669 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2671 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2672 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2673 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2675 // For the disassembler
2676 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2677 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2678 (ins VR128X:$src1, FR32X:$src2),
2679 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2681 XS, EVEX_4V, VEX_LIG;
2682 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2683 (ins VR128X:$src1, FR64X:$src2),
2684 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2686 XD, EVEX_4V, VEX_LIG, VEX_W;
2689 let Predicates = [HasAVX512] in {
2690 let AddedComplexity = 15 in {
2691 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2692 // MOVS{S,D} to the lower bits.
2693 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2694 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2695 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2696 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2697 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2698 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2699 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2700 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2702 // Move low f32 and clear high bits.
2703 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2704 (SUBREG_TO_REG (i32 0),
2705 (VMOVSSZrr (v4f32 (V_SET0)),
2706 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2707 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2708 (SUBREG_TO_REG (i32 0),
2709 (VMOVSSZrr (v4i32 (V_SET0)),
2710 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2713 let AddedComplexity = 20 in {
2714 // MOVSSrm zeros the high parts of the register; represent this
2715 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2716 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2717 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2718 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2719 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2720 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2721 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2723 // MOVSDrm zeros the high parts of the register; represent this
2724 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2725 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2726 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2727 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2728 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2729 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2730 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2731 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2732 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2733 def : Pat<(v2f64 (X86vzload addr:$src)),
2734 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2736 // Represent the same patterns above but in the form they appear for
2738 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2739 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2740 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2741 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2742 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2743 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2744 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2745 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2746 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2748 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2749 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2750 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2751 FR32X:$src)), sub_xmm)>;
2752 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2753 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2754 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2755 FR64X:$src)), sub_xmm)>;
2756 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2757 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2758 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2760 // Move low f64 and clear high bits.
2761 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2762 (SUBREG_TO_REG (i32 0),
2763 (VMOVSDZrr (v2f64 (V_SET0)),
2764 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2766 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2767 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2768 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2770 // Extract and store.
2771 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2773 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2774 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2776 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2778 // Shuffle with VMOVSS
2779 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2780 (VMOVSSZrr (v4i32 VR128X:$src1),
2781 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2782 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2783 (VMOVSSZrr (v4f32 VR128X:$src1),
2784 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2787 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2788 (SUBREG_TO_REG (i32 0),
2789 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2790 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2792 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2793 (SUBREG_TO_REG (i32 0),
2794 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2795 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2798 // Shuffle with VMOVSD
2799 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2800 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2801 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2802 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2803 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2804 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2805 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2806 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2809 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2810 (SUBREG_TO_REG (i32 0),
2811 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2812 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2814 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2815 (SUBREG_TO_REG (i32 0),
2816 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2817 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2820 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2821 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2822 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2823 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2824 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2825 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2826 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2827 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2830 let AddedComplexity = 15 in
2831 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2833 "vmovq\t{$src, $dst|$dst, $src}",
2834 [(set VR128X:$dst, (v2i64 (X86vzmovl
2835 (v2i64 VR128X:$src))))],
2836 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2838 let AddedComplexity = 20 in
2839 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2841 "vmovq\t{$src, $dst|$dst, $src}",
2842 [(set VR128X:$dst, (v2i64 (X86vzmovl
2843 (loadv2i64 addr:$src))))],
2844 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2845 EVEX_CD8<8, CD8VT8>;
2847 let Predicates = [HasAVX512] in {
2848 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2849 let AddedComplexity = 20 in {
2850 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2851 (VMOVDI2PDIZrm addr:$src)>;
2852 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2853 (VMOV64toPQIZrr GR64:$src)>;
2854 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2855 (VMOVDI2PDIZrr GR32:$src)>;
2857 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2858 (VMOVDI2PDIZrm addr:$src)>;
2859 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2860 (VMOVDI2PDIZrm addr:$src)>;
2861 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2862 (VMOVZPQILo2PQIZrm addr:$src)>;
2863 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2864 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2865 def : Pat<(v2i64 (X86vzload addr:$src)),
2866 (VMOVZPQILo2PQIZrm addr:$src)>;
2869 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2870 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2871 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2872 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2873 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2874 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2875 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2878 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2879 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2881 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2882 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2884 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2885 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2887 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2888 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2890 //===----------------------------------------------------------------------===//
2891 // AVX-512 - Non-temporals
2892 //===----------------------------------------------------------------------===//
2893 let SchedRW = [WriteLoad] in {
2894 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2895 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2896 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2897 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2898 EVEX_CD8<64, CD8VF>;
2900 let Predicates = [HasAVX512, HasVLX] in {
2901 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2903 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2904 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2905 EVEX_CD8<64, CD8VF>;
2907 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2909 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2910 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2911 EVEX_CD8<64, CD8VF>;
2915 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2916 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2917 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2918 let SchedRW = [WriteStore], mayStore = 1,
2919 AddedComplexity = 400 in
2920 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2921 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2922 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2925 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2926 string elty, string elsz, string vsz512,
2927 string vsz256, string vsz128, Domain d,
2928 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2929 let Predicates = [prd] in
2930 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2931 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2932 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2935 let Predicates = [prd, HasVLX] in {
2936 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2937 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2938 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2941 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2942 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2943 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2948 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2949 "i", "64", "8", "4", "2", SSEPackedInt,
2950 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2952 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2953 "f", "64", "8", "4", "2", SSEPackedDouble,
2954 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2956 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2957 "f", "32", "16", "8", "4", SSEPackedSingle,
2958 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2960 //===----------------------------------------------------------------------===//
2961 // AVX-512 - Integer arithmetic
2963 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2964 X86VectorVTInfo _, OpndItins itins,
2965 bit IsCommutable = 0> {
2966 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2967 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
2968 "$src2, $src1", "$src1, $src2",
2969 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2970 itins.rr, IsCommutable>,
2971 AVX512BIBase, EVEX_4V;
2974 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2975 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
2976 "$src2, $src1", "$src1, $src2",
2977 (_.VT (OpNode _.RC:$src1,
2978 (bitconvert (_.LdFrag addr:$src2)))),
2980 AVX512BIBase, EVEX_4V;
2983 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2984 X86VectorVTInfo _, OpndItins itins,
2985 bit IsCommutable = 0> :
2986 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2988 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2989 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
2990 "${src2}"##_.BroadcastStr##", $src1",
2991 "$src1, ${src2}"##_.BroadcastStr,
2992 (_.VT (OpNode _.RC:$src1,
2994 (_.ScalarLdFrag addr:$src2)))),
2996 AVX512BIBase, EVEX_4V, EVEX_B;
2999 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3000 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3001 Predicate prd, bit IsCommutable = 0> {
3002 let Predicates = [prd] in
3003 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3004 IsCommutable>, EVEX_V512;
3006 let Predicates = [prd, HasVLX] in {
3007 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3008 IsCommutable>, EVEX_V256;
3009 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3010 IsCommutable>, EVEX_V128;
3014 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3015 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3016 Predicate prd, bit IsCommutable = 0> {
3017 let Predicates = [prd] in
3018 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3019 IsCommutable>, EVEX_V512;
3021 let Predicates = [prd, HasVLX] in {
3022 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3023 IsCommutable>, EVEX_V256;
3024 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3025 IsCommutable>, EVEX_V128;
3029 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3030 OpndItins itins, Predicate prd,
3031 bit IsCommutable = 0> {
3032 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3033 itins, prd, IsCommutable>,
3034 VEX_W, EVEX_CD8<64, CD8VF>;
3037 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3038 OpndItins itins, Predicate prd,
3039 bit IsCommutable = 0> {
3040 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3041 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3044 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3045 OpndItins itins, Predicate prd,
3046 bit IsCommutable = 0> {
3047 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3048 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3051 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3052 OpndItins itins, Predicate prd,
3053 bit IsCommutable = 0> {
3054 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3055 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3058 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3059 SDNode OpNode, OpndItins itins, Predicate prd,
3060 bit IsCommutable = 0> {
3061 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3064 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3068 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3069 SDNode OpNode, OpndItins itins, Predicate prd,
3070 bit IsCommutable = 0> {
3071 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3074 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3078 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3079 bits<8> opc_d, bits<8> opc_q,
3080 string OpcodeStr, SDNode OpNode,
3081 OpndItins itins, bit IsCommutable = 0> {
3082 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3083 itins, HasAVX512, IsCommutable>,
3084 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3085 itins, HasBWI, IsCommutable>;
3088 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3089 SDNode OpNode,X86VectorVTInfo _Src,
3090 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3091 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3092 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3093 "$src2, $src1","$src1, $src2",
3095 (_Src.VT _Src.RC:$src1),
3096 (_Src.VT _Src.RC:$src2))),
3097 itins.rr, IsCommutable>,
3098 AVX512BIBase, EVEX_4V;
3099 let mayLoad = 1 in {
3100 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3101 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3102 "$src2, $src1", "$src1, $src2",
3103 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3104 (bitconvert (_Src.LdFrag addr:$src2)))),
3106 AVX512BIBase, EVEX_4V;
3108 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3109 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3111 "${src2}"##_Dst.BroadcastStr##", $src1",
3112 "$src1, ${src2}"##_Dst.BroadcastStr,
3113 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3114 (_Dst.VT (X86VBroadcast
3115 (_Dst.ScalarLdFrag addr:$src2)))))),
3117 AVX512BIBase, EVEX_4V, EVEX_B;
3121 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3122 SSE_INTALU_ITINS_P, 1>;
3123 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3124 SSE_INTALU_ITINS_P, 0>;
3125 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3126 SSE_INTALU_ITINS_P, HasBWI, 1>;
3127 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3128 SSE_INTALU_ITINS_P, HasBWI, 0>;
3129 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3130 SSE_INTALU_ITINS_P, HasBWI, 1>;
3131 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3132 SSE_INTALU_ITINS_P, HasBWI, 0>;
3133 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3134 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3135 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3136 SSE_INTALU_ITINS_P, HasBWI, 1>;
3137 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3138 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3139 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3141 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3143 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3145 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3146 SSE_INTALU_ITINS_P, HasBWI, 1>;
3148 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3149 SDNode OpNode, bit IsCommutable = 0> {
3151 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3152 v16i32_info, v8i64_info, IsCommutable>,
3153 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3154 let Predicates = [HasVLX] in {
3155 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3156 v8i32x_info, v4i64x_info, IsCommutable>,
3157 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3158 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3159 v4i32x_info, v2i64x_info, IsCommutable>,
3160 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3164 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3166 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3169 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3170 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3171 let mayLoad = 1 in {
3172 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3173 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3175 "${src2}"##_Src.BroadcastStr##", $src1",
3176 "$src1, ${src2}"##_Src.BroadcastStr,
3177 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3178 (_Src.VT (X86VBroadcast
3179 (_Src.ScalarLdFrag addr:$src2))))))>,
3180 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3184 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3185 SDNode OpNode,X86VectorVTInfo _Src,
3186 X86VectorVTInfo _Dst> {
3187 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3188 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3189 "$src2, $src1","$src1, $src2",
3191 (_Src.VT _Src.RC:$src1),
3192 (_Src.VT _Src.RC:$src2)))>,
3193 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3194 let mayLoad = 1 in {
3195 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3196 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3197 "$src2, $src1", "$src1, $src2",
3198 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3199 (bitconvert (_Src.LdFrag addr:$src2))))>,
3200 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3204 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3206 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3208 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3209 v32i16_info>, EVEX_V512;
3210 let Predicates = [HasVLX] in {
3211 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3213 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3214 v16i16x_info>, EVEX_V256;
3215 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3217 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3218 v8i16x_info>, EVEX_V128;
3221 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3223 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3224 v64i8_info>, EVEX_V512;
3225 let Predicates = [HasVLX] in {
3226 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3227 v32i8x_info>, EVEX_V256;
3228 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3229 v16i8x_info>, EVEX_V128;
3233 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3234 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3235 AVX512VLVectorVTInfo _Dst> {
3236 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3237 _Dst.info512>, EVEX_V512;
3238 let Predicates = [HasVLX] in {
3239 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3240 _Dst.info256>, EVEX_V256;
3241 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3242 _Dst.info128>, EVEX_V128;
3246 let Predicates = [HasBWI] in {
3247 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3248 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3249 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3250 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3252 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3253 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3254 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3255 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3258 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3259 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3260 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3261 SSE_INTALU_ITINS_P, HasBWI, 1>;
3262 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3263 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3265 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3266 SSE_INTALU_ITINS_P, HasBWI, 1>;
3267 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3268 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3269 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3270 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3272 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3273 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3274 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3275 SSE_INTALU_ITINS_P, HasBWI, 1>;
3276 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3277 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3279 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3280 SSE_INTALU_ITINS_P, HasBWI, 1>;
3281 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3282 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3283 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3284 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3285 //===----------------------------------------------------------------------===//
3286 // AVX-512 Logical Instructions
3287 //===----------------------------------------------------------------------===//
3289 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3290 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3291 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3292 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3293 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3294 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3295 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3296 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3298 //===----------------------------------------------------------------------===//
3299 // AVX-512 FP arithmetic
3300 //===----------------------------------------------------------------------===//
3301 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3302 SDNode OpNode, SDNode VecNode, OpndItins itins,
3305 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3306 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3307 "$src2, $src1", "$src1, $src2",
3308 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3309 (i32 FROUND_CURRENT)),
3310 itins.rr, IsCommutable>;
3312 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3313 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3314 "$src2, $src1", "$src1, $src2",
3315 (VecNode (_.VT _.RC:$src1),
3316 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3317 (i32 FROUND_CURRENT)),
3318 itins.rm, IsCommutable>;
3319 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3320 Predicates = [HasAVX512] in {
3321 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3322 (ins _.FRC:$src1, _.FRC:$src2),
3323 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3324 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3326 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3327 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3328 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3329 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3330 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3334 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3335 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3337 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3338 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3339 "$rc, $src2, $src1", "$src1, $src2, $rc",
3340 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3341 (i32 imm:$rc)), itins.rr, IsCommutable>,
3344 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3345 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3347 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3348 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3349 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3350 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3351 (i32 FROUND_NO_EXC))>, EVEX_B;
3354 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3356 SizeItins itins, bit IsCommutable> {
3357 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3358 itins.s, IsCommutable>,
3359 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3360 itins.s, IsCommutable>,
3361 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3362 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3363 itins.d, IsCommutable>,
3364 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3365 itins.d, IsCommutable>,
3366 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3369 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3371 SizeItins itins, bit IsCommutable> {
3372 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3373 itins.s, IsCommutable>,
3374 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3375 itins.s, IsCommutable>,
3376 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3377 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3378 itins.d, IsCommutable>,
3379 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3380 itins.d, IsCommutable>,
3381 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3383 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3384 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3385 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3386 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3387 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3388 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3390 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3391 X86VectorVTInfo _, bit IsCommutable> {
3392 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3393 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3394 "$src2, $src1", "$src1, $src2",
3395 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3396 let mayLoad = 1 in {
3397 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3398 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3399 "$src2, $src1", "$src1, $src2",
3400 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3401 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3402 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3403 "${src2}"##_.BroadcastStr##", $src1",
3404 "$src1, ${src2}"##_.BroadcastStr,
3405 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3406 (_.ScalarLdFrag addr:$src2))))>,
3411 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3412 X86VectorVTInfo _> {
3413 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3414 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3415 "$rc, $src2, $src1", "$src1, $src2, $rc",
3416 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3417 EVEX_4V, EVEX_B, EVEX_RC;
3421 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3422 X86VectorVTInfo _> {
3423 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3424 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3425 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3426 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3430 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3431 bit IsCommutable = 0> {
3432 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3433 IsCommutable>, EVEX_V512, PS,
3434 EVEX_CD8<32, CD8VF>;
3435 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3436 IsCommutable>, EVEX_V512, PD, VEX_W,
3437 EVEX_CD8<64, CD8VF>;
3439 // Define only if AVX512VL feature is present.
3440 let Predicates = [HasVLX] in {
3441 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3442 IsCommutable>, EVEX_V128, PS,
3443 EVEX_CD8<32, CD8VF>;
3444 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3445 IsCommutable>, EVEX_V256, PS,
3446 EVEX_CD8<32, CD8VF>;
3447 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3448 IsCommutable>, EVEX_V128, PD, VEX_W,
3449 EVEX_CD8<64, CD8VF>;
3450 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3451 IsCommutable>, EVEX_V256, PD, VEX_W,
3452 EVEX_CD8<64, CD8VF>;
3456 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3457 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3458 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3459 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3460 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3463 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3464 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3465 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3466 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3467 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3470 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3471 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3472 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3473 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3474 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3475 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3476 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3477 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3478 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3479 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3480 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3481 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3482 let Predicates = [HasDQI] in {
3483 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3484 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3485 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3486 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3489 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3490 X86VectorVTInfo _> {
3491 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3492 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3493 "$src2, $src1", "$src1, $src2",
3494 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3495 let mayLoad = 1 in {
3496 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3497 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3498 "$src2, $src1", "$src1, $src2",
3499 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3500 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3501 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3502 "${src2}"##_.BroadcastStr##", $src1",
3503 "$src1, ${src2}"##_.BroadcastStr,
3504 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3505 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3510 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3511 X86VectorVTInfo _> {
3512 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3513 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3514 "$src2, $src1", "$src1, $src2",
3515 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3516 let mayLoad = 1 in {
3517 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3518 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3519 "$src2, $src1", "$src1, $src2",
3520 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3524 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3525 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3526 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3527 EVEX_V512, EVEX_CD8<32, CD8VF>;
3528 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3529 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3530 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3531 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3532 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3533 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3534 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3535 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3536 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3538 // Define only if AVX512VL feature is present.
3539 let Predicates = [HasVLX] in {
3540 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3541 EVEX_V128, EVEX_CD8<32, CD8VF>;
3542 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3543 EVEX_V256, EVEX_CD8<32, CD8VF>;
3544 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3545 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3546 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3547 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3550 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3552 //===----------------------------------------------------------------------===//
3553 // AVX-512 VPTESTM instructions
3554 //===----------------------------------------------------------------------===//
3556 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3557 X86VectorVTInfo _> {
3558 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3559 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3560 "$src2, $src1", "$src1, $src2",
3561 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3564 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3565 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3566 "$src2, $src1", "$src1, $src2",
3567 (OpNode (_.VT _.RC:$src1),
3568 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3570 EVEX_CD8<_.EltSize, CD8VF>;
3573 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3574 X86VectorVTInfo _> {
3576 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3577 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3578 "${src2}"##_.BroadcastStr##", $src1",
3579 "$src1, ${src2}"##_.BroadcastStr,
3580 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3581 (_.ScalarLdFrag addr:$src2))))>,
3582 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3584 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3585 AVX512VLVectorVTInfo _> {
3586 let Predicates = [HasAVX512] in
3587 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3588 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3590 let Predicates = [HasAVX512, HasVLX] in {
3591 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3592 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3593 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3594 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3598 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3599 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3601 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3602 avx512vl_i64_info>, VEX_W;
3605 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3607 let Predicates = [HasBWI] in {
3608 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3610 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3613 let Predicates = [HasVLX, HasBWI] in {
3615 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3617 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3619 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3621 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3626 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3628 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3629 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3631 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3632 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3634 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3635 (v16i32 VR512:$src2), (i16 -1))),
3636 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3638 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3639 (v8i64 VR512:$src2), (i8 -1))),
3640 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3642 //===----------------------------------------------------------------------===//
3643 // AVX-512 Shift instructions
3644 //===----------------------------------------------------------------------===//
3645 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3646 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3647 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3648 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3649 "$src2, $src1", "$src1, $src2",
3650 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3651 SSE_INTSHIFT_ITINS_P.rr>;
3653 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3654 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3655 "$src2, $src1", "$src1, $src2",
3656 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3658 SSE_INTSHIFT_ITINS_P.rm>;
3661 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3662 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3664 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3665 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3666 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3667 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3668 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3671 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3672 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3673 // src2 is always 128-bit
3674 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3675 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3676 "$src2, $src1", "$src1, $src2",
3677 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3678 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3679 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3680 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3681 "$src2, $src1", "$src1, $src2",
3682 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3683 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3687 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3688 ValueType SrcVT, PatFrag bc_frag,
3689 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3690 let Predicates = [prd] in
3691 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3692 VTInfo.info512>, EVEX_V512,
3693 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3694 let Predicates = [prd, HasVLX] in {
3695 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3696 VTInfo.info256>, EVEX_V256,
3697 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3698 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3699 VTInfo.info128>, EVEX_V128,
3700 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3704 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3705 string OpcodeStr, SDNode OpNode> {
3706 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3707 avx512vl_i32_info, HasAVX512>;
3708 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3709 avx512vl_i64_info, HasAVX512>, VEX_W;
3710 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3711 avx512vl_i16_info, HasBWI>;
3714 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3715 string OpcodeStr, SDNode OpNode,
3716 AVX512VLVectorVTInfo VTInfo> {
3717 let Predicates = [HasAVX512] in
3718 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3720 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3721 VTInfo.info512>, EVEX_V512;
3722 let Predicates = [HasAVX512, HasVLX] in {
3723 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3725 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3726 VTInfo.info256>, EVEX_V256;
3727 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3729 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3730 VTInfo.info128>, EVEX_V128;
3734 multiclass avx512_shift_rmi_w<bits<8> opcw,
3735 Format ImmFormR, Format ImmFormM,
3736 string OpcodeStr, SDNode OpNode> {
3737 let Predicates = [HasBWI] in
3738 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3739 v32i16_info>, EVEX_V512;
3740 let Predicates = [HasVLX, HasBWI] in {
3741 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3742 v16i16x_info>, EVEX_V256;
3743 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3744 v8i16x_info>, EVEX_V128;
3748 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3749 Format ImmFormR, Format ImmFormM,
3750 string OpcodeStr, SDNode OpNode> {
3751 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3752 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3753 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3754 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3757 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3758 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3760 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3761 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3763 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3764 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3766 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3767 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3769 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3770 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3771 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3773 //===-------------------------------------------------------------------===//
3774 // Variable Bit Shifts
3775 //===-------------------------------------------------------------------===//
3776 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3777 X86VectorVTInfo _> {
3778 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3779 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3780 "$src2, $src1", "$src1, $src2",
3781 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3782 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3784 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3785 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3786 "$src2, $src1", "$src1, $src2",
3787 (_.VT (OpNode _.RC:$src1,
3788 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3789 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3790 EVEX_CD8<_.EltSize, CD8VF>;
3793 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3794 X86VectorVTInfo _> {
3796 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3797 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3798 "${src2}"##_.BroadcastStr##", $src1",
3799 "$src1, ${src2}"##_.BroadcastStr,
3800 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3801 (_.ScalarLdFrag addr:$src2))))),
3802 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3803 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3805 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3806 AVX512VLVectorVTInfo _> {
3807 let Predicates = [HasAVX512] in
3808 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3809 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3811 let Predicates = [HasAVX512, HasVLX] in {
3812 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3813 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3814 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3815 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3819 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3821 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3823 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3824 avx512vl_i64_info>, VEX_W;
3827 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3829 let Predicates = [HasBWI] in
3830 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3832 let Predicates = [HasVLX, HasBWI] in {
3834 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3836 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3841 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3842 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3843 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3844 avx512_var_shift_w<0x11, "vpsravw", sra>;
3845 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3846 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3847 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3848 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3850 //===-------------------------------------------------------------------===//
3851 // 1-src variable permutation VPERMW/D/Q
3852 //===-------------------------------------------------------------------===//
3853 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3854 AVX512VLVectorVTInfo _> {
3855 let Predicates = [HasAVX512] in
3856 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3857 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3859 let Predicates = [HasAVX512, HasVLX] in
3860 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3861 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3864 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3865 string OpcodeStr, SDNode OpNode,
3866 AVX512VLVectorVTInfo VTInfo> {
3867 let Predicates = [HasAVX512] in
3868 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3870 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3871 VTInfo.info512>, EVEX_V512;
3872 let Predicates = [HasAVX512, HasVLX] in
3873 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3875 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3876 VTInfo.info256>, EVEX_V256;
3880 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
3882 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
3884 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
3885 avx512vl_i64_info>, VEX_W;
3886 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
3888 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
3889 avx512vl_f64_info>, VEX_W;
3891 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
3892 X86VPermi, avx512vl_i64_info>,
3893 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3894 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
3895 X86VPermi, avx512vl_f64_info>,
3896 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3898 //===----------------------------------------------------------------------===//
3899 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
3900 //===----------------------------------------------------------------------===//
3902 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
3903 X86PShufd, avx512vl_i32_info>,
3904 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
3905 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
3906 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
3907 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
3908 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
3910 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3911 let Predicates = [HasBWI] in
3912 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
3914 let Predicates = [HasVLX, HasBWI] in {
3915 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
3916 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
3920 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
3922 //===----------------------------------------------------------------------===//
3923 // AVX-512 - MOVDDUP
3924 //===----------------------------------------------------------------------===//
3926 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3927 X86MemOperand x86memop, PatFrag memop_frag> {
3928 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3929 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3930 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3931 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3934 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3937 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3938 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3939 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3940 (VMOVDDUPZrm addr:$src)>;
3942 //===---------------------------------------------------------------------===//
3943 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3944 //===---------------------------------------------------------------------===//
3945 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3946 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3947 X86MemOperand x86memop> {
3948 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3950 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3952 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3953 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3954 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3957 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3958 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3959 EVEX_CD8<32, CD8VF>;
3960 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3961 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3962 EVEX_CD8<32, CD8VF>;
3964 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3965 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3966 (VMOVSHDUPZrm addr:$src)>;
3967 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3968 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3969 (VMOVSLDUPZrm addr:$src)>;
3971 //===----------------------------------------------------------------------===//
3972 // Move Low to High and High to Low packed FP Instructions
3973 //===----------------------------------------------------------------------===//
3974 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3975 (ins VR128X:$src1, VR128X:$src2),
3976 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3977 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3978 IIC_SSE_MOV_LH>, EVEX_4V;
3979 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3980 (ins VR128X:$src1, VR128X:$src2),
3981 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3982 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3983 IIC_SSE_MOV_LH>, EVEX_4V;
3985 let Predicates = [HasAVX512] in {
3987 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3988 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3989 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3990 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3993 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3994 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3997 //===----------------------------------------------------------------------===//
3998 // FMA - Fused Multiply Operations
4001 let Constraints = "$src1 = $dst" in {
4002 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4003 X86VectorVTInfo _> {
4004 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4005 (ins _.RC:$src2, _.RC:$src3),
4006 OpcodeStr, "$src3, $src2", "$src2, $src3",
4007 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4010 let mayLoad = 1 in {
4011 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4012 (ins _.RC:$src2, _.MemOp:$src3),
4013 OpcodeStr, "$src3, $src2", "$src2, $src3",
4014 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4017 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4018 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4019 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4020 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4022 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4023 AVX512FMA3Base, EVEX_B;
4027 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4028 X86VectorVTInfo _> {
4029 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4030 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4031 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4032 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4033 AVX512FMA3Base, EVEX_B, EVEX_RC;
4035 } // Constraints = "$src1 = $dst"
4037 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4038 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4039 let Predicates = [HasAVX512] in {
4040 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4041 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4042 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4044 let Predicates = [HasVLX, HasAVX512] in {
4045 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4046 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4047 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4048 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4052 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4053 SDNode OpNodeRnd > {
4054 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4056 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4057 avx512vl_f64_info>, VEX_W;
4060 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4061 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4062 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4063 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4064 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4065 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4068 let Constraints = "$src1 = $dst" in {
4069 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4070 X86VectorVTInfo _> {
4071 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4072 (ins _.RC:$src2, _.RC:$src3),
4073 OpcodeStr, "$src3, $src2", "$src2, $src3",
4074 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4077 let mayLoad = 1 in {
4078 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4079 (ins _.RC:$src2, _.MemOp:$src3),
4080 OpcodeStr, "$src3, $src2", "$src2, $src3",
4081 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4084 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4085 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4086 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4087 "$src2, ${src3}"##_.BroadcastStr,
4088 (_.VT (OpNode _.RC:$src2,
4089 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4090 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4094 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4095 X86VectorVTInfo _> {
4096 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4097 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4098 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4099 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4100 AVX512FMA3Base, EVEX_B, EVEX_RC;
4102 } // Constraints = "$src1 = $dst"
4104 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4105 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4106 let Predicates = [HasAVX512] in {
4107 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4108 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4109 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4111 let Predicates = [HasVLX, HasAVX512] in {
4112 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4113 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4114 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4115 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4119 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4120 SDNode OpNodeRnd > {
4121 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4123 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4124 avx512vl_f64_info>, VEX_W;
4127 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4128 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4129 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4130 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4131 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4132 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4134 let Constraints = "$src1 = $dst" in {
4135 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4136 X86VectorVTInfo _> {
4137 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4138 (ins _.RC:$src3, _.RC:$src2),
4139 OpcodeStr, "$src2, $src3", "$src3, $src2",
4140 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4143 let mayLoad = 1 in {
4144 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4145 (ins _.RC:$src3, _.MemOp:$src2),
4146 OpcodeStr, "$src2, $src3", "$src3, $src2",
4147 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4150 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4151 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4152 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4153 "$src3, ${src2}"##_.BroadcastStr,
4154 (_.VT (OpNode _.RC:$src1,
4155 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4156 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4160 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4161 X86VectorVTInfo _> {
4162 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4163 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4164 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4165 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4166 AVX512FMA3Base, EVEX_B, EVEX_RC;
4168 } // Constraints = "$src1 = $dst"
4170 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4171 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4172 let Predicates = [HasAVX512] in {
4173 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4174 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4175 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4177 let Predicates = [HasVLX, HasAVX512] in {
4178 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4179 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4180 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4181 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4185 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4186 SDNode OpNodeRnd > {
4187 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4189 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4190 avx512vl_f64_info>, VEX_W;
4193 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4194 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4195 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4196 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4197 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4198 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4201 let Constraints = "$src1 = $dst" in {
4202 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4203 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4204 dag RHS_r, dag RHS_m > {
4205 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4206 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4207 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4210 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4211 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4212 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4214 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4215 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4216 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4217 AVX512FMA3Base, EVEX_B, EVEX_RC;
4219 let isCodeGenOnly = 1 in {
4220 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4221 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4222 !strconcat(OpcodeStr,
4223 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4226 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4227 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4228 !strconcat(OpcodeStr,
4229 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4231 }// isCodeGenOnly = 1
4233 }// Constraints = "$src1 = $dst"
4235 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4236 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4239 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4240 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4241 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4242 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4243 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4245 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4247 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4248 (_.ScalarLdFrag addr:$src3))))>;
4250 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4251 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4252 (_.VT (OpNode _.RC:$src2,
4253 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4255 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4257 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4259 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4260 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4262 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4263 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4264 (_.VT (OpNode _.RC:$src1,
4265 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4267 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4269 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4271 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4272 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4275 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4276 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4277 let Predicates = [HasAVX512] in {
4278 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4279 OpNodeRnd, f32x_info, "SS">,
4280 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4281 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4282 OpNodeRnd, f64x_info, "SD">,
4283 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4287 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4288 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4289 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4290 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4292 //===----------------------------------------------------------------------===//
4293 // AVX-512 Scalar convert from sign integer to float/double
4294 //===----------------------------------------------------------------------===//
4296 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4297 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4298 PatFrag ld_frag, string asm> {
4299 let hasSideEffects = 0 in {
4300 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4301 (ins DstVT.FRC:$src1, SrcRC:$src),
4302 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4305 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4306 (ins DstVT.FRC:$src1, x86memop:$src),
4307 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4309 } // hasSideEffects = 0
4310 let isCodeGenOnly = 1 in {
4311 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4312 (ins DstVT.RC:$src1, SrcRC:$src2),
4313 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4314 [(set DstVT.RC:$dst,
4315 (OpNode (DstVT.VT DstVT.RC:$src1),
4317 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4319 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4320 (ins DstVT.RC:$src1, x86memop:$src2),
4321 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4322 [(set DstVT.RC:$dst,
4323 (OpNode (DstVT.VT DstVT.RC:$src1),
4324 (ld_frag addr:$src2),
4325 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4326 }//isCodeGenOnly = 1
4329 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4330 X86VectorVTInfo DstVT, string asm> {
4331 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4332 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4334 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4335 [(set DstVT.RC:$dst,
4336 (OpNode (DstVT.VT DstVT.RC:$src1),
4338 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4341 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4342 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4343 PatFrag ld_frag, string asm> {
4344 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4345 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4349 let Predicates = [HasAVX512] in {
4350 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4351 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4352 XS, EVEX_CD8<32, CD8VT1>;
4353 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4354 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4355 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4356 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4357 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4358 XD, EVEX_CD8<32, CD8VT1>;
4359 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4360 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4361 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4363 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4364 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4365 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4366 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4367 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4368 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4369 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4370 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4372 def : Pat<(f32 (sint_to_fp GR32:$src)),
4373 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4374 def : Pat<(f32 (sint_to_fp GR64:$src)),
4375 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4376 def : Pat<(f64 (sint_to_fp GR32:$src)),
4377 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4378 def : Pat<(f64 (sint_to_fp GR64:$src)),
4379 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4381 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4382 v4f32x_info, i32mem, loadi32,
4383 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4384 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4385 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4386 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4387 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4388 i32mem, loadi32, "cvtusi2sd{l}">,
4389 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4390 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4391 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4392 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4394 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4395 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4396 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4397 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4398 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4399 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4400 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4401 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4403 def : Pat<(f32 (uint_to_fp GR32:$src)),
4404 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4405 def : Pat<(f32 (uint_to_fp GR64:$src)),
4406 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4407 def : Pat<(f64 (uint_to_fp GR32:$src)),
4408 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4409 def : Pat<(f64 (uint_to_fp GR64:$src)),
4410 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4413 //===----------------------------------------------------------------------===//
4414 // AVX-512 Scalar convert from float/double to integer
4415 //===----------------------------------------------------------------------===//
4416 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4417 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4419 let hasSideEffects = 0 in {
4420 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4421 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4422 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4423 Requires<[HasAVX512]>;
4425 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4426 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4427 Requires<[HasAVX512]>;
4428 } // hasSideEffects = 0
4430 let Predicates = [HasAVX512] in {
4431 // Convert float/double to signed/unsigned int 32/64
4432 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4433 ssmem, sse_load_f32, "cvtss2si">,
4434 XS, EVEX_CD8<32, CD8VT1>;
4435 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4436 ssmem, sse_load_f32, "cvtss2si">,
4437 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4438 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4439 ssmem, sse_load_f32, "cvtss2usi">,
4440 XS, EVEX_CD8<32, CD8VT1>;
4441 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4442 int_x86_avx512_cvtss2usi64, ssmem,
4443 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4444 EVEX_CD8<32, CD8VT1>;
4445 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4446 sdmem, sse_load_f64, "cvtsd2si">,
4447 XD, EVEX_CD8<64, CD8VT1>;
4448 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4449 sdmem, sse_load_f64, "cvtsd2si">,
4450 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4451 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4452 sdmem, sse_load_f64, "cvtsd2usi">,
4453 XD, EVEX_CD8<64, CD8VT1>;
4454 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4455 int_x86_avx512_cvtsd2usi64, sdmem,
4456 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4457 EVEX_CD8<64, CD8VT1>;
4459 let isCodeGenOnly = 1 in {
4460 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4461 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4462 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4463 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4464 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4465 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4466 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4467 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4468 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4469 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4470 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4471 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4473 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4474 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4475 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4476 } // isCodeGenOnly = 1
4478 // Convert float/double to signed/unsigned int 32/64 with truncation
4479 let isCodeGenOnly = 1 in {
4480 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4481 ssmem, sse_load_f32, "cvttss2si">,
4482 XS, EVEX_CD8<32, CD8VT1>;
4483 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4484 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4485 "cvttss2si">, XS, VEX_W,
4486 EVEX_CD8<32, CD8VT1>;
4487 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4488 sdmem, sse_load_f64, "cvttsd2si">, XD,
4489 EVEX_CD8<64, CD8VT1>;
4490 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4491 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4492 "cvttsd2si">, XD, VEX_W,
4493 EVEX_CD8<64, CD8VT1>;
4494 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4495 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4496 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4497 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4498 int_x86_avx512_cvttss2usi64, ssmem,
4499 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4500 EVEX_CD8<32, CD8VT1>;
4501 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4502 int_x86_avx512_cvttsd2usi,
4503 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4504 EVEX_CD8<64, CD8VT1>;
4505 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4506 int_x86_avx512_cvttsd2usi64, sdmem,
4507 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4508 EVEX_CD8<64, CD8VT1>;
4509 } // isCodeGenOnly = 1
4511 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4512 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4514 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4515 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4516 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4517 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4518 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4519 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4522 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4523 loadf32, "cvttss2si">, XS,
4524 EVEX_CD8<32, CD8VT1>;
4525 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4526 loadf32, "cvttss2usi">, XS,
4527 EVEX_CD8<32, CD8VT1>;
4528 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4529 loadf32, "cvttss2si">, XS, VEX_W,
4530 EVEX_CD8<32, CD8VT1>;
4531 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4532 loadf32, "cvttss2usi">, XS, VEX_W,
4533 EVEX_CD8<32, CD8VT1>;
4534 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4535 loadf64, "cvttsd2si">, XD,
4536 EVEX_CD8<64, CD8VT1>;
4537 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4538 loadf64, "cvttsd2usi">, XD,
4539 EVEX_CD8<64, CD8VT1>;
4540 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4541 loadf64, "cvttsd2si">, XD, VEX_W,
4542 EVEX_CD8<64, CD8VT1>;
4543 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4544 loadf64, "cvttsd2usi">, XD, VEX_W,
4545 EVEX_CD8<64, CD8VT1>;
4547 //===----------------------------------------------------------------------===//
4548 // AVX-512 Convert form float to double and back
4549 //===----------------------------------------------------------------------===//
4550 let hasSideEffects = 0 in {
4551 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4552 (ins FR32X:$src1, FR32X:$src2),
4553 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4554 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4556 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4557 (ins FR32X:$src1, f32mem:$src2),
4558 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4559 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4560 EVEX_CD8<32, CD8VT1>;
4562 // Convert scalar double to scalar single
4563 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4564 (ins FR64X:$src1, FR64X:$src2),
4565 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4566 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4568 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4569 (ins FR64X:$src1, f64mem:$src2),
4570 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4571 []>, EVEX_4V, VEX_LIG, VEX_W,
4572 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4575 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4576 Requires<[HasAVX512]>;
4577 def : Pat<(fextend (loadf32 addr:$src)),
4578 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4580 def : Pat<(extloadf32 addr:$src),
4581 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4582 Requires<[HasAVX512, OptForSize]>;
4584 def : Pat<(extloadf32 addr:$src),
4585 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4586 Requires<[HasAVX512, OptForSpeed]>;
4588 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4589 Requires<[HasAVX512]>;
4591 //===----------------------------------------------------------------------===//
4592 // AVX-512 Vector convert from signed/unsigned integer to float/double
4593 // and from float/double to signed/unsigned integer
4594 //===----------------------------------------------------------------------===//
4596 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4597 X86VectorVTInfo _Src, SDNode OpNode,
4598 string Broadcast = _.BroadcastStr,
4599 string Alias = ""> {
4601 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4602 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4603 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4605 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4606 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4607 (_.VT (OpNode (_Src.VT
4608 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4610 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4611 (ins _Src.MemOp:$src), OpcodeStr,
4612 "${src}"##Broadcast, "${src}"##Broadcast,
4613 (_.VT (OpNode (_Src.VT
4614 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4617 // Coversion with SAE - suppress all exceptions
4618 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4619 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4620 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4621 (ins _Src.RC:$src), OpcodeStr,
4622 "{sae}, $src", "$src, {sae}",
4623 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4624 (i32 FROUND_NO_EXC)))>,
4628 // Conversion with rounding control (RC)
4629 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4630 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4631 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4632 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
4633 "$rc, $src", "$src, $rc",
4634 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
4635 EVEX, EVEX_B, EVEX_RC;
4638 // Extend Float to Double
4639 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
4640 let Predicates = [HasAVX512] in {
4641 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
4642 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
4643 X86vfpextRnd>, EVEX_V512;
4645 let Predicates = [HasVLX] in {
4646 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
4647 X86vfpext, "{1to2}">, EVEX_V128;
4648 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
4653 // Truncate Double to Float
4654 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
4655 let Predicates = [HasAVX512] in {
4656 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
4657 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
4658 X86vfproundRnd>, EVEX_V512;
4660 let Predicates = [HasVLX] in {
4661 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
4662 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
4663 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
4664 "{1to4}", "{y}">, EVEX_V256;
4668 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
4669 VEX_W, PD, EVEX_CD8<64, CD8VF>;
4670 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
4671 PS, EVEX_CD8<32, CD8VH>;
4673 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4674 (VCVTPS2PDZrm addr:$src)>;
4676 let Predicates = [HasVLX] in {
4677 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
4678 (VCVTPS2PDZ256rm addr:$src)>;
4681 // Convert Signed/Unsigned Doubleword to Double
4682 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4684 // No rounding in this op
4685 let Predicates = [HasAVX512] in
4686 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
4689 let Predicates = [HasVLX] in {
4690 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
4691 OpNode128, "{1to2}">, EVEX_V128;
4692 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
4697 // Convert Signed/Unsigned Doubleword to Float
4698 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
4700 let Predicates = [HasAVX512] in
4701 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
4702 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
4703 OpNodeRnd>, EVEX_V512;
4705 let Predicates = [HasVLX] in {
4706 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
4708 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
4713 // Convert Float to Signed/Unsigned Doubleword with truncation
4714 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
4715 SDNode OpNode, SDNode OpNodeRnd> {
4716 let Predicates = [HasAVX512] in {
4717 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
4718 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
4719 OpNodeRnd>, EVEX_V512;
4721 let Predicates = [HasVLX] in {
4722 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
4724 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
4729 // Convert Float to Signed/Unsigned Doubleword
4730 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
4731 SDNode OpNode, SDNode OpNodeRnd> {
4732 let Predicates = [HasAVX512] in {
4733 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
4734 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
4735 OpNodeRnd>, EVEX_V512;
4737 let Predicates = [HasVLX] in {
4738 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
4740 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
4745 // Convert Double to Signed/Unsigned Doubleword with truncation
4746 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
4747 SDNode OpNode, SDNode OpNodeRnd> {
4748 let Predicates = [HasAVX512] in {
4749 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
4750 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
4751 OpNodeRnd>, EVEX_V512;
4753 let Predicates = [HasVLX] in {
4754 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4755 // memory forms of these instructions in Asm Parcer. They have the same
4756 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4757 // due to the same reason.
4758 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
4759 "{1to2}", "{x}">, EVEX_V128;
4760 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
4761 "{1to4}", "{y}">, EVEX_V256;
4765 // Convert Double to Signed/Unsigned Doubleword
4766 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
4767 SDNode OpNode, SDNode OpNodeRnd> {
4768 let Predicates = [HasAVX512] in {
4769 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
4770 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
4771 OpNodeRnd>, EVEX_V512;
4773 let Predicates = [HasVLX] in {
4774 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4775 // memory forms of these instructions in Asm Parcer. They have the same
4776 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4777 // due to the same reason.
4778 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
4779 "{1to2}", "{x}">, EVEX_V128;
4780 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
4781 "{1to4}", "{y}">, EVEX_V256;
4785 // Convert Double to Signed/Unsigned Quardword
4786 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
4787 SDNode OpNode, SDNode OpNodeRnd> {
4788 let Predicates = [HasDQI] in {
4789 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
4790 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
4791 OpNodeRnd>, EVEX_V512;
4793 let Predicates = [HasDQI, HasVLX] in {
4794 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
4796 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
4801 // Convert Double to Signed/Unsigned Quardword with truncation
4802 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
4803 SDNode OpNode, SDNode OpNodeRnd> {
4804 let Predicates = [HasDQI] in {
4805 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
4806 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
4807 OpNodeRnd>, EVEX_V512;
4809 let Predicates = [HasDQI, HasVLX] in {
4810 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
4812 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
4817 // Convert Signed/Unsigned Quardword to Double
4818 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
4819 SDNode OpNode, SDNode OpNodeRnd> {
4820 let Predicates = [HasDQI] in {
4821 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
4822 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
4823 OpNodeRnd>, EVEX_V512;
4825 let Predicates = [HasDQI, HasVLX] in {
4826 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
4828 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
4833 // Convert Float to Signed/Unsigned Quardword
4834 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
4835 SDNode OpNode, SDNode OpNodeRnd> {
4836 let Predicates = [HasDQI] in {
4837 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
4838 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
4839 OpNodeRnd>, EVEX_V512;
4841 let Predicates = [HasDQI, HasVLX] in {
4842 // Explicitly specified broadcast string, since we take only 2 elements
4843 // from v4f32x_info source
4844 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
4845 "{1to2}">, EVEX_V128;
4846 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
4851 // Convert Float to Signed/Unsigned Quardword with truncation
4852 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
4853 SDNode OpNode, SDNode OpNodeRnd> {
4854 let Predicates = [HasDQI] in {
4855 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
4856 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
4857 OpNodeRnd>, EVEX_V512;
4859 let Predicates = [HasDQI, HasVLX] in {
4860 // Explicitly specified broadcast string, since we take only 2 elements
4861 // from v4f32x_info source
4862 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
4863 "{1to2}">, EVEX_V128;
4864 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
4869 // Convert Signed/Unsigned Quardword to Float
4870 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
4871 SDNode OpNode, SDNode OpNodeRnd> {
4872 let Predicates = [HasDQI] in {
4873 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
4874 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
4875 OpNodeRnd>, EVEX_V512;
4877 let Predicates = [HasDQI, HasVLX] in {
4878 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4879 // memory forms of these instructions in Asm Parcer. They have the same
4880 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4881 // due to the same reason.
4882 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
4883 "{1to2}", "{x}">, EVEX_V128;
4884 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
4885 "{1to4}", "{y}">, EVEX_V256;
4889 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
4890 EVEX_CD8<32, CD8VH>;
4892 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
4894 PS, EVEX_CD8<32, CD8VF>;
4896 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
4898 XS, EVEX_CD8<32, CD8VF>;
4900 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
4902 PD, VEX_W, EVEX_CD8<64, CD8VF>;
4904 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
4905 X86VFpToUintRnd>, PS,
4906 EVEX_CD8<32, CD8VF>;
4908 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
4909 X86VFpToUintRnd>, PS, VEX_W,
4910 EVEX_CD8<64, CD8VF>;
4912 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
4913 XS, EVEX_CD8<32, CD8VH>;
4915 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
4916 X86VUintToFpRnd>, XD,
4917 EVEX_CD8<32, CD8VF>;
4919 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
4920 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
4922 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
4923 X86cvtpd2IntRnd>, XD, VEX_W,
4924 EVEX_CD8<64, CD8VF>;
4926 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
4928 PS, EVEX_CD8<32, CD8VF>;
4929 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
4930 X86cvtpd2UIntRnd>, VEX_W,
4931 PS, EVEX_CD8<64, CD8VF>;
4933 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
4934 X86cvtpd2IntRnd>, VEX_W,
4935 PD, EVEX_CD8<64, CD8VF>;
4937 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
4938 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
4940 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
4941 X86cvtpd2UIntRnd>, VEX_W,
4942 PD, EVEX_CD8<64, CD8VF>;
4944 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
4945 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
4947 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
4948 X86VFpToSlongRnd>, VEX_W,
4949 PD, EVEX_CD8<64, CD8VF>;
4951 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
4952 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
4954 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
4955 X86VFpToUlongRnd>, VEX_W,
4956 PD, EVEX_CD8<64, CD8VF>;
4958 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
4959 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
4961 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
4962 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
4964 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
4965 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
4967 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
4968 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
4970 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
4971 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
4973 let Predicates = [NoVLX] in {
4974 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4975 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4976 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4978 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4979 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4980 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4982 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4983 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4984 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4986 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4987 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4988 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4990 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4991 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4992 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4995 let Predicates = [HasAVX512] in {
4996 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4997 (VCVTPD2PSZrm addr:$src)>;
4998 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4999 (VCVTPS2PDZrm addr:$src)>;
5002 //===----------------------------------------------------------------------===//
5003 // Half precision conversion instructions
5004 //===----------------------------------------------------------------------===//
5005 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5006 X86MemOperand x86memop> {
5007 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5008 "vcvtph2ps\t{$src, $dst|$dst, $src}",
5010 let hasSideEffects = 0, mayLoad = 1 in
5011 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5012 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5015 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
5016 X86MemOperand x86memop> {
5017 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
5018 (ins srcRC:$src1, i32u8imm:$src2),
5019 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5021 let hasSideEffects = 0, mayStore = 1 in
5022 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5023 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
5024 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
5027 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5028 EVEX_CD8<32, CD8VH>;
5029 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
5030 EVEX_CD8<32, CD8VH>;
5032 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
5033 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
5034 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
5036 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5037 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5038 (VCVTPH2PSZrr VR256X:$src)>;
5040 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5041 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5042 "ucomiss">, PS, EVEX, VEX_LIG,
5043 EVEX_CD8<32, CD8VT1>;
5044 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5045 "ucomisd">, PD, EVEX,
5046 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5047 let Pattern = []<dag> in {
5048 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5049 "comiss">, PS, EVEX, VEX_LIG,
5050 EVEX_CD8<32, CD8VT1>;
5051 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5052 "comisd">, PD, EVEX,
5053 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5055 let isCodeGenOnly = 1 in {
5056 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5057 load, "ucomiss">, PS, EVEX, VEX_LIG,
5058 EVEX_CD8<32, CD8VT1>;
5059 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5060 load, "ucomisd">, PD, EVEX,
5061 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5063 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5064 load, "comiss">, PS, EVEX, VEX_LIG,
5065 EVEX_CD8<32, CD8VT1>;
5066 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5067 load, "comisd">, PD, EVEX,
5068 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5072 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5073 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
5074 X86MemOperand x86memop> {
5075 let hasSideEffects = 0 in {
5076 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5077 (ins RC:$src1, RC:$src2),
5078 !strconcat(OpcodeStr,
5079 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5080 let mayLoad = 1 in {
5081 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5082 (ins RC:$src1, x86memop:$src2),
5083 !strconcat(OpcodeStr,
5084 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5089 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
5090 EVEX_CD8<32, CD8VT1>;
5091 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
5092 VEX_W, EVEX_CD8<64, CD8VT1>;
5093 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
5094 EVEX_CD8<32, CD8VT1>;
5095 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
5096 VEX_W, EVEX_CD8<64, CD8VT1>;
5098 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
5099 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5100 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5101 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5103 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
5104 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5105 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5106 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5108 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
5109 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5110 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5111 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5113 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
5114 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5115 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5116 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5118 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5119 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5120 X86VectorVTInfo _> {
5121 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5122 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5123 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5124 let mayLoad = 1 in {
5125 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5126 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5128 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5129 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5130 (ins _.ScalarMemOp:$src), OpcodeStr,
5131 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5133 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5138 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5139 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5140 EVEX_V512, EVEX_CD8<32, CD8VF>;
5141 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5142 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5144 // Define only if AVX512VL feature is present.
5145 let Predicates = [HasVLX] in {
5146 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5147 OpNode, v4f32x_info>,
5148 EVEX_V128, EVEX_CD8<32, CD8VF>;
5149 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5150 OpNode, v8f32x_info>,
5151 EVEX_V256, EVEX_CD8<32, CD8VF>;
5152 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5153 OpNode, v2f64x_info>,
5154 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5155 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5156 OpNode, v4f64x_info>,
5157 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5161 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5162 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5164 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5165 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5166 (VRSQRT14PSZr VR512:$src)>;
5167 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5168 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5169 (VRSQRT14PDZr VR512:$src)>;
5171 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5172 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5173 (VRCP14PSZr VR512:$src)>;
5174 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5175 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5176 (VRCP14PDZr VR512:$src)>;
5178 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5179 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5182 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5183 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5184 "$src2, $src1", "$src1, $src2",
5185 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5186 (i32 FROUND_CURRENT))>;
5188 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5189 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5190 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5191 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5192 (i32 FROUND_NO_EXC))>, EVEX_B;
5194 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5195 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5196 "$src2, $src1", "$src1, $src2",
5197 (OpNode (_.VT _.RC:$src1),
5198 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5199 (i32 FROUND_CURRENT))>;
5202 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5203 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5204 EVEX_CD8<32, CD8VT1>;
5205 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5206 EVEX_CD8<64, CD8VT1>, VEX_W;
5209 let hasSideEffects = 0, Predicates = [HasERI] in {
5210 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5211 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5214 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5215 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5217 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5220 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5221 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5222 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5224 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5225 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5227 (bitconvert (_.LdFrag addr:$src))),
5228 (i32 FROUND_CURRENT))>;
5230 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5231 (ins _.MemOp:$src), OpcodeStr,
5232 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5234 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5235 (i32 FROUND_CURRENT))>, EVEX_B;
5237 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5239 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5240 (ins _.RC:$src), OpcodeStr,
5241 "{sae}, $src", "$src, {sae}",
5242 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5245 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5246 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5247 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5248 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5249 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5250 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5251 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5254 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5256 // Define only if AVX512VL feature is present.
5257 let Predicates = [HasVLX] in {
5258 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5259 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5260 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5261 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5262 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5263 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5264 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5265 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5268 let Predicates = [HasERI], hasSideEffects = 0 in {
5270 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5271 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5272 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5274 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5275 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5277 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5278 SDNode OpNodeRnd, X86VectorVTInfo _>{
5279 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5280 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5281 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5282 EVEX, EVEX_B, EVEX_RC;
5285 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5286 SDNode OpNode, X86VectorVTInfo _>{
5287 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5288 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5289 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5290 let mayLoad = 1 in {
5291 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5292 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5294 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5296 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5297 (ins _.ScalarMemOp:$src), OpcodeStr,
5298 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5300 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5305 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
5306 Intrinsic F32Int, Intrinsic F64Int,
5307 OpndItins itins_s, OpndItins itins_d> {
5308 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
5309 (ins FR32X:$src1, FR32X:$src2),
5310 !strconcat(OpcodeStr,
5311 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5312 [], itins_s.rr>, XS, EVEX_4V;
5313 let isCodeGenOnly = 1 in
5314 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
5315 (ins VR128X:$src1, VR128X:$src2),
5316 !strconcat(OpcodeStr,
5317 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5319 (F32Int VR128X:$src1, VR128X:$src2))],
5320 itins_s.rr>, XS, EVEX_4V;
5321 let mayLoad = 1 in {
5322 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
5323 (ins FR32X:$src1, f32mem:$src2),
5324 !strconcat(OpcodeStr,
5325 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5326 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5327 let isCodeGenOnly = 1 in
5328 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
5329 (ins VR128X:$src1, ssmem:$src2),
5330 !strconcat(OpcodeStr,
5331 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5333 (F32Int VR128X:$src1, sse_load_f32:$src2))],
5334 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5336 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
5337 (ins FR64X:$src1, FR64X:$src2),
5338 !strconcat(OpcodeStr,
5339 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5341 let isCodeGenOnly = 1 in
5342 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
5343 (ins VR128X:$src1, VR128X:$src2),
5344 !strconcat(OpcodeStr,
5345 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5347 (F64Int VR128X:$src1, VR128X:$src2))],
5348 itins_s.rr>, XD, EVEX_4V, VEX_W;
5349 let mayLoad = 1 in {
5350 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
5351 (ins FR64X:$src1, f64mem:$src2),
5352 !strconcat(OpcodeStr,
5353 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5354 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5355 let isCodeGenOnly = 1 in
5356 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
5357 (ins VR128X:$src1, sdmem:$src2),
5358 !strconcat(OpcodeStr,
5359 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5361 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
5362 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5366 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5368 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5370 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5371 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5373 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5374 // Define only if AVX512VL feature is present.
5375 let Predicates = [HasVLX] in {
5376 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5377 OpNode, v4f32x_info>,
5378 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5379 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5380 OpNode, v8f32x_info>,
5381 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5382 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5383 OpNode, v2f64x_info>,
5384 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5385 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5386 OpNode, v4f64x_info>,
5387 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5391 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5393 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5394 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5395 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5396 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5399 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5400 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5402 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
5403 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
5404 SSE_SQRTSS, SSE_SQRTSD>;
5406 let Predicates = [HasAVX512] in {
5407 def : Pat<(f32 (fsqrt FR32X:$src)),
5408 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5409 def : Pat<(f32 (fsqrt (load addr:$src))),
5410 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5411 Requires<[OptForSize]>;
5412 def : Pat<(f64 (fsqrt FR64X:$src)),
5413 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5414 def : Pat<(f64 (fsqrt (load addr:$src))),
5415 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5416 Requires<[OptForSize]>;
5418 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5419 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5420 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5421 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5422 Requires<[OptForSize]>;
5424 def : Pat<(f32 (X86frcp FR32X:$src)),
5425 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5426 def : Pat<(f32 (X86frcp (load addr:$src))),
5427 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5428 Requires<[OptForSize]>;
5430 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5431 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5432 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5434 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5435 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5437 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5438 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5439 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5441 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5442 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5446 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5448 let ExeDomain = _.ExeDomain in {
5449 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5450 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5451 "$src3, $src2, $src1", "$src1, $src2, $src3",
5452 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5453 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5455 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5456 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5457 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5458 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5459 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5462 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5463 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5464 "$src3, $src2, $src1", "$src1, $src2, $src3",
5465 (_.VT (X86RndScales (_.VT _.RC:$src1),
5466 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5467 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5469 let Predicates = [HasAVX512] in {
5470 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5471 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5472 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5473 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5474 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5475 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5476 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5477 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5478 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5479 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5480 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5481 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5482 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5483 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5484 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5486 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5487 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5488 addr:$src, (i32 0x1))), _.FRC)>;
5489 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5490 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5491 addr:$src, (i32 0x2))), _.FRC)>;
5492 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5493 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5494 addr:$src, (i32 0x3))), _.FRC)>;
5495 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5496 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5497 addr:$src, (i32 0x4))), _.FRC)>;
5498 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5499 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5500 addr:$src, (i32 0xc))), _.FRC)>;
5504 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5505 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5507 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5508 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5510 //-------------------------------------------------
5511 // Integer truncate and extend operations
5512 //-------------------------------------------------
5514 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5515 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5516 X86MemOperand x86memop> {
5518 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5519 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5520 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5523 // for intrinsic patter match
5524 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5525 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5527 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5530 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5531 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5532 DestInfo.ImmAllZerosV)),
5533 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5536 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5537 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5538 DestInfo.RC:$src0)),
5539 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5540 DestInfo.KRCWM:$mask ,
5543 let mayStore = 1 in {
5544 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5545 (ins x86memop:$dst, SrcInfo.RC:$src),
5546 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5549 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5550 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5551 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5556 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5557 X86VectorVTInfo DestInfo,
5558 PatFrag truncFrag, PatFrag mtruncFrag > {
5560 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5561 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5562 addr:$dst, SrcInfo.RC:$src)>;
5564 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5565 (SrcInfo.VT SrcInfo.RC:$src)),
5566 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5567 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5570 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5571 X86VectorVTInfo DestInfo, string sat > {
5573 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5574 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5575 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5576 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5577 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5578 (SrcInfo.VT SrcInfo.RC:$src))>;
5580 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5581 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5582 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5583 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5584 (SrcInfo.VT SrcInfo.RC:$src))>;
5587 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5588 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5589 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5590 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5591 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5592 Predicate prd = HasAVX512>{
5594 let Predicates = [HasVLX, prd] in {
5595 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5596 DestInfoZ128, x86memopZ128>,
5597 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5598 truncFrag, mtruncFrag>, EVEX_V128;
5600 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5601 DestInfoZ256, x86memopZ256>,
5602 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5603 truncFrag, mtruncFrag>, EVEX_V256;
5605 let Predicates = [prd] in
5606 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5607 DestInfoZ, x86memopZ>,
5608 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5609 truncFrag, mtruncFrag>, EVEX_V512;
5612 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5613 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5614 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5615 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5616 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5618 let Predicates = [HasVLX, prd] in {
5619 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5620 DestInfoZ128, x86memopZ128>,
5621 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5624 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5625 DestInfoZ256, x86memopZ256>,
5626 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5629 let Predicates = [prd] in
5630 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5631 DestInfoZ, x86memopZ>,
5632 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5636 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5637 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5638 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5639 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5641 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5642 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5643 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5644 sat>, EVEX_CD8<8, CD8VO>;
5647 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5648 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5649 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5650 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
5652 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
5653 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
5654 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5655 sat>, EVEX_CD8<16, CD8VQ>;
5658 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5659 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5660 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5661 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
5663 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
5664 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
5665 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5666 sat>, EVEX_CD8<32, CD8VH>;
5669 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5670 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5671 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5672 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
5674 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
5675 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
5676 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5677 sat>, EVEX_CD8<8, CD8VQ>;
5680 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5681 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5682 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5683 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
5685 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
5686 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
5687 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5688 sat>, EVEX_CD8<16, CD8VH>;
5691 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5692 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
5693 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5694 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
5696 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
5697 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
5698 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5699 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
5702 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
5703 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
5704 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
5706 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
5707 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
5708 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
5710 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
5711 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
5712 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
5714 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
5715 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
5716 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
5718 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
5719 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
5720 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
5722 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
5723 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
5724 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
5726 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5727 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5728 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5730 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5731 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5732 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5735 let mayLoad = 1 in {
5736 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5737 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5738 (DestInfo.VT (LdFrag addr:$src))>,
5743 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5744 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5745 let Predicates = [HasVLX, HasBWI] in {
5746 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5747 v16i8x_info, i64mem, LdFrag, OpNode>,
5748 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5750 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5751 v16i8x_info, i128mem, LdFrag, OpNode>,
5752 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5754 let Predicates = [HasBWI] in {
5755 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
5756 v32i8x_info, i256mem, LdFrag, OpNode>,
5757 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
5761 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5762 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5763 let Predicates = [HasVLX, HasAVX512] in {
5764 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5765 v16i8x_info, i32mem, LdFrag, OpNode>,
5766 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
5768 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5769 v16i8x_info, i64mem, LdFrag, OpNode>,
5770 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
5772 let Predicates = [HasAVX512] in {
5773 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5774 v16i8x_info, i128mem, LdFrag, OpNode>,
5775 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
5779 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5780 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5781 let Predicates = [HasVLX, HasAVX512] in {
5782 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5783 v16i8x_info, i16mem, LdFrag, OpNode>,
5784 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
5786 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5787 v16i8x_info, i32mem, LdFrag, OpNode>,
5788 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
5790 let Predicates = [HasAVX512] in {
5791 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5792 v16i8x_info, i64mem, LdFrag, OpNode>,
5793 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
5797 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5798 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5799 let Predicates = [HasVLX, HasAVX512] in {
5800 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5801 v8i16x_info, i64mem, LdFrag, OpNode>,
5802 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
5804 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5805 v8i16x_info, i128mem, LdFrag, OpNode>,
5806 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
5808 let Predicates = [HasAVX512] in {
5809 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5810 v16i16x_info, i256mem, LdFrag, OpNode>,
5811 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
5815 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5816 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5817 let Predicates = [HasVLX, HasAVX512] in {
5818 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5819 v8i16x_info, i32mem, LdFrag, OpNode>,
5820 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
5822 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5823 v8i16x_info, i64mem, LdFrag, OpNode>,
5824 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
5826 let Predicates = [HasAVX512] in {
5827 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5828 v8i16x_info, i128mem, LdFrag, OpNode>,
5829 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
5833 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5834 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
5836 let Predicates = [HasVLX, HasAVX512] in {
5837 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5838 v4i32x_info, i64mem, LdFrag, OpNode>,
5839 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
5841 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5842 v4i32x_info, i128mem, LdFrag, OpNode>,
5843 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
5845 let Predicates = [HasAVX512] in {
5846 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5847 v8i32x_info, i256mem, LdFrag, OpNode>,
5848 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
5852 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
5853 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
5854 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
5855 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
5856 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
5857 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
5860 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
5861 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
5862 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
5863 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
5864 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
5865 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
5867 //===----------------------------------------------------------------------===//
5868 // GATHER - SCATTER Operations
5870 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5871 X86MemOperand memop, PatFrag GatherNode> {
5872 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
5873 ExeDomain = _.ExeDomain in
5874 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5875 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5876 !strconcat(OpcodeStr#_.Suffix,
5877 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5878 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5879 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5880 vectoraddr:$src2))]>, EVEX, EVEX_K,
5881 EVEX_CD8<_.EltSize, CD8VT1>;
5884 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
5885 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5886 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
5887 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
5888 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
5889 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
5890 let Predicates = [HasVLX] in {
5891 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
5892 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
5893 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
5894 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
5895 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
5896 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
5897 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5898 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
5902 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
5903 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5904 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
5905 mgatherv16i32>, EVEX_V512;
5906 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
5907 mgatherv8i64>, EVEX_V512;
5908 let Predicates = [HasVLX] in {
5909 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
5910 vy32xmem, mgatherv8i32>, EVEX_V256;
5911 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5912 vy64xmem, mgatherv4i64>, EVEX_V256;
5913 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
5914 vx32xmem, mgatherv4i32>, EVEX_V128;
5915 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5916 vx64xmem, mgatherv2i64>, EVEX_V128;
5921 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
5922 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
5924 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
5925 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
5927 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5928 X86MemOperand memop, PatFrag ScatterNode> {
5930 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
5932 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5933 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5934 !strconcat(OpcodeStr#_.Suffix,
5935 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5936 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5937 _.KRCWM:$mask, vectoraddr:$dst))]>,
5938 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5941 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
5942 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5943 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
5944 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
5945 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
5946 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
5947 let Predicates = [HasVLX] in {
5948 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
5949 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
5950 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
5951 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
5952 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
5953 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
5954 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
5955 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
5959 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
5960 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5961 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
5962 mscatterv16i32>, EVEX_V512;
5963 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
5964 mscatterv8i64>, EVEX_V512;
5965 let Predicates = [HasVLX] in {
5966 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
5967 vy32xmem, mscatterv8i32>, EVEX_V256;
5968 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
5969 vy64xmem, mscatterv4i64>, EVEX_V256;
5970 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
5971 vx32xmem, mscatterv4i32>, EVEX_V128;
5972 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
5973 vx64xmem, mscatterv2i64>, EVEX_V128;
5977 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
5978 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
5980 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
5981 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
5984 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5985 RegisterClass KRC, X86MemOperand memop> {
5986 let Predicates = [HasPFI], hasSideEffects = 1 in
5987 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5988 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5992 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5993 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5995 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5996 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5998 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5999 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6001 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6002 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6004 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6005 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6007 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6008 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6010 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6011 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6013 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6014 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6016 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6017 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6019 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6020 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6022 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6023 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6025 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6026 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6028 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6029 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6031 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6032 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6034 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6035 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6037 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6038 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6039 //===----------------------------------------------------------------------===//
6040 // VSHUFPS - VSHUFPD Operations
6042 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
6043 ValueType vt, string OpcodeStr, PatFrag mem_frag,
6045 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
6046 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6047 !strconcat(OpcodeStr,
6048 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6049 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
6050 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
6051 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
6052 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
6053 (ins RC:$src1, RC:$src2, u8imm:$src3),
6054 !strconcat(OpcodeStr,
6055 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6056 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
6057 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
6058 EVEX_4V, Sched<[WriteShuffle]>;
6061 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
6062 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
6063 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
6064 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
6066 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
6067 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
6068 def : Pat<(v16i32 (X86Shufp VR512:$src1,
6069 (loadv16i32 addr:$src2), (i8 imm:$imm))),
6070 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
6072 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
6073 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
6074 def : Pat<(v8i64 (X86Shufp VR512:$src1,
6075 (loadv8i64 addr:$src2), (i8 imm:$imm))),
6076 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
6078 // Helper fragments to match sext vXi1 to vXiY.
6079 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6080 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6082 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
6083 RegisterClass RC, RegisterClass KRC,
6084 X86MemOperand x86memop,
6085 X86MemOperand x86scalar_mop, string BrdcstStr> {
6086 let hasSideEffects = 0 in {
6087 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
6089 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
6092 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6093 (ins x86memop:$src),
6094 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
6097 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6098 (ins x86scalar_mop:$src),
6099 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
6100 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
6102 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
6103 (ins KRC:$mask, RC:$src),
6104 !strconcat(OpcodeStr,
6105 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
6108 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6109 (ins KRC:$mask, x86memop:$src),
6110 !strconcat(OpcodeStr,
6111 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
6114 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6115 (ins KRC:$mask, x86scalar_mop:$src),
6116 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
6117 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
6119 []>, EVEX, EVEX_KZ, EVEX_B;
6121 let Constraints = "$src1 = $dst" in {
6122 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
6123 (ins RC:$src1, KRC:$mask, RC:$src2),
6124 !strconcat(OpcodeStr,
6125 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6128 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6129 (ins RC:$src1, KRC:$mask, x86memop:$src2),
6130 !strconcat(OpcodeStr,
6131 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6134 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6135 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
6136 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
6137 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
6138 []>, EVEX, EVEX_K, EVEX_B;
6143 let Predicates = [HasCDI] in {
6144 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
6145 i512mem, i32mem, "{1to16}">,
6146 EVEX_V512, EVEX_CD8<32, CD8VF>;
6149 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
6150 i512mem, i64mem, "{1to8}">,
6151 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
6155 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
6157 (VPCONFLICTDrrk VR512:$src1,
6158 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
6160 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
6162 (VPCONFLICTQrrk VR512:$src1,
6163 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
6165 let Predicates = [HasCDI] in {
6166 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
6167 i512mem, i32mem, "{1to16}">,
6168 EVEX_V512, EVEX_CD8<32, CD8VF>;
6171 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
6172 i512mem, i64mem, "{1to8}">,
6173 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
6177 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
6179 (VPLZCNTDrrk VR512:$src1,
6180 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
6182 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
6184 (VPLZCNTQrrk VR512:$src1,
6185 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
6187 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
6188 (VPLZCNTDrm addr:$src)>;
6189 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
6190 (VPLZCNTDrr VR512:$src)>;
6191 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
6192 (VPLZCNTQrm addr:$src)>;
6193 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
6194 (VPLZCNTQrr VR512:$src)>;
6196 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6197 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6198 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6200 def : Pat<(store VK1:$src, addr:$dst),
6202 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6203 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6205 def : Pat<(store VK8:$src, addr:$dst),
6207 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6208 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6210 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6211 (truncstore node:$val, node:$ptr), [{
6212 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6215 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6216 (MOV8mr addr:$dst, GR8:$src)>;
6218 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6219 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6220 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6221 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6224 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6225 string OpcodeStr, Predicate prd> {
6226 let Predicates = [prd] in
6227 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6229 let Predicates = [prd, HasVLX] in {
6230 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6231 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6235 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6236 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6238 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6240 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6242 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6246 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6248 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6249 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6250 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6251 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6254 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6255 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6256 let Predicates = [prd] in
6257 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6260 let Predicates = [prd, HasVLX] in {
6261 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6263 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6268 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6269 avx512vl_i8_info, HasBWI>;
6270 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6271 avx512vl_i16_info, HasBWI>, VEX_W;
6272 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6273 avx512vl_i32_info, HasDQI>;
6274 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6275 avx512vl_i64_info, HasDQI>, VEX_W;
6277 //===----------------------------------------------------------------------===//
6278 // AVX-512 - COMPRESS and EXPAND
6281 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6283 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6284 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6285 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6287 let mayStore = 1 in {
6288 def mr : AVX5128I<opc, MRMDestMem, (outs),
6289 (ins _.MemOp:$dst, _.RC:$src),
6290 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6291 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6293 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6294 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6295 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6296 [(store (_.VT (vselect _.KRCWM:$mask,
6297 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6299 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6303 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6304 AVX512VLVectorVTInfo VTInfo> {
6305 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6307 let Predicates = [HasVLX] in {
6308 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6309 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6313 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6315 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6317 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6319 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6323 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6325 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6326 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6327 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6330 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6331 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6332 (_.VT (X86expand (_.VT (bitconvert
6333 (_.LdFrag addr:$src1)))))>,
6334 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6337 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6338 AVX512VLVectorVTInfo VTInfo> {
6339 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6341 let Predicates = [HasVLX] in {
6342 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6343 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6347 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6349 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6351 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6353 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6356 //handle instruction reg_vec1 = op(reg_vec,imm)
6358 // op(broadcast(eltVt),imm)
6359 //all instruction created with FROUND_CURRENT
6360 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6362 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6363 (ins _.RC:$src1, i32u8imm:$src2),
6364 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6365 (OpNode (_.VT _.RC:$src1),
6367 (i32 FROUND_CURRENT))>;
6368 let mayLoad = 1 in {
6369 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6370 (ins _.MemOp:$src1, i32u8imm:$src2),
6371 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6372 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6374 (i32 FROUND_CURRENT))>;
6375 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6376 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6377 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6378 "${src1}"##_.BroadcastStr##", $src2",
6379 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6381 (i32 FROUND_CURRENT))>, EVEX_B;
6385 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6386 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6387 SDNode OpNode, X86VectorVTInfo _>{
6388 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6389 (ins _.RC:$src1, i32u8imm:$src2),
6390 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6391 "$src1, {sae}, $src2",
6392 (OpNode (_.VT _.RC:$src1),
6394 (i32 FROUND_NO_EXC))>, EVEX_B;
6397 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6398 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6399 let Predicates = [prd] in {
6400 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6401 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6404 let Predicates = [prd, HasVLX] in {
6405 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6407 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6412 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6413 // op(reg_vec2,mem_vec,imm)
6414 // op(reg_vec2,broadcast(eltVt),imm)
6415 //all instruction created with FROUND_CURRENT
6416 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6418 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6419 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6420 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6421 (OpNode (_.VT _.RC:$src1),
6424 (i32 FROUND_CURRENT))>;
6425 let mayLoad = 1 in {
6426 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6427 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6428 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6429 (OpNode (_.VT _.RC:$src1),
6430 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6432 (i32 FROUND_CURRENT))>;
6433 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6434 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6435 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6436 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6437 (OpNode (_.VT _.RC:$src1),
6438 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6440 (i32 FROUND_CURRENT))>, EVEX_B;
6444 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6445 // op(reg_vec2,mem_vec,imm)
6446 // op(reg_vec2,broadcast(eltVt),imm)
6447 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6449 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6450 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6451 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6452 (OpNode (_.VT _.RC:$src1),
6455 let mayLoad = 1 in {
6456 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6457 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
6458 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6459 (OpNode (_.VT _.RC:$src1),
6460 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6462 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6463 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6464 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6465 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6466 (OpNode (_.VT _.RC:$src1),
6467 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6468 (i8 imm:$src3))>, EVEX_B;
6472 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6473 // op(reg_vec2,mem_scalar,imm)
6474 //all instruction created with FROUND_CURRENT
6475 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6476 X86VectorVTInfo _> {
6478 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6479 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6480 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6481 (OpNode (_.VT _.RC:$src1),
6484 (i32 FROUND_CURRENT))>;
6485 let mayLoad = 1 in {
6486 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6487 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6488 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6489 (OpNode (_.VT _.RC:$src1),
6490 (_.VT (scalar_to_vector
6491 (_.ScalarLdFrag addr:$src2))),
6493 (i32 FROUND_CURRENT))>;
6495 let isAsmParserOnly = 1 in {
6496 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6497 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6498 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6504 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6505 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6506 SDNode OpNode, X86VectorVTInfo _>{
6507 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6508 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6509 OpcodeStr, "$src3,{sae}, $src2, $src1",
6510 "$src1, $src2,{sae}, $src3",
6511 (OpNode (_.VT _.RC:$src1),
6514 (i32 FROUND_NO_EXC))>, EVEX_B;
6516 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6517 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6518 SDNode OpNode, X86VectorVTInfo _> {
6519 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6520 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6521 OpcodeStr, "$src3,{sae}, $src2, $src1",
6522 "$src1, $src2,{sae}, $src3",
6523 (OpNode (_.VT _.RC:$src1),
6526 (i32 FROUND_NO_EXC))>, EVEX_B;
6529 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6530 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6531 let Predicates = [prd] in {
6532 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6533 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6537 let Predicates = [prd, HasVLX] in {
6538 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6540 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6545 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6546 bits<8> opc, SDNode OpNode>{
6547 let Predicates = [HasAVX512] in {
6548 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6550 let Predicates = [HasAVX512, HasVLX] in {
6551 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6552 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6556 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6557 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6558 let Predicates = [prd] in {
6559 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6560 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6564 multiclass avx512_common_fp_sae_packed_imm_all<string OpcodeStr, bits<8> opcPs,
6565 bits<8> opcPd, SDNode OpNode, Predicate prd>{
6566 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info, opcPs,
6567 OpNode, prd>, EVEX_CD8<32, CD8VF>;
6568 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info, opcPd,
6569 OpNode, prd>,EVEX_CD8<64, CD8VF> , VEX_W;
6572 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6573 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6574 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6575 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6576 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6577 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6579 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6580 0x55, X86VFixupimm, HasAVX512>,
6581 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6582 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6583 0x55, X86VFixupimm, HasAVX512>,
6584 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6586 defm VREDUCE : avx512_common_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56, X86VReduce, HasDQI>,AVX512AIi8Base,EVEX;
6587 defm VRNDSCALE : avx512_common_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09, X86VRndScale, HasAVX512>,AVX512AIi8Base, EVEX;
6589 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6590 0x50, X86VRange, HasDQI>,
6591 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6592 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6593 0x50, X86VRange, HasDQI>,
6594 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6596 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6597 0x51, X86VRange, HasDQI>,
6598 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6599 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6600 0x51, X86VRange, HasDQI>,
6601 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6603 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6604 0x57, X86Reduces, HasDQI>,
6605 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6606 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6607 0x57, X86Reduces, HasDQI>,
6608 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6610 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6611 bits<8> opc, SDNode OpNode = X86Shuf128>{
6612 let Predicates = [HasAVX512] in {
6613 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6616 let Predicates = [HasAVX512, HasVLX] in {
6617 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6620 let Predicates = [HasAVX512] in {
6621 def : Pat<(v16f32 (ffloor VR512:$src)),
6622 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6623 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6624 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6625 def : Pat<(v16f32 (fceil VR512:$src)),
6626 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6627 def : Pat<(v16f32 (frint VR512:$src)),
6628 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6629 def : Pat<(v16f32 (ftrunc VR512:$src)),
6630 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6632 def : Pat<(v8f64 (ffloor VR512:$src)),
6633 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6634 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6635 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6636 def : Pat<(v8f64 (fceil VR512:$src)),
6637 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6638 def : Pat<(v8f64 (frint VR512:$src)),
6639 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6640 def : Pat<(v8f64 (ftrunc VR512:$src)),
6641 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6644 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6645 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6646 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6647 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6648 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6649 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6650 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6651 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6653 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6654 AVX512VLVectorVTInfo VTInfo_FP>{
6655 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6656 AVX512AIi8Base, EVEX_4V;
6657 let isCodeGenOnly = 1 in {
6658 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6659 AVX512AIi8Base, EVEX_4V;
6663 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6664 EVEX_CD8<32, CD8VF>;
6665 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6666 EVEX_CD8<64, CD8VF>, VEX_W;
6668 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6669 X86VectorVTInfo _> {
6670 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6671 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6673 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6676 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6677 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6679 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6680 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6683 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6684 X86VectorVTInfo _> :
6685 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6687 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6688 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6689 "${src1}"##_.BroadcastStr,
6690 "${src1}"##_.BroadcastStr,
6691 (_.VT (OpNode (X86VBroadcast
6692 (_.ScalarLdFrag addr:$src1))))>,
6693 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6696 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6697 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6698 let Predicates = [prd] in
6699 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6701 let Predicates = [prd, HasVLX] in {
6702 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6704 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6709 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6710 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6711 let Predicates = [prd] in
6712 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6715 let Predicates = [prd, HasVLX] in {
6716 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6718 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6723 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6724 SDNode OpNode, Predicate prd> {
6725 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6727 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6730 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6731 SDNode OpNode, Predicate prd> {
6732 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6733 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6736 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6737 bits<8> opc_d, bits<8> opc_q,
6738 string OpcodeStr, SDNode OpNode> {
6739 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6741 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6745 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6748 (bc_v16i32 (v16i1sextv16i32)),
6749 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6750 (VPABSDZrr VR512:$src)>;
6752 (bc_v8i64 (v8i1sextv8i64)),
6753 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6754 (VPABSQZrr VR512:$src)>;
6756 //===----------------------------------------------------------------------===//
6757 // AVX-512 - Unpack Instructions
6758 //===----------------------------------------------------------------------===//
6759 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
6760 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
6762 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
6763 SSE_INTALU_ITINS_P, HasBWI>;
6764 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
6765 SSE_INTALU_ITINS_P, HasBWI>;
6766 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
6767 SSE_INTALU_ITINS_P, HasBWI>;
6768 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
6769 SSE_INTALU_ITINS_P, HasBWI>;
6771 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
6772 SSE_INTALU_ITINS_P, HasAVX512>;
6773 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
6774 SSE_INTALU_ITINS_P, HasAVX512>;
6775 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
6776 SSE_INTALU_ITINS_P, HasAVX512>;
6777 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
6778 SSE_INTALU_ITINS_P, HasAVX512>;