1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 let Predicates = [HasCDI] in {
521 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
522 VK16, v16i32, v16i1>, EVEX_V512;
523 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
524 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
527 //===----------------------------------------------------------------------===//
530 // -- immediate form --
531 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
532 SDNode OpNode, PatFrag mem_frag,
533 X86MemOperand x86memop, ValueType OpVT> {
534 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
535 (ins RC:$src1, i8imm:$src2),
536 !strconcat(OpcodeStr,
537 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
539 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
541 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
542 (ins x86memop:$src1, i8imm:$src2),
543 !strconcat(OpcodeStr,
544 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
546 (OpVT (OpNode (mem_frag addr:$src1),
547 (i8 imm:$src2))))]>, EVEX;
550 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
551 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
552 let ExeDomain = SSEPackedDouble in
553 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
554 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
556 // -- VPERM - register form --
557 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
558 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
560 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
561 (ins RC:$src1, RC:$src2),
562 !strconcat(OpcodeStr,
563 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
565 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
567 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
568 (ins RC:$src1, x86memop:$src2),
569 !strconcat(OpcodeStr,
570 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
572 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
576 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
577 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
578 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
579 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
580 let ExeDomain = SSEPackedSingle in
581 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
582 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
583 let ExeDomain = SSEPackedDouble in
584 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
585 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
587 // -- VPERM2I - 3 source operands form --
588 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
589 PatFrag mem_frag, X86MemOperand x86memop,
590 SDNode OpNode, ValueType OpVT> {
591 let Constraints = "$src1 = $dst" in {
592 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
593 (ins RC:$src1, RC:$src2, RC:$src3),
594 !strconcat(OpcodeStr,
595 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
597 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
600 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
601 (ins RC:$src1, RC:$src2, x86memop:$src3),
602 !strconcat(OpcodeStr,
603 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
605 (OpVT (OpNode RC:$src1, RC:$src2,
606 (mem_frag addr:$src3))))]>, EVEX_4V;
609 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
610 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
611 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
612 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
613 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
614 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
615 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
616 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
618 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
619 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
620 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
621 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
622 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
623 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
624 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
625 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
627 def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
628 (v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
629 (VPERMT2PSrr VR512:$src1, VR512:$idx, VR512:$src2)>;
631 def : Pat<(v16i32 (int_x86_avx512_mask_vpermt_d_512 (v16i32 VR512:$idx),
632 (v16i32 VR512:$src1), (v16i32 VR512:$src2), (i16 -1))),
633 (VPERMT2Drr VR512:$src1, VR512:$idx, VR512:$src2)>;
635 def : Pat<(v8f64 (int_x86_avx512_mask_vpermt_pd_512 (v8i64 VR512:$idx),
636 (v8f64 VR512:$src1), (v8f64 VR512:$src2), (i8 -1))),
637 (VPERMT2PDrr VR512:$src1, VR512:$idx, VR512:$src2)>;
639 def : Pat<(v8i64 (int_x86_avx512_mask_vpermt_q_512 (v8i64 VR512:$idx),
640 (v8i64 VR512:$src1), (v8i64 VR512:$src2), (i8 -1))),
641 (VPERMT2Qrr VR512:$src1, VR512:$idx, VR512:$src2)>;
642 //===----------------------------------------------------------------------===//
643 // AVX-512 - BLEND using mask
645 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
646 RegisterClass KRC, RegisterClass RC,
647 X86MemOperand x86memop, PatFrag mem_frag,
648 SDNode OpNode, ValueType vt> {
649 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
650 (ins KRC:$mask, RC:$src1, RC:$src2),
651 !strconcat(OpcodeStr,
652 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
653 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
654 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
656 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
657 (ins KRC:$mask, RC:$src1, x86memop:$src2),
658 !strconcat(OpcodeStr,
659 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
660 []>, EVEX_4V, EVEX_K;
663 let ExeDomain = SSEPackedSingle in
664 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
665 VK16WM, VR512, f512mem,
666 memopv16f32, vselect, v16f32>,
667 EVEX_CD8<32, CD8VF>, EVEX_V512;
668 let ExeDomain = SSEPackedDouble in
669 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
670 VK8WM, VR512, f512mem,
671 memopv8f64, vselect, v8f64>,
672 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
674 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
675 (v16f32 VR512:$src2), (i16 GR16:$mask))),
676 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
677 VR512:$src1, VR512:$src2)>;
679 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
680 (v8f64 VR512:$src2), (i8 GR8:$mask))),
681 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
682 VR512:$src1, VR512:$src2)>;
684 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
685 VK16WM, VR512, f512mem,
686 memopv16i32, vselect, v16i32>,
687 EVEX_CD8<32, CD8VF>, EVEX_V512;
689 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
690 VK8WM, VR512, f512mem,
691 memopv8i64, vselect, v8i64>,
692 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
694 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
695 (v16i32 VR512:$src2), (i16 GR16:$mask))),
696 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
697 VR512:$src1, VR512:$src2)>;
699 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
700 (v8i64 VR512:$src2), (i8 GR8:$mask))),
701 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
702 VR512:$src1, VR512:$src2)>;
704 let Predicates = [HasAVX512] in {
705 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
706 (v8f32 VR256X:$src2))),
708 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
709 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
710 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
712 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
713 (v8i32 VR256X:$src2))),
715 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
716 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
717 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
719 //===----------------------------------------------------------------------===//
720 // Compare Instructions
721 //===----------------------------------------------------------------------===//
723 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
724 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
725 Operand CC, SDNode OpNode, ValueType VT,
726 PatFrag ld_frag, string asm, string asm_alt> {
727 def rr : AVX512Ii8<0xC2, MRMSrcReg,
728 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
729 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
730 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
731 def rm : AVX512Ii8<0xC2, MRMSrcMem,
732 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
733 [(set VK1:$dst, (OpNode (VT RC:$src1),
734 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
735 let isAsmParserOnly = 1, hasSideEffects = 0 in {
736 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
737 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
739 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
740 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
741 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
745 let Predicates = [HasAVX512] in {
746 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
747 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
750 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
751 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
752 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
756 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
757 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
758 SDNode OpNode, ValueType vt> {
759 def rr : AVX512BI<opc, MRMSrcReg,
760 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
761 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
762 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
763 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
764 def rm : AVX512BI<opc, MRMSrcMem,
765 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
766 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
767 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
768 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
771 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
772 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
774 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
775 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
776 VEX_W, EVEX_CD8<64, CD8VF>;
778 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
779 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
781 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
782 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
783 VEX_W, EVEX_CD8<64, CD8VF>;
785 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
786 (COPY_TO_REGCLASS (VPCMPGTDZrr
787 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
788 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
790 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
791 (COPY_TO_REGCLASS (VPCMPEQDZrr
792 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
793 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
795 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
796 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
797 SDNode OpNode, ValueType vt, Operand CC, string asm,
799 def rri : AVX512AIi8<opc, MRMSrcReg,
800 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
801 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
802 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
803 def rmi : AVX512AIi8<opc, MRMSrcMem,
804 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
805 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
806 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
807 // Accept explicit immediate argument form instead of comparison code.
808 let isAsmParserOnly = 1, hasSideEffects = 0 in {
809 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
810 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
811 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
812 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
813 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
814 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
818 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
819 X86cmpm, v16i32, AVXCC,
820 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
821 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
822 EVEX_V512, EVEX_CD8<32, CD8VF>;
823 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
824 X86cmpmu, v16i32, AVXCC,
825 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
826 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
827 EVEX_V512, EVEX_CD8<32, CD8VF>;
829 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
830 X86cmpm, v8i64, AVXCC,
831 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
832 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
833 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
834 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
835 X86cmpmu, v8i64, AVXCC,
836 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
837 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
838 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
840 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
841 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
842 X86MemOperand x86memop, ValueType vt,
843 string suffix, Domain d> {
844 def rri : AVX512PIi8<0xC2, MRMSrcReg,
845 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
846 !strconcat("vcmp${cc}", suffix,
847 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
848 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
849 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
850 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
851 !strconcat("vcmp${cc}", suffix,
852 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
854 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
855 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
856 !strconcat("vcmp${cc}", suffix,
857 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
859 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
861 // Accept explicit immediate argument form instead of comparison code.
862 let isAsmParserOnly = 1, hasSideEffects = 0 in {
863 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
864 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
865 !strconcat("vcmp", suffix,
866 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
867 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
868 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
869 !strconcat("vcmp", suffix,
870 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
874 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
875 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
877 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
878 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
881 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
882 (COPY_TO_REGCLASS (VCMPPSZrri
883 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
884 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
886 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
887 (COPY_TO_REGCLASS (VPCMPDZrri
888 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
889 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
891 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
892 (COPY_TO_REGCLASS (VPCMPUDZrri
893 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
894 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
897 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
898 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
900 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
901 (I8Imm imm:$cc)), GR16)>;
903 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
904 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
906 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
907 (I8Imm imm:$cc)), GR8)>;
909 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
910 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
912 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
913 (I8Imm imm:$cc)), GR16)>;
915 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
916 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
918 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
919 (I8Imm imm:$cc)), GR8)>;
921 // Mask register copy, including
922 // - copy between mask registers
923 // - load/store mask registers
924 // - copy from GPR to mask register and vice versa
926 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
927 string OpcodeStr, RegisterClass KRC,
928 ValueType vt, X86MemOperand x86memop> {
929 let hasSideEffects = 0 in {
930 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
931 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
933 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
934 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
935 [(set KRC:$dst, (vt (load addr:$src)))]>;
937 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
938 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
942 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
944 RegisterClass KRC, RegisterClass GRC> {
945 let hasSideEffects = 0 in {
946 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
947 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
948 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
949 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
953 let Predicates = [HasAVX512] in {
954 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
956 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
960 let Predicates = [HasAVX512] in {
961 // GR16 from/to 16-bit mask
962 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
963 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
964 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
965 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
967 // Store kreg in memory
968 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
969 (KMOVWmk addr:$dst, VK16:$src)>;
971 def : Pat<(store VK8:$src, addr:$dst),
972 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
974 def : Pat<(i1 (load addr:$src)),
975 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
977 def : Pat<(v8i1 (load addr:$src)),
978 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
980 def : Pat<(i1 (trunc (i32 GR32:$src))),
981 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
983 def : Pat<(i1 (trunc (i8 GR8:$src))),
985 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
987 def : Pat<(i1 (trunc (i16 GR16:$src))),
989 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
992 def : Pat<(i32 (zext VK1:$src)),
993 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
994 def : Pat<(i8 (zext VK1:$src)),
997 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
998 def : Pat<(i64 (zext VK1:$src)),
999 (AND64ri8 (SUBREG_TO_REG (i64 0),
1000 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1001 def : Pat<(i16 (zext VK1:$src)),
1003 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1005 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1006 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1007 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1008 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1010 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1011 let Predicates = [HasAVX512] in {
1012 // GR from/to 8-bit mask without native support
1013 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1015 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1017 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1019 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1022 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1023 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1024 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1025 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1029 // Mask unary operation
1031 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1032 RegisterClass KRC, SDPatternOperator OpNode> {
1033 let Predicates = [HasAVX512] in
1034 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1035 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1036 [(set KRC:$dst, (OpNode KRC:$src))]>;
1039 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1040 SDPatternOperator OpNode> {
1041 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1045 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1047 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1048 let Predicates = [HasAVX512] in
1049 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1051 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1052 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1054 defm : avx512_mask_unop_int<"knot", "KNOT">;
1056 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1057 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1058 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1060 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1061 def : Pat<(not VK8:$src),
1063 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1065 // Mask binary operation
1066 // - KAND, KANDN, KOR, KXNOR, KXOR
1067 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1068 RegisterClass KRC, SDPatternOperator OpNode> {
1069 let Predicates = [HasAVX512] in
1070 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1071 !strconcat(OpcodeStr,
1072 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1073 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1076 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1077 SDPatternOperator OpNode> {
1078 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1082 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1083 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1085 let isCommutable = 1 in {
1086 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1087 let isCommutable = 0 in
1088 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1089 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1090 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1091 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1094 def : Pat<(xor VK1:$src1, VK1:$src2),
1095 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1096 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1098 def : Pat<(or VK1:$src1, VK1:$src2),
1099 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1100 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1102 def : Pat<(and VK1:$src1, VK1:$src2),
1103 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1104 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1106 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1107 let Predicates = [HasAVX512] in
1108 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1109 (i16 GR16:$src1), (i16 GR16:$src2)),
1110 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1111 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1112 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1115 defm : avx512_mask_binop_int<"kand", "KAND">;
1116 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1117 defm : avx512_mask_binop_int<"kor", "KOR">;
1118 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1119 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1121 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1122 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1123 let Predicates = [HasAVX512] in
1124 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1126 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1127 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1130 defm : avx512_binop_pat<and, KANDWrr>;
1131 defm : avx512_binop_pat<andn, KANDNWrr>;
1132 defm : avx512_binop_pat<or, KORWrr>;
1133 defm : avx512_binop_pat<xnor, KXNORWrr>;
1134 defm : avx512_binop_pat<xor, KXORWrr>;
1137 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1138 RegisterClass KRC> {
1139 let Predicates = [HasAVX512] in
1140 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1141 !strconcat(OpcodeStr,
1142 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1145 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1146 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1150 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1151 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1152 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1153 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1156 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1157 let Predicates = [HasAVX512] in
1158 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1159 (i16 GR16:$src1), (i16 GR16:$src2)),
1160 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1161 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1162 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1164 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1167 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1169 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1170 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1171 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1172 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1175 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1176 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1180 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1182 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1183 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1184 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1187 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1189 let Predicates = [HasAVX512] in
1190 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1191 !strconcat(OpcodeStr,
1192 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1193 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1196 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1198 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1202 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1203 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1205 // Mask setting all 0s or 1s
1206 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1207 let Predicates = [HasAVX512] in
1208 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1209 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1210 [(set KRC:$dst, (VT Val))]>;
1213 multiclass avx512_mask_setop_w<PatFrag Val> {
1214 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1215 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1218 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1219 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1221 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1222 let Predicates = [HasAVX512] in {
1223 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1224 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1225 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1226 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1227 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1229 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1230 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1232 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1233 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1235 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1236 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1238 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1239 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1241 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1242 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1243 //===----------------------------------------------------------------------===//
1244 // AVX-512 - Aligned and unaligned load and store
1247 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1248 X86MemOperand x86memop, PatFrag ld_frag,
1249 string asm, Domain d,
1250 ValueType vt, bit IsReMaterializable = 1> {
1251 let hasSideEffects = 0 in {
1252 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1253 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1255 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1257 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1258 [], d>, EVEX, EVEX_KZ;
1260 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1261 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1262 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1263 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1264 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1265 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1266 (ins RC:$src1, KRC:$mask, RC:$src2),
1268 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1271 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1272 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1274 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1275 [], d>, EVEX, EVEX_K;
1278 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1279 (ins KRC:$mask, x86memop:$src2),
1281 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1282 [], d>, EVEX, EVEX_KZ;
1285 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1286 X86MemOperand x86memop, PatFrag store_frag,
1287 string asm, Domain d, ValueType vt> {
1288 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1289 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1290 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1292 let Constraints = "$src1 = $dst" in
1293 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1294 (ins RC:$src1, KRC:$mask, RC:$src2),
1296 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1298 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1299 (ins KRC:$mask, RC:$src),
1301 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1302 [], d>, EVEX, EVEX_KZ;
1304 let mayStore = 1 in {
1305 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1306 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1307 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1308 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1309 (ins x86memop:$dst, KRC:$mask, RC:$src),
1311 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1312 [], d>, EVEX, EVEX_K;
1313 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1314 (ins x86memop:$dst, KRC:$mask, RC:$src),
1316 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1317 [], d>, EVEX, EVEX_KZ;
1321 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1322 "vmovaps", SSEPackedSingle, v16f32>,
1323 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1324 "vmovaps", SSEPackedSingle, v16f32>,
1325 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1326 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1327 "vmovapd", SSEPackedDouble, v8f64>,
1328 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1329 "vmovapd", SSEPackedDouble, v8f64>,
1330 PD, EVEX_V512, VEX_W,
1331 EVEX_CD8<64, CD8VF>;
1332 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1333 "vmovups", SSEPackedSingle, v16f32>,
1334 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1335 "vmovups", SSEPackedSingle, v16f32>,
1336 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1337 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1338 "vmovupd", SSEPackedDouble, v8f64, 0>,
1339 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1340 "vmovupd", SSEPackedDouble, v8f64>,
1341 PD, EVEX_V512, VEX_W,
1342 EVEX_CD8<64, CD8VF>;
1343 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1344 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1345 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1347 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1348 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1349 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1351 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1353 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1355 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1357 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1360 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1361 "vmovdqa32", SSEPackedInt, v16i32>,
1362 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1363 "vmovdqa32", SSEPackedInt, v16i32>,
1364 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1365 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1366 "vmovdqa64", SSEPackedInt, v8i64>,
1367 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1368 "vmovdqa64", SSEPackedInt, v8i64>,
1369 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1370 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1371 "vmovdqu32", SSEPackedInt, v16i32>,
1372 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1373 "vmovdqu32", SSEPackedInt, v16i32>,
1374 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1375 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1376 "vmovdqu64", SSEPackedInt, v8i64>,
1377 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1378 "vmovdqu64", SSEPackedInt, v8i64>,
1379 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1381 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1382 (v16i32 immAllZerosV), GR16:$mask)),
1383 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1385 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1386 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1387 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1389 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1391 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1393 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1395 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1398 let AddedComplexity = 20 in {
1399 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1400 (bc_v8i64 (v16i32 immAllZerosV)))),
1401 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1403 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1404 (v8i64 VR512:$src))),
1405 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1408 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1409 (v16i32 immAllZerosV))),
1410 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1412 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1413 (v16i32 VR512:$src))),
1414 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1416 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1417 (v16f32 VR512:$src2))),
1418 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1419 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1420 (v8f64 VR512:$src2))),
1421 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1422 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1423 (v16i32 VR512:$src2))),
1424 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1425 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1426 (v8i64 VR512:$src2))),
1427 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1429 // Move Int Doubleword to Packed Double Int
1431 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1432 "vmovd\t{$src, $dst|$dst, $src}",
1434 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1436 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1437 "vmovd\t{$src, $dst|$dst, $src}",
1439 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1440 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1441 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1442 "vmovq\t{$src, $dst|$dst, $src}",
1444 (v2i64 (scalar_to_vector GR64:$src)))],
1445 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1446 let isCodeGenOnly = 1 in {
1447 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1448 "vmovq\t{$src, $dst|$dst, $src}",
1449 [(set FR64:$dst, (bitconvert GR64:$src))],
1450 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1451 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1452 "vmovq\t{$src, $dst|$dst, $src}",
1453 [(set GR64:$dst, (bitconvert FR64:$src))],
1454 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1456 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1457 "vmovq\t{$src, $dst|$dst, $src}",
1458 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1459 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1460 EVEX_CD8<64, CD8VT1>;
1462 // Move Int Doubleword to Single Scalar
1464 let isCodeGenOnly = 1 in {
1465 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1466 "vmovd\t{$src, $dst|$dst, $src}",
1467 [(set FR32X:$dst, (bitconvert GR32:$src))],
1468 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1470 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1471 "vmovd\t{$src, $dst|$dst, $src}",
1472 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1473 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1476 // Move doubleword from xmm register to r/m32
1478 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1479 "vmovd\t{$src, $dst|$dst, $src}",
1480 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1481 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1483 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1484 (ins i32mem:$dst, VR128X:$src),
1485 "vmovd\t{$src, $dst|$dst, $src}",
1486 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1487 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1488 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1490 // Move quadword from xmm1 register to r/m64
1492 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1493 "vmovq\t{$src, $dst|$dst, $src}",
1494 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1496 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1497 Requires<[HasAVX512, In64BitMode]>;
1499 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1500 (ins i64mem:$dst, VR128X:$src),
1501 "vmovq\t{$src, $dst|$dst, $src}",
1502 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1503 addr:$dst)], IIC_SSE_MOVDQ>,
1504 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1505 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1507 // Move Scalar Single to Double Int
1509 let isCodeGenOnly = 1 in {
1510 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1512 "vmovd\t{$src, $dst|$dst, $src}",
1513 [(set GR32:$dst, (bitconvert FR32X:$src))],
1514 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1515 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1516 (ins i32mem:$dst, FR32X:$src),
1517 "vmovd\t{$src, $dst|$dst, $src}",
1518 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1519 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1522 // Move Quadword Int to Packed Quadword Int
1524 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1526 "vmovq\t{$src, $dst|$dst, $src}",
1528 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1529 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1531 //===----------------------------------------------------------------------===//
1532 // AVX-512 MOVSS, MOVSD
1533 //===----------------------------------------------------------------------===//
1535 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1536 SDNode OpNode, ValueType vt,
1537 X86MemOperand x86memop, PatFrag mem_pat> {
1538 let hasSideEffects = 0 in {
1539 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1540 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1541 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1542 (scalar_to_vector RC:$src2))))],
1543 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1544 let Constraints = "$src1 = $dst" in
1545 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1546 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1548 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1549 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1550 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1551 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1552 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1554 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1555 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1556 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1558 } //hasSideEffects = 0
1561 let ExeDomain = SSEPackedSingle in
1562 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1563 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1565 let ExeDomain = SSEPackedDouble in
1566 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1567 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1569 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1570 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1571 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1573 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1574 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1575 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1577 // For the disassembler
1578 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1579 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1580 (ins VR128X:$src1, FR32X:$src2),
1581 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1583 XS, EVEX_4V, VEX_LIG;
1584 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1585 (ins VR128X:$src1, FR64X:$src2),
1586 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1588 XD, EVEX_4V, VEX_LIG, VEX_W;
1591 let Predicates = [HasAVX512] in {
1592 let AddedComplexity = 15 in {
1593 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1594 // MOVS{S,D} to the lower bits.
1595 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1596 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1597 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1598 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1599 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1600 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1601 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1602 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1604 // Move low f32 and clear high bits.
1605 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1606 (SUBREG_TO_REG (i32 0),
1607 (VMOVSSZrr (v4f32 (V_SET0)),
1608 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1609 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1610 (SUBREG_TO_REG (i32 0),
1611 (VMOVSSZrr (v4i32 (V_SET0)),
1612 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1615 let AddedComplexity = 20 in {
1616 // MOVSSrm zeros the high parts of the register; represent this
1617 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1619 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1620 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1621 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1622 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1623 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1625 // MOVSDrm zeros the high parts of the register; represent this
1626 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1627 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1628 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1629 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1630 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1631 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1632 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1633 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1634 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1635 def : Pat<(v2f64 (X86vzload addr:$src)),
1636 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1638 // Represent the same patterns above but in the form they appear for
1640 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1641 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1642 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1643 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1644 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1645 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1646 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1647 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1648 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1650 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1651 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1652 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1653 FR32X:$src)), sub_xmm)>;
1654 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1655 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1656 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1657 FR64X:$src)), sub_xmm)>;
1658 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1659 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1660 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1662 // Move low f64 and clear high bits.
1663 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1664 (SUBREG_TO_REG (i32 0),
1665 (VMOVSDZrr (v2f64 (V_SET0)),
1666 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1668 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1669 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1670 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1672 // Extract and store.
1673 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1675 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1676 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1678 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1680 // Shuffle with VMOVSS
1681 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1682 (VMOVSSZrr (v4i32 VR128X:$src1),
1683 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1684 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1685 (VMOVSSZrr (v4f32 VR128X:$src1),
1686 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1689 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1690 (SUBREG_TO_REG (i32 0),
1691 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1692 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1694 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1695 (SUBREG_TO_REG (i32 0),
1696 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1697 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1700 // Shuffle with VMOVSD
1701 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1702 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1703 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1704 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1705 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1706 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1707 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1708 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1711 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1712 (SUBREG_TO_REG (i32 0),
1713 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1714 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1716 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1717 (SUBREG_TO_REG (i32 0),
1718 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1719 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1722 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1723 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1724 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1725 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1726 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1727 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1728 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1729 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1732 let AddedComplexity = 15 in
1733 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1735 "vmovq\t{$src, $dst|$dst, $src}",
1736 [(set VR128X:$dst, (v2i64 (X86vzmovl
1737 (v2i64 VR128X:$src))))],
1738 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1740 let AddedComplexity = 20 in
1741 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1743 "vmovq\t{$src, $dst|$dst, $src}",
1744 [(set VR128X:$dst, (v2i64 (X86vzmovl
1745 (loadv2i64 addr:$src))))],
1746 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1747 EVEX_CD8<8, CD8VT8>;
1749 let Predicates = [HasAVX512] in {
1750 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1751 let AddedComplexity = 20 in {
1752 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1753 (VMOVDI2PDIZrm addr:$src)>;
1754 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1755 (VMOV64toPQIZrr GR64:$src)>;
1756 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1757 (VMOVDI2PDIZrr GR32:$src)>;
1759 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1760 (VMOVDI2PDIZrm addr:$src)>;
1761 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1762 (VMOVDI2PDIZrm addr:$src)>;
1763 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1764 (VMOVZPQILo2PQIZrm addr:$src)>;
1765 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1766 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1767 def : Pat<(v2i64 (X86vzload addr:$src)),
1768 (VMOVZPQILo2PQIZrm addr:$src)>;
1771 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1772 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1773 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1774 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1775 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1776 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1777 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1780 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1781 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1783 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1784 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1786 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1787 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1789 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1790 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1792 //===----------------------------------------------------------------------===//
1793 // AVX-512 - Non-temporals
1794 //===----------------------------------------------------------------------===//
1796 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1798 "vmovntdqa\t{$src, $dst|$dst, $src}",
1800 (int_x86_avx512_movntdqa addr:$src))]>,
1803 //===----------------------------------------------------------------------===//
1804 // AVX-512 - Integer arithmetic
1806 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1807 ValueType OpVT, RegisterClass KRC,
1808 RegisterClass RC, PatFrag memop_frag,
1809 X86MemOperand x86memop, PatFrag scalar_mfrag,
1810 X86MemOperand x86scalar_mop, string BrdcstStr,
1811 OpndItins itins, bit IsCommutable = 0> {
1812 let isCommutable = IsCommutable in
1813 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1814 (ins RC:$src1, RC:$src2),
1815 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1816 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1818 let AddedComplexity = 30 in {
1819 let Constraints = "$src0 = $dst" in
1820 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1821 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1822 !strconcat(OpcodeStr,
1823 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1824 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1825 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1827 itins.rr>, EVEX_4V, EVEX_K;
1828 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1829 (ins KRC:$mask, RC:$src1, RC:$src2),
1830 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1831 "|$dst {${mask}} {z}, $src1, $src2}"),
1832 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1833 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1834 (OpVT immAllZerosV))))],
1835 itins.rr>, EVEX_4V, EVEX_KZ;
1838 let mayLoad = 1 in {
1839 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1840 (ins RC:$src1, x86memop:$src2),
1841 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1842 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1844 let AddedComplexity = 30 in {
1845 let Constraints = "$src0 = $dst" in
1846 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1847 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1848 !strconcat(OpcodeStr,
1849 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1850 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1851 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1853 itins.rm>, EVEX_4V, EVEX_K;
1854 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1855 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1856 !strconcat(OpcodeStr,
1857 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1858 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1859 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1860 (OpVT immAllZerosV))))],
1861 itins.rm>, EVEX_4V, EVEX_KZ;
1863 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1864 (ins RC:$src1, x86scalar_mop:$src2),
1865 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1866 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1867 [(set RC:$dst, (OpNode RC:$src1,
1868 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1869 itins.rm>, EVEX_4V, EVEX_B;
1870 let AddedComplexity = 30 in {
1871 let Constraints = "$src0 = $dst" in
1872 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1873 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1874 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1875 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1877 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1878 (OpNode (OpVT RC:$src1),
1879 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1881 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1882 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1883 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1884 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1885 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1887 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1888 (OpNode (OpVT RC:$src1),
1889 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1890 (OpVT immAllZerosV))))],
1891 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1896 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
1897 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
1898 PatFrag memop_frag, X86MemOperand x86memop,
1899 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
1900 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
1901 let isCommutable = IsCommutable in
1903 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1904 (ins RC:$src1, RC:$src2),
1905 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1907 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1908 (ins KRC:$mask, RC:$src1, RC:$src2),
1909 !strconcat(OpcodeStr,
1910 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1911 [], itins.rr>, EVEX_4V, EVEX_K;
1912 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1913 (ins KRC:$mask, RC:$src1, RC:$src2),
1914 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1915 "|$dst {${mask}} {z}, $src1, $src2}"),
1916 [], itins.rr>, EVEX_4V, EVEX_KZ;
1918 let mayLoad = 1 in {
1919 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1920 (ins RC:$src1, x86memop:$src2),
1921 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1923 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1924 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1925 !strconcat(OpcodeStr,
1926 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1927 [], itins.rm>, EVEX_4V, EVEX_K;
1928 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1929 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1930 !strconcat(OpcodeStr,
1931 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1932 [], itins.rm>, EVEX_4V, EVEX_KZ;
1933 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1934 (ins RC:$src1, x86scalar_mop:$src2),
1935 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1936 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1937 [], itins.rm>, EVEX_4V, EVEX_B;
1938 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1939 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1940 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1941 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1943 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1944 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1945 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1946 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1947 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1949 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1953 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
1954 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1955 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1957 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
1958 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1959 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1961 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
1962 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1963 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1965 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
1966 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1967 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1969 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
1970 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1971 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1973 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
1974 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1975 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
1976 EVEX_CD8<64, CD8VF>, VEX_W;
1978 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
1979 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1980 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
1982 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1983 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1985 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1986 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1987 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1988 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1989 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1990 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1992 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
1993 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1994 SSE_INTALU_ITINS_P, 1>,
1995 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1996 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
1997 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1998 SSE_INTALU_ITINS_P, 0>,
1999 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2001 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2002 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2003 SSE_INTALU_ITINS_P, 1>,
2004 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2005 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2006 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2007 SSE_INTALU_ITINS_P, 0>,
2008 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2010 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2011 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2012 SSE_INTALU_ITINS_P, 1>,
2013 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2014 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2015 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2016 SSE_INTALU_ITINS_P, 0>,
2017 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2019 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2020 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2021 SSE_INTALU_ITINS_P, 1>,
2022 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2023 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2024 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2025 SSE_INTALU_ITINS_P, 0>,
2026 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2028 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2029 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2030 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2031 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2032 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2033 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2034 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2035 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2036 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2037 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2038 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2039 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2040 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2041 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2042 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2043 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2044 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2045 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2046 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2047 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2048 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2049 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2050 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2051 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2052 //===----------------------------------------------------------------------===//
2053 // AVX-512 - Unpack Instructions
2054 //===----------------------------------------------------------------------===//
2056 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2057 PatFrag mem_frag, RegisterClass RC,
2058 X86MemOperand x86memop, string asm,
2060 def rr : AVX512PI<opc, MRMSrcReg,
2061 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2063 (vt (OpNode RC:$src1, RC:$src2)))],
2065 def rm : AVX512PI<opc, MRMSrcMem,
2066 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2068 (vt (OpNode RC:$src1,
2069 (bitconvert (mem_frag addr:$src2)))))],
2073 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2074 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2075 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2076 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2077 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2078 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2079 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2080 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2081 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2082 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2083 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2084 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2086 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2087 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2088 X86MemOperand x86memop> {
2089 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2090 (ins RC:$src1, RC:$src2),
2091 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2092 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2093 IIC_SSE_UNPCK>, EVEX_4V;
2094 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2095 (ins RC:$src1, x86memop:$src2),
2096 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2097 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2098 (bitconvert (memop_frag addr:$src2)))))],
2099 IIC_SSE_UNPCK>, EVEX_4V;
2101 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2102 VR512, memopv16i32, i512mem>, EVEX_V512,
2103 EVEX_CD8<32, CD8VF>;
2104 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2105 VR512, memopv8i64, i512mem>, EVEX_V512,
2106 VEX_W, EVEX_CD8<64, CD8VF>;
2107 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2108 VR512, memopv16i32, i512mem>, EVEX_V512,
2109 EVEX_CD8<32, CD8VF>;
2110 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2111 VR512, memopv8i64, i512mem>, EVEX_V512,
2112 VEX_W, EVEX_CD8<64, CD8VF>;
2113 //===----------------------------------------------------------------------===//
2117 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2118 SDNode OpNode, PatFrag mem_frag,
2119 X86MemOperand x86memop, ValueType OpVT> {
2120 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2121 (ins RC:$src1, i8imm:$src2),
2122 !strconcat(OpcodeStr,
2123 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2125 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2127 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2128 (ins x86memop:$src1, i8imm:$src2),
2129 !strconcat(OpcodeStr,
2130 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2132 (OpVT (OpNode (mem_frag addr:$src1),
2133 (i8 imm:$src2))))]>, EVEX;
2136 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2137 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2139 let ExeDomain = SSEPackedSingle in
2140 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2141 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2142 EVEX_CD8<32, CD8VF>;
2143 let ExeDomain = SSEPackedDouble in
2144 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2145 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2146 VEX_W, EVEX_CD8<32, CD8VF>;
2148 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2149 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2150 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2151 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2153 //===----------------------------------------------------------------------===//
2154 // AVX-512 Logical Instructions
2155 //===----------------------------------------------------------------------===//
2157 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2158 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2159 EVEX_V512, EVEX_CD8<32, CD8VF>;
2160 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2161 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2162 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2163 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2164 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2165 EVEX_V512, EVEX_CD8<32, CD8VF>;
2166 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2167 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2168 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2169 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2170 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2171 EVEX_V512, EVEX_CD8<32, CD8VF>;
2172 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2173 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2174 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2175 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2176 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2177 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2178 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2179 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2180 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2182 //===----------------------------------------------------------------------===//
2183 // AVX-512 FP arithmetic
2184 //===----------------------------------------------------------------------===//
2186 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2188 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2189 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2190 EVEX_CD8<32, CD8VT1>;
2191 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2192 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2193 EVEX_CD8<64, CD8VT1>;
2196 let isCommutable = 1 in {
2197 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2198 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2199 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2200 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2202 let isCommutable = 0 in {
2203 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2204 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2207 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2209 RegisterClass RC, ValueType vt,
2210 X86MemOperand x86memop, PatFrag mem_frag,
2211 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2213 Domain d, OpndItins itins, bit commutable> {
2214 let isCommutable = commutable in {
2215 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2216 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2217 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2220 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2221 !strconcat(OpcodeStr,
2222 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2223 [], itins.rr, d>, EVEX_4V, EVEX_K;
2225 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2226 !strconcat(OpcodeStr,
2227 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2228 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2231 let mayLoad = 1 in {
2232 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2233 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2234 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2235 itins.rm, d>, EVEX_4V;
2237 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2238 (ins RC:$src1, x86scalar_mop:$src2),
2239 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2240 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2241 [(set RC:$dst, (OpNode RC:$src1,
2242 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2243 itins.rm, d>, EVEX_4V, EVEX_B;
2245 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2246 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2247 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2248 [], itins.rm, d>, EVEX_4V, EVEX_K;
2250 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2251 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2252 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2253 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2255 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2256 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2257 " \t{${src2}", BrdcstStr,
2258 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2259 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2261 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2262 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2263 " \t{${src2}", BrdcstStr,
2264 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2266 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2270 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2271 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2272 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2274 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2275 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2276 SSE_ALU_ITINS_P.d, 1>,
2277 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2279 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2280 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2281 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2282 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2283 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2284 SSE_ALU_ITINS_P.d, 1>,
2285 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2287 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2288 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2289 SSE_ALU_ITINS_P.s, 1>,
2290 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2291 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2292 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2293 SSE_ALU_ITINS_P.s, 1>,
2294 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2296 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2297 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2298 SSE_ALU_ITINS_P.d, 1>,
2299 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2300 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2301 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2302 SSE_ALU_ITINS_P.d, 1>,
2303 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2305 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2306 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2307 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2308 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2309 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2310 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2312 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2313 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2314 SSE_ALU_ITINS_P.d, 0>,
2315 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2316 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2317 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2318 SSE_ALU_ITINS_P.d, 0>,
2319 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2321 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2322 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2323 (i16 -1), FROUND_CURRENT)),
2324 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2326 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2327 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2328 (i8 -1), FROUND_CURRENT)),
2329 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2331 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2332 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2333 (i16 -1), FROUND_CURRENT)),
2334 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2336 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2337 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2338 (i8 -1), FROUND_CURRENT)),
2339 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2340 //===----------------------------------------------------------------------===//
2341 // AVX-512 VPTESTM instructions
2342 //===----------------------------------------------------------------------===//
2344 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2345 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2346 SDNode OpNode, ValueType vt> {
2347 def rr : AVX512PI<opc, MRMSrcReg,
2348 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2349 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2350 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2351 SSEPackedInt>, EVEX_4V;
2352 def rm : AVX512PI<opc, MRMSrcMem,
2353 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2354 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2355 [(set KRC:$dst, (OpNode (vt RC:$src1),
2356 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2359 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2360 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2361 EVEX_CD8<32, CD8VF>;
2362 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2363 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2364 EVEX_CD8<64, CD8VF>;
2366 let Predicates = [HasCDI] in {
2367 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2368 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2369 EVEX_CD8<32, CD8VF>;
2370 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2371 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2372 EVEX_CD8<64, CD8VF>;
2375 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2376 (v16i32 VR512:$src2), (i16 -1))),
2377 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2379 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2380 (v8i64 VR512:$src2), (i8 -1))),
2381 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2382 //===----------------------------------------------------------------------===//
2383 // AVX-512 Shift instructions
2384 //===----------------------------------------------------------------------===//
2385 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2386 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2387 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2388 RegisterClass KRC> {
2389 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2390 (ins RC:$src1, i8imm:$src2),
2391 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2392 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2393 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2394 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2395 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2396 !strconcat(OpcodeStr,
2397 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2398 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2399 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2400 (ins x86memop:$src1, i8imm:$src2),
2401 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2402 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2403 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2404 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2405 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2406 !strconcat(OpcodeStr,
2407 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2408 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2411 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2412 RegisterClass RC, ValueType vt, ValueType SrcVT,
2413 PatFrag bc_frag, RegisterClass KRC> {
2414 // src2 is always 128-bit
2415 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2416 (ins RC:$src1, VR128X:$src2),
2417 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2418 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2419 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2420 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2421 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2422 !strconcat(OpcodeStr,
2423 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2424 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2425 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2426 (ins RC:$src1, i128mem:$src2),
2427 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2428 [(set RC:$dst, (vt (OpNode RC:$src1,
2429 (bc_frag (memopv2i64 addr:$src2)))))],
2430 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2431 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2432 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2433 !strconcat(OpcodeStr,
2434 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2435 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2438 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2439 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2440 EVEX_V512, EVEX_CD8<32, CD8VF>;
2441 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2442 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2443 EVEX_CD8<32, CD8VQ>;
2445 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2446 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2447 EVEX_CD8<64, CD8VF>, VEX_W;
2448 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2449 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2450 EVEX_CD8<64, CD8VQ>, VEX_W;
2452 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2453 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2454 EVEX_CD8<32, CD8VF>;
2455 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2456 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2457 EVEX_CD8<32, CD8VQ>;
2459 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2460 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2461 EVEX_CD8<64, CD8VF>, VEX_W;
2462 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2463 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2464 EVEX_CD8<64, CD8VQ>, VEX_W;
2466 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2467 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2468 EVEX_V512, EVEX_CD8<32, CD8VF>;
2469 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2470 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2471 EVEX_CD8<32, CD8VQ>;
2473 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2474 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2475 EVEX_CD8<64, CD8VF>, VEX_W;
2476 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2477 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2478 EVEX_CD8<64, CD8VQ>, VEX_W;
2480 //===-------------------------------------------------------------------===//
2481 // Variable Bit Shifts
2482 //===-------------------------------------------------------------------===//
2483 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2484 RegisterClass RC, ValueType vt,
2485 X86MemOperand x86memop, PatFrag mem_frag> {
2486 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2487 (ins RC:$src1, RC:$src2),
2488 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2490 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2492 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2493 (ins RC:$src1, x86memop:$src2),
2494 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2496 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2500 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2501 i512mem, memopv16i32>, EVEX_V512,
2502 EVEX_CD8<32, CD8VF>;
2503 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2504 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2505 EVEX_CD8<64, CD8VF>;
2506 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2507 i512mem, memopv16i32>, EVEX_V512,
2508 EVEX_CD8<32, CD8VF>;
2509 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2510 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2511 EVEX_CD8<64, CD8VF>;
2512 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2513 i512mem, memopv16i32>, EVEX_V512,
2514 EVEX_CD8<32, CD8VF>;
2515 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2516 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2517 EVEX_CD8<64, CD8VF>;
2519 //===----------------------------------------------------------------------===//
2520 // AVX-512 - MOVDDUP
2521 //===----------------------------------------------------------------------===//
2523 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2524 X86MemOperand x86memop, PatFrag memop_frag> {
2525 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2526 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2527 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2528 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2529 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2531 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2534 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2535 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2536 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2537 (VMOVDDUPZrm addr:$src)>;
2539 //===---------------------------------------------------------------------===//
2540 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2541 //===---------------------------------------------------------------------===//
2542 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2543 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2544 X86MemOperand x86memop> {
2545 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2546 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2547 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2549 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2550 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2551 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2554 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2555 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2556 EVEX_CD8<32, CD8VF>;
2557 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2558 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2559 EVEX_CD8<32, CD8VF>;
2561 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2562 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2563 (VMOVSHDUPZrm addr:$src)>;
2564 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2565 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2566 (VMOVSLDUPZrm addr:$src)>;
2568 //===----------------------------------------------------------------------===//
2569 // Move Low to High and High to Low packed FP Instructions
2570 //===----------------------------------------------------------------------===//
2571 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2572 (ins VR128X:$src1, VR128X:$src2),
2573 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2574 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2575 IIC_SSE_MOV_LH>, EVEX_4V;
2576 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2577 (ins VR128X:$src1, VR128X:$src2),
2578 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2579 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2580 IIC_SSE_MOV_LH>, EVEX_4V;
2582 let Predicates = [HasAVX512] in {
2584 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2585 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2586 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2587 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2590 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2591 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2594 //===----------------------------------------------------------------------===//
2595 // FMA - Fused Multiply Operations
2597 let Constraints = "$src1 = $dst" in {
2598 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2599 RegisterClass RC, X86MemOperand x86memop,
2600 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2601 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2602 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2603 (ins RC:$src1, RC:$src2, RC:$src3),
2604 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2605 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2608 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2609 (ins RC:$src1, RC:$src2, x86memop:$src3),
2610 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2611 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2612 (mem_frag addr:$src3))))]>;
2613 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2614 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2615 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2616 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2617 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2618 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2620 } // Constraints = "$src1 = $dst"
2622 let ExeDomain = SSEPackedSingle in {
2623 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2624 memopv16f32, f32mem, loadf32, "{1to16}",
2625 X86Fmadd, v16f32>, EVEX_V512,
2626 EVEX_CD8<32, CD8VF>;
2627 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2628 memopv16f32, f32mem, loadf32, "{1to16}",
2629 X86Fmsub, v16f32>, EVEX_V512,
2630 EVEX_CD8<32, CD8VF>;
2631 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2632 memopv16f32, f32mem, loadf32, "{1to16}",
2633 X86Fmaddsub, v16f32>,
2634 EVEX_V512, EVEX_CD8<32, CD8VF>;
2635 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2636 memopv16f32, f32mem, loadf32, "{1to16}",
2637 X86Fmsubadd, v16f32>,
2638 EVEX_V512, EVEX_CD8<32, CD8VF>;
2639 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2640 memopv16f32, f32mem, loadf32, "{1to16}",
2641 X86Fnmadd, v16f32>, EVEX_V512,
2642 EVEX_CD8<32, CD8VF>;
2643 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2644 memopv16f32, f32mem, loadf32, "{1to16}",
2645 X86Fnmsub, v16f32>, EVEX_V512,
2646 EVEX_CD8<32, CD8VF>;
2648 let ExeDomain = SSEPackedDouble in {
2649 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2650 memopv8f64, f64mem, loadf64, "{1to8}",
2651 X86Fmadd, v8f64>, EVEX_V512,
2652 VEX_W, EVEX_CD8<64, CD8VF>;
2653 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2654 memopv8f64, f64mem, loadf64, "{1to8}",
2655 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2656 EVEX_CD8<64, CD8VF>;
2657 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2658 memopv8f64, f64mem, loadf64, "{1to8}",
2659 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2660 EVEX_CD8<64, CD8VF>;
2661 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2662 memopv8f64, f64mem, loadf64, "{1to8}",
2663 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2664 EVEX_CD8<64, CD8VF>;
2665 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2666 memopv8f64, f64mem, loadf64, "{1to8}",
2667 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2668 EVEX_CD8<64, CD8VF>;
2669 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2670 memopv8f64, f64mem, loadf64, "{1to8}",
2671 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2672 EVEX_CD8<64, CD8VF>;
2675 let Constraints = "$src1 = $dst" in {
2676 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2677 RegisterClass RC, X86MemOperand x86memop,
2678 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2679 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2681 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2682 (ins RC:$src1, RC:$src3, x86memop:$src2),
2683 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2684 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2685 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2686 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2687 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2688 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2689 [(set RC:$dst, (OpNode RC:$src1,
2690 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2692 } // Constraints = "$src1 = $dst"
2695 let ExeDomain = SSEPackedSingle in {
2696 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2697 memopv16f32, f32mem, loadf32, "{1to16}",
2698 X86Fmadd, v16f32>, EVEX_V512,
2699 EVEX_CD8<32, CD8VF>;
2700 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2701 memopv16f32, f32mem, loadf32, "{1to16}",
2702 X86Fmsub, v16f32>, EVEX_V512,
2703 EVEX_CD8<32, CD8VF>;
2704 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2705 memopv16f32, f32mem, loadf32, "{1to16}",
2706 X86Fmaddsub, v16f32>,
2707 EVEX_V512, EVEX_CD8<32, CD8VF>;
2708 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2709 memopv16f32, f32mem, loadf32, "{1to16}",
2710 X86Fmsubadd, v16f32>,
2711 EVEX_V512, EVEX_CD8<32, CD8VF>;
2712 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2713 memopv16f32, f32mem, loadf32, "{1to16}",
2714 X86Fnmadd, v16f32>, EVEX_V512,
2715 EVEX_CD8<32, CD8VF>;
2716 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2717 memopv16f32, f32mem, loadf32, "{1to16}",
2718 X86Fnmsub, v16f32>, EVEX_V512,
2719 EVEX_CD8<32, CD8VF>;
2721 let ExeDomain = SSEPackedDouble in {
2722 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2723 memopv8f64, f64mem, loadf64, "{1to8}",
2724 X86Fmadd, v8f64>, EVEX_V512,
2725 VEX_W, EVEX_CD8<64, CD8VF>;
2726 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2727 memopv8f64, f64mem, loadf64, "{1to8}",
2728 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2729 EVEX_CD8<64, CD8VF>;
2730 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2731 memopv8f64, f64mem, loadf64, "{1to8}",
2732 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2733 EVEX_CD8<64, CD8VF>;
2734 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2735 memopv8f64, f64mem, loadf64, "{1to8}",
2736 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2737 EVEX_CD8<64, CD8VF>;
2738 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2739 memopv8f64, f64mem, loadf64, "{1to8}",
2740 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2741 EVEX_CD8<64, CD8VF>;
2742 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2743 memopv8f64, f64mem, loadf64, "{1to8}",
2744 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2745 EVEX_CD8<64, CD8VF>;
2749 let Constraints = "$src1 = $dst" in {
2750 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2751 RegisterClass RC, ValueType OpVT,
2752 X86MemOperand x86memop, Operand memop,
2754 let isCommutable = 1 in
2755 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2756 (ins RC:$src1, RC:$src2, RC:$src3),
2757 !strconcat(OpcodeStr,
2758 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2760 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2762 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2763 (ins RC:$src1, RC:$src2, f128mem:$src3),
2764 !strconcat(OpcodeStr,
2765 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2767 (OpVT (OpNode RC:$src2, RC:$src1,
2768 (mem_frag addr:$src3))))]>;
2771 } // Constraints = "$src1 = $dst"
2773 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2774 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2775 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2776 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2777 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2778 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2779 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2780 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2781 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2782 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2783 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2784 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2785 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2786 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2787 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2788 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2790 //===----------------------------------------------------------------------===//
2791 // AVX-512 Scalar convert from sign integer to float/double
2792 //===----------------------------------------------------------------------===//
2794 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2795 X86MemOperand x86memop, string asm> {
2796 let hasSideEffects = 0 in {
2797 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2798 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2801 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2802 (ins DstRC:$src1, x86memop:$src),
2803 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2805 } // hasSideEffects = 0
2807 let Predicates = [HasAVX512] in {
2808 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2809 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2810 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2811 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2812 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2813 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2814 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2815 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2817 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2818 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2819 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2820 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2821 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2822 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2823 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2824 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2826 def : Pat<(f32 (sint_to_fp GR32:$src)),
2827 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2828 def : Pat<(f32 (sint_to_fp GR64:$src)),
2829 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2830 def : Pat<(f64 (sint_to_fp GR32:$src)),
2831 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2832 def : Pat<(f64 (sint_to_fp GR64:$src)),
2833 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2835 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2836 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2837 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2838 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2839 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2840 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2841 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2842 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2844 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2845 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2846 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2847 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2848 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2849 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2850 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2851 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2853 def : Pat<(f32 (uint_to_fp GR32:$src)),
2854 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2855 def : Pat<(f32 (uint_to_fp GR64:$src)),
2856 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2857 def : Pat<(f64 (uint_to_fp GR32:$src)),
2858 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2859 def : Pat<(f64 (uint_to_fp GR64:$src)),
2860 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2863 //===----------------------------------------------------------------------===//
2864 // AVX-512 Scalar convert from float/double to integer
2865 //===----------------------------------------------------------------------===//
2866 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2867 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2869 let hasSideEffects = 0 in {
2870 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2871 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2872 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2873 Requires<[HasAVX512]>;
2875 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2876 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2877 Requires<[HasAVX512]>;
2878 } // hasSideEffects = 0
2880 let Predicates = [HasAVX512] in {
2881 // Convert float/double to signed/unsigned int 32/64
2882 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2883 ssmem, sse_load_f32, "cvtss2si">,
2884 XS, EVEX_CD8<32, CD8VT1>;
2885 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2886 ssmem, sse_load_f32, "cvtss2si">,
2887 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2888 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2889 ssmem, sse_load_f32, "cvtss2usi">,
2890 XS, EVEX_CD8<32, CD8VT1>;
2891 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2892 int_x86_avx512_cvtss2usi64, ssmem,
2893 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2894 EVEX_CD8<32, CD8VT1>;
2895 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2896 sdmem, sse_load_f64, "cvtsd2si">,
2897 XD, EVEX_CD8<64, CD8VT1>;
2898 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2899 sdmem, sse_load_f64, "cvtsd2si">,
2900 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2901 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2902 sdmem, sse_load_f64, "cvtsd2usi">,
2903 XD, EVEX_CD8<64, CD8VT1>;
2904 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2905 int_x86_avx512_cvtsd2usi64, sdmem,
2906 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2907 EVEX_CD8<64, CD8VT1>;
2909 let isCodeGenOnly = 1 in {
2910 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2911 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2912 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2913 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2914 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2915 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2916 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2917 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2918 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2919 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2920 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2921 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2923 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2924 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2925 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2926 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2927 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2928 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2929 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2930 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2931 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2932 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2933 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2934 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2935 } // isCodeGenOnly = 1
2937 // Convert float/double to signed/unsigned int 32/64 with truncation
2938 let isCodeGenOnly = 1 in {
2939 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2940 ssmem, sse_load_f32, "cvttss2si">,
2941 XS, EVEX_CD8<32, CD8VT1>;
2942 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2943 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2944 "cvttss2si">, XS, VEX_W,
2945 EVEX_CD8<32, CD8VT1>;
2946 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2947 sdmem, sse_load_f64, "cvttsd2si">, XD,
2948 EVEX_CD8<64, CD8VT1>;
2949 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2950 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2951 "cvttsd2si">, XD, VEX_W,
2952 EVEX_CD8<64, CD8VT1>;
2953 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2954 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2955 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2956 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2957 int_x86_avx512_cvttss2usi64, ssmem,
2958 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2959 EVEX_CD8<32, CD8VT1>;
2960 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2961 int_x86_avx512_cvttsd2usi,
2962 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2963 EVEX_CD8<64, CD8VT1>;
2964 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2965 int_x86_avx512_cvttsd2usi64, sdmem,
2966 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2967 EVEX_CD8<64, CD8VT1>;
2968 } // isCodeGenOnly = 1
2970 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2971 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2973 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2974 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2975 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2976 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2977 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2978 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2981 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2982 loadf32, "cvttss2si">, XS,
2983 EVEX_CD8<32, CD8VT1>;
2984 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2985 loadf32, "cvttss2usi">, XS,
2986 EVEX_CD8<32, CD8VT1>;
2987 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2988 loadf32, "cvttss2si">, XS, VEX_W,
2989 EVEX_CD8<32, CD8VT1>;
2990 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2991 loadf32, "cvttss2usi">, XS, VEX_W,
2992 EVEX_CD8<32, CD8VT1>;
2993 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2994 loadf64, "cvttsd2si">, XD,
2995 EVEX_CD8<64, CD8VT1>;
2996 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2997 loadf64, "cvttsd2usi">, XD,
2998 EVEX_CD8<64, CD8VT1>;
2999 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3000 loadf64, "cvttsd2si">, XD, VEX_W,
3001 EVEX_CD8<64, CD8VT1>;
3002 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3003 loadf64, "cvttsd2usi">, XD, VEX_W,
3004 EVEX_CD8<64, CD8VT1>;
3006 //===----------------------------------------------------------------------===//
3007 // AVX-512 Convert form float to double and back
3008 //===----------------------------------------------------------------------===//
3009 let hasSideEffects = 0 in {
3010 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3011 (ins FR32X:$src1, FR32X:$src2),
3012 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3013 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3015 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3016 (ins FR32X:$src1, f32mem:$src2),
3017 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3018 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3019 EVEX_CD8<32, CD8VT1>;
3021 // Convert scalar double to scalar single
3022 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3023 (ins FR64X:$src1, FR64X:$src2),
3024 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3025 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3027 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3028 (ins FR64X:$src1, f64mem:$src2),
3029 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3030 []>, EVEX_4V, VEX_LIG, VEX_W,
3031 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3034 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3035 Requires<[HasAVX512]>;
3036 def : Pat<(fextend (loadf32 addr:$src)),
3037 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3039 def : Pat<(extloadf32 addr:$src),
3040 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3041 Requires<[HasAVX512, OptForSize]>;
3043 def : Pat<(extloadf32 addr:$src),
3044 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3045 Requires<[HasAVX512, OptForSpeed]>;
3047 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3048 Requires<[HasAVX512]>;
3050 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3051 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3052 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3054 let hasSideEffects = 0 in {
3055 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3056 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3058 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3059 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3060 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3061 [], d>, EVEX, EVEX_B, EVEX_RC;
3063 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3064 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3066 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3067 } // hasSideEffects = 0
3070 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3071 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3072 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3074 let hasSideEffects = 0 in {
3075 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3076 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3078 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3080 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3081 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3083 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3084 } // hasSideEffects = 0
3087 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3088 memopv8f64, f512mem, v8f32, v8f64,
3089 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3090 EVEX_CD8<64, CD8VF>;
3092 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3093 memopv4f64, f256mem, v8f64, v8f32,
3094 SSEPackedDouble>, EVEX_V512, PS,
3095 EVEX_CD8<32, CD8VH>;
3096 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3097 (VCVTPS2PDZrm addr:$src)>;
3099 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3100 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3101 (VCVTPD2PSZrr VR512:$src)>;
3103 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3104 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3105 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3107 //===----------------------------------------------------------------------===//
3108 // AVX-512 Vector convert from sign integer to float/double
3109 //===----------------------------------------------------------------------===//
3111 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3112 memopv8i64, i512mem, v16f32, v16i32,
3113 SSEPackedSingle>, EVEX_V512, PS,
3114 EVEX_CD8<32, CD8VF>;
3116 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3117 memopv4i64, i256mem, v8f64, v8i32,
3118 SSEPackedDouble>, EVEX_V512, XS,
3119 EVEX_CD8<32, CD8VH>;
3121 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3122 memopv16f32, f512mem, v16i32, v16f32,
3123 SSEPackedSingle>, EVEX_V512, XS,
3124 EVEX_CD8<32, CD8VF>;
3126 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3127 memopv8f64, f512mem, v8i32, v8f64,
3128 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3129 EVEX_CD8<64, CD8VF>;
3131 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3132 memopv16f32, f512mem, v16i32, v16f32,
3133 SSEPackedSingle>, EVEX_V512, PS,
3134 EVEX_CD8<32, CD8VF>;
3136 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3137 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3138 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3139 (VCVTTPS2UDQZrr VR512:$src)>;
3141 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3142 memopv8f64, f512mem, v8i32, v8f64,
3143 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3144 EVEX_CD8<64, CD8VF>;
3146 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3147 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3148 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3149 (VCVTTPD2UDQZrr VR512:$src)>;
3151 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3152 memopv4i64, f256mem, v8f64, v8i32,
3153 SSEPackedDouble>, EVEX_V512, XS,
3154 EVEX_CD8<32, CD8VH>;
3156 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3157 memopv16i32, f512mem, v16f32, v16i32,
3158 SSEPackedSingle>, EVEX_V512, XD,
3159 EVEX_CD8<32, CD8VF>;
3161 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3162 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3163 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3165 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3166 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3167 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3169 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3170 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3171 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3173 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3174 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3175 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3177 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3178 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3179 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3180 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3181 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3182 (VCVTDQ2PDZrr VR256X:$src)>;
3183 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3184 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3185 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3186 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3187 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3188 (VCVTUDQ2PDZrr VR256X:$src)>;
3190 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3191 RegisterClass DstRC, PatFrag mem_frag,
3192 X86MemOperand x86memop, Domain d> {
3193 let hasSideEffects = 0 in {
3194 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3195 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3197 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3198 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3199 [], d>, EVEX, EVEX_B, EVEX_RC;
3201 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3202 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3204 } // hasSideEffects = 0
3207 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3208 memopv16f32, f512mem, SSEPackedSingle>, PD,
3209 EVEX_V512, EVEX_CD8<32, CD8VF>;
3210 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3211 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3212 EVEX_V512, EVEX_CD8<64, CD8VF>;
3214 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3215 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3216 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3218 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3219 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3220 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3222 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3223 memopv16f32, f512mem, SSEPackedSingle>,
3224 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3225 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3226 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3227 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3229 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3230 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3231 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3233 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3234 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3235 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3237 let Predicates = [HasAVX512] in {
3238 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3239 (VCVTPD2PSZrm addr:$src)>;
3240 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3241 (VCVTPS2PDZrm addr:$src)>;
3244 //===----------------------------------------------------------------------===//
3245 // Half precision conversion instructions
3246 //===----------------------------------------------------------------------===//
3247 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3248 X86MemOperand x86memop> {
3249 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3250 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3252 let hasSideEffects = 0, mayLoad = 1 in
3253 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3254 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3257 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3258 X86MemOperand x86memop> {
3259 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3260 (ins srcRC:$src1, i32i8imm:$src2),
3261 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3263 let hasSideEffects = 0, mayStore = 1 in
3264 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3265 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3266 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3269 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3270 EVEX_CD8<32, CD8VH>;
3271 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3272 EVEX_CD8<32, CD8VH>;
3274 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3275 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3276 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3278 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3279 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3280 (VCVTPH2PSZrr VR256X:$src)>;
3282 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3283 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3284 "ucomiss">, PS, EVEX, VEX_LIG,
3285 EVEX_CD8<32, CD8VT1>;
3286 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3287 "ucomisd">, PD, EVEX,
3288 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3289 let Pattern = []<dag> in {
3290 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3291 "comiss">, PS, EVEX, VEX_LIG,
3292 EVEX_CD8<32, CD8VT1>;
3293 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3294 "comisd">, PD, EVEX,
3295 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3297 let isCodeGenOnly = 1 in {
3298 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3299 load, "ucomiss">, PS, EVEX, VEX_LIG,
3300 EVEX_CD8<32, CD8VT1>;
3301 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3302 load, "ucomisd">, PD, EVEX,
3303 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3305 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3306 load, "comiss">, PS, EVEX, VEX_LIG,
3307 EVEX_CD8<32, CD8VT1>;
3308 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3309 load, "comisd">, PD, EVEX,
3310 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3314 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3315 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3316 X86MemOperand x86memop> {
3317 let hasSideEffects = 0 in {
3318 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3319 (ins RC:$src1, RC:$src2),
3320 !strconcat(OpcodeStr,
3321 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3322 let mayLoad = 1 in {
3323 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3324 (ins RC:$src1, x86memop:$src2),
3325 !strconcat(OpcodeStr,
3326 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3331 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3332 EVEX_CD8<32, CD8VT1>;
3333 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3334 VEX_W, EVEX_CD8<64, CD8VT1>;
3335 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3336 EVEX_CD8<32, CD8VT1>;
3337 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3338 VEX_W, EVEX_CD8<64, CD8VT1>;
3340 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3341 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3342 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3343 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3345 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3346 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3347 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3348 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3350 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3351 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3352 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3353 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3355 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3356 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3357 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3358 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3360 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3361 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3362 RegisterClass RC, X86MemOperand x86memop,
3363 PatFrag mem_frag, ValueType OpVt> {
3364 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3365 !strconcat(OpcodeStr,
3366 " \t{$src, $dst|$dst, $src}"),
3367 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3369 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3370 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3371 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3374 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3375 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3376 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3377 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3378 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3379 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3380 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3381 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3383 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3384 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3385 (VRSQRT14PSZr VR512:$src)>;
3386 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3387 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3388 (VRSQRT14PDZr VR512:$src)>;
3390 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3391 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3392 (VRCP14PSZr VR512:$src)>;
3393 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3394 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3395 (VRCP14PDZr VR512:$src)>;
3397 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3398 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3399 X86MemOperand x86memop> {
3400 let hasSideEffects = 0, Predicates = [HasERI] in {
3401 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3402 (ins RC:$src1, RC:$src2),
3403 !strconcat(OpcodeStr,
3404 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3405 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3406 (ins RC:$src1, RC:$src2),
3407 !strconcat(OpcodeStr,
3408 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3409 []>, EVEX_4V, EVEX_B;
3410 let mayLoad = 1 in {
3411 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3412 (ins RC:$src1, x86memop:$src2),
3413 !strconcat(OpcodeStr,
3414 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3419 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3420 EVEX_CD8<32, CD8VT1>;
3421 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3422 VEX_W, EVEX_CD8<64, CD8VT1>;
3423 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3424 EVEX_CD8<32, CD8VT1>;
3425 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3426 VEX_W, EVEX_CD8<64, CD8VT1>;
3428 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3429 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3431 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3432 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3434 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3435 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3437 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3438 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3440 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3441 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3443 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3444 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3446 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3447 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3449 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3450 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3452 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3453 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3454 RegisterClass RC, X86MemOperand x86memop> {
3455 let hasSideEffects = 0, Predicates = [HasERI] in {
3456 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3457 !strconcat(OpcodeStr,
3458 " \t{$src, $dst|$dst, $src}"),
3460 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3461 !strconcat(OpcodeStr,
3462 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3464 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3465 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3469 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3470 EVEX_V512, EVEX_CD8<32, CD8VF>;
3471 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3472 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3473 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3474 EVEX_V512, EVEX_CD8<32, CD8VF>;
3475 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3476 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3478 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3479 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3480 (VRSQRT28PSZrb VR512:$src)>;
3481 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3482 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3483 (VRSQRT28PDZrb VR512:$src)>;
3485 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3486 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3487 (VRCP28PSZrb VR512:$src)>;
3488 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3489 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3490 (VRCP28PDZrb VR512:$src)>;
3492 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3493 Intrinsic V16F32Int, Intrinsic V8F64Int,
3494 OpndItins itins_s, OpndItins itins_d> {
3495 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3496 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3497 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3501 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3502 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3504 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3505 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3507 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3508 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3509 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3513 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3514 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3515 [(set VR512:$dst, (OpNode
3516 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3517 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3519 let isCodeGenOnly = 1 in {
3520 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3521 !strconcat(OpcodeStr,
3522 "ps\t{$src, $dst|$dst, $src}"),
3523 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3525 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3526 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3528 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3529 EVEX_V512, EVEX_CD8<32, CD8VF>;
3530 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3531 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3532 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3533 EVEX, EVEX_V512, VEX_W;
3534 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3535 !strconcat(OpcodeStr,
3536 "pd\t{$src, $dst|$dst, $src}"),
3537 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3538 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3539 } // isCodeGenOnly = 1
3542 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3543 Intrinsic F32Int, Intrinsic F64Int,
3544 OpndItins itins_s, OpndItins itins_d> {
3545 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3546 (ins FR32X:$src1, FR32X:$src2),
3547 !strconcat(OpcodeStr,
3548 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3549 [], itins_s.rr>, XS, EVEX_4V;
3550 let isCodeGenOnly = 1 in
3551 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3552 (ins VR128X:$src1, VR128X:$src2),
3553 !strconcat(OpcodeStr,
3554 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3556 (F32Int VR128X:$src1, VR128X:$src2))],
3557 itins_s.rr>, XS, EVEX_4V;
3558 let mayLoad = 1 in {
3559 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3560 (ins FR32X:$src1, f32mem:$src2),
3561 !strconcat(OpcodeStr,
3562 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3563 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3564 let isCodeGenOnly = 1 in
3565 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3566 (ins VR128X:$src1, ssmem:$src2),
3567 !strconcat(OpcodeStr,
3568 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3570 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3571 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3573 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3574 (ins FR64X:$src1, FR64X:$src2),
3575 !strconcat(OpcodeStr,
3576 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3578 let isCodeGenOnly = 1 in
3579 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3580 (ins VR128X:$src1, VR128X:$src2),
3581 !strconcat(OpcodeStr,
3582 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3584 (F64Int VR128X:$src1, VR128X:$src2))],
3585 itins_s.rr>, XD, EVEX_4V, VEX_W;
3586 let mayLoad = 1 in {
3587 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3588 (ins FR64X:$src1, f64mem:$src2),
3589 !strconcat(OpcodeStr,
3590 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3591 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3592 let isCodeGenOnly = 1 in
3593 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3594 (ins VR128X:$src1, sdmem:$src2),
3595 !strconcat(OpcodeStr,
3596 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3598 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3599 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3604 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3605 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3606 SSE_SQRTSS, SSE_SQRTSD>,
3607 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3608 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3609 SSE_SQRTPS, SSE_SQRTPD>;
3611 let Predicates = [HasAVX512] in {
3612 def : Pat<(f32 (fsqrt FR32X:$src)),
3613 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3614 def : Pat<(f32 (fsqrt (load addr:$src))),
3615 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3616 Requires<[OptForSize]>;
3617 def : Pat<(f64 (fsqrt FR64X:$src)),
3618 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3619 def : Pat<(f64 (fsqrt (load addr:$src))),
3620 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3621 Requires<[OptForSize]>;
3623 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3624 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3625 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3626 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3627 Requires<[OptForSize]>;
3629 def : Pat<(f32 (X86frcp FR32X:$src)),
3630 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3631 def : Pat<(f32 (X86frcp (load addr:$src))),
3632 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3633 Requires<[OptForSize]>;
3635 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3636 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3637 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3639 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3640 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3642 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3643 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3644 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3646 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3647 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3651 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3652 X86MemOperand x86memop, RegisterClass RC,
3653 PatFrag mem_frag32, PatFrag mem_frag64,
3654 Intrinsic V4F32Int, Intrinsic V2F64Int,
3656 let ExeDomain = SSEPackedSingle in {
3657 // Intrinsic operation, reg.
3658 // Vector intrinsic operation, reg
3659 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3660 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3661 !strconcat(OpcodeStr,
3662 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3663 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3665 // Vector intrinsic operation, mem
3666 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3667 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3668 !strconcat(OpcodeStr,
3669 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3671 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3672 EVEX_CD8<32, VForm>;
3673 } // ExeDomain = SSEPackedSingle
3675 let ExeDomain = SSEPackedDouble in {
3676 // Vector intrinsic operation, reg
3677 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3678 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3679 !strconcat(OpcodeStr,
3680 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3681 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3683 // Vector intrinsic operation, mem
3684 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3685 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3686 !strconcat(OpcodeStr,
3687 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3689 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3690 EVEX_CD8<64, VForm>;
3691 } // ExeDomain = SSEPackedDouble
3694 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3698 let ExeDomain = GenericDomain in {
3700 let hasSideEffects = 0 in
3701 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3702 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3703 !strconcat(OpcodeStr,
3704 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3707 // Intrinsic operation, reg.
3708 let isCodeGenOnly = 1 in
3709 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3710 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3711 !strconcat(OpcodeStr,
3712 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3713 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3715 // Intrinsic operation, mem.
3716 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3717 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3718 !strconcat(OpcodeStr,
3719 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3720 [(set VR128X:$dst, (F32Int VR128X:$src1,
3721 sse_load_f32:$src2, imm:$src3))]>,
3722 EVEX_CD8<32, CD8VT1>;
3725 let hasSideEffects = 0 in
3726 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3727 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3728 !strconcat(OpcodeStr,
3729 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3732 // Intrinsic operation, reg.
3733 let isCodeGenOnly = 1 in
3734 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3735 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3736 !strconcat(OpcodeStr,
3737 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3738 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3741 // Intrinsic operation, mem.
3742 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3743 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3744 !strconcat(OpcodeStr,
3745 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3747 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3748 VEX_W, EVEX_CD8<64, CD8VT1>;
3749 } // ExeDomain = GenericDomain
3752 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3753 X86MemOperand x86memop, RegisterClass RC,
3754 PatFrag mem_frag, Domain d> {
3755 let ExeDomain = d in {
3756 // Intrinsic operation, reg.
3757 // Vector intrinsic operation, reg
3758 def r : AVX512AIi8<opc, MRMSrcReg,
3759 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3760 !strconcat(OpcodeStr,
3761 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3764 // Vector intrinsic operation, mem
3765 def m : AVX512AIi8<opc, MRMSrcMem,
3766 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3767 !strconcat(OpcodeStr,
3768 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3774 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3775 memopv16f32, SSEPackedSingle>, EVEX_V512,
3776 EVEX_CD8<32, CD8VF>;
3778 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3779 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3781 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3784 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3785 memopv8f64, SSEPackedDouble>, EVEX_V512,
3786 VEX_W, EVEX_CD8<64, CD8VF>;
3788 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3789 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3791 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3793 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3794 Operand x86memop, RegisterClass RC, Domain d> {
3795 let ExeDomain = d in {
3796 def r : AVX512AIi8<opc, MRMSrcReg,
3797 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3798 !strconcat(OpcodeStr,
3799 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3802 def m : AVX512AIi8<opc, MRMSrcMem,
3803 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3804 !strconcat(OpcodeStr,
3805 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3810 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3811 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3813 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3814 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3816 def : Pat<(ffloor FR32X:$src),
3817 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3818 def : Pat<(f64 (ffloor FR64X:$src)),
3819 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3820 def : Pat<(f32 (fnearbyint FR32X:$src)),
3821 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3822 def : Pat<(f64 (fnearbyint FR64X:$src)),
3823 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3824 def : Pat<(f32 (fceil FR32X:$src)),
3825 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3826 def : Pat<(f64 (fceil FR64X:$src)),
3827 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3828 def : Pat<(f32 (frint FR32X:$src)),
3829 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3830 def : Pat<(f64 (frint FR64X:$src)),
3831 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3832 def : Pat<(f32 (ftrunc FR32X:$src)),
3833 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3834 def : Pat<(f64 (ftrunc FR64X:$src)),
3835 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3837 def : Pat<(v16f32 (ffloor VR512:$src)),
3838 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3839 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3840 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3841 def : Pat<(v16f32 (fceil VR512:$src)),
3842 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3843 def : Pat<(v16f32 (frint VR512:$src)),
3844 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3845 def : Pat<(v16f32 (ftrunc VR512:$src)),
3846 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3848 def : Pat<(v8f64 (ffloor VR512:$src)),
3849 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3850 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3851 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3852 def : Pat<(v8f64 (fceil VR512:$src)),
3853 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3854 def : Pat<(v8f64 (frint VR512:$src)),
3855 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3856 def : Pat<(v8f64 (ftrunc VR512:$src)),
3857 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3859 //-------------------------------------------------
3860 // Integer truncate and extend operations
3861 //-------------------------------------------------
3863 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3864 RegisterClass dstRC, RegisterClass srcRC,
3865 RegisterClass KRC, X86MemOperand x86memop> {
3866 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3868 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3871 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3872 (ins KRC:$mask, srcRC:$src),
3873 !strconcat(OpcodeStr,
3874 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
3877 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3878 (ins KRC:$mask, srcRC:$src),
3879 !strconcat(OpcodeStr,
3880 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3883 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3884 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3887 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
3888 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
3889 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
3893 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3894 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3895 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3896 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3897 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3898 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3899 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3900 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3901 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3902 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3903 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3904 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3905 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3906 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3907 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3908 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3909 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3910 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3911 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3912 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3913 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3914 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3915 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3916 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3917 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3918 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3919 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3920 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3921 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3922 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3924 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3925 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3926 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3927 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3928 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3930 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3931 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
3932 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3933 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
3934 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3935 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
3936 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3937 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
3940 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3941 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
3942 PatFrag mem_frag, X86MemOperand x86memop,
3943 ValueType OpVT, ValueType InVT> {
3945 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3947 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3948 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3950 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3951 (ins KRC:$mask, SrcRC:$src),
3952 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
3955 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3956 (ins KRC:$mask, SrcRC:$src),
3957 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
3960 let mayLoad = 1 in {
3961 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3962 (ins x86memop:$src),
3963 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3965 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3968 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3969 (ins KRC:$mask, x86memop:$src),
3970 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
3974 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3975 (ins KRC:$mask, x86memop:$src),
3976 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
3982 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
3983 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3985 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
3986 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3988 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
3989 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3990 EVEX_CD8<16, CD8VH>;
3991 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
3992 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3993 EVEX_CD8<16, CD8VQ>;
3994 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
3995 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3996 EVEX_CD8<32, CD8VH>;
3998 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
3999 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4001 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4002 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4004 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4005 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4006 EVEX_CD8<16, CD8VH>;
4007 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4008 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4009 EVEX_CD8<16, CD8VQ>;
4010 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4011 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4012 EVEX_CD8<32, CD8VH>;
4014 //===----------------------------------------------------------------------===//
4015 // GATHER - SCATTER Operations
4017 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4018 RegisterClass RC, X86MemOperand memop> {
4020 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4021 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4022 (ins RC:$src1, KRC:$mask, memop:$src2),
4023 !strconcat(OpcodeStr,
4024 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4028 let ExeDomain = SSEPackedDouble in {
4029 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4030 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4031 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4032 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4035 let ExeDomain = SSEPackedSingle in {
4036 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4037 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4038 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4039 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4042 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4043 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4044 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4045 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4047 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4048 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4049 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4050 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4052 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4053 RegisterClass RC, X86MemOperand memop> {
4054 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4055 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4056 (ins memop:$dst, KRC:$mask, RC:$src2),
4057 !strconcat(OpcodeStr,
4058 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4062 let ExeDomain = SSEPackedDouble in {
4063 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4064 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4065 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4066 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4069 let ExeDomain = SSEPackedSingle in {
4070 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4071 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4072 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4073 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4076 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4077 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4078 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4079 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4081 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4082 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4083 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4084 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4087 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4088 RegisterClass KRC, X86MemOperand memop> {
4089 let Predicates = [HasPFI], hasSideEffects = 1 in
4090 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4091 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4095 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4096 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4098 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4099 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4101 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4102 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4104 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4105 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4107 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4108 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4110 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4111 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4113 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4114 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4116 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4117 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4119 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4120 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4122 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4123 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4125 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4126 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4128 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4129 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4131 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4132 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4134 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4135 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4137 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4138 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4140 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4141 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4142 //===----------------------------------------------------------------------===//
4143 // VSHUFPS - VSHUFPD Operations
4145 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4146 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4148 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4149 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4150 !strconcat(OpcodeStr,
4151 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4152 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4153 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4154 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4155 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4156 (ins RC:$src1, RC:$src2, i8imm:$src3),
4157 !strconcat(OpcodeStr,
4158 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4159 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4160 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4161 EVEX_4V, Sched<[WriteShuffle]>;
4164 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4165 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4166 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4167 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4169 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4170 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4171 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4172 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4173 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4175 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4176 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4177 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4178 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4179 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4181 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4182 X86MemOperand x86memop> {
4183 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4184 (ins RC:$src1, RC:$src2, i8imm:$src3),
4185 !strconcat(OpcodeStr,
4186 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4189 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4190 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4191 !strconcat(OpcodeStr,
4192 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4195 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4196 EVEX_V512, EVEX_CD8<32, CD8VF>;
4197 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4198 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4200 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4201 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4202 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4203 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4204 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4205 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4206 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4207 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4209 // Helper fragments to match sext vXi1 to vXiY.
4210 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4211 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4213 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4214 RegisterClass KRC, RegisterClass RC,
4215 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4217 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4218 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4220 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4221 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4223 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4224 !strconcat(OpcodeStr,
4225 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4227 let mayLoad = 1 in {
4228 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4229 (ins x86memop:$src),
4230 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4232 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4233 (ins KRC:$mask, x86memop:$src),
4234 !strconcat(OpcodeStr,
4235 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4237 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4238 (ins KRC:$mask, x86memop:$src),
4239 !strconcat(OpcodeStr,
4240 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4242 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4243 (ins x86scalar_mop:$src),
4244 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4245 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4247 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4248 (ins KRC:$mask, x86scalar_mop:$src),
4249 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4250 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4251 []>, EVEX, EVEX_B, EVEX_K;
4252 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4253 (ins KRC:$mask, x86scalar_mop:$src),
4254 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4255 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4257 []>, EVEX, EVEX_B, EVEX_KZ;
4261 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4262 i512mem, i32mem, "{1to16}">, EVEX_V512,
4263 EVEX_CD8<32, CD8VF>;
4264 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4265 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4266 EVEX_CD8<64, CD8VF>;
4269 (bc_v16i32 (v16i1sextv16i32)),
4270 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4271 (VPABSDZrr VR512:$src)>;
4273 (bc_v8i64 (v8i1sextv8i64)),
4274 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4275 (VPABSQZrr VR512:$src)>;
4277 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4278 (v16i32 immAllZerosV), (i16 -1))),
4279 (VPABSDZrr VR512:$src)>;
4280 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4281 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4282 (VPABSQZrr VR512:$src)>;
4284 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4285 RegisterClass RC, RegisterClass KRC,
4286 X86MemOperand x86memop,
4287 X86MemOperand x86scalar_mop, string BrdcstStr> {
4288 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4290 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4292 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4293 (ins x86memop:$src),
4294 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4296 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4297 (ins x86scalar_mop:$src),
4298 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4299 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4301 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4302 (ins KRC:$mask, RC:$src),
4303 !strconcat(OpcodeStr,
4304 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4306 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4307 (ins KRC:$mask, x86memop:$src),
4308 !strconcat(OpcodeStr,
4309 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4311 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4312 (ins KRC:$mask, x86scalar_mop:$src),
4313 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4314 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4316 []>, EVEX, EVEX_KZ, EVEX_B;
4318 let Constraints = "$src1 = $dst" in {
4319 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4320 (ins RC:$src1, KRC:$mask, RC:$src2),
4321 !strconcat(OpcodeStr,
4322 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4324 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4325 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4326 !strconcat(OpcodeStr,
4327 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4329 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4330 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4331 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4332 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4333 []>, EVEX, EVEX_K, EVEX_B;
4337 let Predicates = [HasCDI] in {
4338 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4339 i512mem, i32mem, "{1to16}">,
4340 EVEX_V512, EVEX_CD8<32, CD8VF>;
4343 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4344 i512mem, i64mem, "{1to8}">,
4345 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4349 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4351 (VPCONFLICTDrrk VR512:$src1,
4352 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4354 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4356 (VPCONFLICTQrrk VR512:$src1,
4357 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4359 let Predicates = [HasCDI] in {
4360 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4361 i512mem, i32mem, "{1to16}">,
4362 EVEX_V512, EVEX_CD8<32, CD8VF>;
4365 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4366 i512mem, i64mem, "{1to8}">,
4367 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4371 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4373 (VPLZCNTDrrk VR512:$src1,
4374 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4376 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4378 (VPLZCNTQrrk VR512:$src1,
4379 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4381 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4382 (VPLZCNTDrm addr:$src)>;
4383 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4384 (VPLZCNTDrr VR512:$src)>;
4385 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4386 (VPLZCNTQrm addr:$src)>;
4387 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4388 (VPLZCNTQrr VR512:$src)>;
4390 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4391 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4392 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4394 def : Pat<(store VK1:$src, addr:$dst),
4395 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4397 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4398 (truncstore node:$val, node:$ptr), [{
4399 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4402 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4403 (MOV8mr addr:$dst, GR8:$src)>;