1 // Common base class of AVX512_masking and AVX512_masking_3src.
2 multiclass AVX512_masking_common<bits<8> O, Format F, dag Outs, dag Ins,
3 dag MaskingIns, dag ZeroMaskingIns,
5 string AttSrcAsm, string IntelSrcAsm,
6 dag RHS, dag MaskingRHS, ValueType OpVT,
7 RegisterClass RC, RegisterClass KRC,
8 string MaskingConstraint = ""> {
9 def NAME: AVX512<O, F, Outs, Ins,
10 OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
11 "$dst, "#IntelSrcAsm#"}",
12 [(set RC:$dst, RHS)]>;
14 // Prefer over VMOV*rrk Pat<>
15 let AddedComplexity = 20 in
16 def NAME#k: AVX512<O, F, Outs, MaskingIns,
17 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
18 "$dst {${mask}}, "#IntelSrcAsm#"}",
19 [(set RC:$dst, MaskingRHS)]>,
21 // In case of the 3src subclass this is overridden with a let.
22 string Constraints = MaskingConstraint;
24 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
25 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
26 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
27 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
29 (vselect KRC:$mask, RHS,
31 (v16i32 immAllZerosV)))))]>,
35 // This multiclass generates the unconditional/non-masking, the masking and
36 // the zero-masking variant of the instruction. In the masking case, the
37 // perserved vector elements come from a new dummy input operand tied to $dst.
38 multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
40 string AttSrcAsm, string IntelSrcAsm,
41 dag RHS, ValueType OpVT, RegisterClass RC,
43 AVX512_masking_common<O, F, Outs,
45 !con((ins RC:$src0, KRC:$mask), Ins),
46 !con((ins KRC:$mask), Ins),
47 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
48 (vselect KRC:$mask, RHS, RC:$src0), OpVT, RC, KRC,
51 // Similar to AVX512_masking but in this case one of the source operands
52 // ($src1) is already tied to $dst so we just use that for the preserved
53 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
55 multiclass AVX512_masking_3src<bits<8> O, Format F, dag Outs, dag NonTiedIns,
57 string AttSrcAsm, string IntelSrcAsm,
58 dag RHS, ValueType OpVT,
59 RegisterClass RC, RegisterClass KRC> :
60 AVX512_masking_common<O, F, Outs,
61 !con((ins RC:$src1), NonTiedIns),
62 !con((ins RC:$src1), !con((ins KRC:$mask),
64 !con((ins RC:$src1), !con((ins KRC:$mask),
66 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
67 (vselect KRC:$mask, RHS, RC:$src1), OpVT, RC, KRC>;
69 // Bitcasts between 512-bit vector types. Return the original type since
70 // no instruction is needed for the conversion
71 let Predicates = [HasAVX512] in {
72 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
73 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
74 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
75 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
76 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
77 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
78 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
79 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
80 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
81 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
82 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
83 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
84 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
85 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
86 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
87 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
88 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
89 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
90 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
91 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
92 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
93 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
94 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
95 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
96 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
97 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
98 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
99 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
100 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
101 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
102 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
104 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
105 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
106 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
107 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
108 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
109 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
110 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
111 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
112 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
113 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
114 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
115 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
116 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
117 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
118 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
119 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
120 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
121 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
122 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
123 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
124 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
125 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
126 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
127 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
128 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
129 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
130 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
131 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
132 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
133 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
135 // Bitcasts between 256-bit vector types. Return the original type since
136 // no instruction is needed for the conversion
137 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
138 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
139 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
140 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
141 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
142 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
143 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
144 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
145 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
146 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
147 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
148 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
149 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
150 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
151 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
152 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
153 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
154 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
155 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
156 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
157 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
158 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
159 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
160 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
161 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
162 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
163 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
164 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
165 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
166 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
170 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
173 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
174 isPseudo = 1, Predicates = [HasAVX512] in {
175 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
176 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
179 let Predicates = [HasAVX512] in {
180 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
181 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
182 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
185 //===----------------------------------------------------------------------===//
186 // AVX-512 - VECTOR INSERT
189 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
190 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
191 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
192 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
193 []>, EVEX_4V, EVEX_V512;
195 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
196 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
197 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
198 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
201 // -- 64x4 fp form --
202 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
203 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
204 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
205 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
206 []>, EVEX_4V, EVEX_V512, VEX_W;
208 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
209 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
210 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
213 // -- 32x4 integer form --
214 let hasSideEffects = 0 in {
215 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
216 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
217 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
218 []>, EVEX_4V, EVEX_V512;
220 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
221 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
222 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
223 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
226 let hasSideEffects = 0 in {
228 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
229 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
230 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
231 []>, EVEX_4V, EVEX_V512, VEX_W;
233 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
234 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
235 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
236 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
239 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
240 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
241 (INSERT_get_vinsert128_imm VR512:$ins))>;
242 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
243 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
244 (INSERT_get_vinsert128_imm VR512:$ins))>;
245 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
246 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
247 (INSERT_get_vinsert128_imm VR512:$ins))>;
248 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
249 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
250 (INSERT_get_vinsert128_imm VR512:$ins))>;
252 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
253 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
254 (INSERT_get_vinsert128_imm VR512:$ins))>;
255 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
256 (bc_v4i32 (loadv2i64 addr:$src2)),
257 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
258 (INSERT_get_vinsert128_imm VR512:$ins))>;
259 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
260 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
261 (INSERT_get_vinsert128_imm VR512:$ins))>;
262 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
263 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
264 (INSERT_get_vinsert128_imm VR512:$ins))>;
266 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
267 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
268 (INSERT_get_vinsert256_imm VR512:$ins))>;
269 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
270 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
271 (INSERT_get_vinsert256_imm VR512:$ins))>;
272 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
273 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
274 (INSERT_get_vinsert256_imm VR512:$ins))>;
275 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
276 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
277 (INSERT_get_vinsert256_imm VR512:$ins))>;
279 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
280 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
281 (INSERT_get_vinsert256_imm VR512:$ins))>;
282 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
283 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
284 (INSERT_get_vinsert256_imm VR512:$ins))>;
285 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
286 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
287 (INSERT_get_vinsert256_imm VR512:$ins))>;
288 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
289 (bc_v8i32 (loadv4i64 addr:$src2)),
290 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
291 (INSERT_get_vinsert256_imm VR512:$ins))>;
293 // vinsertps - insert f32 to XMM
294 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
295 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
296 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
297 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
299 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
300 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
301 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
302 [(set VR128X:$dst, (X86insertps VR128X:$src1,
303 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
304 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
306 //===----------------------------------------------------------------------===//
307 // AVX-512 VECTOR EXTRACT
309 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
311 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
312 (ins VR512:$src1, i8imm:$src2),
313 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
314 []>, EVEX, EVEX_V512;
315 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
316 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
317 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
318 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
321 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
322 (ins VR512:$src1, i8imm:$src2),
323 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
324 []>, EVEX, EVEX_V512, VEX_W;
326 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
327 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
328 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
329 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
332 let hasSideEffects = 0 in {
334 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
335 (ins VR512:$src1, i8imm:$src2),
336 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
337 []>, EVEX, EVEX_V512;
338 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
339 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
340 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
341 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
344 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
345 (ins VR512:$src1, i8imm:$src2),
346 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
347 []>, EVEX, EVEX_V512, VEX_W;
349 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
350 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
351 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
352 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
355 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
356 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
357 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
359 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
360 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
361 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
363 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
364 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
365 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
367 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
368 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
369 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
372 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
373 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
374 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
376 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
377 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
378 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
380 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
381 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
382 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
384 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
385 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
386 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
388 // A 256-bit subvector extract from the first 512-bit vector position
389 // is a subregister copy that needs no instruction.
390 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
391 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
392 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
393 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
394 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
395 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
396 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
397 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
400 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
401 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
402 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
403 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
404 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
405 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
406 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
407 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
410 // A 128-bit subvector insert to the first 512-bit vector position
411 // is a subregister copy that needs no instruction.
412 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
413 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
414 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
416 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
417 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
418 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
420 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
421 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
422 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
424 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
425 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
426 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
429 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
430 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
431 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
432 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
433 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
434 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
435 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
436 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
438 // vextractps - extract 32 bits from XMM
439 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
440 (ins VR128X:$src1, u32u8imm:$src2),
441 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
442 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
445 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
446 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
447 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
448 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
449 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
451 //===---------------------------------------------------------------------===//
454 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
455 RegisterClass DestRC,
456 RegisterClass SrcRC, X86MemOperand x86memop> {
457 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
458 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
460 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
461 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
463 let ExeDomain = SSEPackedSingle in {
464 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
469 let ExeDomain = SSEPackedDouble in {
470 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
472 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
475 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
476 (VBROADCASTSSZrm addr:$src)>;
477 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
478 (VBROADCASTSDZrm addr:$src)>;
480 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
481 (VBROADCASTSSZrm addr:$src)>;
482 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
483 (VBROADCASTSDZrm addr:$src)>;
485 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
486 RegisterClass SrcRC, RegisterClass KRC> {
487 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
488 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
489 []>, EVEX, EVEX_V512;
490 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
491 (ins KRC:$mask, SrcRC:$src),
492 !strconcat(OpcodeStr,
493 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
494 []>, EVEX, EVEX_V512, EVEX_KZ;
497 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
498 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
501 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
502 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
504 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
505 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
507 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
508 (VPBROADCASTDrZrr GR32:$src)>;
509 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
510 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
511 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
512 (VPBROADCASTQrZrr GR64:$src)>;
513 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
514 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
516 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
517 (VPBROADCASTDrZrr GR32:$src)>;
518 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
519 (VPBROADCASTQrZrr GR64:$src)>;
521 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
522 (v16i32 immAllZerosV), (i16 GR16:$mask))),
523 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
524 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
525 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
526 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
528 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
529 X86MemOperand x86memop, PatFrag ld_frag,
530 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
532 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
533 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
535 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
536 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
538 !strconcat(OpcodeStr,
539 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
541 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
544 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
545 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
547 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
548 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
550 !strconcat(OpcodeStr,
551 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
552 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
553 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
557 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
558 loadi32, VR512, v16i32, v4i32, VK16WM>,
559 EVEX_V512, EVEX_CD8<32, CD8VT1>;
560 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
561 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
562 EVEX_CD8<64, CD8VT1>;
564 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
565 X86MemOperand x86memop, PatFrag ld_frag,
568 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
569 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
571 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
573 !strconcat(OpcodeStr,
574 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
579 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
580 i128mem, loadv2i64, VK16WM>,
581 EVEX_V512, EVEX_CD8<32, CD8VT4>;
582 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
583 i256mem, loadv4i64, VK16WM>, VEX_W,
584 EVEX_V512, EVEX_CD8<64, CD8VT4>;
586 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
587 (VPBROADCASTDZrr VR128X:$src)>;
588 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
589 (VPBROADCASTQZrr VR128X:$src)>;
591 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
592 (VBROADCASTSSZrr VR128X:$src)>;
593 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
594 (VBROADCASTSDZrr VR128X:$src)>;
596 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
597 (VBROADCASTSSZrr VR128X:$src)>;
598 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
599 (VBROADCASTSDZrr VR128X:$src)>;
601 // Provide fallback in case the load node that is used in the patterns above
602 // is used by additional users, which prevents the pattern selection.
603 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
604 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
605 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
606 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
609 let Predicates = [HasAVX512] in {
610 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
612 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
613 addr:$src)), sub_ymm)>;
615 //===----------------------------------------------------------------------===//
616 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
619 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
620 RegisterClass DstRC, RegisterClass KRC,
621 ValueType OpVT, ValueType SrcVT> {
622 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
623 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
627 let Predicates = [HasCDI] in {
628 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
629 VK16, v16i32, v16i1>, EVEX_V512;
630 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
631 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
634 //===----------------------------------------------------------------------===//
637 // -- immediate form --
638 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
639 SDNode OpNode, PatFrag mem_frag,
640 X86MemOperand x86memop, ValueType OpVT> {
641 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
642 (ins RC:$src1, i8imm:$src2),
643 !strconcat(OpcodeStr,
644 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
646 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
648 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
649 (ins x86memop:$src1, i8imm:$src2),
650 !strconcat(OpcodeStr,
651 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
653 (OpVT (OpNode (mem_frag addr:$src1),
654 (i8 imm:$src2))))]>, EVEX;
657 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
658 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
659 let ExeDomain = SSEPackedDouble in
660 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
661 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
663 // -- VPERM - register form --
664 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
665 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
667 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
668 (ins RC:$src1, RC:$src2),
669 !strconcat(OpcodeStr,
670 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
672 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
674 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
675 (ins RC:$src1, x86memop:$src2),
676 !strconcat(OpcodeStr,
677 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
679 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
683 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
684 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
685 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
686 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
687 let ExeDomain = SSEPackedSingle in
688 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
689 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
690 let ExeDomain = SSEPackedDouble in
691 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
692 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
694 // -- VPERM2I - 3 source operands form --
695 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
696 PatFrag mem_frag, X86MemOperand x86memop,
697 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
698 let Constraints = "$src1 = $dst" in {
699 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
700 (ins RC:$src1, RC:$src2, RC:$src3),
701 !strconcat(OpcodeStr,
702 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
704 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
707 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
708 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
709 !strconcat(OpcodeStr,
710 " \t{$src3, $src2, $dst {${mask}}|"
711 "$dst {${mask}}, $src2, $src3}"),
712 [(set RC:$dst, (OpVT (vselect KRC:$mask,
713 (OpNode RC:$src1, RC:$src2,
718 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
719 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
720 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
721 !strconcat(OpcodeStr,
722 " \t{$src3, $src2, $dst {${mask}} {z} |",
723 "$dst {${mask}} {z}, $src2, $src3}"),
724 [(set RC:$dst, (OpVT (vselect KRC:$mask,
725 (OpNode RC:$src1, RC:$src2,
728 (v16i32 immAllZerosV))))))]>,
731 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
732 (ins RC:$src1, RC:$src2, x86memop:$src3),
733 !strconcat(OpcodeStr,
734 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
736 (OpVT (OpNode RC:$src1, RC:$src2,
737 (mem_frag addr:$src3))))]>, EVEX_4V;
739 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
740 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
741 !strconcat(OpcodeStr,
742 " \t{$src3, $src2, $dst {${mask}}|"
743 "$dst {${mask}}, $src2, $src3}"),
745 (OpVT (vselect KRC:$mask,
746 (OpNode RC:$src1, RC:$src2,
747 (mem_frag addr:$src3)),
751 let AddedComplexity = 10 in // Prefer over the rrkz variant
752 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
753 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
754 !strconcat(OpcodeStr,
755 " \t{$src3, $src2, $dst {${mask}} {z}|"
756 "$dst {${mask}} {z}, $src2, $src3}"),
758 (OpVT (vselect KRC:$mask,
759 (OpNode RC:$src1, RC:$src2,
760 (mem_frag addr:$src3)),
762 (v16i32 immAllZerosV))))))]>,
766 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
767 i512mem, X86VPermiv3, v16i32, VK16WM>,
768 EVEX_V512, EVEX_CD8<32, CD8VF>;
769 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
770 i512mem, X86VPermiv3, v8i64, VK8WM>,
771 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
772 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
773 i512mem, X86VPermiv3, v16f32, VK16WM>,
774 EVEX_V512, EVEX_CD8<32, CD8VF>;
775 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
776 i512mem, X86VPermiv3, v8f64, VK8WM>,
777 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
779 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
780 PatFrag mem_frag, X86MemOperand x86memop,
781 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
782 ValueType MaskVT, RegisterClass MRC> :
783 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
785 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
786 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
787 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
789 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
790 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
791 (!cast<Instruction>(NAME#rrk) VR512:$src1,
792 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
795 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
796 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
797 EVEX_V512, EVEX_CD8<32, CD8VF>;
798 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
799 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
800 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
801 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
802 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
803 EVEX_V512, EVEX_CD8<32, CD8VF>;
804 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
805 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
806 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
808 //===----------------------------------------------------------------------===//
809 // AVX-512 - BLEND using mask
811 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
812 RegisterClass KRC, RegisterClass RC,
813 X86MemOperand x86memop, PatFrag mem_frag,
814 SDNode OpNode, ValueType vt> {
815 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
816 (ins KRC:$mask, RC:$src1, RC:$src2),
817 !strconcat(OpcodeStr,
818 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
819 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
820 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
822 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
823 (ins KRC:$mask, RC:$src1, x86memop:$src2),
824 !strconcat(OpcodeStr,
825 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
826 []>, EVEX_4V, EVEX_K;
829 let ExeDomain = SSEPackedSingle in
830 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
831 VK16WM, VR512, f512mem,
832 memopv16f32, vselect, v16f32>,
833 EVEX_CD8<32, CD8VF>, EVEX_V512;
834 let ExeDomain = SSEPackedDouble in
835 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
836 VK8WM, VR512, f512mem,
837 memopv8f64, vselect, v8f64>,
838 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
840 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
841 (v16f32 VR512:$src2), (i16 GR16:$mask))),
842 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
843 VR512:$src1, VR512:$src2)>;
845 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
846 (v8f64 VR512:$src2), (i8 GR8:$mask))),
847 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
848 VR512:$src1, VR512:$src2)>;
850 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
851 VK16WM, VR512, f512mem,
852 memopv16i32, vselect, v16i32>,
853 EVEX_CD8<32, CD8VF>, EVEX_V512;
855 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
856 VK8WM, VR512, f512mem,
857 memopv8i64, vselect, v8i64>,
858 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
860 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
861 (v16i32 VR512:$src2), (i16 GR16:$mask))),
862 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
863 VR512:$src1, VR512:$src2)>;
865 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
866 (v8i64 VR512:$src2), (i8 GR8:$mask))),
867 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
868 VR512:$src1, VR512:$src2)>;
870 let Predicates = [HasAVX512] in {
871 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
872 (v8f32 VR256X:$src2))),
874 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
875 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
876 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
878 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
879 (v8i32 VR256X:$src2))),
881 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
882 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
883 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
885 //===----------------------------------------------------------------------===//
886 // Compare Instructions
887 //===----------------------------------------------------------------------===//
889 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
890 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
891 Operand CC, SDNode OpNode, ValueType VT,
892 PatFrag ld_frag, string asm, string asm_alt> {
893 def rr : AVX512Ii8<0xC2, MRMSrcReg,
894 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
895 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
896 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
897 def rm : AVX512Ii8<0xC2, MRMSrcMem,
898 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
899 [(set VK1:$dst, (OpNode (VT RC:$src1),
900 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
901 let isAsmParserOnly = 1, hasSideEffects = 0 in {
902 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
903 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
904 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
905 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
906 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
907 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
911 let Predicates = [HasAVX512] in {
912 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
913 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
914 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
916 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
917 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
918 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
922 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
923 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
924 SDNode OpNode, ValueType vt> {
925 def rr : AVX512BI<opc, MRMSrcReg,
926 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
927 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
928 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
929 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
930 def rm : AVX512BI<opc, MRMSrcMem,
931 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
932 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
933 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
934 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
937 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
938 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
940 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
941 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
942 VEX_W, EVEX_CD8<64, CD8VF>;
944 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
945 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
947 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
948 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
949 VEX_W, EVEX_CD8<64, CD8VF>;
951 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
952 (COPY_TO_REGCLASS (VPCMPGTDZrr
953 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
954 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
956 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
957 (COPY_TO_REGCLASS (VPCMPEQDZrr
958 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
959 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
961 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
962 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
963 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
964 def rri : AVX512AIi8<opc, MRMSrcReg,
965 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
966 !strconcat("vpcmp${cc}", Suffix,
967 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
968 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
969 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
970 def rmi : AVX512AIi8<opc, MRMSrcMem,
971 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
972 !strconcat("vpcmp${cc}", Suffix,
973 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
974 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
975 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
976 // Accept explicit immediate argument form instead of comparison code.
977 let isAsmParserOnly = 1, hasSideEffects = 0 in {
978 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
979 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
980 !strconcat("vpcmp", Suffix,
981 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
982 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
983 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
984 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
985 !strconcat("vpcmp", Suffix,
986 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
987 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
988 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
989 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
990 !strconcat("vpcmp", Suffix,
991 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
992 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
993 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
994 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
995 !strconcat("vpcmp", Suffix,
996 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
997 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1001 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
1002 X86cmpm, v16i32, AVXCC, "d">,
1003 EVEX_V512, EVEX_CD8<32, CD8VF>;
1004 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
1005 X86cmpmu, v16i32, AVXCC, "ud">,
1006 EVEX_V512, EVEX_CD8<32, CD8VF>;
1008 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
1009 X86cmpm, v8i64, AVXCC, "q">,
1010 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1011 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
1012 X86cmpmu, v8i64, AVXCC, "uq">,
1013 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1015 // avx512_cmp_packed - compare packed instructions
1016 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1017 X86MemOperand x86memop, ValueType vt,
1018 string suffix, Domain d> {
1019 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1020 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1021 !strconcat("vcmp${cc}", suffix,
1022 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1023 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1024 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1025 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1026 !strconcat("vcmp${cc}", suffix,
1027 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1029 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1030 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1031 !strconcat("vcmp${cc}", suffix,
1032 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1034 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1036 // Accept explicit immediate argument form instead of comparison code.
1037 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1038 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1039 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1040 !strconcat("vcmp", suffix,
1041 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1042 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1043 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1044 !strconcat("vcmp", suffix,
1045 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1049 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1050 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1051 EVEX_CD8<32, CD8VF>;
1052 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1053 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1054 EVEX_CD8<64, CD8VF>;
1056 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1057 (COPY_TO_REGCLASS (VCMPPSZrri
1058 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1059 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1061 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1062 (COPY_TO_REGCLASS (VPCMPDZrri
1063 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1064 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1066 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1067 (COPY_TO_REGCLASS (VPCMPUDZrri
1068 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1069 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1072 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1073 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1075 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1076 (I8Imm imm:$cc)), GR16)>;
1078 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1079 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1081 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1082 (I8Imm imm:$cc)), GR8)>;
1084 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1085 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1087 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1088 (I8Imm imm:$cc)), GR16)>;
1090 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1091 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1093 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1094 (I8Imm imm:$cc)), GR8)>;
1096 // Mask register copy, including
1097 // - copy between mask registers
1098 // - load/store mask registers
1099 // - copy from GPR to mask register and vice versa
1101 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1102 string OpcodeStr, RegisterClass KRC,
1103 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1104 let hasSideEffects = 0 in {
1105 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1106 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1108 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1109 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1110 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1112 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1113 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1117 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1119 RegisterClass KRC, RegisterClass GRC> {
1120 let hasSideEffects = 0 in {
1121 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1122 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1123 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1124 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1128 let Predicates = [HasDQI] in
1129 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1131 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1134 let Predicates = [HasAVX512] in
1135 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1137 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1140 let Predicates = [HasBWI] in {
1141 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1142 i32mem>, VEX, PD, VEX_W;
1143 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1147 let Predicates = [HasBWI] in {
1148 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1149 i64mem>, VEX, PS, VEX_W;
1150 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1154 // GR from/to mask register
1155 let Predicates = [HasDQI] in {
1156 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1157 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1158 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1159 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1161 let Predicates = [HasAVX512] in {
1162 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1163 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1164 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1165 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1167 let Predicates = [HasBWI] in {
1168 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1169 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1171 let Predicates = [HasBWI] in {
1172 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1173 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1177 let Predicates = [HasDQI] in {
1178 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1179 (KMOVBmk addr:$dst, VK8:$src)>;
1181 let Predicates = [HasAVX512] in {
1182 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1183 (KMOVWmk addr:$dst, VK16:$src)>;
1184 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1185 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1186 def : Pat<(i1 (load addr:$src)),
1187 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1188 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1189 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1191 let Predicates = [HasBWI] in {
1192 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1193 (KMOVDmk addr:$dst, VK32:$src)>;
1195 let Predicates = [HasBWI] in {
1196 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1197 (KMOVQmk addr:$dst, VK64:$src)>;
1200 let Predicates = [HasAVX512] in {
1201 def : Pat<(i1 (trunc (i64 GR64:$src))),
1202 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1205 def : Pat<(i1 (trunc (i32 GR32:$src))),
1206 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1208 def : Pat<(i1 (trunc (i8 GR8:$src))),
1210 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1212 def : Pat<(i1 (trunc (i16 GR16:$src))),
1214 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1217 def : Pat<(i32 (zext VK1:$src)),
1218 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1219 def : Pat<(i8 (zext VK1:$src)),
1222 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1223 def : Pat<(i64 (zext VK1:$src)),
1224 (AND64ri8 (SUBREG_TO_REG (i64 0),
1225 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1226 def : Pat<(i16 (zext VK1:$src)),
1228 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1230 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1231 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1232 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1233 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1235 let Predicates = [HasBWI] in {
1236 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1237 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1238 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1239 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1243 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1244 let Predicates = [HasAVX512] in {
1245 // GR from/to 8-bit mask without native support
1246 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1248 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1250 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1252 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1255 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1256 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1257 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1258 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1260 let Predicates = [HasBWI] in {
1261 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1262 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1263 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1264 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1267 // Mask unary operation
1269 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1270 RegisterClass KRC, SDPatternOperator OpNode,
1272 let Predicates = [prd] in
1273 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1274 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1275 [(set KRC:$dst, (OpNode KRC:$src))]>;
1278 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1279 SDPatternOperator OpNode> {
1280 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1282 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1283 HasAVX512>, VEX, PS;
1284 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1285 HasBWI>, VEX, PD, VEX_W;
1286 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1287 HasBWI>, VEX, PS, VEX_W;
1290 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1292 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1293 let Predicates = [HasAVX512] in
1294 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1296 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1297 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1299 defm : avx512_mask_unop_int<"knot", "KNOT">;
1301 let Predicates = [HasDQI] in
1302 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1303 let Predicates = [HasAVX512] in
1304 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1305 let Predicates = [HasBWI] in
1306 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1307 let Predicates = [HasBWI] in
1308 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1310 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1311 let Predicates = [HasAVX512] in {
1312 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1313 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1315 def : Pat<(not VK8:$src),
1317 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1320 // Mask binary operation
1321 // - KAND, KANDN, KOR, KXNOR, KXOR
1322 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1323 RegisterClass KRC, SDPatternOperator OpNode,
1325 let Predicates = [prd] in
1326 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1327 !strconcat(OpcodeStr,
1328 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1329 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1332 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1333 SDPatternOperator OpNode> {
1334 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1335 HasDQI>, VEX_4V, VEX_L, PD;
1336 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1337 HasAVX512>, VEX_4V, VEX_L, PS;
1338 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1339 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1340 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1341 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1344 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1345 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1347 let isCommutable = 1 in {
1348 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1349 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1350 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1351 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1353 let isCommutable = 0 in
1354 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1356 def : Pat<(xor VK1:$src1, VK1:$src2),
1357 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1358 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1360 def : Pat<(or VK1:$src1, VK1:$src2),
1361 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1362 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1364 def : Pat<(and VK1:$src1, VK1:$src2),
1365 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1366 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1368 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1369 let Predicates = [HasAVX512] in
1370 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1371 (i16 GR16:$src1), (i16 GR16:$src2)),
1372 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1373 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1374 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1377 defm : avx512_mask_binop_int<"kand", "KAND">;
1378 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1379 defm : avx512_mask_binop_int<"kor", "KOR">;
1380 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1381 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1383 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1384 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1385 let Predicates = [HasAVX512] in
1386 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1388 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1389 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1392 defm : avx512_binop_pat<and, KANDWrr>;
1393 defm : avx512_binop_pat<andn, KANDNWrr>;
1394 defm : avx512_binop_pat<or, KORWrr>;
1395 defm : avx512_binop_pat<xnor, KXNORWrr>;
1396 defm : avx512_binop_pat<xor, KXORWrr>;
1399 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1400 RegisterClass KRC> {
1401 let Predicates = [HasAVX512] in
1402 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1403 !strconcat(OpcodeStr,
1404 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1407 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1408 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1412 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1413 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1414 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1415 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1418 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1419 let Predicates = [HasAVX512] in
1420 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1421 (i16 GR16:$src1), (i16 GR16:$src2)),
1422 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1423 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1424 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1426 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1429 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1431 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1432 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1433 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1434 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1437 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1438 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1442 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1444 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1445 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1446 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1449 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1451 let Predicates = [HasAVX512] in
1452 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1453 !strconcat(OpcodeStr,
1454 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1455 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1458 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1460 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1464 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1465 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1467 // Mask setting all 0s or 1s
1468 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1469 let Predicates = [HasAVX512] in
1470 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1471 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1472 [(set KRC:$dst, (VT Val))]>;
1475 multiclass avx512_mask_setop_w<PatFrag Val> {
1476 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1477 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1480 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1481 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1483 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1484 let Predicates = [HasAVX512] in {
1485 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1486 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1487 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1488 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1489 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1491 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1492 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1494 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1495 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1497 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1498 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1500 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1501 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1503 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1504 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1505 //===----------------------------------------------------------------------===//
1506 // AVX-512 - Aligned and unaligned load and store
1509 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1510 RegisterClass KRC, RegisterClass RC,
1511 ValueType vt, ValueType zvt, X86MemOperand memop,
1512 Domain d, bit IsReMaterializable = 1> {
1513 let hasSideEffects = 0 in {
1514 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1515 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1517 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1518 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1519 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1521 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1522 SchedRW = [WriteLoad] in
1523 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1524 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1525 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1528 let AddedComplexity = 20 in {
1529 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1530 let hasSideEffects = 0 in
1531 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1532 (ins RC:$src0, KRC:$mask, RC:$src1),
1533 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1534 "${dst} {${mask}}, $src1}"),
1535 [(set RC:$dst, (vt (vselect KRC:$mask,
1539 let mayLoad = 1, SchedRW = [WriteLoad] in
1540 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1541 (ins RC:$src0, KRC:$mask, memop:$src1),
1542 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1543 "${dst} {${mask}}, $src1}"),
1546 (vt (bitconvert (ld_frag addr:$src1))),
1550 let mayLoad = 1, SchedRW = [WriteLoad] in
1551 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1552 (ins KRC:$mask, memop:$src),
1553 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1554 "${dst} {${mask}} {z}, $src}"),
1557 (vt (bitconvert (ld_frag addr:$src))),
1558 (vt (bitconvert (zvt immAllZerosV))))))],
1563 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1564 string elty, string elsz, string vsz512,
1565 string vsz256, string vsz128, Domain d,
1566 Predicate prd, bit IsReMaterializable = 1> {
1567 let Predicates = [prd] in
1568 defm Z : avx512_load<opc, OpcodeStr,
1569 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1570 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1571 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1572 !cast<X86MemOperand>(elty##"512mem"), d,
1573 IsReMaterializable>, EVEX_V512;
1575 let Predicates = [prd, HasVLX] in {
1576 defm Z256 : avx512_load<opc, OpcodeStr,
1577 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1578 "v"##vsz256##elty##elsz, "v4i64")),
1579 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1580 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1581 !cast<X86MemOperand>(elty##"256mem"), d,
1582 IsReMaterializable>, EVEX_V256;
1584 defm Z128 : avx512_load<opc, OpcodeStr,
1585 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1586 "v"##vsz128##elty##elsz, "v2i64")),
1587 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1588 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1589 !cast<X86MemOperand>(elty##"128mem"), d,
1590 IsReMaterializable>, EVEX_V128;
1595 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1596 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1597 X86MemOperand memop, Domain d> {
1598 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1599 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1602 let Constraints = "$src1 = $dst" in
1603 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1604 (ins RC:$src1, KRC:$mask, RC:$src2),
1605 !strconcat(OpcodeStr,
1606 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1608 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1609 (ins KRC:$mask, RC:$src),
1610 !strconcat(OpcodeStr,
1611 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1612 [], d>, EVEX, EVEX_KZ;
1614 let mayStore = 1 in {
1615 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1617 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1618 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1619 (ins memop:$dst, KRC:$mask, RC:$src),
1620 !strconcat(OpcodeStr,
1621 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1622 [], d>, EVEX, EVEX_K;
1627 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1628 string st_suff_512, string st_suff_256,
1629 string st_suff_128, string elty, string elsz,
1630 string vsz512, string vsz256, string vsz128,
1631 Domain d, Predicate prd> {
1632 let Predicates = [prd] in
1633 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1634 !cast<ValueType>("v"##vsz512##elty##elsz),
1635 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1636 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1638 let Predicates = [prd, HasVLX] in {
1639 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1640 !cast<ValueType>("v"##vsz256##elty##elsz),
1641 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1642 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1644 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1645 !cast<ValueType>("v"##vsz128##elty##elsz),
1646 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1647 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1651 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1652 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1653 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1654 "512", "256", "", "f", "32", "16", "8", "4",
1655 SSEPackedSingle, HasAVX512>,
1656 PS, EVEX_CD8<32, CD8VF>;
1658 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1659 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1660 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1661 "512", "256", "", "f", "64", "8", "4", "2",
1662 SSEPackedDouble, HasAVX512>,
1663 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1665 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1666 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1667 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1668 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1669 PS, EVEX_CD8<32, CD8VF>;
1671 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1672 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1673 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1674 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1675 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1677 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1678 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1679 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1681 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1682 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1683 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1685 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1687 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1689 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1691 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1694 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1695 "16", "8", "4", SSEPackedInt, HasAVX512>,
1696 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1697 "512", "256", "", "i", "32", "16", "8", "4",
1698 SSEPackedInt, HasAVX512>,
1699 PD, EVEX_CD8<32, CD8VF>;
1701 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1702 "8", "4", "2", SSEPackedInt, HasAVX512>,
1703 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1704 "512", "256", "", "i", "64", "8", "4", "2",
1705 SSEPackedInt, HasAVX512>,
1706 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1708 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1709 "64", "32", "16", SSEPackedInt, HasBWI>,
1710 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1711 "i", "8", "64", "32", "16", SSEPackedInt,
1712 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1714 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1715 "32", "16", "8", SSEPackedInt, HasBWI>,
1716 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1717 "i", "16", "32", "16", "8", SSEPackedInt,
1718 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1720 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1721 "16", "8", "4", SSEPackedInt, HasAVX512>,
1722 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1723 "i", "32", "16", "8", "4", SSEPackedInt,
1724 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1726 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1727 "8", "4", "2", SSEPackedInt, HasAVX512>,
1728 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1729 "i", "64", "8", "4", "2", SSEPackedInt,
1730 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1732 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1733 (v16i32 immAllZerosV), GR16:$mask)),
1734 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1736 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1737 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1738 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1740 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1742 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1744 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1746 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1749 let AddedComplexity = 20 in {
1750 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1751 (bc_v8i64 (v16i32 immAllZerosV)))),
1752 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
1754 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1755 (v8i64 VR512:$src))),
1756 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1759 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1760 (v16i32 immAllZerosV))),
1761 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
1763 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1764 (v16i32 VR512:$src))),
1765 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1768 // Move Int Doubleword to Packed Double Int
1770 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1771 "vmovd\t{$src, $dst|$dst, $src}",
1773 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1775 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1776 "vmovd\t{$src, $dst|$dst, $src}",
1778 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1779 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1780 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1781 "vmovq\t{$src, $dst|$dst, $src}",
1783 (v2i64 (scalar_to_vector GR64:$src)))],
1784 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1785 let isCodeGenOnly = 1 in {
1786 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1787 "vmovq\t{$src, $dst|$dst, $src}",
1788 [(set FR64:$dst, (bitconvert GR64:$src))],
1789 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1790 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1791 "vmovq\t{$src, $dst|$dst, $src}",
1792 [(set GR64:$dst, (bitconvert FR64:$src))],
1793 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1795 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1796 "vmovq\t{$src, $dst|$dst, $src}",
1797 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1798 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1799 EVEX_CD8<64, CD8VT1>;
1801 // Move Int Doubleword to Single Scalar
1803 let isCodeGenOnly = 1 in {
1804 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1805 "vmovd\t{$src, $dst|$dst, $src}",
1806 [(set FR32X:$dst, (bitconvert GR32:$src))],
1807 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1809 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1810 "vmovd\t{$src, $dst|$dst, $src}",
1811 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1812 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1815 // Move doubleword from xmm register to r/m32
1817 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1818 "vmovd\t{$src, $dst|$dst, $src}",
1819 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1820 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1822 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1823 (ins i32mem:$dst, VR128X:$src),
1824 "vmovd\t{$src, $dst|$dst, $src}",
1825 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1826 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1827 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1829 // Move quadword from xmm1 register to r/m64
1831 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1832 "vmovq\t{$src, $dst|$dst, $src}",
1833 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1835 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1836 Requires<[HasAVX512, In64BitMode]>;
1838 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1839 (ins i64mem:$dst, VR128X:$src),
1840 "vmovq\t{$src, $dst|$dst, $src}",
1841 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1842 addr:$dst)], IIC_SSE_MOVDQ>,
1843 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1844 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1846 // Move Scalar Single to Double Int
1848 let isCodeGenOnly = 1 in {
1849 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1851 "vmovd\t{$src, $dst|$dst, $src}",
1852 [(set GR32:$dst, (bitconvert FR32X:$src))],
1853 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1854 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1855 (ins i32mem:$dst, FR32X:$src),
1856 "vmovd\t{$src, $dst|$dst, $src}",
1857 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1858 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1861 // Move Quadword Int to Packed Quadword Int
1863 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1865 "vmovq\t{$src, $dst|$dst, $src}",
1867 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1868 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1870 //===----------------------------------------------------------------------===//
1871 // AVX-512 MOVSS, MOVSD
1872 //===----------------------------------------------------------------------===//
1874 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1875 SDNode OpNode, ValueType vt,
1876 X86MemOperand x86memop, PatFrag mem_pat> {
1877 let hasSideEffects = 0 in {
1878 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1879 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1880 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1881 (scalar_to_vector RC:$src2))))],
1882 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1883 let Constraints = "$src1 = $dst" in
1884 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1885 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1887 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1888 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1889 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1890 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1891 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1893 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1894 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1895 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1897 } //hasSideEffects = 0
1900 let ExeDomain = SSEPackedSingle in
1901 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1902 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1904 let ExeDomain = SSEPackedDouble in
1905 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1906 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1908 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1909 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1910 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1912 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1913 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1914 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1916 // For the disassembler
1917 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1918 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1919 (ins VR128X:$src1, FR32X:$src2),
1920 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1922 XS, EVEX_4V, VEX_LIG;
1923 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1924 (ins VR128X:$src1, FR64X:$src2),
1925 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1927 XD, EVEX_4V, VEX_LIG, VEX_W;
1930 let Predicates = [HasAVX512] in {
1931 let AddedComplexity = 15 in {
1932 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1933 // MOVS{S,D} to the lower bits.
1934 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1935 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1936 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1937 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1938 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1939 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1940 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1941 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1943 // Move low f32 and clear high bits.
1944 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1945 (SUBREG_TO_REG (i32 0),
1946 (VMOVSSZrr (v4f32 (V_SET0)),
1947 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1948 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1949 (SUBREG_TO_REG (i32 0),
1950 (VMOVSSZrr (v4i32 (V_SET0)),
1951 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1954 let AddedComplexity = 20 in {
1955 // MOVSSrm zeros the high parts of the register; represent this
1956 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1957 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1958 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1959 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1960 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1961 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1962 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1964 // MOVSDrm zeros the high parts of the register; represent this
1965 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1966 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1967 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1968 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1969 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1970 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1971 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1972 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1973 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1974 def : Pat<(v2f64 (X86vzload addr:$src)),
1975 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1977 // Represent the same patterns above but in the form they appear for
1979 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1980 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1981 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1982 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1983 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1984 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1985 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1986 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1987 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1989 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1990 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1991 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1992 FR32X:$src)), sub_xmm)>;
1993 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1994 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1995 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1996 FR64X:$src)), sub_xmm)>;
1997 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1998 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1999 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2001 // Move low f64 and clear high bits.
2002 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2003 (SUBREG_TO_REG (i32 0),
2004 (VMOVSDZrr (v2f64 (V_SET0)),
2005 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2007 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2008 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2009 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2011 // Extract and store.
2012 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2014 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2015 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2017 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2019 // Shuffle with VMOVSS
2020 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2021 (VMOVSSZrr (v4i32 VR128X:$src1),
2022 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2023 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2024 (VMOVSSZrr (v4f32 VR128X:$src1),
2025 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2028 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2029 (SUBREG_TO_REG (i32 0),
2030 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2031 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2033 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2034 (SUBREG_TO_REG (i32 0),
2035 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2036 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2039 // Shuffle with VMOVSD
2040 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2041 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2042 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2043 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2044 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2045 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2046 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2047 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2050 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2051 (SUBREG_TO_REG (i32 0),
2052 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2053 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2055 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2056 (SUBREG_TO_REG (i32 0),
2057 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2058 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2061 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2062 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2063 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2064 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2065 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2066 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2067 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2068 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2071 let AddedComplexity = 15 in
2072 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2074 "vmovq\t{$src, $dst|$dst, $src}",
2075 [(set VR128X:$dst, (v2i64 (X86vzmovl
2076 (v2i64 VR128X:$src))))],
2077 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2079 let AddedComplexity = 20 in
2080 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2082 "vmovq\t{$src, $dst|$dst, $src}",
2083 [(set VR128X:$dst, (v2i64 (X86vzmovl
2084 (loadv2i64 addr:$src))))],
2085 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2086 EVEX_CD8<8, CD8VT8>;
2088 let Predicates = [HasAVX512] in {
2089 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2090 let AddedComplexity = 20 in {
2091 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2092 (VMOVDI2PDIZrm addr:$src)>;
2093 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2094 (VMOV64toPQIZrr GR64:$src)>;
2095 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2096 (VMOVDI2PDIZrr GR32:$src)>;
2098 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2099 (VMOVDI2PDIZrm addr:$src)>;
2100 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2101 (VMOVDI2PDIZrm addr:$src)>;
2102 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2103 (VMOVZPQILo2PQIZrm addr:$src)>;
2104 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2105 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2106 def : Pat<(v2i64 (X86vzload addr:$src)),
2107 (VMOVZPQILo2PQIZrm addr:$src)>;
2110 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2111 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2112 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2113 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2114 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2115 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2116 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2119 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2120 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2122 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2123 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2125 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2126 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2128 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2129 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2131 //===----------------------------------------------------------------------===//
2132 // AVX-512 - Non-temporals
2133 //===----------------------------------------------------------------------===//
2134 let SchedRW = [WriteLoad] in {
2135 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2136 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2137 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2138 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2139 EVEX_CD8<64, CD8VF>;
2141 let Predicates = [HasAVX512, HasVLX] in {
2142 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2144 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2145 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2146 EVEX_CD8<64, CD8VF>;
2148 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2150 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2151 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2152 EVEX_CD8<64, CD8VF>;
2156 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2157 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2158 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2159 let SchedRW = [WriteStore], mayStore = 1,
2160 AddedComplexity = 400 in
2161 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2163 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2166 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2167 string elty, string elsz, string vsz512,
2168 string vsz256, string vsz128, Domain d,
2169 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2170 let Predicates = [prd] in
2171 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2172 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2173 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2176 let Predicates = [prd, HasVLX] in {
2177 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2178 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2179 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2182 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2183 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2184 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2189 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2190 "i", "64", "8", "4", "2", SSEPackedInt,
2191 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2193 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2194 "f", "64", "8", "4", "2", SSEPackedDouble,
2195 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2197 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2198 "f", "32", "16", "8", "4", SSEPackedSingle,
2199 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2201 //===----------------------------------------------------------------------===//
2202 // AVX-512 - Integer arithmetic
2204 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2205 ValueType OpVT, RegisterClass KRC,
2206 RegisterClass RC, PatFrag memop_frag,
2207 X86MemOperand x86memop, PatFrag scalar_mfrag,
2208 X86MemOperand x86scalar_mop, string BrdcstStr,
2209 OpndItins itins, bit IsCommutable = 0> {
2210 let isCommutable = IsCommutable in
2211 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2212 (ins RC:$src1, RC:$src2),
2213 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2214 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2216 let AddedComplexity = 30 in {
2217 let Constraints = "$src0 = $dst" in
2218 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2219 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2220 !strconcat(OpcodeStr,
2221 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2222 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2223 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2225 itins.rr>, EVEX_4V, EVEX_K;
2226 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2227 (ins KRC:$mask, RC:$src1, RC:$src2),
2228 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2229 "|$dst {${mask}} {z}, $src1, $src2}"),
2230 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2231 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2232 (OpVT immAllZerosV))))],
2233 itins.rr>, EVEX_4V, EVEX_KZ;
2236 let mayLoad = 1 in {
2237 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2238 (ins RC:$src1, x86memop:$src2),
2239 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2240 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2242 let AddedComplexity = 30 in {
2243 let Constraints = "$src0 = $dst" in
2244 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2245 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2246 !strconcat(OpcodeStr,
2247 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2248 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2249 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2251 itins.rm>, EVEX_4V, EVEX_K;
2252 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2253 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2254 !strconcat(OpcodeStr,
2255 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2256 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2257 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2258 (OpVT immAllZerosV))))],
2259 itins.rm>, EVEX_4V, EVEX_KZ;
2261 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2262 (ins RC:$src1, x86scalar_mop:$src2),
2263 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2264 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2265 [(set RC:$dst, (OpNode RC:$src1,
2266 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2267 itins.rm>, EVEX_4V, EVEX_B;
2268 let AddedComplexity = 30 in {
2269 let Constraints = "$src0 = $dst" in
2270 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2271 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2272 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2273 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2275 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2276 (OpNode (OpVT RC:$src1),
2277 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2279 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2280 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2281 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2282 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2283 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2285 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2286 (OpNode (OpVT RC:$src1),
2287 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2288 (OpVT immAllZerosV))))],
2289 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2294 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2295 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2296 PatFrag memop_frag, X86MemOperand x86memop,
2297 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2298 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2299 let isCommutable = IsCommutable in
2301 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2302 (ins RC:$src1, RC:$src2),
2303 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2305 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2306 (ins KRC:$mask, RC:$src1, RC:$src2),
2307 !strconcat(OpcodeStr,
2308 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2309 [], itins.rr>, EVEX_4V, EVEX_K;
2310 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2311 (ins KRC:$mask, RC:$src1, RC:$src2),
2312 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2313 "|$dst {${mask}} {z}, $src1, $src2}"),
2314 [], itins.rr>, EVEX_4V, EVEX_KZ;
2316 let mayLoad = 1 in {
2317 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2318 (ins RC:$src1, x86memop:$src2),
2319 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2321 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2322 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2323 !strconcat(OpcodeStr,
2324 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2325 [], itins.rm>, EVEX_4V, EVEX_K;
2326 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2327 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2328 !strconcat(OpcodeStr,
2329 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2330 [], itins.rm>, EVEX_4V, EVEX_KZ;
2331 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2332 (ins RC:$src1, x86scalar_mop:$src2),
2333 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2334 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2335 [], itins.rm>, EVEX_4V, EVEX_B;
2336 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2337 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2338 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2339 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2341 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2342 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2343 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2344 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2345 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2347 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2351 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2352 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2353 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2355 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2356 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2357 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2359 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2360 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2361 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2363 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2364 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2365 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2367 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2368 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2369 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2371 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2372 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2373 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2374 EVEX_CD8<64, CD8VF>, VEX_W;
2376 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2377 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2378 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2380 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2381 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2383 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2384 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2385 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2386 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2387 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2388 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2390 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2391 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2392 SSE_INTALU_ITINS_P, 1>,
2393 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2394 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2395 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2396 SSE_INTALU_ITINS_P, 0>,
2397 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2399 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2400 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2401 SSE_INTALU_ITINS_P, 1>,
2402 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2403 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2404 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2405 SSE_INTALU_ITINS_P, 0>,
2406 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2408 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2409 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2410 SSE_INTALU_ITINS_P, 1>,
2411 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2412 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2413 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2414 SSE_INTALU_ITINS_P, 0>,
2415 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2417 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2418 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2419 SSE_INTALU_ITINS_P, 1>,
2420 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2421 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2422 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2423 SSE_INTALU_ITINS_P, 0>,
2424 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2426 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2427 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2428 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2429 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2430 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2431 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2432 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2433 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2434 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2435 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2436 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2437 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2438 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2439 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2440 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2441 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2442 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2443 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2444 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2445 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2446 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2447 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2448 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2449 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2450 //===----------------------------------------------------------------------===//
2451 // AVX-512 - Unpack Instructions
2452 //===----------------------------------------------------------------------===//
2454 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2455 PatFrag mem_frag, RegisterClass RC,
2456 X86MemOperand x86memop, string asm,
2458 def rr : AVX512PI<opc, MRMSrcReg,
2459 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2461 (vt (OpNode RC:$src1, RC:$src2)))],
2463 def rm : AVX512PI<opc, MRMSrcMem,
2464 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2466 (vt (OpNode RC:$src1,
2467 (bitconvert (mem_frag addr:$src2)))))],
2471 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2472 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2473 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2474 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2475 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2476 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2477 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2478 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2479 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2480 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2481 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2482 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2484 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2485 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2486 X86MemOperand x86memop> {
2487 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2488 (ins RC:$src1, RC:$src2),
2489 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2490 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2491 IIC_SSE_UNPCK>, EVEX_4V;
2492 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2493 (ins RC:$src1, x86memop:$src2),
2494 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2495 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2496 (bitconvert (memop_frag addr:$src2)))))],
2497 IIC_SSE_UNPCK>, EVEX_4V;
2499 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2500 VR512, memopv16i32, i512mem>, EVEX_V512,
2501 EVEX_CD8<32, CD8VF>;
2502 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2503 VR512, memopv8i64, i512mem>, EVEX_V512,
2504 VEX_W, EVEX_CD8<64, CD8VF>;
2505 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2506 VR512, memopv16i32, i512mem>, EVEX_V512,
2507 EVEX_CD8<32, CD8VF>;
2508 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2509 VR512, memopv8i64, i512mem>, EVEX_V512,
2510 VEX_W, EVEX_CD8<64, CD8VF>;
2511 //===----------------------------------------------------------------------===//
2515 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2516 SDNode OpNode, PatFrag mem_frag,
2517 X86MemOperand x86memop, ValueType OpVT> {
2518 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2519 (ins RC:$src1, i8imm:$src2),
2520 !strconcat(OpcodeStr,
2521 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2523 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2525 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2526 (ins x86memop:$src1, i8imm:$src2),
2527 !strconcat(OpcodeStr,
2528 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2530 (OpVT (OpNode (mem_frag addr:$src1),
2531 (i8 imm:$src2))))]>, EVEX;
2534 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2535 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2537 let ExeDomain = SSEPackedSingle in
2538 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2539 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2540 EVEX_CD8<32, CD8VF>;
2541 let ExeDomain = SSEPackedDouble in
2542 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2543 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2544 VEX_W, EVEX_CD8<32, CD8VF>;
2546 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2547 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2548 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2549 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2551 //===----------------------------------------------------------------------===//
2552 // AVX-512 Logical Instructions
2553 //===----------------------------------------------------------------------===//
2555 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2556 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2557 EVEX_V512, EVEX_CD8<32, CD8VF>;
2558 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2559 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2560 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2561 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2562 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2563 EVEX_V512, EVEX_CD8<32, CD8VF>;
2564 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2565 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2566 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2567 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2568 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2569 EVEX_V512, EVEX_CD8<32, CD8VF>;
2570 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2571 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2572 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2573 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2574 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2575 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2576 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2577 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2578 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2580 //===----------------------------------------------------------------------===//
2581 // AVX-512 FP arithmetic
2582 //===----------------------------------------------------------------------===//
2584 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2586 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2587 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2588 EVEX_CD8<32, CD8VT1>;
2589 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2590 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2591 EVEX_CD8<64, CD8VT1>;
2594 let isCommutable = 1 in {
2595 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2596 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2597 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2598 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2600 let isCommutable = 0 in {
2601 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2602 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2605 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2607 RegisterClass RC, ValueType vt,
2608 X86MemOperand x86memop, PatFrag mem_frag,
2609 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2611 Domain d, OpndItins itins, bit commutable> {
2612 let isCommutable = commutable in {
2613 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2614 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2615 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2618 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2619 !strconcat(OpcodeStr,
2620 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2621 [], itins.rr, d>, EVEX_4V, EVEX_K;
2623 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2624 !strconcat(OpcodeStr,
2625 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2626 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2629 let mayLoad = 1 in {
2630 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2631 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2632 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2633 itins.rm, d>, EVEX_4V;
2635 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2636 (ins RC:$src1, x86scalar_mop:$src2),
2637 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2638 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2639 [(set RC:$dst, (OpNode RC:$src1,
2640 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2641 itins.rm, d>, EVEX_4V, EVEX_B;
2643 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2644 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2645 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2646 [], itins.rm, d>, EVEX_4V, EVEX_K;
2648 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2649 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2650 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2651 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2653 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2654 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2655 " \t{${src2}", BrdcstStr,
2656 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2657 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2659 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2660 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2661 " \t{${src2}", BrdcstStr,
2662 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2664 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2668 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2669 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2670 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2672 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2673 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2674 SSE_ALU_ITINS_P.d, 1>,
2675 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2677 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2678 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2679 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2680 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2681 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2682 SSE_ALU_ITINS_P.d, 1>,
2683 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2685 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2686 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2687 SSE_ALU_ITINS_P.s, 1>,
2688 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2689 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2690 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2691 SSE_ALU_ITINS_P.s, 1>,
2692 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2694 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2695 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2696 SSE_ALU_ITINS_P.d, 1>,
2697 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2698 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2699 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2700 SSE_ALU_ITINS_P.d, 1>,
2701 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2703 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2704 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2705 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2706 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2707 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2708 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2710 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2711 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2712 SSE_ALU_ITINS_P.d, 0>,
2713 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2714 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2715 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2716 SSE_ALU_ITINS_P.d, 0>,
2717 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2719 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2720 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2721 (i16 -1), FROUND_CURRENT)),
2722 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2724 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2725 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2726 (i8 -1), FROUND_CURRENT)),
2727 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2729 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2730 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2731 (i16 -1), FROUND_CURRENT)),
2732 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2734 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2735 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2736 (i8 -1), FROUND_CURRENT)),
2737 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2738 //===----------------------------------------------------------------------===//
2739 // AVX-512 VPTESTM instructions
2740 //===----------------------------------------------------------------------===//
2742 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2743 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2744 SDNode OpNode, ValueType vt> {
2745 def rr : AVX512PI<opc, MRMSrcReg,
2746 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2747 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2748 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2749 SSEPackedInt>, EVEX_4V;
2750 def rm : AVX512PI<opc, MRMSrcMem,
2751 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2752 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2753 [(set KRC:$dst, (OpNode (vt RC:$src1),
2754 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2757 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2758 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2759 EVEX_CD8<32, CD8VF>;
2760 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2761 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2762 EVEX_CD8<64, CD8VF>;
2764 let Predicates = [HasCDI] in {
2765 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2766 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2767 EVEX_CD8<32, CD8VF>;
2768 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2769 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2770 EVEX_CD8<64, CD8VF>;
2773 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2774 (v16i32 VR512:$src2), (i16 -1))),
2775 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2777 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2778 (v8i64 VR512:$src2), (i8 -1))),
2779 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2780 //===----------------------------------------------------------------------===//
2781 // AVX-512 Shift instructions
2782 //===----------------------------------------------------------------------===//
2783 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2784 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2785 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2786 RegisterClass KRC> {
2787 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2788 (ins RC:$src1, i8imm:$src2),
2789 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2790 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2791 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2792 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2793 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2794 !strconcat(OpcodeStr,
2795 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2796 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2797 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2798 (ins x86memop:$src1, i8imm:$src2),
2799 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2800 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2801 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2802 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2803 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2804 !strconcat(OpcodeStr,
2805 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2806 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2809 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2810 RegisterClass RC, ValueType vt, ValueType SrcVT,
2811 PatFrag bc_frag, RegisterClass KRC> {
2812 // src2 is always 128-bit
2813 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2814 (ins RC:$src1, VR128X:$src2),
2815 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2816 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2817 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2818 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2819 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2820 !strconcat(OpcodeStr,
2821 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2822 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2823 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2824 (ins RC:$src1, i128mem:$src2),
2825 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2826 [(set RC:$dst, (vt (OpNode RC:$src1,
2827 (bc_frag (memopv2i64 addr:$src2)))))],
2828 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2829 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2830 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2831 !strconcat(OpcodeStr,
2832 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2833 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2836 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2837 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2838 EVEX_V512, EVEX_CD8<32, CD8VF>;
2839 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2840 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2841 EVEX_CD8<32, CD8VQ>;
2843 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2844 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2845 EVEX_CD8<64, CD8VF>, VEX_W;
2846 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2847 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2848 EVEX_CD8<64, CD8VQ>, VEX_W;
2850 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2851 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2852 EVEX_CD8<32, CD8VF>;
2853 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2854 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2855 EVEX_CD8<32, CD8VQ>;
2857 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2858 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2859 EVEX_CD8<64, CD8VF>, VEX_W;
2860 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2861 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2862 EVEX_CD8<64, CD8VQ>, VEX_W;
2864 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2865 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2866 EVEX_V512, EVEX_CD8<32, CD8VF>;
2867 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2868 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2869 EVEX_CD8<32, CD8VQ>;
2871 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2872 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2873 EVEX_CD8<64, CD8VF>, VEX_W;
2874 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2875 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2876 EVEX_CD8<64, CD8VQ>, VEX_W;
2878 //===-------------------------------------------------------------------===//
2879 // Variable Bit Shifts
2880 //===-------------------------------------------------------------------===//
2881 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2882 RegisterClass RC, ValueType vt,
2883 X86MemOperand x86memop, PatFrag mem_frag> {
2884 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2885 (ins RC:$src1, RC:$src2),
2886 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2888 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2890 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2891 (ins RC:$src1, x86memop:$src2),
2892 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2894 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2898 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2899 i512mem, memopv16i32>, EVEX_V512,
2900 EVEX_CD8<32, CD8VF>;
2901 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2902 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2903 EVEX_CD8<64, CD8VF>;
2904 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2905 i512mem, memopv16i32>, EVEX_V512,
2906 EVEX_CD8<32, CD8VF>;
2907 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2908 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2909 EVEX_CD8<64, CD8VF>;
2910 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2911 i512mem, memopv16i32>, EVEX_V512,
2912 EVEX_CD8<32, CD8VF>;
2913 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2914 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2915 EVEX_CD8<64, CD8VF>;
2917 //===----------------------------------------------------------------------===//
2918 // AVX-512 - MOVDDUP
2919 //===----------------------------------------------------------------------===//
2921 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2922 X86MemOperand x86memop, PatFrag memop_frag> {
2923 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2924 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2925 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2926 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2927 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2929 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2932 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2933 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2934 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2935 (VMOVDDUPZrm addr:$src)>;
2937 //===---------------------------------------------------------------------===//
2938 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2939 //===---------------------------------------------------------------------===//
2940 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2941 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2942 X86MemOperand x86memop> {
2943 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2944 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2945 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2947 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2948 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2949 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2952 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2953 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2954 EVEX_CD8<32, CD8VF>;
2955 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2956 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2957 EVEX_CD8<32, CD8VF>;
2959 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2960 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2961 (VMOVSHDUPZrm addr:$src)>;
2962 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2963 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2964 (VMOVSLDUPZrm addr:$src)>;
2966 //===----------------------------------------------------------------------===//
2967 // Move Low to High and High to Low packed FP Instructions
2968 //===----------------------------------------------------------------------===//
2969 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2970 (ins VR128X:$src1, VR128X:$src2),
2971 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2972 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2973 IIC_SSE_MOV_LH>, EVEX_4V;
2974 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2975 (ins VR128X:$src1, VR128X:$src2),
2976 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2977 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2978 IIC_SSE_MOV_LH>, EVEX_4V;
2980 let Predicates = [HasAVX512] in {
2982 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2983 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2984 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2985 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2988 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2989 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2992 //===----------------------------------------------------------------------===//
2993 // FMA - Fused Multiply Operations
2995 let Constraints = "$src1 = $dst" in {
2996 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2997 RegisterClass RC, X86MemOperand x86memop,
2998 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2999 string BrdcstStr, SDNode OpNode, ValueType OpVT,
3000 RegisterClass KRC> {
3001 defm r: AVX512_masking_3src<opc, MRMSrcReg, (outs RC:$dst),
3002 (ins RC:$src2, RC:$src3),
3003 OpcodeStr, "$src3, $src2", "$src2, $src3",
3004 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)), OpVT, RC, KRC>,
3008 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3009 (ins RC:$src1, RC:$src2, x86memop:$src3),
3010 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3011 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
3012 (mem_frag addr:$src3))))]>;
3013 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3014 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
3015 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
3016 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
3017 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
3018 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
3020 } // Constraints = "$src1 = $dst"
3022 let ExeDomain = SSEPackedSingle in {
3023 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
3024 memopv16f32, f32mem, loadf32, "{1to16}",
3025 X86Fmadd, v16f32, VK16WM>, EVEX_V512,
3026 EVEX_CD8<32, CD8VF>;
3027 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
3028 memopv16f32, f32mem, loadf32, "{1to16}",
3029 X86Fmsub, v16f32, VK16WM>, EVEX_V512,
3030 EVEX_CD8<32, CD8VF>;
3031 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
3032 memopv16f32, f32mem, loadf32, "{1to16}",
3033 X86Fmaddsub, v16f32, VK16WM>,
3034 EVEX_V512, EVEX_CD8<32, CD8VF>;
3035 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
3036 memopv16f32, f32mem, loadf32, "{1to16}",
3037 X86Fmsubadd, v16f32, VK16WM>,
3038 EVEX_V512, EVEX_CD8<32, CD8VF>;
3039 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
3040 memopv16f32, f32mem, loadf32, "{1to16}",
3041 X86Fnmadd, v16f32, VK16WM>, EVEX_V512,
3042 EVEX_CD8<32, CD8VF>;
3043 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
3044 memopv16f32, f32mem, loadf32, "{1to16}",
3045 X86Fnmsub, v16f32, VK16WM>, EVEX_V512,
3046 EVEX_CD8<32, CD8VF>;
3048 let ExeDomain = SSEPackedDouble in {
3049 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
3050 memopv8f64, f64mem, loadf64, "{1to8}",
3051 X86Fmadd, v8f64, VK8WM>, EVEX_V512,
3052 VEX_W, EVEX_CD8<64, CD8VF>;
3053 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
3054 memopv8f64, f64mem, loadf64, "{1to8}",
3055 X86Fmsub, v8f64, VK8WM>, EVEX_V512, VEX_W,
3056 EVEX_CD8<64, CD8VF>;
3057 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
3058 memopv8f64, f64mem, loadf64, "{1to8}",
3059 X86Fmaddsub, v8f64, VK8WM>,
3060 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3061 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
3062 memopv8f64, f64mem, loadf64, "{1to8}",
3063 X86Fmsubadd, v8f64, VK8WM>,
3064 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3065 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
3066 memopv8f64, f64mem, loadf64, "{1to8}",
3067 X86Fnmadd, v8f64, VK8WM>, EVEX_V512, VEX_W,
3068 EVEX_CD8<64, CD8VF>;
3069 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
3070 memopv8f64, f64mem, loadf64, "{1to8}",
3071 X86Fnmsub, v8f64, VK8WM>, EVEX_V512, VEX_W,
3072 EVEX_CD8<64, CD8VF>;
3075 let Constraints = "$src1 = $dst" in {
3076 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
3077 RegisterClass RC, X86MemOperand x86memop,
3078 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
3079 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
3081 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3082 (ins RC:$src1, RC:$src3, x86memop:$src2),
3083 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3084 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
3085 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3086 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
3087 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3088 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
3089 [(set RC:$dst, (OpNode RC:$src1,
3090 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
3092 } // Constraints = "$src1 = $dst"
3095 let ExeDomain = SSEPackedSingle in {
3096 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
3097 memopv16f32, f32mem, loadf32, "{1to16}",
3098 X86Fmadd, v16f32>, EVEX_V512,
3099 EVEX_CD8<32, CD8VF>;
3100 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
3101 memopv16f32, f32mem, loadf32, "{1to16}",
3102 X86Fmsub, v16f32>, EVEX_V512,
3103 EVEX_CD8<32, CD8VF>;
3104 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
3105 memopv16f32, f32mem, loadf32, "{1to16}",
3106 X86Fmaddsub, v16f32>,
3107 EVEX_V512, EVEX_CD8<32, CD8VF>;
3108 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
3109 memopv16f32, f32mem, loadf32, "{1to16}",
3110 X86Fmsubadd, v16f32>,
3111 EVEX_V512, EVEX_CD8<32, CD8VF>;
3112 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
3113 memopv16f32, f32mem, loadf32, "{1to16}",
3114 X86Fnmadd, v16f32>, EVEX_V512,
3115 EVEX_CD8<32, CD8VF>;
3116 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
3117 memopv16f32, f32mem, loadf32, "{1to16}",
3118 X86Fnmsub, v16f32>, EVEX_V512,
3119 EVEX_CD8<32, CD8VF>;
3121 let ExeDomain = SSEPackedDouble in {
3122 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
3123 memopv8f64, f64mem, loadf64, "{1to8}",
3124 X86Fmadd, v8f64>, EVEX_V512,
3125 VEX_W, EVEX_CD8<64, CD8VF>;
3126 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
3127 memopv8f64, f64mem, loadf64, "{1to8}",
3128 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
3129 EVEX_CD8<64, CD8VF>;
3130 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
3131 memopv8f64, f64mem, loadf64, "{1to8}",
3132 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
3133 EVEX_CD8<64, CD8VF>;
3134 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
3135 memopv8f64, f64mem, loadf64, "{1to8}",
3136 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
3137 EVEX_CD8<64, CD8VF>;
3138 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
3139 memopv8f64, f64mem, loadf64, "{1to8}",
3140 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
3141 EVEX_CD8<64, CD8VF>;
3142 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
3143 memopv8f64, f64mem, loadf64, "{1to8}",
3144 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
3145 EVEX_CD8<64, CD8VF>;
3149 let Constraints = "$src1 = $dst" in {
3150 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3151 RegisterClass RC, ValueType OpVT,
3152 X86MemOperand x86memop, Operand memop,
3154 let isCommutable = 1 in
3155 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3156 (ins RC:$src1, RC:$src2, RC:$src3),
3157 !strconcat(OpcodeStr,
3158 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3160 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3162 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3163 (ins RC:$src1, RC:$src2, f128mem:$src3),
3164 !strconcat(OpcodeStr,
3165 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3167 (OpVT (OpNode RC:$src2, RC:$src1,
3168 (mem_frag addr:$src3))))]>;
3171 } // Constraints = "$src1 = $dst"
3173 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3174 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3175 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3176 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3177 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3178 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3179 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3180 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3181 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3182 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3183 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3184 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3185 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3186 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3187 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3188 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3190 //===----------------------------------------------------------------------===//
3191 // AVX-512 Scalar convert from sign integer to float/double
3192 //===----------------------------------------------------------------------===//
3194 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3195 X86MemOperand x86memop, string asm> {
3196 let hasSideEffects = 0 in {
3197 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3198 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3201 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3202 (ins DstRC:$src1, x86memop:$src),
3203 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3205 } // hasSideEffects = 0
3207 let Predicates = [HasAVX512] in {
3208 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3209 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3210 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3211 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3212 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3213 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3214 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3215 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3217 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3218 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3219 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3220 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3221 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3222 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3223 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3224 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3226 def : Pat<(f32 (sint_to_fp GR32:$src)),
3227 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3228 def : Pat<(f32 (sint_to_fp GR64:$src)),
3229 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3230 def : Pat<(f64 (sint_to_fp GR32:$src)),
3231 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3232 def : Pat<(f64 (sint_to_fp GR64:$src)),
3233 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3235 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3236 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3237 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3238 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3239 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3240 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3241 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3242 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3244 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3245 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3246 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3247 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3248 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3249 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3250 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3251 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3253 def : Pat<(f32 (uint_to_fp GR32:$src)),
3254 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3255 def : Pat<(f32 (uint_to_fp GR64:$src)),
3256 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3257 def : Pat<(f64 (uint_to_fp GR32:$src)),
3258 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3259 def : Pat<(f64 (uint_to_fp GR64:$src)),
3260 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3263 //===----------------------------------------------------------------------===//
3264 // AVX-512 Scalar convert from float/double to integer
3265 //===----------------------------------------------------------------------===//
3266 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3267 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3269 let hasSideEffects = 0 in {
3270 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3271 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3272 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3273 Requires<[HasAVX512]>;
3275 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3276 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3277 Requires<[HasAVX512]>;
3278 } // hasSideEffects = 0
3280 let Predicates = [HasAVX512] in {
3281 // Convert float/double to signed/unsigned int 32/64
3282 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3283 ssmem, sse_load_f32, "cvtss2si">,
3284 XS, EVEX_CD8<32, CD8VT1>;
3285 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3286 ssmem, sse_load_f32, "cvtss2si">,
3287 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3288 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3289 ssmem, sse_load_f32, "cvtss2usi">,
3290 XS, EVEX_CD8<32, CD8VT1>;
3291 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3292 int_x86_avx512_cvtss2usi64, ssmem,
3293 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3294 EVEX_CD8<32, CD8VT1>;
3295 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3296 sdmem, sse_load_f64, "cvtsd2si">,
3297 XD, EVEX_CD8<64, CD8VT1>;
3298 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3299 sdmem, sse_load_f64, "cvtsd2si">,
3300 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3301 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3302 sdmem, sse_load_f64, "cvtsd2usi">,
3303 XD, EVEX_CD8<64, CD8VT1>;
3304 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3305 int_x86_avx512_cvtsd2usi64, sdmem,
3306 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3307 EVEX_CD8<64, CD8VT1>;
3309 let isCodeGenOnly = 1 in {
3310 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3311 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3312 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3313 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3314 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3315 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3316 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3317 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3318 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3319 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3320 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3321 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3323 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3324 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3325 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3326 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3327 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3328 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3329 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3330 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3331 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3332 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3333 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3334 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3335 } // isCodeGenOnly = 1
3337 // Convert float/double to signed/unsigned int 32/64 with truncation
3338 let isCodeGenOnly = 1 in {
3339 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3340 ssmem, sse_load_f32, "cvttss2si">,
3341 XS, EVEX_CD8<32, CD8VT1>;
3342 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3343 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3344 "cvttss2si">, XS, VEX_W,
3345 EVEX_CD8<32, CD8VT1>;
3346 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3347 sdmem, sse_load_f64, "cvttsd2si">, XD,
3348 EVEX_CD8<64, CD8VT1>;
3349 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3350 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3351 "cvttsd2si">, XD, VEX_W,
3352 EVEX_CD8<64, CD8VT1>;
3353 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3354 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3355 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3356 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3357 int_x86_avx512_cvttss2usi64, ssmem,
3358 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3359 EVEX_CD8<32, CD8VT1>;
3360 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3361 int_x86_avx512_cvttsd2usi,
3362 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3363 EVEX_CD8<64, CD8VT1>;
3364 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3365 int_x86_avx512_cvttsd2usi64, sdmem,
3366 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3367 EVEX_CD8<64, CD8VT1>;
3368 } // isCodeGenOnly = 1
3370 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3371 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3373 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3374 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3375 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3376 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3377 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3378 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3381 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3382 loadf32, "cvttss2si">, XS,
3383 EVEX_CD8<32, CD8VT1>;
3384 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3385 loadf32, "cvttss2usi">, XS,
3386 EVEX_CD8<32, CD8VT1>;
3387 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3388 loadf32, "cvttss2si">, XS, VEX_W,
3389 EVEX_CD8<32, CD8VT1>;
3390 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3391 loadf32, "cvttss2usi">, XS, VEX_W,
3392 EVEX_CD8<32, CD8VT1>;
3393 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3394 loadf64, "cvttsd2si">, XD,
3395 EVEX_CD8<64, CD8VT1>;
3396 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3397 loadf64, "cvttsd2usi">, XD,
3398 EVEX_CD8<64, CD8VT1>;
3399 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3400 loadf64, "cvttsd2si">, XD, VEX_W,
3401 EVEX_CD8<64, CD8VT1>;
3402 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3403 loadf64, "cvttsd2usi">, XD, VEX_W,
3404 EVEX_CD8<64, CD8VT1>;
3406 //===----------------------------------------------------------------------===//
3407 // AVX-512 Convert form float to double and back
3408 //===----------------------------------------------------------------------===//
3409 let hasSideEffects = 0 in {
3410 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3411 (ins FR32X:$src1, FR32X:$src2),
3412 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3413 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3415 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3416 (ins FR32X:$src1, f32mem:$src2),
3417 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3418 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3419 EVEX_CD8<32, CD8VT1>;
3421 // Convert scalar double to scalar single
3422 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3423 (ins FR64X:$src1, FR64X:$src2),
3424 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3425 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3427 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3428 (ins FR64X:$src1, f64mem:$src2),
3429 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3430 []>, EVEX_4V, VEX_LIG, VEX_W,
3431 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3434 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3435 Requires<[HasAVX512]>;
3436 def : Pat<(fextend (loadf32 addr:$src)),
3437 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3439 def : Pat<(extloadf32 addr:$src),
3440 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3441 Requires<[HasAVX512, OptForSize]>;
3443 def : Pat<(extloadf32 addr:$src),
3444 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3445 Requires<[HasAVX512, OptForSpeed]>;
3447 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3448 Requires<[HasAVX512]>;
3450 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3451 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3452 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3454 let hasSideEffects = 0 in {
3455 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3456 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3458 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3459 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3460 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3461 [], d>, EVEX, EVEX_B, EVEX_RC;
3463 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3464 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3466 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3467 } // hasSideEffects = 0
3470 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3471 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3472 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3474 let hasSideEffects = 0 in {
3475 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3476 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3478 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3480 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3481 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3483 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3484 } // hasSideEffects = 0
3487 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3488 memopv8f64, f512mem, v8f32, v8f64,
3489 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3490 EVEX_CD8<64, CD8VF>;
3492 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3493 memopv4f64, f256mem, v8f64, v8f32,
3494 SSEPackedDouble>, EVEX_V512, PS,
3495 EVEX_CD8<32, CD8VH>;
3496 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3497 (VCVTPS2PDZrm addr:$src)>;
3499 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3500 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3501 (VCVTPD2PSZrr VR512:$src)>;
3503 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3504 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3505 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3507 //===----------------------------------------------------------------------===//
3508 // AVX-512 Vector convert from sign integer to float/double
3509 //===----------------------------------------------------------------------===//
3511 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3512 memopv8i64, i512mem, v16f32, v16i32,
3513 SSEPackedSingle>, EVEX_V512, PS,
3514 EVEX_CD8<32, CD8VF>;
3516 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3517 memopv4i64, i256mem, v8f64, v8i32,
3518 SSEPackedDouble>, EVEX_V512, XS,
3519 EVEX_CD8<32, CD8VH>;
3521 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3522 memopv16f32, f512mem, v16i32, v16f32,
3523 SSEPackedSingle>, EVEX_V512, XS,
3524 EVEX_CD8<32, CD8VF>;
3526 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3527 memopv8f64, f512mem, v8i32, v8f64,
3528 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3529 EVEX_CD8<64, CD8VF>;
3531 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3532 memopv16f32, f512mem, v16i32, v16f32,
3533 SSEPackedSingle>, EVEX_V512, PS,
3534 EVEX_CD8<32, CD8VF>;
3536 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3537 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3538 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3539 (VCVTTPS2UDQZrr VR512:$src)>;
3541 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3542 memopv8f64, f512mem, v8i32, v8f64,
3543 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3544 EVEX_CD8<64, CD8VF>;
3546 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3547 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3548 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3549 (VCVTTPD2UDQZrr VR512:$src)>;
3551 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3552 memopv4i64, f256mem, v8f64, v8i32,
3553 SSEPackedDouble>, EVEX_V512, XS,
3554 EVEX_CD8<32, CD8VH>;
3556 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3557 memopv16i32, f512mem, v16f32, v16i32,
3558 SSEPackedSingle>, EVEX_V512, XD,
3559 EVEX_CD8<32, CD8VF>;
3561 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3562 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3563 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3565 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3566 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3567 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3569 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3570 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3571 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3573 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3574 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3575 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3577 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3578 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3579 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3581 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3582 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3583 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3584 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3585 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3586 (VCVTDQ2PDZrr VR256X:$src)>;
3587 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3588 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3589 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3590 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3591 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3592 (VCVTUDQ2PDZrr VR256X:$src)>;
3594 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3595 RegisterClass DstRC, PatFrag mem_frag,
3596 X86MemOperand x86memop, Domain d> {
3597 let hasSideEffects = 0 in {
3598 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3599 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3601 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3602 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3603 [], d>, EVEX, EVEX_B, EVEX_RC;
3605 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3606 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3608 } // hasSideEffects = 0
3611 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3612 memopv16f32, f512mem, SSEPackedSingle>, PD,
3613 EVEX_V512, EVEX_CD8<32, CD8VF>;
3614 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3615 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3616 EVEX_V512, EVEX_CD8<64, CD8VF>;
3618 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3619 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3620 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3622 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3623 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3624 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3626 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3627 memopv16f32, f512mem, SSEPackedSingle>,
3628 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3629 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3630 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3631 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3633 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3634 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3635 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3637 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3638 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3639 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3641 let Predicates = [HasAVX512] in {
3642 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3643 (VCVTPD2PSZrm addr:$src)>;
3644 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3645 (VCVTPS2PDZrm addr:$src)>;
3648 //===----------------------------------------------------------------------===//
3649 // Half precision conversion instructions
3650 //===----------------------------------------------------------------------===//
3651 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3652 X86MemOperand x86memop> {
3653 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3654 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3656 let hasSideEffects = 0, mayLoad = 1 in
3657 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3658 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3661 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3662 X86MemOperand x86memop> {
3663 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3664 (ins srcRC:$src1, i32i8imm:$src2),
3665 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3667 let hasSideEffects = 0, mayStore = 1 in
3668 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3669 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3670 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3673 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3674 EVEX_CD8<32, CD8VH>;
3675 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3676 EVEX_CD8<32, CD8VH>;
3678 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3679 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3680 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3682 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3683 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3684 (VCVTPH2PSZrr VR256X:$src)>;
3686 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3687 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3688 "ucomiss">, PS, EVEX, VEX_LIG,
3689 EVEX_CD8<32, CD8VT1>;
3690 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3691 "ucomisd">, PD, EVEX,
3692 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3693 let Pattern = []<dag> in {
3694 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3695 "comiss">, PS, EVEX, VEX_LIG,
3696 EVEX_CD8<32, CD8VT1>;
3697 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3698 "comisd">, PD, EVEX,
3699 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3701 let isCodeGenOnly = 1 in {
3702 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3703 load, "ucomiss">, PS, EVEX, VEX_LIG,
3704 EVEX_CD8<32, CD8VT1>;
3705 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3706 load, "ucomisd">, PD, EVEX,
3707 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3709 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3710 load, "comiss">, PS, EVEX, VEX_LIG,
3711 EVEX_CD8<32, CD8VT1>;
3712 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3713 load, "comisd">, PD, EVEX,
3714 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3718 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3719 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3720 X86MemOperand x86memop> {
3721 let hasSideEffects = 0 in {
3722 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3723 (ins RC:$src1, RC:$src2),
3724 !strconcat(OpcodeStr,
3725 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3726 let mayLoad = 1 in {
3727 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3728 (ins RC:$src1, x86memop:$src2),
3729 !strconcat(OpcodeStr,
3730 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3735 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3736 EVEX_CD8<32, CD8VT1>;
3737 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3738 VEX_W, EVEX_CD8<64, CD8VT1>;
3739 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3740 EVEX_CD8<32, CD8VT1>;
3741 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3742 VEX_W, EVEX_CD8<64, CD8VT1>;
3744 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3745 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3746 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3747 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3749 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3750 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3751 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3752 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3754 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3755 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3756 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3757 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3759 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3760 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3761 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3762 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3764 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3765 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3766 RegisterClass RC, X86MemOperand x86memop,
3767 PatFrag mem_frag, ValueType OpVt> {
3768 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3769 !strconcat(OpcodeStr,
3770 " \t{$src, $dst|$dst, $src}"),
3771 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3773 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3774 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3775 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3778 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3779 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3780 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3781 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3782 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3783 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3784 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3785 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3787 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3788 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3789 (VRSQRT14PSZr VR512:$src)>;
3790 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3791 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3792 (VRSQRT14PDZr VR512:$src)>;
3794 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3795 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3796 (VRCP14PSZr VR512:$src)>;
3797 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3798 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3799 (VRCP14PDZr VR512:$src)>;
3801 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3802 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3803 X86MemOperand x86memop> {
3804 let hasSideEffects = 0, Predicates = [HasERI] in {
3805 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3806 (ins RC:$src1, RC:$src2),
3807 !strconcat(OpcodeStr,
3808 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3809 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3810 (ins RC:$src1, RC:$src2),
3811 !strconcat(OpcodeStr,
3812 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3813 []>, EVEX_4V, EVEX_B;
3814 let mayLoad = 1 in {
3815 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3816 (ins RC:$src1, x86memop:$src2),
3817 !strconcat(OpcodeStr,
3818 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3823 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3824 EVEX_CD8<32, CD8VT1>;
3825 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3826 VEX_W, EVEX_CD8<64, CD8VT1>;
3827 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3828 EVEX_CD8<32, CD8VT1>;
3829 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3830 VEX_W, EVEX_CD8<64, CD8VT1>;
3832 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3833 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3835 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3836 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3838 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3839 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3841 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3842 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3844 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3845 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3847 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3848 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3850 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3851 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3853 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3854 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3856 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3857 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3858 RegisterClass RC, X86MemOperand x86memop> {
3859 let hasSideEffects = 0, Predicates = [HasERI] in {
3860 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3861 !strconcat(OpcodeStr,
3862 " \t{$src, $dst|$dst, $src}"),
3864 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3865 !strconcat(OpcodeStr,
3866 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3868 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3869 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3873 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3874 EVEX_V512, EVEX_CD8<32, CD8VF>;
3875 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3876 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3877 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3878 EVEX_V512, EVEX_CD8<32, CD8VF>;
3879 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3880 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3882 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3883 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3884 (VRSQRT28PSZrb VR512:$src)>;
3885 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3886 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3887 (VRSQRT28PDZrb VR512:$src)>;
3889 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3890 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3891 (VRCP28PSZrb VR512:$src)>;
3892 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3893 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3894 (VRCP28PDZrb VR512:$src)>;
3896 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3897 OpndItins itins_s, OpndItins itins_d> {
3898 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3899 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3900 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3904 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3905 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3907 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3908 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3910 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3911 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3912 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3916 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3917 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3918 [(set VR512:$dst, (OpNode
3919 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3920 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3924 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3925 Intrinsic F32Int, Intrinsic F64Int,
3926 OpndItins itins_s, OpndItins itins_d> {
3927 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3928 (ins FR32X:$src1, FR32X:$src2),
3929 !strconcat(OpcodeStr,
3930 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3931 [], itins_s.rr>, XS, EVEX_4V;
3932 let isCodeGenOnly = 1 in
3933 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3934 (ins VR128X:$src1, VR128X:$src2),
3935 !strconcat(OpcodeStr,
3936 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3938 (F32Int VR128X:$src1, VR128X:$src2))],
3939 itins_s.rr>, XS, EVEX_4V;
3940 let mayLoad = 1 in {
3941 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3942 (ins FR32X:$src1, f32mem:$src2),
3943 !strconcat(OpcodeStr,
3944 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3945 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3946 let isCodeGenOnly = 1 in
3947 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3948 (ins VR128X:$src1, ssmem:$src2),
3949 !strconcat(OpcodeStr,
3950 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3952 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3953 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3955 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3956 (ins FR64X:$src1, FR64X:$src2),
3957 !strconcat(OpcodeStr,
3958 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3960 let isCodeGenOnly = 1 in
3961 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3962 (ins VR128X:$src1, VR128X:$src2),
3963 !strconcat(OpcodeStr,
3964 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3966 (F64Int VR128X:$src1, VR128X:$src2))],
3967 itins_s.rr>, XD, EVEX_4V, VEX_W;
3968 let mayLoad = 1 in {
3969 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3970 (ins FR64X:$src1, f64mem:$src2),
3971 !strconcat(OpcodeStr,
3972 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3973 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3974 let isCodeGenOnly = 1 in
3975 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3976 (ins VR128X:$src1, sdmem:$src2),
3977 !strconcat(OpcodeStr,
3978 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3980 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3981 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3986 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3987 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3988 SSE_SQRTSS, SSE_SQRTSD>,
3989 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3990 SSE_SQRTPS, SSE_SQRTPD>;
3992 let Predicates = [HasAVX512] in {
3993 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3994 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3995 (VSQRTPSZrr VR512:$src1)>;
3996 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3997 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3998 (VSQRTPDZrr VR512:$src1)>;
4000 def : Pat<(f32 (fsqrt FR32X:$src)),
4001 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4002 def : Pat<(f32 (fsqrt (load addr:$src))),
4003 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4004 Requires<[OptForSize]>;
4005 def : Pat<(f64 (fsqrt FR64X:$src)),
4006 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4007 def : Pat<(f64 (fsqrt (load addr:$src))),
4008 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4009 Requires<[OptForSize]>;
4011 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4012 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4013 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4014 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4015 Requires<[OptForSize]>;
4017 def : Pat<(f32 (X86frcp FR32X:$src)),
4018 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4019 def : Pat<(f32 (X86frcp (load addr:$src))),
4020 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4021 Requires<[OptForSize]>;
4023 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4024 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4025 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4027 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4028 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4030 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4031 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4032 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4034 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4035 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4039 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4040 X86MemOperand x86memop, RegisterClass RC,
4041 PatFrag mem_frag32, PatFrag mem_frag64,
4042 Intrinsic V4F32Int, Intrinsic V2F64Int,
4044 let ExeDomain = SSEPackedSingle in {
4045 // Intrinsic operation, reg.
4046 // Vector intrinsic operation, reg
4047 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4048 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4049 !strconcat(OpcodeStr,
4050 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4051 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4053 // Vector intrinsic operation, mem
4054 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4055 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4056 !strconcat(OpcodeStr,
4057 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4059 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4060 EVEX_CD8<32, VForm>;
4061 } // ExeDomain = SSEPackedSingle
4063 let ExeDomain = SSEPackedDouble in {
4064 // Vector intrinsic operation, reg
4065 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4066 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4067 !strconcat(OpcodeStr,
4068 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4069 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4071 // Vector intrinsic operation, mem
4072 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4073 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4074 !strconcat(OpcodeStr,
4075 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4077 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4078 EVEX_CD8<64, VForm>;
4079 } // ExeDomain = SSEPackedDouble
4082 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4086 let ExeDomain = GenericDomain in {
4088 let hasSideEffects = 0 in
4089 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4090 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4091 !strconcat(OpcodeStr,
4092 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4095 // Intrinsic operation, reg.
4096 let isCodeGenOnly = 1 in
4097 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4098 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4099 !strconcat(OpcodeStr,
4100 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4101 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4103 // Intrinsic operation, mem.
4104 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4105 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4106 !strconcat(OpcodeStr,
4107 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4108 [(set VR128X:$dst, (F32Int VR128X:$src1,
4109 sse_load_f32:$src2, imm:$src3))]>,
4110 EVEX_CD8<32, CD8VT1>;
4113 let hasSideEffects = 0 in
4114 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4115 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4116 !strconcat(OpcodeStr,
4117 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4120 // Intrinsic operation, reg.
4121 let isCodeGenOnly = 1 in
4122 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4123 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4124 !strconcat(OpcodeStr,
4125 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4126 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4129 // Intrinsic operation, mem.
4130 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4131 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4132 !strconcat(OpcodeStr,
4133 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4135 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4136 VEX_W, EVEX_CD8<64, CD8VT1>;
4137 } // ExeDomain = GenericDomain
4140 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4141 X86MemOperand x86memop, RegisterClass RC,
4142 PatFrag mem_frag, Domain d> {
4143 let ExeDomain = d in {
4144 // Intrinsic operation, reg.
4145 // Vector intrinsic operation, reg
4146 def r : AVX512AIi8<opc, MRMSrcReg,
4147 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4148 !strconcat(OpcodeStr,
4149 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4152 // Vector intrinsic operation, mem
4153 def m : AVX512AIi8<opc, MRMSrcMem,
4154 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4155 !strconcat(OpcodeStr,
4156 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4162 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4163 memopv16f32, SSEPackedSingle>, EVEX_V512,
4164 EVEX_CD8<32, CD8VF>;
4166 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4167 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4169 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4172 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4173 memopv8f64, SSEPackedDouble>, EVEX_V512,
4174 VEX_W, EVEX_CD8<64, CD8VF>;
4176 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4177 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4179 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4181 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4182 Operand x86memop, RegisterClass RC, Domain d> {
4183 let ExeDomain = d in {
4184 def r : AVX512AIi8<opc, MRMSrcReg,
4185 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4186 !strconcat(OpcodeStr,
4187 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4190 def m : AVX512AIi8<opc, MRMSrcMem,
4191 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4192 !strconcat(OpcodeStr,
4193 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4198 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4199 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4201 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4202 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4204 def : Pat<(ffloor FR32X:$src),
4205 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4206 def : Pat<(f64 (ffloor FR64X:$src)),
4207 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4208 def : Pat<(f32 (fnearbyint FR32X:$src)),
4209 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4210 def : Pat<(f64 (fnearbyint FR64X:$src)),
4211 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4212 def : Pat<(f32 (fceil FR32X:$src)),
4213 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4214 def : Pat<(f64 (fceil FR64X:$src)),
4215 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4216 def : Pat<(f32 (frint FR32X:$src)),
4217 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4218 def : Pat<(f64 (frint FR64X:$src)),
4219 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4220 def : Pat<(f32 (ftrunc FR32X:$src)),
4221 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4222 def : Pat<(f64 (ftrunc FR64X:$src)),
4223 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4225 def : Pat<(v16f32 (ffloor VR512:$src)),
4226 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4227 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4228 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4229 def : Pat<(v16f32 (fceil VR512:$src)),
4230 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4231 def : Pat<(v16f32 (frint VR512:$src)),
4232 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4233 def : Pat<(v16f32 (ftrunc VR512:$src)),
4234 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4236 def : Pat<(v8f64 (ffloor VR512:$src)),
4237 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4238 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4239 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4240 def : Pat<(v8f64 (fceil VR512:$src)),
4241 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4242 def : Pat<(v8f64 (frint VR512:$src)),
4243 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4244 def : Pat<(v8f64 (ftrunc VR512:$src)),
4245 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4247 //-------------------------------------------------
4248 // Integer truncate and extend operations
4249 //-------------------------------------------------
4251 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4252 RegisterClass dstRC, RegisterClass srcRC,
4253 RegisterClass KRC, X86MemOperand x86memop> {
4254 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4256 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4259 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4260 (ins KRC:$mask, srcRC:$src),
4261 !strconcat(OpcodeStr,
4262 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4265 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4266 (ins KRC:$mask, srcRC:$src),
4267 !strconcat(OpcodeStr,
4268 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4271 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4272 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4275 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4276 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4277 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4281 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4282 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4283 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4284 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4285 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4286 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4287 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4288 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4289 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4290 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4291 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4292 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4293 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4294 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4295 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4296 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4297 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4298 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4299 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4300 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4301 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4302 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4303 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4304 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4305 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4306 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4307 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4308 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4309 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4310 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4312 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4313 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4314 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4315 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4316 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4318 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4319 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4320 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4321 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4322 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4323 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4324 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4325 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4328 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4329 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4330 PatFrag mem_frag, X86MemOperand x86memop,
4331 ValueType OpVT, ValueType InVT> {
4333 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4335 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4336 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4338 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4339 (ins KRC:$mask, SrcRC:$src),
4340 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4343 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4344 (ins KRC:$mask, SrcRC:$src),
4345 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4348 let mayLoad = 1 in {
4349 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4350 (ins x86memop:$src),
4351 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4353 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4356 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4357 (ins KRC:$mask, x86memop:$src),
4358 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4362 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4363 (ins KRC:$mask, x86memop:$src),
4364 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4370 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4371 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4373 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4374 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4376 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4377 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4378 EVEX_CD8<16, CD8VH>;
4379 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4380 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4381 EVEX_CD8<16, CD8VQ>;
4382 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4383 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4384 EVEX_CD8<32, CD8VH>;
4386 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4387 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4389 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4390 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4392 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4393 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4394 EVEX_CD8<16, CD8VH>;
4395 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4396 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4397 EVEX_CD8<16, CD8VQ>;
4398 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4399 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4400 EVEX_CD8<32, CD8VH>;
4402 //===----------------------------------------------------------------------===//
4403 // GATHER - SCATTER Operations
4405 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4406 RegisterClass RC, X86MemOperand memop> {
4408 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4409 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4410 (ins RC:$src1, KRC:$mask, memop:$src2),
4411 !strconcat(OpcodeStr,
4412 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4416 let ExeDomain = SSEPackedDouble in {
4417 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4418 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4419 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4420 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4423 let ExeDomain = SSEPackedSingle in {
4424 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4425 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4426 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4427 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4430 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4431 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4432 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4433 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4435 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4436 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4437 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4438 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4440 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4441 RegisterClass RC, X86MemOperand memop> {
4442 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4443 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4444 (ins memop:$dst, KRC:$mask, RC:$src2),
4445 !strconcat(OpcodeStr,
4446 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4450 let ExeDomain = SSEPackedDouble in {
4451 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4452 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4453 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4454 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4457 let ExeDomain = SSEPackedSingle in {
4458 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4459 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4460 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4461 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4464 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4465 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4466 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4467 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4469 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4470 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4471 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4472 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4475 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4476 RegisterClass KRC, X86MemOperand memop> {
4477 let Predicates = [HasPFI], hasSideEffects = 1 in
4478 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4479 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4483 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4484 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4486 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4487 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4489 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4490 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4492 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4493 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4495 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4496 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4498 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4499 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4501 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4502 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4504 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4505 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4507 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4508 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4510 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4511 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4513 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4514 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4516 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4517 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4519 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4520 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4522 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4523 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4525 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4526 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4528 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4529 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4530 //===----------------------------------------------------------------------===//
4531 // VSHUFPS - VSHUFPD Operations
4533 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4534 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4536 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4537 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4538 !strconcat(OpcodeStr,
4539 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4540 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4541 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4542 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4543 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4544 (ins RC:$src1, RC:$src2, i8imm:$src3),
4545 !strconcat(OpcodeStr,
4546 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4547 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4548 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4549 EVEX_4V, Sched<[WriteShuffle]>;
4552 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4553 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4554 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4555 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4557 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4558 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4559 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4560 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4561 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4563 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4564 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4565 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4566 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4567 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4569 multiclass avx512_valign<string Suffix, RegisterClass RC, RegisterClass KRC,
4570 RegisterClass MRC, X86MemOperand x86memop,
4571 ValueType IntVT, ValueType FloatVT> {
4572 defm rri : AVX512_masking<0x03, MRMSrcReg, (outs RC:$dst),
4573 (ins RC:$src1, RC:$src2, i8imm:$src3),
4575 "$src3, $src2, $src1", "$src1, $src2, $src3",
4576 (IntVT (X86VAlign RC:$src2, RC:$src1,
4579 AVX512AIi8Base, EVEX_4V;
4581 // Also match valign of packed floats.
4582 def : Pat<(FloatVT (X86VAlign RC:$src1, RC:$src2, (i8 imm:$imm))),
4583 (!cast<Instruction>(NAME##rri) RC:$src2, RC:$src1, imm:$imm)>;
4586 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4587 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4588 !strconcat("valign"##Suffix,
4589 " \t{$src3, $src2, $src1, $dst|"
4590 "$dst, $src1, $src2, $src3}"),
4593 defm VALIGND : avx512_valign<"d", VR512, VK16WM, GR16, i512mem, v16i32, v16f32>,
4594 EVEX_V512, EVEX_CD8<32, CD8VF>;
4595 defm VALIGNQ : avx512_valign<"q", VR512, VK8WM, GR8, i512mem, v8i64, v8f64>,
4596 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4598 // Helper fragments to match sext vXi1 to vXiY.
4599 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4600 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4602 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4603 RegisterClass KRC, RegisterClass RC,
4604 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4606 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4607 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4609 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4610 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4612 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4613 !strconcat(OpcodeStr,
4614 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4616 let mayLoad = 1 in {
4617 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4618 (ins x86memop:$src),
4619 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4621 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4622 (ins KRC:$mask, x86memop:$src),
4623 !strconcat(OpcodeStr,
4624 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4626 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4627 (ins KRC:$mask, x86memop:$src),
4628 !strconcat(OpcodeStr,
4629 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4631 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4632 (ins x86scalar_mop:$src),
4633 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4634 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4636 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4637 (ins KRC:$mask, x86scalar_mop:$src),
4638 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4639 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4640 []>, EVEX, EVEX_B, EVEX_K;
4641 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4642 (ins KRC:$mask, x86scalar_mop:$src),
4643 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4644 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4646 []>, EVEX, EVEX_B, EVEX_KZ;
4650 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4651 i512mem, i32mem, "{1to16}">, EVEX_V512,
4652 EVEX_CD8<32, CD8VF>;
4653 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4654 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4655 EVEX_CD8<64, CD8VF>;
4658 (bc_v16i32 (v16i1sextv16i32)),
4659 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4660 (VPABSDZrr VR512:$src)>;
4662 (bc_v8i64 (v8i1sextv8i64)),
4663 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4664 (VPABSQZrr VR512:$src)>;
4666 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4667 (v16i32 immAllZerosV), (i16 -1))),
4668 (VPABSDZrr VR512:$src)>;
4669 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4670 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4671 (VPABSQZrr VR512:$src)>;
4673 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4674 RegisterClass RC, RegisterClass KRC,
4675 X86MemOperand x86memop,
4676 X86MemOperand x86scalar_mop, string BrdcstStr> {
4677 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4679 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4681 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4682 (ins x86memop:$src),
4683 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4685 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4686 (ins x86scalar_mop:$src),
4687 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4688 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4690 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4691 (ins KRC:$mask, RC:$src),
4692 !strconcat(OpcodeStr,
4693 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4695 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4696 (ins KRC:$mask, x86memop:$src),
4697 !strconcat(OpcodeStr,
4698 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4700 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4701 (ins KRC:$mask, x86scalar_mop:$src),
4702 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4703 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4705 []>, EVEX, EVEX_KZ, EVEX_B;
4707 let Constraints = "$src1 = $dst" in {
4708 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4709 (ins RC:$src1, KRC:$mask, RC:$src2),
4710 !strconcat(OpcodeStr,
4711 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4713 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4714 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4715 !strconcat(OpcodeStr,
4716 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4718 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4719 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4720 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4721 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4722 []>, EVEX, EVEX_K, EVEX_B;
4726 let Predicates = [HasCDI] in {
4727 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4728 i512mem, i32mem, "{1to16}">,
4729 EVEX_V512, EVEX_CD8<32, CD8VF>;
4732 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4733 i512mem, i64mem, "{1to8}">,
4734 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4738 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4740 (VPCONFLICTDrrk VR512:$src1,
4741 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4743 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4745 (VPCONFLICTQrrk VR512:$src1,
4746 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4748 let Predicates = [HasCDI] in {
4749 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4750 i512mem, i32mem, "{1to16}">,
4751 EVEX_V512, EVEX_CD8<32, CD8VF>;
4754 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4755 i512mem, i64mem, "{1to8}">,
4756 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4760 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4762 (VPLZCNTDrrk VR512:$src1,
4763 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4765 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4767 (VPLZCNTQrrk VR512:$src1,
4768 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4770 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4771 (VPLZCNTDrm addr:$src)>;
4772 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4773 (VPLZCNTDrr VR512:$src)>;
4774 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4775 (VPLZCNTQrm addr:$src)>;
4776 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4777 (VPLZCNTQrr VR512:$src)>;
4779 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4780 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4781 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4783 def : Pat<(store VK1:$src, addr:$dst),
4784 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4786 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4787 (truncstore node:$val, node:$ptr), [{
4788 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4791 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4792 (MOV8mr addr:$dst, GR8:$src)>;