1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
25 string VTName = "v" # NumElts # EltVT;
28 ValueType VT = !cast<ValueType>(VTName);
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
35 // "i" for integer types and "f" for floating-point types
36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
38 // Size of RC in bits, e.g. 512 for VR512.
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
63 // The corresponding float type, e.g. v16f32 for v16i32
64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
84 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
85 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
86 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
87 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
88 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
89 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
91 // "x" in v32i8x_info means RC = VR256X
92 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
93 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
94 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
95 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
97 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
98 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
99 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
100 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
102 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
103 X86VectorVTInfo i128> {
104 X86VectorVTInfo info512 = i512;
105 X86VectorVTInfo info256 = i256;
106 X86VectorVTInfo info128 = i128;
109 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
111 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
113 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
115 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
119 // Common base class of AVX512_masking and AVX512_masking_3src.
120 multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
122 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
124 string AttSrcAsm, string IntelSrcAsm,
125 dag RHS, dag MaskingRHS,
126 string MaskingConstraint = ""> {
127 def NAME: AVX512<O, F, Outs, Ins,
128 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
129 "$dst, "#IntelSrcAsm#"}",
130 [(set _.RC:$dst, RHS)]>;
132 // Prefer over VMOV*rrk Pat<>
133 let AddedComplexity = 20 in
134 def NAME#k: AVX512<O, F, Outs, MaskingIns,
135 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
136 "$dst {${mask}}, "#IntelSrcAsm#"}",
137 [(set _.RC:$dst, MaskingRHS)]>,
139 // In case of the 3src subclass this is overridden with a let.
140 string Constraints = MaskingConstraint;
142 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
143 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
144 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
145 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
147 (vselect _.KRCWM:$mask, RHS,
149 (v16i32 immAllZerosV)))))]>,
153 // This multiclass generates the unconditional/non-masking, the masking and
154 // the zero-masking variant of the instruction. In the masking case, the
155 // perserved vector elements come from a new dummy input operand tied to $dst.
156 multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
157 dag Outs, dag Ins, string OpcodeStr,
158 string AttSrcAsm, string IntelSrcAsm,
160 AVX512_masking_common<O, F, _, Outs, Ins,
161 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
162 !con((ins _.KRCWM:$mask), Ins),
163 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
164 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
167 // Similar to AVX512_masking but in this case one of the source operands
168 // ($src1) is already tied to $dst so we just use that for the preserved
169 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
171 multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
172 dag Outs, dag NonTiedIns, string OpcodeStr,
173 string AttSrcAsm, string IntelSrcAsm,
175 AVX512_masking_common<O, F, _, Outs,
176 !con((ins _.RC:$src1), NonTiedIns),
177 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
178 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
179 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
180 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
182 // Bitcasts between 512-bit vector types. Return the original type since
183 // no instruction is needed for the conversion
184 let Predicates = [HasAVX512] in {
185 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
186 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
187 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
188 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
189 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
190 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
191 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
192 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
193 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
194 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
195 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
196 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
197 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
198 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
199 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
200 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
201 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
202 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
203 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
204 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
205 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
206 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
207 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
208 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
209 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
210 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
211 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
212 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
213 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
214 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
215 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
217 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
218 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
219 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
220 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
221 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
222 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
223 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
224 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
225 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
226 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
227 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
228 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
229 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
230 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
231 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
232 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
233 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
234 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
235 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
236 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
237 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
238 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
239 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
240 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
241 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
242 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
243 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
244 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
245 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
246 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
248 // Bitcasts between 256-bit vector types. Return the original type since
249 // no instruction is needed for the conversion
250 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
251 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
252 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
253 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
254 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
255 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
256 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
257 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
258 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
259 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
260 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
261 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
262 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
263 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
264 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
265 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
266 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
267 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
268 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
269 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
270 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
271 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
272 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
273 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
274 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
275 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
276 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
277 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
278 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
279 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
283 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
286 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
287 isPseudo = 1, Predicates = [HasAVX512] in {
288 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
289 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
292 let Predicates = [HasAVX512] in {
293 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
294 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
295 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
298 //===----------------------------------------------------------------------===//
299 // AVX-512 - VECTOR INSERT
302 multiclass vinsert_for_size<int Opcode,
303 X86VectorVTInfo From, X86VectorVTInfo To,
304 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
305 PatFrag vinsert_insert,
306 SDNodeXForm INSERT_get_vinsert_imm> {
307 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
308 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
309 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
310 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
311 "$dst, $src1, $src2, $src3}",
312 []>, EVEX_4V, EVEX_V512;
315 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
316 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
317 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
318 "$dst, $src1, $src2, $src3}",
319 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
322 // Codegen pattern, e.g. v4i32 -> v16i32 for vinserti32x4
323 def : Pat<(vinsert_insert:$ins
324 (To.VT VR512:$src1), (From.VT From.RC:$src2), (iPTR imm)),
325 (To.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
326 VR512:$src1, From.RC:$src2,
327 (INSERT_get_vinsert_imm VR512:$ins)))>;
329 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
331 def : Pat<(vinsert_insert:$ins
332 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
333 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
334 VR512:$src1, From.RC:$src2,
335 (INSERT_get_vinsert_imm VR512:$ins)))>;
338 multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
339 ValueType EltVT64, int Opcode64> {
340 defm NAME # "32x4" : vinsert_for_size<Opcode32,
341 X86VectorVTInfo< 4, EltVT32, VR128X>,
342 X86VectorVTInfo<16, EltVT32, VR512>,
343 X86VectorVTInfo< 2, EltVT64, VR128X>,
344 X86VectorVTInfo< 8, EltVT64, VR512>,
346 INSERT_get_vinsert128_imm>;
347 defm NAME # "64x4" : vinsert_for_size<Opcode64,
348 X86VectorVTInfo< 4, EltVT64, VR256X>,
349 X86VectorVTInfo< 8, EltVT64, VR512>,
350 X86VectorVTInfo< 8, EltVT32, VR256>,
351 X86VectorVTInfo<16, EltVT32, VR512>,
353 INSERT_get_vinsert256_imm>, VEX_W;
356 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
357 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
359 // vinsertps - insert f32 to XMM
360 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
361 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
362 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
363 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
365 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
366 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
367 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
368 [(set VR128X:$dst, (X86insertps VR128X:$src1,
369 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
370 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
372 //===----------------------------------------------------------------------===//
373 // AVX-512 VECTOR EXTRACT
376 multiclass vextract_for_size<int Opcode,
377 X86VectorVTInfo From, X86VectorVTInfo To,
378 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
379 PatFrag vextract_extract,
380 SDNodeXForm EXTRACT_get_vextract_imm> {
381 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
382 def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
383 (ins VR512:$src1, i8imm:$idx),
384 "vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
385 "$dst, $src1, $idx}",
386 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
390 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
391 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
392 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
393 "$dst, $src1, $src2}",
394 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
397 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
399 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
400 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
402 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
404 // A 128/256-bit subvector extract from the first 512-bit vector position is
405 // a subregister copy that needs no instruction.
406 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
408 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
410 // And for the alternative types.
411 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
413 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
416 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
417 ValueType EltVT64, int Opcode64> {
418 defm NAME # "32x4" : vextract_for_size<Opcode32,
419 X86VectorVTInfo<16, EltVT32, VR512>,
420 X86VectorVTInfo< 4, EltVT32, VR128X>,
421 X86VectorVTInfo< 8, EltVT64, VR512>,
422 X86VectorVTInfo< 2, EltVT64, VR128X>,
424 EXTRACT_get_vextract128_imm>;
425 defm NAME # "64x4" : vextract_for_size<Opcode64,
426 X86VectorVTInfo< 8, EltVT64, VR512>,
427 X86VectorVTInfo< 4, EltVT64, VR256X>,
428 X86VectorVTInfo<16, EltVT32, VR512>,
429 X86VectorVTInfo< 8, EltVT32, VR256>,
431 EXTRACT_get_vextract256_imm>, VEX_W;
434 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
435 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
437 // A 128-bit subvector insert to the first 512-bit vector position
438 // is a subregister copy that needs no instruction.
439 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
440 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
441 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
443 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
444 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
445 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
447 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
448 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
449 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
451 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
452 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
453 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
456 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
457 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
458 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
459 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
460 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
461 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
462 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
463 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
465 // vextractps - extract 32 bits from XMM
466 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
467 (ins VR128X:$src1, i32i8imm:$src2),
468 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
469 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
472 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
473 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
474 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
475 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
476 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
478 //===---------------------------------------------------------------------===//
481 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
482 RegisterClass DestRC,
483 RegisterClass SrcRC, X86MemOperand x86memop> {
484 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
485 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
487 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
488 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
490 let ExeDomain = SSEPackedSingle in {
491 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
493 EVEX_V512, EVEX_CD8<32, CD8VT1>;
496 let ExeDomain = SSEPackedDouble in {
497 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
499 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
502 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
503 (VBROADCASTSSZrm addr:$src)>;
504 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
505 (VBROADCASTSDZrm addr:$src)>;
507 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
508 (VBROADCASTSSZrm addr:$src)>;
509 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
510 (VBROADCASTSDZrm addr:$src)>;
512 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
513 RegisterClass SrcRC, RegisterClass KRC> {
514 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
515 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
516 []>, EVEX, EVEX_V512;
517 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
518 (ins KRC:$mask, SrcRC:$src),
519 !strconcat(OpcodeStr,
520 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
521 []>, EVEX, EVEX_V512, EVEX_KZ;
524 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
525 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
528 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
529 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
531 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
532 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
534 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
535 (VPBROADCASTDrZrr GR32:$src)>;
536 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
537 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
538 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
539 (VPBROADCASTQrZrr GR64:$src)>;
540 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
541 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
543 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
544 (VPBROADCASTDrZrr GR32:$src)>;
545 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
546 (VPBROADCASTQrZrr GR64:$src)>;
548 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
549 (v16i32 immAllZerosV), (i16 GR16:$mask))),
550 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
551 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
552 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
553 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
555 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
556 X86MemOperand x86memop, PatFrag ld_frag,
557 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
559 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
560 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
562 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
563 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
565 !strconcat(OpcodeStr,
566 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
568 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
571 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
572 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
574 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
575 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
577 !strconcat(OpcodeStr,
578 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
579 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
580 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
584 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
585 loadi32, VR512, v16i32, v4i32, VK16WM>,
586 EVEX_V512, EVEX_CD8<32, CD8VT1>;
587 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
588 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
589 EVEX_CD8<64, CD8VT1>;
591 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
592 X86MemOperand x86memop, PatFrag ld_frag,
595 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
596 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
598 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
600 !strconcat(OpcodeStr,
601 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
606 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
607 i128mem, loadv2i64, VK16WM>,
608 EVEX_V512, EVEX_CD8<32, CD8VT4>;
609 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
610 i256mem, loadv4i64, VK16WM>, VEX_W,
611 EVEX_V512, EVEX_CD8<64, CD8VT4>;
613 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
614 (VPBROADCASTDZrr VR128X:$src)>;
615 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
616 (VPBROADCASTQZrr VR128X:$src)>;
618 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
619 (VBROADCASTSSZrr VR128X:$src)>;
620 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
621 (VBROADCASTSDZrr VR128X:$src)>;
623 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
624 (VBROADCASTSSZrr VR128X:$src)>;
625 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
626 (VBROADCASTSDZrr VR128X:$src)>;
628 // Provide fallback in case the load node that is used in the patterns above
629 // is used by additional users, which prevents the pattern selection.
630 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
631 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
632 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
633 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
636 let Predicates = [HasAVX512] in {
637 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
639 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
640 addr:$src)), sub_ymm)>;
642 //===----------------------------------------------------------------------===//
643 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
646 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
647 RegisterClass DstRC, RegisterClass KRC,
648 ValueType OpVT, ValueType SrcVT> {
649 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
650 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
654 let Predicates = [HasCDI] in {
655 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
656 VK16, v16i32, v16i1>, EVEX_V512;
657 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
658 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
661 //===----------------------------------------------------------------------===//
664 // -- immediate form --
665 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
666 SDNode OpNode, PatFrag mem_frag,
667 X86MemOperand x86memop, ValueType OpVT> {
668 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
669 (ins RC:$src1, i8imm:$src2),
670 !strconcat(OpcodeStr,
671 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
673 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
675 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
676 (ins x86memop:$src1, i8imm:$src2),
677 !strconcat(OpcodeStr,
678 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
680 (OpVT (OpNode (mem_frag addr:$src1),
681 (i8 imm:$src2))))]>, EVEX;
684 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
685 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
686 let ExeDomain = SSEPackedDouble in
687 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
688 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
690 // -- VPERM - register form --
691 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
692 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
694 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
695 (ins RC:$src1, RC:$src2),
696 !strconcat(OpcodeStr,
697 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
699 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
701 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
702 (ins RC:$src1, x86memop:$src2),
703 !strconcat(OpcodeStr,
704 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
706 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
710 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
711 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
712 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
713 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
714 let ExeDomain = SSEPackedSingle in
715 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
716 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
717 let ExeDomain = SSEPackedDouble in
718 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
719 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
721 // -- VPERM2I - 3 source operands form --
722 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
723 PatFrag mem_frag, X86MemOperand x86memop,
724 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
725 let Constraints = "$src1 = $dst" in {
726 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
727 (ins RC:$src1, RC:$src2, RC:$src3),
728 !strconcat(OpcodeStr,
729 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
731 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
734 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
735 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
736 !strconcat(OpcodeStr,
737 " \t{$src3, $src2, $dst {${mask}}|"
738 "$dst {${mask}}, $src2, $src3}"),
739 [(set RC:$dst, (OpVT (vselect KRC:$mask,
740 (OpNode RC:$src1, RC:$src2,
745 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
746 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
747 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
748 !strconcat(OpcodeStr,
749 " \t{$src3, $src2, $dst {${mask}} {z} |",
750 "$dst {${mask}} {z}, $src2, $src3}"),
751 [(set RC:$dst, (OpVT (vselect KRC:$mask,
752 (OpNode RC:$src1, RC:$src2,
755 (v16i32 immAllZerosV))))))]>,
758 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
759 (ins RC:$src1, RC:$src2, x86memop:$src3),
760 !strconcat(OpcodeStr,
761 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
763 (OpVT (OpNode RC:$src1, RC:$src2,
764 (mem_frag addr:$src3))))]>, EVEX_4V;
766 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
767 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
768 !strconcat(OpcodeStr,
769 " \t{$src3, $src2, $dst {${mask}}|"
770 "$dst {${mask}}, $src2, $src3}"),
772 (OpVT (vselect KRC:$mask,
773 (OpNode RC:$src1, RC:$src2,
774 (mem_frag addr:$src3)),
778 let AddedComplexity = 10 in // Prefer over the rrkz variant
779 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
780 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
781 !strconcat(OpcodeStr,
782 " \t{$src3, $src2, $dst {${mask}} {z}|"
783 "$dst {${mask}} {z}, $src2, $src3}"),
785 (OpVT (vselect KRC:$mask,
786 (OpNode RC:$src1, RC:$src2,
787 (mem_frag addr:$src3)),
789 (v16i32 immAllZerosV))))))]>,
793 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
794 i512mem, X86VPermiv3, v16i32, VK16WM>,
795 EVEX_V512, EVEX_CD8<32, CD8VF>;
796 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
797 i512mem, X86VPermiv3, v8i64, VK8WM>,
798 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
799 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
800 i512mem, X86VPermiv3, v16f32, VK16WM>,
801 EVEX_V512, EVEX_CD8<32, CD8VF>;
802 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
803 i512mem, X86VPermiv3, v8f64, VK8WM>,
804 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
806 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
807 PatFrag mem_frag, X86MemOperand x86memop,
808 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
809 ValueType MaskVT, RegisterClass MRC> :
810 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
812 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
813 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
814 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
816 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
817 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
818 (!cast<Instruction>(NAME#rrk) VR512:$src1,
819 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
822 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
823 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
824 EVEX_V512, EVEX_CD8<32, CD8VF>;
825 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
826 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
827 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
828 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
829 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
830 EVEX_V512, EVEX_CD8<32, CD8VF>;
831 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
832 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
833 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
835 //===----------------------------------------------------------------------===//
836 // AVX-512 - BLEND using mask
838 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
839 RegisterClass KRC, RegisterClass RC,
840 X86MemOperand x86memop, PatFrag mem_frag,
841 SDNode OpNode, ValueType vt> {
842 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
843 (ins KRC:$mask, RC:$src1, RC:$src2),
844 !strconcat(OpcodeStr,
845 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
846 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
847 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
849 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
850 (ins KRC:$mask, RC:$src1, x86memop:$src2),
851 !strconcat(OpcodeStr,
852 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
853 []>, EVEX_4V, EVEX_K;
856 let ExeDomain = SSEPackedSingle in
857 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
858 VK16WM, VR512, f512mem,
859 memopv16f32, vselect, v16f32>,
860 EVEX_CD8<32, CD8VF>, EVEX_V512;
861 let ExeDomain = SSEPackedDouble in
862 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
863 VK8WM, VR512, f512mem,
864 memopv8f64, vselect, v8f64>,
865 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
867 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
868 (v16f32 VR512:$src2), (i16 GR16:$mask))),
869 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
870 VR512:$src1, VR512:$src2)>;
872 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
873 (v8f64 VR512:$src2), (i8 GR8:$mask))),
874 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
875 VR512:$src1, VR512:$src2)>;
877 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
878 VK16WM, VR512, f512mem,
879 memopv16i32, vselect, v16i32>,
880 EVEX_CD8<32, CD8VF>, EVEX_V512;
882 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
883 VK8WM, VR512, f512mem,
884 memopv8i64, vselect, v8i64>,
885 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
887 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
888 (v16i32 VR512:$src2), (i16 GR16:$mask))),
889 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
890 VR512:$src1, VR512:$src2)>;
892 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
893 (v8i64 VR512:$src2), (i8 GR8:$mask))),
894 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
895 VR512:$src1, VR512:$src2)>;
897 let Predicates = [HasAVX512] in {
898 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
899 (v8f32 VR256X:$src2))),
901 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
902 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
903 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
905 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
906 (v8i32 VR256X:$src2))),
908 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
909 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
910 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
912 //===----------------------------------------------------------------------===//
913 // Compare Instructions
914 //===----------------------------------------------------------------------===//
916 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
917 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
918 Operand CC, SDNode OpNode, ValueType VT,
919 PatFrag ld_frag, string asm, string asm_alt> {
920 def rr : AVX512Ii8<0xC2, MRMSrcReg,
921 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
922 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
923 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
924 def rm : AVX512Ii8<0xC2, MRMSrcMem,
925 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
926 [(set VK1:$dst, (OpNode (VT RC:$src1),
927 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
928 let isAsmParserOnly = 1, hasSideEffects = 0 in {
929 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
930 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
931 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
932 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
933 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
934 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
938 let Predicates = [HasAVX512] in {
939 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
940 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
941 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
943 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
944 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
945 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
949 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
951 def rr : AVX512BI<opc, MRMSrcReg,
952 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
953 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
955 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
957 def rm : AVX512BI<opc, MRMSrcMem,
958 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
959 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
960 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
961 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
962 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
963 def rrk : AVX512BI<opc, MRMSrcReg,
964 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
965 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
966 "$dst {${mask}}, $src1, $src2}"),
967 [(set _.KRC:$dst, (and _.KRCWM:$mask,
968 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
969 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
971 def rmk : AVX512BI<opc, MRMSrcMem,
972 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
974 "$dst {${mask}}, $src1, $src2}"),
975 [(set _.KRC:$dst, (and _.KRCWM:$mask,
976 (OpNode (_.VT _.RC:$src1),
978 (_.LdFrag addr:$src2))))))],
979 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
982 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
984 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
986 def rmb : AVX512BI<opc, MRMSrcMem,
987 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
988 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
989 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
990 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
991 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
992 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
993 def rmbk : AVX512BI<opc, MRMSrcMem,
994 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
995 _.ScalarMemOp:$src2),
996 !strconcat(OpcodeStr,
997 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
998 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
999 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1000 (OpNode (_.VT _.RC:$src1),
1002 (_.ScalarLdFrag addr:$src2)))))],
1003 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1007 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1008 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1009 let Predicates = [prd] in
1010 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1013 let Predicates = [prd, HasVLX] in {
1014 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1016 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1021 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1022 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1024 let Predicates = [prd] in
1025 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1028 let Predicates = [prd, HasVLX] in {
1029 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1031 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1036 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1037 avx512vl_i8_info, HasBWI>,
1040 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1041 avx512vl_i16_info, HasBWI>,
1042 EVEX_CD8<16, CD8VF>;
1044 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1045 avx512vl_i32_info, HasAVX512>,
1046 EVEX_CD8<32, CD8VF>;
1048 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1049 avx512vl_i64_info, HasAVX512>,
1050 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1052 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1053 avx512vl_i8_info, HasBWI>,
1056 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1057 avx512vl_i16_info, HasBWI>,
1058 EVEX_CD8<16, CD8VF>;
1060 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1061 avx512vl_i32_info, HasAVX512>,
1062 EVEX_CD8<32, CD8VF>;
1064 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1065 avx512vl_i64_info, HasAVX512>,
1066 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1068 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1069 (COPY_TO_REGCLASS (VPCMPGTDZrr
1070 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1071 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1073 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1074 (COPY_TO_REGCLASS (VPCMPEQDZrr
1075 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1076 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1078 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1079 X86VectorVTInfo _> {
1080 def rri : AVX512AIi8<opc, MRMSrcReg,
1081 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1082 !strconcat("vpcmp${cc}", Suffix,
1083 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1084 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1086 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1088 def rmi : AVX512AIi8<opc, MRMSrcMem,
1089 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1090 !strconcat("vpcmp${cc}", Suffix,
1091 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1092 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1093 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1095 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1096 def rrik : AVX512AIi8<opc, MRMSrcReg,
1097 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1099 !strconcat("vpcmp${cc}", Suffix,
1100 "\t{$src2, $src1, $dst {${mask}}|",
1101 "$dst {${mask}}, $src1, $src2}"),
1102 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1103 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1105 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1107 def rmik : AVX512AIi8<opc, MRMSrcMem,
1108 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1110 !strconcat("vpcmp${cc}", Suffix,
1111 "\t{$src2, $src1, $dst {${mask}}|",
1112 "$dst {${mask}}, $src1, $src2}"),
1113 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1114 (OpNode (_.VT _.RC:$src1),
1115 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1117 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1119 // Accept explicit immediate argument form instead of comparison code.
1120 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1121 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1122 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1123 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1124 "$dst, $src1, $src2, $cc}"),
1125 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1126 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1127 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1128 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1129 "$dst, $src1, $src2, $cc}"),
1130 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1131 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1132 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1134 !strconcat("vpcmp", Suffix,
1135 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1136 "$dst {${mask}}, $src1, $src2, $cc}"),
1137 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1138 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1139 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1141 !strconcat("vpcmp", Suffix,
1142 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1143 "$dst {${mask}}, $src1, $src2, $cc}"),
1144 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1148 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1149 X86VectorVTInfo _> :
1150 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1151 let mayLoad = 1 in {
1152 def rmib : AVX512AIi8<opc, MRMSrcMem,
1153 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1155 !strconcat("vpcmp${cc}", Suffix,
1156 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1157 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1158 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1159 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1161 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1162 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1163 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1164 _.ScalarMemOp:$src2, AVXCC:$cc),
1165 !strconcat("vpcmp${cc}", Suffix,
1166 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1167 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1168 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1169 (OpNode (_.VT _.RC:$src1),
1170 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1172 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1175 // Accept explicit immediate argument form instead of comparison code.
1176 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1177 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1178 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1180 !strconcat("vpcmp", Suffix,
1181 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1182 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1183 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1184 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1185 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1186 _.ScalarMemOp:$src2, i8imm:$cc),
1187 !strconcat("vpcmp", Suffix,
1188 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1189 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1190 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1194 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1195 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1196 let Predicates = [prd] in
1197 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1199 let Predicates = [prd, HasVLX] in {
1200 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1201 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1205 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1206 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1207 let Predicates = [prd] in
1208 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1211 let Predicates = [prd, HasVLX] in {
1212 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1214 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1219 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1220 HasBWI>, EVEX_CD8<8, CD8VF>;
1221 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1222 HasBWI>, EVEX_CD8<8, CD8VF>;
1224 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1225 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1226 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1227 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1229 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1230 HasAVX512>, EVEX_CD8<32, CD8VF>;
1231 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1232 HasAVX512>, EVEX_CD8<32, CD8VF>;
1234 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1235 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1236 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1237 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1239 // avx512_cmp_packed - compare packed instructions
1240 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1241 X86MemOperand x86memop, ValueType vt,
1242 string suffix, Domain d> {
1243 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1244 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1245 !strconcat("vcmp${cc}", suffix,
1246 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1247 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1248 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1249 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1250 !strconcat("vcmp${cc}", suffix,
1251 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1253 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1254 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1255 !strconcat("vcmp${cc}", suffix,
1256 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1258 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1260 // Accept explicit immediate argument form instead of comparison code.
1261 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1262 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1263 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1264 !strconcat("vcmp", suffix,
1265 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1266 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1267 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1268 !strconcat("vcmp", suffix,
1269 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1273 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1274 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1275 EVEX_CD8<32, CD8VF>;
1276 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1277 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1278 EVEX_CD8<64, CD8VF>;
1280 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1281 (COPY_TO_REGCLASS (VCMPPSZrri
1282 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1283 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1285 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1286 (COPY_TO_REGCLASS (VPCMPDZrri
1287 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1288 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1290 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1291 (COPY_TO_REGCLASS (VPCMPUDZrri
1292 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1293 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1296 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1297 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1299 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1300 (I8Imm imm:$cc)), GR16)>;
1302 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1303 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1305 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1306 (I8Imm imm:$cc)), GR8)>;
1308 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1309 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1311 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1312 (I8Imm imm:$cc)), GR16)>;
1314 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1315 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1317 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1318 (I8Imm imm:$cc)), GR8)>;
1320 // Mask register copy, including
1321 // - copy between mask registers
1322 // - load/store mask registers
1323 // - copy from GPR to mask register and vice versa
1325 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1326 string OpcodeStr, RegisterClass KRC,
1327 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1328 let hasSideEffects = 0 in {
1329 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1330 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1332 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1333 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1334 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1336 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1337 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1341 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1343 RegisterClass KRC, RegisterClass GRC> {
1344 let hasSideEffects = 0 in {
1345 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1346 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1347 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1348 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1352 let Predicates = [HasDQI] in
1353 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1355 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1358 let Predicates = [HasAVX512] in
1359 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1361 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1364 let Predicates = [HasBWI] in {
1365 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1366 i32mem>, VEX, PD, VEX_W;
1367 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1371 let Predicates = [HasBWI] in {
1372 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1373 i64mem>, VEX, PS, VEX_W;
1374 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1378 // GR from/to mask register
1379 let Predicates = [HasDQI] in {
1380 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1381 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1382 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1383 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1385 let Predicates = [HasAVX512] in {
1386 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1387 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1388 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1389 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1391 let Predicates = [HasBWI] in {
1392 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1393 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1395 let Predicates = [HasBWI] in {
1396 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1397 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1401 let Predicates = [HasDQI] in {
1402 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1403 (KMOVBmk addr:$dst, VK8:$src)>;
1405 let Predicates = [HasAVX512] in {
1406 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1407 (KMOVWmk addr:$dst, VK16:$src)>;
1408 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1409 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1410 def : Pat<(i1 (load addr:$src)),
1411 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1412 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1413 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1415 let Predicates = [HasBWI] in {
1416 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1417 (KMOVDmk addr:$dst, VK32:$src)>;
1419 let Predicates = [HasBWI] in {
1420 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1421 (KMOVQmk addr:$dst, VK64:$src)>;
1424 let Predicates = [HasAVX512] in {
1425 def : Pat<(i1 (trunc (i64 GR64:$src))),
1426 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1429 def : Pat<(i1 (trunc (i32 GR32:$src))),
1430 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1432 def : Pat<(i1 (trunc (i8 GR8:$src))),
1434 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1436 def : Pat<(i1 (trunc (i16 GR16:$src))),
1438 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1441 def : Pat<(i32 (zext VK1:$src)),
1442 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1443 def : Pat<(i8 (zext VK1:$src)),
1446 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1447 def : Pat<(i64 (zext VK1:$src)),
1448 (AND64ri8 (SUBREG_TO_REG (i64 0),
1449 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1450 def : Pat<(i16 (zext VK1:$src)),
1452 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1454 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1455 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1456 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1457 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1459 let Predicates = [HasBWI] in {
1460 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1461 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1462 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1463 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1467 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1468 let Predicates = [HasAVX512] in {
1469 // GR from/to 8-bit mask without native support
1470 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1472 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1474 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1476 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1479 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1480 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1481 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1482 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1484 let Predicates = [HasBWI] in {
1485 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1486 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1487 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1488 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1491 // Mask unary operation
1493 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1494 RegisterClass KRC, SDPatternOperator OpNode,
1496 let Predicates = [prd] in
1497 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1498 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1499 [(set KRC:$dst, (OpNode KRC:$src))]>;
1502 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1503 SDPatternOperator OpNode> {
1504 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1506 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1507 HasAVX512>, VEX, PS;
1508 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1509 HasBWI>, VEX, PD, VEX_W;
1510 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1511 HasBWI>, VEX, PS, VEX_W;
1514 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1516 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1517 let Predicates = [HasAVX512] in
1518 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1520 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1521 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1523 defm : avx512_mask_unop_int<"knot", "KNOT">;
1525 let Predicates = [HasDQI] in
1526 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1527 let Predicates = [HasAVX512] in
1528 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1529 let Predicates = [HasBWI] in
1530 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1531 let Predicates = [HasBWI] in
1532 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1534 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1535 let Predicates = [HasAVX512] in {
1536 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1537 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1539 def : Pat<(not VK8:$src),
1541 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1544 // Mask binary operation
1545 // - KAND, KANDN, KOR, KXNOR, KXOR
1546 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1547 RegisterClass KRC, SDPatternOperator OpNode,
1549 let Predicates = [prd] in
1550 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1551 !strconcat(OpcodeStr,
1552 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1553 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1556 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1557 SDPatternOperator OpNode> {
1558 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1559 HasDQI>, VEX_4V, VEX_L, PD;
1560 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1561 HasAVX512>, VEX_4V, VEX_L, PS;
1562 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1563 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1564 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1565 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1568 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1569 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1571 let isCommutable = 1 in {
1572 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1573 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1574 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1575 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1577 let isCommutable = 0 in
1578 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1580 def : Pat<(xor VK1:$src1, VK1:$src2),
1581 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1582 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1584 def : Pat<(or VK1:$src1, VK1:$src2),
1585 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1586 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1588 def : Pat<(and VK1:$src1, VK1:$src2),
1589 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1590 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1592 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1593 let Predicates = [HasAVX512] in
1594 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1595 (i16 GR16:$src1), (i16 GR16:$src2)),
1596 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1597 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1598 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1601 defm : avx512_mask_binop_int<"kand", "KAND">;
1602 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1603 defm : avx512_mask_binop_int<"kor", "KOR">;
1604 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1605 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1607 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1608 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1609 let Predicates = [HasAVX512] in
1610 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1612 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1613 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1616 defm : avx512_binop_pat<and, KANDWrr>;
1617 defm : avx512_binop_pat<andn, KANDNWrr>;
1618 defm : avx512_binop_pat<or, KORWrr>;
1619 defm : avx512_binop_pat<xnor, KXNORWrr>;
1620 defm : avx512_binop_pat<xor, KXORWrr>;
1623 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1624 RegisterClass KRC> {
1625 let Predicates = [HasAVX512] in
1626 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1627 !strconcat(OpcodeStr,
1628 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1631 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1632 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1636 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1637 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1638 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1639 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1642 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1643 let Predicates = [HasAVX512] in
1644 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1645 (i16 GR16:$src1), (i16 GR16:$src2)),
1646 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1647 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1648 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1650 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1653 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1655 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1656 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1657 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1658 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1661 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1662 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1666 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1668 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1669 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1670 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1673 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1675 let Predicates = [HasAVX512] in
1676 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1677 !strconcat(OpcodeStr,
1678 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1679 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1682 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1684 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1688 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1689 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1691 // Mask setting all 0s or 1s
1692 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1693 let Predicates = [HasAVX512] in
1694 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1695 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1696 [(set KRC:$dst, (VT Val))]>;
1699 multiclass avx512_mask_setop_w<PatFrag Val> {
1700 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1701 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1704 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1705 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1707 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1708 let Predicates = [HasAVX512] in {
1709 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1710 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1711 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1712 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1713 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1715 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1716 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1718 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1719 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1721 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1722 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1724 let Predicates = [HasVLX] in {
1725 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1726 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1727 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1728 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1729 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1730 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1731 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1732 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1735 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1736 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1738 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1739 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1740 //===----------------------------------------------------------------------===//
1741 // AVX-512 - Aligned and unaligned load and store
1744 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1745 RegisterClass KRC, RegisterClass RC,
1746 ValueType vt, ValueType zvt, X86MemOperand memop,
1747 Domain d, bit IsReMaterializable = 1> {
1748 let hasSideEffects = 0 in {
1749 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1752 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1753 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1754 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1756 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1757 SchedRW = [WriteLoad] in
1758 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1760 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1763 let AddedComplexity = 20 in {
1764 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1765 let hasSideEffects = 0 in
1766 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1767 (ins RC:$src0, KRC:$mask, RC:$src1),
1768 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1769 "${dst} {${mask}}, $src1}"),
1770 [(set RC:$dst, (vt (vselect KRC:$mask,
1774 let mayLoad = 1, SchedRW = [WriteLoad] in
1775 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1776 (ins RC:$src0, KRC:$mask, memop:$src1),
1777 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1778 "${dst} {${mask}}, $src1}"),
1781 (vt (bitconvert (ld_frag addr:$src1))),
1785 let mayLoad = 1, SchedRW = [WriteLoad] in
1786 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1787 (ins KRC:$mask, memop:$src),
1788 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1789 "${dst} {${mask}} {z}, $src}"),
1792 (vt (bitconvert (ld_frag addr:$src))),
1793 (vt (bitconvert (zvt immAllZerosV))))))],
1798 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1799 string elty, string elsz, string vsz512,
1800 string vsz256, string vsz128, Domain d,
1801 Predicate prd, bit IsReMaterializable = 1> {
1802 let Predicates = [prd] in
1803 defm Z : avx512_load<opc, OpcodeStr,
1804 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1805 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1806 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1807 !cast<X86MemOperand>(elty##"512mem"), d,
1808 IsReMaterializable>, EVEX_V512;
1810 let Predicates = [prd, HasVLX] in {
1811 defm Z256 : avx512_load<opc, OpcodeStr,
1812 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1813 "v"##vsz256##elty##elsz, "v4i64")),
1814 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1815 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1816 !cast<X86MemOperand>(elty##"256mem"), d,
1817 IsReMaterializable>, EVEX_V256;
1819 defm Z128 : avx512_load<opc, OpcodeStr,
1820 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1821 "v"##vsz128##elty##elsz, "v2i64")),
1822 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1823 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1824 !cast<X86MemOperand>(elty##"128mem"), d,
1825 IsReMaterializable>, EVEX_V128;
1830 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1831 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1832 X86MemOperand memop, Domain d> {
1833 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1834 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1835 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1837 let Constraints = "$src1 = $dst" in
1838 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1839 (ins RC:$src1, KRC:$mask, RC:$src2),
1840 !strconcat(OpcodeStr,
1841 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1843 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1844 (ins KRC:$mask, RC:$src),
1845 !strconcat(OpcodeStr,
1846 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1847 [], d>, EVEX, EVEX_KZ;
1849 let mayStore = 1 in {
1850 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1851 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1852 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1853 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1854 (ins memop:$dst, KRC:$mask, RC:$src),
1855 !strconcat(OpcodeStr,
1856 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1857 [], d>, EVEX, EVEX_K;
1862 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1863 string st_suff_512, string st_suff_256,
1864 string st_suff_128, string elty, string elsz,
1865 string vsz512, string vsz256, string vsz128,
1866 Domain d, Predicate prd> {
1867 let Predicates = [prd] in
1868 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1869 !cast<ValueType>("v"##vsz512##elty##elsz),
1870 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1871 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1873 let Predicates = [prd, HasVLX] in {
1874 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1875 !cast<ValueType>("v"##vsz256##elty##elsz),
1876 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1877 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1879 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1880 !cast<ValueType>("v"##vsz128##elty##elsz),
1881 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1882 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1886 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1887 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1888 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1889 "512", "256", "", "f", "32", "16", "8", "4",
1890 SSEPackedSingle, HasAVX512>,
1891 PS, EVEX_CD8<32, CD8VF>;
1893 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1894 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1895 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1896 "512", "256", "", "f", "64", "8", "4", "2",
1897 SSEPackedDouble, HasAVX512>,
1898 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1900 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1901 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1902 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1903 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1904 PS, EVEX_CD8<32, CD8VF>;
1906 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1907 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1908 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1909 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1910 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1912 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1913 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1914 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1916 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1917 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1918 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1920 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1922 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1924 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1926 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1929 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1930 "16", "8", "4", SSEPackedInt, HasAVX512>,
1931 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1932 "512", "256", "", "i", "32", "16", "8", "4",
1933 SSEPackedInt, HasAVX512>,
1934 PD, EVEX_CD8<32, CD8VF>;
1936 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1937 "8", "4", "2", SSEPackedInt, HasAVX512>,
1938 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1939 "512", "256", "", "i", "64", "8", "4", "2",
1940 SSEPackedInt, HasAVX512>,
1941 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1943 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1944 "64", "32", "16", SSEPackedInt, HasBWI>,
1945 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1946 "i", "8", "64", "32", "16", SSEPackedInt,
1947 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1949 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1950 "32", "16", "8", SSEPackedInt, HasBWI>,
1951 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1952 "i", "16", "32", "16", "8", SSEPackedInt,
1953 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1955 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1956 "16", "8", "4", SSEPackedInt, HasAVX512>,
1957 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1958 "i", "32", "16", "8", "4", SSEPackedInt,
1959 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1961 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1962 "8", "4", "2", SSEPackedInt, HasAVX512>,
1963 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1964 "i", "64", "8", "4", "2", SSEPackedInt,
1965 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1967 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1968 (v16i32 immAllZerosV), GR16:$mask)),
1969 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1971 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1972 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1973 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1975 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1977 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1979 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1981 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1984 let AddedComplexity = 20 in {
1985 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1986 (bc_v8i64 (v16i32 immAllZerosV)))),
1987 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
1989 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1990 (v8i64 VR512:$src))),
1991 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1994 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1995 (v16i32 immAllZerosV))),
1996 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
1998 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1999 (v16i32 VR512:$src))),
2000 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2003 // Move Int Doubleword to Packed Double Int
2005 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2006 "vmovd\t{$src, $dst|$dst, $src}",
2008 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2010 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2011 "vmovd\t{$src, $dst|$dst, $src}",
2013 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2014 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2015 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2016 "vmovq\t{$src, $dst|$dst, $src}",
2018 (v2i64 (scalar_to_vector GR64:$src)))],
2019 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2020 let isCodeGenOnly = 1 in {
2021 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2022 "vmovq\t{$src, $dst|$dst, $src}",
2023 [(set FR64:$dst, (bitconvert GR64:$src))],
2024 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2025 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2026 "vmovq\t{$src, $dst|$dst, $src}",
2027 [(set GR64:$dst, (bitconvert FR64:$src))],
2028 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2030 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2031 "vmovq\t{$src, $dst|$dst, $src}",
2032 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2033 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2034 EVEX_CD8<64, CD8VT1>;
2036 // Move Int Doubleword to Single Scalar
2038 let isCodeGenOnly = 1 in {
2039 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2040 "vmovd\t{$src, $dst|$dst, $src}",
2041 [(set FR32X:$dst, (bitconvert GR32:$src))],
2042 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2044 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2045 "vmovd\t{$src, $dst|$dst, $src}",
2046 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2047 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2050 // Move doubleword from xmm register to r/m32
2052 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2053 "vmovd\t{$src, $dst|$dst, $src}",
2054 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2055 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2057 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2058 (ins i32mem:$dst, VR128X:$src),
2059 "vmovd\t{$src, $dst|$dst, $src}",
2060 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2061 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2062 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2064 // Move quadword from xmm1 register to r/m64
2066 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2067 "vmovq\t{$src, $dst|$dst, $src}",
2068 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2070 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2071 Requires<[HasAVX512, In64BitMode]>;
2073 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2074 (ins i64mem:$dst, VR128X:$src),
2075 "vmovq\t{$src, $dst|$dst, $src}",
2076 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2077 addr:$dst)], IIC_SSE_MOVDQ>,
2078 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2079 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2081 // Move Scalar Single to Double Int
2083 let isCodeGenOnly = 1 in {
2084 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2086 "vmovd\t{$src, $dst|$dst, $src}",
2087 [(set GR32:$dst, (bitconvert FR32X:$src))],
2088 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2089 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2090 (ins i32mem:$dst, FR32X:$src),
2091 "vmovd\t{$src, $dst|$dst, $src}",
2092 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2093 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2096 // Move Quadword Int to Packed Quadword Int
2098 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2100 "vmovq\t{$src, $dst|$dst, $src}",
2102 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2103 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2105 //===----------------------------------------------------------------------===//
2106 // AVX-512 MOVSS, MOVSD
2107 //===----------------------------------------------------------------------===//
2109 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2110 SDNode OpNode, ValueType vt,
2111 X86MemOperand x86memop, PatFrag mem_pat> {
2112 let hasSideEffects = 0 in {
2113 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2114 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2115 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2116 (scalar_to_vector RC:$src2))))],
2117 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2118 let Constraints = "$src1 = $dst" in
2119 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2120 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2122 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2123 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2124 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2125 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2126 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2128 let mayStore = 1 in {
2129 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2130 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2131 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2133 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2134 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2135 [], IIC_SSE_MOV_S_MR>,
2136 EVEX, VEX_LIG, EVEX_K;
2138 } //hasSideEffects = 0
2141 let ExeDomain = SSEPackedSingle in
2142 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2143 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2145 let ExeDomain = SSEPackedDouble in
2146 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2147 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2149 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2150 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2151 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2153 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2154 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2155 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2157 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2158 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2159 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2161 // For the disassembler
2162 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2163 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2164 (ins VR128X:$src1, FR32X:$src2),
2165 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2167 XS, EVEX_4V, VEX_LIG;
2168 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2169 (ins VR128X:$src1, FR64X:$src2),
2170 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2172 XD, EVEX_4V, VEX_LIG, VEX_W;
2175 let Predicates = [HasAVX512] in {
2176 let AddedComplexity = 15 in {
2177 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2178 // MOVS{S,D} to the lower bits.
2179 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2180 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2181 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2182 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2183 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2184 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2185 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2186 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2188 // Move low f32 and clear high bits.
2189 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2190 (SUBREG_TO_REG (i32 0),
2191 (VMOVSSZrr (v4f32 (V_SET0)),
2192 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2193 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2194 (SUBREG_TO_REG (i32 0),
2195 (VMOVSSZrr (v4i32 (V_SET0)),
2196 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2199 let AddedComplexity = 20 in {
2200 // MOVSSrm zeros the high parts of the register; represent this
2201 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2202 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2203 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2204 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2205 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2206 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2207 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2209 // MOVSDrm zeros the high parts of the register; represent this
2210 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2211 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2212 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2213 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2214 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2215 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2216 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2217 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2218 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2219 def : Pat<(v2f64 (X86vzload addr:$src)),
2220 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2222 // Represent the same patterns above but in the form they appear for
2224 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2225 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2226 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2227 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2228 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2229 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2230 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2231 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2232 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2234 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2235 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2236 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2237 FR32X:$src)), sub_xmm)>;
2238 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2239 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2240 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2241 FR64X:$src)), sub_xmm)>;
2242 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2243 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2244 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2246 // Move low f64 and clear high bits.
2247 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2248 (SUBREG_TO_REG (i32 0),
2249 (VMOVSDZrr (v2f64 (V_SET0)),
2250 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2252 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2253 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2254 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2256 // Extract and store.
2257 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2259 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2260 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2262 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2264 // Shuffle with VMOVSS
2265 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2266 (VMOVSSZrr (v4i32 VR128X:$src1),
2267 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2268 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2269 (VMOVSSZrr (v4f32 VR128X:$src1),
2270 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2273 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2274 (SUBREG_TO_REG (i32 0),
2275 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2276 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2278 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2279 (SUBREG_TO_REG (i32 0),
2280 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2281 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2284 // Shuffle with VMOVSD
2285 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2286 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2287 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2288 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2289 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2290 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2291 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2292 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2295 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2296 (SUBREG_TO_REG (i32 0),
2297 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2298 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2300 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2301 (SUBREG_TO_REG (i32 0),
2302 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2303 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2306 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2307 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2308 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2309 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2310 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2311 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2312 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2313 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2316 let AddedComplexity = 15 in
2317 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2319 "vmovq\t{$src, $dst|$dst, $src}",
2320 [(set VR128X:$dst, (v2i64 (X86vzmovl
2321 (v2i64 VR128X:$src))))],
2322 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2324 let AddedComplexity = 20 in
2325 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2327 "vmovq\t{$src, $dst|$dst, $src}",
2328 [(set VR128X:$dst, (v2i64 (X86vzmovl
2329 (loadv2i64 addr:$src))))],
2330 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2331 EVEX_CD8<8, CD8VT8>;
2333 let Predicates = [HasAVX512] in {
2334 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2335 let AddedComplexity = 20 in {
2336 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2337 (VMOVDI2PDIZrm addr:$src)>;
2338 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2339 (VMOV64toPQIZrr GR64:$src)>;
2340 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2341 (VMOVDI2PDIZrr GR32:$src)>;
2343 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2344 (VMOVDI2PDIZrm addr:$src)>;
2345 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2346 (VMOVDI2PDIZrm addr:$src)>;
2347 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2348 (VMOVZPQILo2PQIZrm addr:$src)>;
2349 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2350 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2351 def : Pat<(v2i64 (X86vzload addr:$src)),
2352 (VMOVZPQILo2PQIZrm addr:$src)>;
2355 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2356 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2357 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2358 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2359 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2360 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2361 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2364 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2365 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2367 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2368 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2370 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2371 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2373 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2374 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2376 //===----------------------------------------------------------------------===//
2377 // AVX-512 - Non-temporals
2378 //===----------------------------------------------------------------------===//
2379 let SchedRW = [WriteLoad] in {
2380 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2381 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2382 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2383 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2384 EVEX_CD8<64, CD8VF>;
2386 let Predicates = [HasAVX512, HasVLX] in {
2387 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2389 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2390 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2391 EVEX_CD8<64, CD8VF>;
2393 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2395 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2396 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2397 EVEX_CD8<64, CD8VF>;
2401 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2402 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2403 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2404 let SchedRW = [WriteStore], mayStore = 1,
2405 AddedComplexity = 400 in
2406 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2407 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2408 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2411 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2412 string elty, string elsz, string vsz512,
2413 string vsz256, string vsz128, Domain d,
2414 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2415 let Predicates = [prd] in
2416 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2417 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2418 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2421 let Predicates = [prd, HasVLX] in {
2422 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2423 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2424 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2427 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2428 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2429 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2434 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2435 "i", "64", "8", "4", "2", SSEPackedInt,
2436 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2438 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2439 "f", "64", "8", "4", "2", SSEPackedDouble,
2440 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2442 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2443 "f", "32", "16", "8", "4", SSEPackedSingle,
2444 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2446 //===----------------------------------------------------------------------===//
2447 // AVX-512 - Integer arithmetic
2449 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2450 ValueType OpVT, RegisterClass KRC,
2451 RegisterClass RC, PatFrag memop_frag,
2452 X86MemOperand x86memop, PatFrag scalar_mfrag,
2453 X86MemOperand x86scalar_mop, string BrdcstStr,
2454 OpndItins itins, bit IsCommutable = 0> {
2455 let isCommutable = IsCommutable in
2456 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2457 (ins RC:$src1, RC:$src2),
2458 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2459 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2461 let AddedComplexity = 30 in {
2462 let Constraints = "$src0 = $dst" in
2463 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2464 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2465 !strconcat(OpcodeStr,
2466 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2467 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2468 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2470 itins.rr>, EVEX_4V, EVEX_K;
2471 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2472 (ins KRC:$mask, RC:$src1, RC:$src2),
2473 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2474 "|$dst {${mask}} {z}, $src1, $src2}"),
2475 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2476 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2477 (OpVT immAllZerosV))))],
2478 itins.rr>, EVEX_4V, EVEX_KZ;
2481 let mayLoad = 1 in {
2482 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2483 (ins RC:$src1, x86memop:$src2),
2484 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2485 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2487 let AddedComplexity = 30 in {
2488 let Constraints = "$src0 = $dst" in
2489 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2490 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2491 !strconcat(OpcodeStr,
2492 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2493 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2494 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2496 itins.rm>, EVEX_4V, EVEX_K;
2497 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2498 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2499 !strconcat(OpcodeStr,
2500 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2501 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2502 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2503 (OpVT immAllZerosV))))],
2504 itins.rm>, EVEX_4V, EVEX_KZ;
2506 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2507 (ins RC:$src1, x86scalar_mop:$src2),
2508 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2509 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2510 [(set RC:$dst, (OpNode RC:$src1,
2511 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2512 itins.rm>, EVEX_4V, EVEX_B;
2513 let AddedComplexity = 30 in {
2514 let Constraints = "$src0 = $dst" in
2515 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2516 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2517 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2518 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2520 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2521 (OpNode (OpVT RC:$src1),
2522 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2524 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2525 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2526 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2527 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2528 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2530 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2531 (OpNode (OpVT RC:$src1),
2532 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2533 (OpVT immAllZerosV))))],
2534 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2539 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2540 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2541 PatFrag memop_frag, X86MemOperand x86memop,
2542 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2543 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2544 let isCommutable = IsCommutable in
2546 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2547 (ins RC:$src1, RC:$src2),
2548 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2550 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2551 (ins KRC:$mask, RC:$src1, RC:$src2),
2552 !strconcat(OpcodeStr,
2553 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2554 [], itins.rr>, EVEX_4V, EVEX_K;
2555 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2556 (ins KRC:$mask, RC:$src1, RC:$src2),
2557 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2558 "|$dst {${mask}} {z}, $src1, $src2}"),
2559 [], itins.rr>, EVEX_4V, EVEX_KZ;
2561 let mayLoad = 1 in {
2562 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2563 (ins RC:$src1, x86memop:$src2),
2564 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2566 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2567 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2568 !strconcat(OpcodeStr,
2569 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2570 [], itins.rm>, EVEX_4V, EVEX_K;
2571 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2572 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2573 !strconcat(OpcodeStr,
2574 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2575 [], itins.rm>, EVEX_4V, EVEX_KZ;
2576 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2577 (ins RC:$src1, x86scalar_mop:$src2),
2578 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2579 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2580 [], itins.rm>, EVEX_4V, EVEX_B;
2581 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2582 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2583 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2584 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2586 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2587 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2588 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2589 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2590 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2592 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2596 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2597 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2598 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2600 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2601 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2602 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2604 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2605 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2606 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2608 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2609 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2610 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2612 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2613 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2614 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2616 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2617 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2618 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2619 EVEX_CD8<64, CD8VF>, VEX_W;
2621 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2622 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2623 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2625 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2626 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2628 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2629 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2630 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2631 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2632 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2633 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2635 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2636 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2637 SSE_INTALU_ITINS_P, 1>,
2638 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2639 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2640 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2641 SSE_INTALU_ITINS_P, 0>,
2642 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2644 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2645 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2646 SSE_INTALU_ITINS_P, 1>,
2647 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2648 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2649 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2650 SSE_INTALU_ITINS_P, 0>,
2651 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2653 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2654 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2655 SSE_INTALU_ITINS_P, 1>,
2656 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2657 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2658 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2659 SSE_INTALU_ITINS_P, 0>,
2660 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2662 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2663 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2664 SSE_INTALU_ITINS_P, 1>,
2665 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2666 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2667 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2668 SSE_INTALU_ITINS_P, 0>,
2669 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2671 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2672 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2673 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2674 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2675 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2676 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2677 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2678 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2679 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2680 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2681 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2682 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2683 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2684 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2685 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2686 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2687 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2688 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2689 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2690 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2691 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2692 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2693 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2694 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2695 //===----------------------------------------------------------------------===//
2696 // AVX-512 - Unpack Instructions
2697 //===----------------------------------------------------------------------===//
2699 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2700 PatFrag mem_frag, RegisterClass RC,
2701 X86MemOperand x86memop, string asm,
2703 def rr : AVX512PI<opc, MRMSrcReg,
2704 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2706 (vt (OpNode RC:$src1, RC:$src2)))],
2708 def rm : AVX512PI<opc, MRMSrcMem,
2709 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2711 (vt (OpNode RC:$src1,
2712 (bitconvert (mem_frag addr:$src2)))))],
2716 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2717 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2718 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2719 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2720 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2721 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2722 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2723 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2724 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2725 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2726 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2727 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2729 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2730 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2731 X86MemOperand x86memop> {
2732 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2733 (ins RC:$src1, RC:$src2),
2734 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2735 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2736 IIC_SSE_UNPCK>, EVEX_4V;
2737 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2738 (ins RC:$src1, x86memop:$src2),
2739 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2740 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2741 (bitconvert (memop_frag addr:$src2)))))],
2742 IIC_SSE_UNPCK>, EVEX_4V;
2744 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2745 VR512, memopv16i32, i512mem>, EVEX_V512,
2746 EVEX_CD8<32, CD8VF>;
2747 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2748 VR512, memopv8i64, i512mem>, EVEX_V512,
2749 VEX_W, EVEX_CD8<64, CD8VF>;
2750 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2751 VR512, memopv16i32, i512mem>, EVEX_V512,
2752 EVEX_CD8<32, CD8VF>;
2753 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2754 VR512, memopv8i64, i512mem>, EVEX_V512,
2755 VEX_W, EVEX_CD8<64, CD8VF>;
2756 //===----------------------------------------------------------------------===//
2760 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2761 SDNode OpNode, PatFrag mem_frag,
2762 X86MemOperand x86memop, ValueType OpVT> {
2763 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2764 (ins RC:$src1, i8imm:$src2),
2765 !strconcat(OpcodeStr,
2766 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2768 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2770 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2771 (ins x86memop:$src1, i8imm:$src2),
2772 !strconcat(OpcodeStr,
2773 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2775 (OpVT (OpNode (mem_frag addr:$src1),
2776 (i8 imm:$src2))))]>, EVEX;
2779 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2780 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2782 let ExeDomain = SSEPackedSingle in
2783 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
2784 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2785 EVEX_CD8<32, CD8VF>;
2786 let ExeDomain = SSEPackedDouble in
2787 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
2788 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2789 VEX_W, EVEX_CD8<32, CD8VF>;
2791 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2792 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2793 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2794 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2796 //===----------------------------------------------------------------------===//
2797 // AVX-512 Logical Instructions
2798 //===----------------------------------------------------------------------===//
2800 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2801 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2802 EVEX_V512, EVEX_CD8<32, CD8VF>;
2803 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2804 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2805 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2806 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2807 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2808 EVEX_V512, EVEX_CD8<32, CD8VF>;
2809 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2810 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2811 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2812 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2813 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2814 EVEX_V512, EVEX_CD8<32, CD8VF>;
2815 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2816 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2817 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2818 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2819 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2820 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2821 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2822 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2823 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2825 //===----------------------------------------------------------------------===//
2826 // AVX-512 FP arithmetic
2827 //===----------------------------------------------------------------------===//
2829 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2831 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2832 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2833 EVEX_CD8<32, CD8VT1>;
2834 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2835 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2836 EVEX_CD8<64, CD8VT1>;
2839 let isCommutable = 1 in {
2840 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2841 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2842 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2843 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2845 let isCommutable = 0 in {
2846 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2847 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2850 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2852 RegisterClass RC, ValueType vt,
2853 X86MemOperand x86memop, PatFrag mem_frag,
2854 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2856 Domain d, OpndItins itins, bit commutable> {
2857 let isCommutable = commutable in {
2858 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2859 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2860 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2863 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2864 !strconcat(OpcodeStr,
2865 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2866 [], itins.rr, d>, EVEX_4V, EVEX_K;
2868 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2869 !strconcat(OpcodeStr,
2870 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2871 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2874 let mayLoad = 1 in {
2875 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2876 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2877 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2878 itins.rm, d>, EVEX_4V;
2880 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2881 (ins RC:$src1, x86scalar_mop:$src2),
2882 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2883 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2884 [(set RC:$dst, (OpNode RC:$src1,
2885 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2886 itins.rm, d>, EVEX_4V, EVEX_B;
2888 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2889 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2890 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2891 [], itins.rm, d>, EVEX_4V, EVEX_K;
2893 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2894 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2895 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2896 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2898 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2899 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2900 " \t{${src2}", BrdcstStr,
2901 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2902 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2904 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2905 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2906 " \t{${src2}", BrdcstStr,
2907 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2909 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2913 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2914 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2915 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2917 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2918 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2919 SSE_ALU_ITINS_P.d, 1>,
2920 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2922 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2923 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2924 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2925 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2926 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2927 SSE_ALU_ITINS_P.d, 1>,
2928 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2930 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2931 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2932 SSE_ALU_ITINS_P.s, 1>,
2933 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2934 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2935 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2936 SSE_ALU_ITINS_P.s, 1>,
2937 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2939 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2940 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2941 SSE_ALU_ITINS_P.d, 1>,
2942 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2943 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2944 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2945 SSE_ALU_ITINS_P.d, 1>,
2946 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2948 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2949 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2950 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2951 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2952 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2953 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2955 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2956 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2957 SSE_ALU_ITINS_P.d, 0>,
2958 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2959 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2960 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2961 SSE_ALU_ITINS_P.d, 0>,
2962 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2964 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2965 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2966 (i16 -1), FROUND_CURRENT)),
2967 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2969 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2970 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2971 (i8 -1), FROUND_CURRENT)),
2972 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2974 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2975 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2976 (i16 -1), FROUND_CURRENT)),
2977 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2979 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2980 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2981 (i8 -1), FROUND_CURRENT)),
2982 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2983 //===----------------------------------------------------------------------===//
2984 // AVX-512 VPTESTM instructions
2985 //===----------------------------------------------------------------------===//
2987 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2988 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2989 SDNode OpNode, ValueType vt> {
2990 def rr : AVX512PI<opc, MRMSrcReg,
2991 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2992 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2993 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2994 SSEPackedInt>, EVEX_4V;
2995 def rm : AVX512PI<opc, MRMSrcMem,
2996 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2997 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2998 [(set KRC:$dst, (OpNode (vt RC:$src1),
2999 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3002 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3003 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3004 EVEX_CD8<32, CD8VF>;
3005 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3006 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3007 EVEX_CD8<64, CD8VF>;
3009 let Predicates = [HasCDI] in {
3010 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3011 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3012 EVEX_CD8<32, CD8VF>;
3013 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3014 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3015 EVEX_CD8<64, CD8VF>;
3018 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3019 (v16i32 VR512:$src2), (i16 -1))),
3020 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3022 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3023 (v8i64 VR512:$src2), (i8 -1))),
3024 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3025 //===----------------------------------------------------------------------===//
3026 // AVX-512 Shift instructions
3027 //===----------------------------------------------------------------------===//
3028 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3029 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3030 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3031 RegisterClass KRC> {
3032 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3033 (ins RC:$src1, i8imm:$src2),
3034 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3035 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
3036 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3037 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3038 (ins KRC:$mask, RC:$src1, i8imm:$src2),
3039 !strconcat(OpcodeStr,
3040 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3041 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3042 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3043 (ins x86memop:$src1, i8imm:$src2),
3044 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3045 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
3046 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3047 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3048 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
3049 !strconcat(OpcodeStr,
3050 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3051 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3054 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3055 RegisterClass RC, ValueType vt, ValueType SrcVT,
3056 PatFrag bc_frag, RegisterClass KRC> {
3057 // src2 is always 128-bit
3058 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3059 (ins RC:$src1, VR128X:$src2),
3060 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3061 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3062 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3063 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3064 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3065 !strconcat(OpcodeStr,
3066 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3067 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3068 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3069 (ins RC:$src1, i128mem:$src2),
3070 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3071 [(set RC:$dst, (vt (OpNode RC:$src1,
3072 (bc_frag (memopv2i64 addr:$src2)))))],
3073 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3074 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3075 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3076 !strconcat(OpcodeStr,
3077 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3078 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3081 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3082 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3083 EVEX_V512, EVEX_CD8<32, CD8VF>;
3084 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3085 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3086 EVEX_CD8<32, CD8VQ>;
3088 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3089 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3090 EVEX_CD8<64, CD8VF>, VEX_W;
3091 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3092 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3093 EVEX_CD8<64, CD8VQ>, VEX_W;
3095 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3096 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3097 EVEX_CD8<32, CD8VF>;
3098 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3099 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3100 EVEX_CD8<32, CD8VQ>;
3102 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3103 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3104 EVEX_CD8<64, CD8VF>, VEX_W;
3105 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3106 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3107 EVEX_CD8<64, CD8VQ>, VEX_W;
3109 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3110 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3111 EVEX_V512, EVEX_CD8<32, CD8VF>;
3112 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3113 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3114 EVEX_CD8<32, CD8VQ>;
3116 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3117 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3118 EVEX_CD8<64, CD8VF>, VEX_W;
3119 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3120 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3121 EVEX_CD8<64, CD8VQ>, VEX_W;
3123 //===-------------------------------------------------------------------===//
3124 // Variable Bit Shifts
3125 //===-------------------------------------------------------------------===//
3126 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3127 RegisterClass RC, ValueType vt,
3128 X86MemOperand x86memop, PatFrag mem_frag> {
3129 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3130 (ins RC:$src1, RC:$src2),
3131 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3133 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3135 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3136 (ins RC:$src1, x86memop:$src2),
3137 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3139 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3143 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3144 i512mem, memopv16i32>, EVEX_V512,
3145 EVEX_CD8<32, CD8VF>;
3146 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3147 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3148 EVEX_CD8<64, CD8VF>;
3149 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3150 i512mem, memopv16i32>, EVEX_V512,
3151 EVEX_CD8<32, CD8VF>;
3152 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3153 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3154 EVEX_CD8<64, CD8VF>;
3155 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3156 i512mem, memopv16i32>, EVEX_V512,
3157 EVEX_CD8<32, CD8VF>;
3158 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3159 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3160 EVEX_CD8<64, CD8VF>;
3162 //===----------------------------------------------------------------------===//
3163 // AVX-512 - MOVDDUP
3164 //===----------------------------------------------------------------------===//
3166 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3167 X86MemOperand x86memop, PatFrag memop_frag> {
3168 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3169 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3170 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3171 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3172 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3174 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3177 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3178 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3179 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3180 (VMOVDDUPZrm addr:$src)>;
3182 //===---------------------------------------------------------------------===//
3183 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3184 //===---------------------------------------------------------------------===//
3185 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3186 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3187 X86MemOperand x86memop> {
3188 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3189 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3190 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3192 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3193 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3194 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3197 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3198 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3199 EVEX_CD8<32, CD8VF>;
3200 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3201 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3202 EVEX_CD8<32, CD8VF>;
3204 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3205 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3206 (VMOVSHDUPZrm addr:$src)>;
3207 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3208 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3209 (VMOVSLDUPZrm addr:$src)>;
3211 //===----------------------------------------------------------------------===//
3212 // Move Low to High and High to Low packed FP Instructions
3213 //===----------------------------------------------------------------------===//
3214 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3215 (ins VR128X:$src1, VR128X:$src2),
3216 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3217 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3218 IIC_SSE_MOV_LH>, EVEX_4V;
3219 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3220 (ins VR128X:$src1, VR128X:$src2),
3221 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3222 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3223 IIC_SSE_MOV_LH>, EVEX_4V;
3225 let Predicates = [HasAVX512] in {
3227 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3228 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3229 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3230 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3233 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3234 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3237 //===----------------------------------------------------------------------===//
3238 // FMA - Fused Multiply Operations
3240 let Constraints = "$src1 = $dst" in {
3241 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3242 X86VectorVTInfo _> {
3243 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3244 (ins _.RC:$src2, _.RC:$src3),
3245 OpcodeStr, "$src3, $src2", "$src2, $src3",
3246 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3250 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3251 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3252 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3253 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3254 (_.MemOpFrag addr:$src3))))]>;
3255 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3256 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3257 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3258 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3259 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3260 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3262 } // Constraints = "$src1 = $dst"
3264 let ExeDomain = SSEPackedSingle in {
3265 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3267 EVEX_V512, EVEX_CD8<32, CD8VF>;
3268 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3270 EVEX_V512, EVEX_CD8<32, CD8VF>;
3271 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3273 EVEX_V512, EVEX_CD8<32, CD8VF>;
3274 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3276 EVEX_V512, EVEX_CD8<32, CD8VF>;
3277 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3279 EVEX_V512, EVEX_CD8<32, CD8VF>;
3280 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3282 EVEX_V512, EVEX_CD8<32, CD8VF>;
3284 let ExeDomain = SSEPackedDouble in {
3285 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3287 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3288 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3290 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3291 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3293 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3294 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3296 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3297 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3299 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3300 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3302 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3305 let Constraints = "$src1 = $dst" in {
3306 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3307 X86VectorVTInfo _> {
3309 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3310 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3311 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3312 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3314 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3315 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3316 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3317 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3319 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3320 (_.ScalarLdFrag addr:$src2))),
3321 _.RC:$src3))]>, EVEX_B;
3323 } // Constraints = "$src1 = $dst"
3326 let ExeDomain = SSEPackedSingle in {
3327 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3329 EVEX_V512, EVEX_CD8<32, CD8VF>;
3330 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3332 EVEX_V512, EVEX_CD8<32, CD8VF>;
3333 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3335 EVEX_V512, EVEX_CD8<32, CD8VF>;
3336 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3338 EVEX_V512, EVEX_CD8<32, CD8VF>;
3339 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3341 EVEX_V512, EVEX_CD8<32, CD8VF>;
3342 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3344 EVEX_V512, EVEX_CD8<32, CD8VF>;
3346 let ExeDomain = SSEPackedDouble in {
3347 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3349 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3350 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3352 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3353 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3355 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3356 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3358 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3359 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3361 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3362 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3364 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3368 let Constraints = "$src1 = $dst" in {
3369 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3370 RegisterClass RC, ValueType OpVT,
3371 X86MemOperand x86memop, Operand memop,
3373 let isCommutable = 1 in
3374 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3375 (ins RC:$src1, RC:$src2, RC:$src3),
3376 !strconcat(OpcodeStr,
3377 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3379 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3381 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3382 (ins RC:$src1, RC:$src2, f128mem:$src3),
3383 !strconcat(OpcodeStr,
3384 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3386 (OpVT (OpNode RC:$src2, RC:$src1,
3387 (mem_frag addr:$src3))))]>;
3390 } // Constraints = "$src1 = $dst"
3392 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3393 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3394 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3395 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3396 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3397 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3398 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3399 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3400 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3401 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3402 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3403 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3404 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3405 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3406 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3407 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3409 //===----------------------------------------------------------------------===//
3410 // AVX-512 Scalar convert from sign integer to float/double
3411 //===----------------------------------------------------------------------===//
3413 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3414 X86MemOperand x86memop, string asm> {
3415 let hasSideEffects = 0 in {
3416 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3417 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3420 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3421 (ins DstRC:$src1, x86memop:$src),
3422 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3424 } // hasSideEffects = 0
3426 let Predicates = [HasAVX512] in {
3427 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3428 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3429 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3430 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3431 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3432 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3433 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3434 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3436 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3437 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3438 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3439 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3440 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3441 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3442 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3443 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3445 def : Pat<(f32 (sint_to_fp GR32:$src)),
3446 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3447 def : Pat<(f32 (sint_to_fp GR64:$src)),
3448 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3449 def : Pat<(f64 (sint_to_fp GR32:$src)),
3450 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3451 def : Pat<(f64 (sint_to_fp GR64:$src)),
3452 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3454 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3455 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3456 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3457 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3458 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3459 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3460 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3461 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3463 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3464 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3465 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3466 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3467 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3468 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3469 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3470 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3472 def : Pat<(f32 (uint_to_fp GR32:$src)),
3473 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3474 def : Pat<(f32 (uint_to_fp GR64:$src)),
3475 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3476 def : Pat<(f64 (uint_to_fp GR32:$src)),
3477 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3478 def : Pat<(f64 (uint_to_fp GR64:$src)),
3479 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3482 //===----------------------------------------------------------------------===//
3483 // AVX-512 Scalar convert from float/double to integer
3484 //===----------------------------------------------------------------------===//
3485 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3486 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3488 let hasSideEffects = 0 in {
3489 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3490 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3491 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3492 Requires<[HasAVX512]>;
3494 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3495 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3496 Requires<[HasAVX512]>;
3497 } // hasSideEffects = 0
3499 let Predicates = [HasAVX512] in {
3500 // Convert float/double to signed/unsigned int 32/64
3501 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3502 ssmem, sse_load_f32, "cvtss2si">,
3503 XS, EVEX_CD8<32, CD8VT1>;
3504 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3505 ssmem, sse_load_f32, "cvtss2si">,
3506 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3507 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3508 ssmem, sse_load_f32, "cvtss2usi">,
3509 XS, EVEX_CD8<32, CD8VT1>;
3510 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3511 int_x86_avx512_cvtss2usi64, ssmem,
3512 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3513 EVEX_CD8<32, CD8VT1>;
3514 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3515 sdmem, sse_load_f64, "cvtsd2si">,
3516 XD, EVEX_CD8<64, CD8VT1>;
3517 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3518 sdmem, sse_load_f64, "cvtsd2si">,
3519 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3520 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3521 sdmem, sse_load_f64, "cvtsd2usi">,
3522 XD, EVEX_CD8<64, CD8VT1>;
3523 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3524 int_x86_avx512_cvtsd2usi64, sdmem,
3525 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3526 EVEX_CD8<64, CD8VT1>;
3528 let isCodeGenOnly = 1 in {
3529 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3530 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3531 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3532 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3533 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3534 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3535 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3536 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3537 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3538 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3539 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3540 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3542 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3543 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3544 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3545 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3546 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3547 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3548 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3549 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3550 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3551 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3552 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3553 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3554 } // isCodeGenOnly = 1
3556 // Convert float/double to signed/unsigned int 32/64 with truncation
3557 let isCodeGenOnly = 1 in {
3558 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3559 ssmem, sse_load_f32, "cvttss2si">,
3560 XS, EVEX_CD8<32, CD8VT1>;
3561 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3562 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3563 "cvttss2si">, XS, VEX_W,
3564 EVEX_CD8<32, CD8VT1>;
3565 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3566 sdmem, sse_load_f64, "cvttsd2si">, XD,
3567 EVEX_CD8<64, CD8VT1>;
3568 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3569 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3570 "cvttsd2si">, XD, VEX_W,
3571 EVEX_CD8<64, CD8VT1>;
3572 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3573 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3574 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3575 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3576 int_x86_avx512_cvttss2usi64, ssmem,
3577 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3578 EVEX_CD8<32, CD8VT1>;
3579 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3580 int_x86_avx512_cvttsd2usi,
3581 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3582 EVEX_CD8<64, CD8VT1>;
3583 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3584 int_x86_avx512_cvttsd2usi64, sdmem,
3585 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3586 EVEX_CD8<64, CD8VT1>;
3587 } // isCodeGenOnly = 1
3589 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3590 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3593 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3594 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3595 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3596 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3597 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3600 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3601 loadf32, "cvttss2si">, XS,
3602 EVEX_CD8<32, CD8VT1>;
3603 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3604 loadf32, "cvttss2usi">, XS,
3605 EVEX_CD8<32, CD8VT1>;
3606 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3607 loadf32, "cvttss2si">, XS, VEX_W,
3608 EVEX_CD8<32, CD8VT1>;
3609 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3610 loadf32, "cvttss2usi">, XS, VEX_W,
3611 EVEX_CD8<32, CD8VT1>;
3612 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3613 loadf64, "cvttsd2si">, XD,
3614 EVEX_CD8<64, CD8VT1>;
3615 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3616 loadf64, "cvttsd2usi">, XD,
3617 EVEX_CD8<64, CD8VT1>;
3618 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3619 loadf64, "cvttsd2si">, XD, VEX_W,
3620 EVEX_CD8<64, CD8VT1>;
3621 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3622 loadf64, "cvttsd2usi">, XD, VEX_W,
3623 EVEX_CD8<64, CD8VT1>;
3625 //===----------------------------------------------------------------------===//
3626 // AVX-512 Convert form float to double and back
3627 //===----------------------------------------------------------------------===//
3628 let hasSideEffects = 0 in {
3629 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3630 (ins FR32X:$src1, FR32X:$src2),
3631 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3632 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3634 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3635 (ins FR32X:$src1, f32mem:$src2),
3636 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3637 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3638 EVEX_CD8<32, CD8VT1>;
3640 // Convert scalar double to scalar single
3641 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3642 (ins FR64X:$src1, FR64X:$src2),
3643 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3644 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3646 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3647 (ins FR64X:$src1, f64mem:$src2),
3648 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3649 []>, EVEX_4V, VEX_LIG, VEX_W,
3650 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3653 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3654 Requires<[HasAVX512]>;
3655 def : Pat<(fextend (loadf32 addr:$src)),
3656 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3658 def : Pat<(extloadf32 addr:$src),
3659 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3660 Requires<[HasAVX512, OptForSize]>;
3662 def : Pat<(extloadf32 addr:$src),
3663 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3664 Requires<[HasAVX512, OptForSpeed]>;
3666 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3667 Requires<[HasAVX512]>;
3669 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3670 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3671 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3673 let hasSideEffects = 0 in {
3674 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3675 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3677 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3678 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3679 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3680 [], d>, EVEX, EVEX_B, EVEX_RC;
3682 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3683 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3685 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3686 } // hasSideEffects = 0
3689 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3690 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3691 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3693 let hasSideEffects = 0 in {
3694 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3695 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3697 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3699 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3700 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3702 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3703 } // hasSideEffects = 0
3706 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3707 memopv8f64, f512mem, v8f32, v8f64,
3708 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3709 EVEX_CD8<64, CD8VF>;
3711 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3712 memopv4f64, f256mem, v8f64, v8f32,
3713 SSEPackedDouble>, EVEX_V512, PS,
3714 EVEX_CD8<32, CD8VH>;
3715 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3716 (VCVTPS2PDZrm addr:$src)>;
3718 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3719 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3720 (VCVTPD2PSZrr VR512:$src)>;
3722 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3723 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3724 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3726 //===----------------------------------------------------------------------===//
3727 // AVX-512 Vector convert from sign integer to float/double
3728 //===----------------------------------------------------------------------===//
3730 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3731 memopv8i64, i512mem, v16f32, v16i32,
3732 SSEPackedSingle>, EVEX_V512, PS,
3733 EVEX_CD8<32, CD8VF>;
3735 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3736 memopv4i64, i256mem, v8f64, v8i32,
3737 SSEPackedDouble>, EVEX_V512, XS,
3738 EVEX_CD8<32, CD8VH>;
3740 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3741 memopv16f32, f512mem, v16i32, v16f32,
3742 SSEPackedSingle>, EVEX_V512, XS,
3743 EVEX_CD8<32, CD8VF>;
3745 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3746 memopv8f64, f512mem, v8i32, v8f64,
3747 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3748 EVEX_CD8<64, CD8VF>;
3750 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3751 memopv16f32, f512mem, v16i32, v16f32,
3752 SSEPackedSingle>, EVEX_V512, PS,
3753 EVEX_CD8<32, CD8VF>;
3755 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3756 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3757 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3758 (VCVTTPS2UDQZrr VR512:$src)>;
3760 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3761 memopv8f64, f512mem, v8i32, v8f64,
3762 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3763 EVEX_CD8<64, CD8VF>;
3765 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3766 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3767 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3768 (VCVTTPD2UDQZrr VR512:$src)>;
3770 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3771 memopv4i64, f256mem, v8f64, v8i32,
3772 SSEPackedDouble>, EVEX_V512, XS,
3773 EVEX_CD8<32, CD8VH>;
3775 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3776 memopv16i32, f512mem, v16f32, v16i32,
3777 SSEPackedSingle>, EVEX_V512, XD,
3778 EVEX_CD8<32, CD8VF>;
3780 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3781 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3782 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3784 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3785 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3786 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3788 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3789 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3790 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3792 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3793 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3794 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3796 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3797 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3798 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3800 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3801 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3802 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3803 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3804 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3805 (VCVTDQ2PDZrr VR256X:$src)>;
3806 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3807 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3808 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3809 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3810 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3811 (VCVTUDQ2PDZrr VR256X:$src)>;
3813 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3814 RegisterClass DstRC, PatFrag mem_frag,
3815 X86MemOperand x86memop, Domain d> {
3816 let hasSideEffects = 0 in {
3817 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3818 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3820 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3821 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3822 [], d>, EVEX, EVEX_B, EVEX_RC;
3824 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3825 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3827 } // hasSideEffects = 0
3830 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3831 memopv16f32, f512mem, SSEPackedSingle>, PD,
3832 EVEX_V512, EVEX_CD8<32, CD8VF>;
3833 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3834 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3835 EVEX_V512, EVEX_CD8<64, CD8VF>;
3837 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3838 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3839 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3841 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3842 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3843 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3845 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3846 memopv16f32, f512mem, SSEPackedSingle>,
3847 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3848 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3849 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3850 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3852 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3853 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3854 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3856 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3857 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3858 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3860 let Predicates = [HasAVX512] in {
3861 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3862 (VCVTPD2PSZrm addr:$src)>;
3863 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3864 (VCVTPS2PDZrm addr:$src)>;
3867 //===----------------------------------------------------------------------===//
3868 // Half precision conversion instructions
3869 //===----------------------------------------------------------------------===//
3870 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3871 X86MemOperand x86memop> {
3872 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3873 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3875 let hasSideEffects = 0, mayLoad = 1 in
3876 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3877 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3880 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3881 X86MemOperand x86memop> {
3882 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3883 (ins srcRC:$src1, i32i8imm:$src2),
3884 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3886 let hasSideEffects = 0, mayStore = 1 in
3887 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3888 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3889 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3892 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3893 EVEX_CD8<32, CD8VH>;
3894 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3895 EVEX_CD8<32, CD8VH>;
3897 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3898 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3899 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3901 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3902 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3903 (VCVTPH2PSZrr VR256X:$src)>;
3905 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3906 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3907 "ucomiss">, PS, EVEX, VEX_LIG,
3908 EVEX_CD8<32, CD8VT1>;
3909 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3910 "ucomisd">, PD, EVEX,
3911 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3912 let Pattern = []<dag> in {
3913 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3914 "comiss">, PS, EVEX, VEX_LIG,
3915 EVEX_CD8<32, CD8VT1>;
3916 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3917 "comisd">, PD, EVEX,
3918 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3920 let isCodeGenOnly = 1 in {
3921 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3922 load, "ucomiss">, PS, EVEX, VEX_LIG,
3923 EVEX_CD8<32, CD8VT1>;
3924 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3925 load, "ucomisd">, PD, EVEX,
3926 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3928 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3929 load, "comiss">, PS, EVEX, VEX_LIG,
3930 EVEX_CD8<32, CD8VT1>;
3931 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3932 load, "comisd">, PD, EVEX,
3933 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3937 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3938 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3939 X86MemOperand x86memop> {
3940 let hasSideEffects = 0 in {
3941 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3942 (ins RC:$src1, RC:$src2),
3943 !strconcat(OpcodeStr,
3944 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3945 let mayLoad = 1 in {
3946 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3947 (ins RC:$src1, x86memop:$src2),
3948 !strconcat(OpcodeStr,
3949 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3954 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3955 EVEX_CD8<32, CD8VT1>;
3956 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3957 VEX_W, EVEX_CD8<64, CD8VT1>;
3958 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3959 EVEX_CD8<32, CD8VT1>;
3960 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3961 VEX_W, EVEX_CD8<64, CD8VT1>;
3963 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3964 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3965 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3966 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3968 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3969 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3970 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3971 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3973 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3974 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3975 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3976 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3978 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3979 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3980 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3981 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3983 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3984 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3985 RegisterClass RC, X86MemOperand x86memop,
3986 PatFrag mem_frag, ValueType OpVt> {
3987 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3988 !strconcat(OpcodeStr,
3989 " \t{$src, $dst|$dst, $src}"),
3990 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3992 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3993 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3994 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3997 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3998 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3999 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4000 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4001 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4002 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4003 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4004 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4006 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4007 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4008 (VRSQRT14PSZr VR512:$src)>;
4009 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4010 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4011 (VRSQRT14PDZr VR512:$src)>;
4013 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4014 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4015 (VRCP14PSZr VR512:$src)>;
4016 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4017 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4018 (VRCP14PDZr VR512:$src)>;
4020 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4021 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4022 X86MemOperand x86memop> {
4023 let hasSideEffects = 0, Predicates = [HasERI] in {
4024 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4025 (ins RC:$src1, RC:$src2),
4026 !strconcat(OpcodeStr,
4027 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4028 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4029 (ins RC:$src1, RC:$src2),
4030 !strconcat(OpcodeStr,
4031 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4032 []>, EVEX_4V, EVEX_B;
4033 let mayLoad = 1 in {
4034 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4035 (ins RC:$src1, x86memop:$src2),
4036 !strconcat(OpcodeStr,
4037 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4042 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4043 EVEX_CD8<32, CD8VT1>;
4044 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4045 VEX_W, EVEX_CD8<64, CD8VT1>;
4046 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4047 EVEX_CD8<32, CD8VT1>;
4048 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4049 VEX_W, EVEX_CD8<64, CD8VT1>;
4051 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4052 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4054 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4055 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4057 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4058 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4060 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4061 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4063 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4064 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4066 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4067 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4069 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4070 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4072 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4073 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4075 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4076 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4077 RegisterClass RC, X86MemOperand x86memop> {
4078 let hasSideEffects = 0, Predicates = [HasERI] in {
4079 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4080 !strconcat(OpcodeStr,
4081 " \t{$src, $dst|$dst, $src}"),
4083 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4084 !strconcat(OpcodeStr,
4085 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4087 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4088 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4092 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4093 EVEX_V512, EVEX_CD8<32, CD8VF>;
4094 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4095 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4096 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4097 EVEX_V512, EVEX_CD8<32, CD8VF>;
4098 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4099 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4101 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4102 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4103 (VRSQRT28PSZrb VR512:$src)>;
4104 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4105 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4106 (VRSQRT28PDZrb VR512:$src)>;
4108 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4109 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4110 (VRCP28PSZrb VR512:$src)>;
4111 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4112 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4113 (VRCP28PDZrb VR512:$src)>;
4115 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4116 OpndItins itins_s, OpndItins itins_d> {
4117 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4118 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4119 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4123 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4124 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4126 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4127 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4129 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4130 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4131 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4135 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4136 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4137 [(set VR512:$dst, (OpNode
4138 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4139 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4143 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4144 Intrinsic F32Int, Intrinsic F64Int,
4145 OpndItins itins_s, OpndItins itins_d> {
4146 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4147 (ins FR32X:$src1, FR32X:$src2),
4148 !strconcat(OpcodeStr,
4149 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4150 [], itins_s.rr>, XS, EVEX_4V;
4151 let isCodeGenOnly = 1 in
4152 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4153 (ins VR128X:$src1, VR128X:$src2),
4154 !strconcat(OpcodeStr,
4155 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4157 (F32Int VR128X:$src1, VR128X:$src2))],
4158 itins_s.rr>, XS, EVEX_4V;
4159 let mayLoad = 1 in {
4160 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4161 (ins FR32X:$src1, f32mem:$src2),
4162 !strconcat(OpcodeStr,
4163 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4164 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4165 let isCodeGenOnly = 1 in
4166 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4167 (ins VR128X:$src1, ssmem:$src2),
4168 !strconcat(OpcodeStr,
4169 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4171 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4172 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4174 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4175 (ins FR64X:$src1, FR64X:$src2),
4176 !strconcat(OpcodeStr,
4177 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4179 let isCodeGenOnly = 1 in
4180 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4181 (ins VR128X:$src1, VR128X:$src2),
4182 !strconcat(OpcodeStr,
4183 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4185 (F64Int VR128X:$src1, VR128X:$src2))],
4186 itins_s.rr>, XD, EVEX_4V, VEX_W;
4187 let mayLoad = 1 in {
4188 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4189 (ins FR64X:$src1, f64mem:$src2),
4190 !strconcat(OpcodeStr,
4191 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4192 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4193 let isCodeGenOnly = 1 in
4194 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4195 (ins VR128X:$src1, sdmem:$src2),
4196 !strconcat(OpcodeStr,
4197 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4199 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4200 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4205 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4206 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4207 SSE_SQRTSS, SSE_SQRTSD>,
4208 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
4209 SSE_SQRTPS, SSE_SQRTPD>;
4211 let Predicates = [HasAVX512] in {
4212 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4213 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4214 (VSQRTPSZrr VR512:$src1)>;
4215 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4216 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4217 (VSQRTPDZrr VR512:$src1)>;
4219 def : Pat<(f32 (fsqrt FR32X:$src)),
4220 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4221 def : Pat<(f32 (fsqrt (load addr:$src))),
4222 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4223 Requires<[OptForSize]>;
4224 def : Pat<(f64 (fsqrt FR64X:$src)),
4225 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4226 def : Pat<(f64 (fsqrt (load addr:$src))),
4227 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4228 Requires<[OptForSize]>;
4230 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4231 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4232 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4233 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4234 Requires<[OptForSize]>;
4236 def : Pat<(f32 (X86frcp FR32X:$src)),
4237 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4238 def : Pat<(f32 (X86frcp (load addr:$src))),
4239 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4240 Requires<[OptForSize]>;
4242 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4243 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4244 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4246 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4247 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4249 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4250 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4251 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4253 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4254 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4258 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4259 X86MemOperand x86memop, RegisterClass RC,
4260 PatFrag mem_frag32, PatFrag mem_frag64,
4261 Intrinsic V4F32Int, Intrinsic V2F64Int,
4263 let ExeDomain = SSEPackedSingle in {
4264 // Intrinsic operation, reg.
4265 // Vector intrinsic operation, reg
4266 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4267 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4268 !strconcat(OpcodeStr,
4269 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4270 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4272 // Vector intrinsic operation, mem
4273 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4274 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4275 !strconcat(OpcodeStr,
4276 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4278 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4279 EVEX_CD8<32, VForm>;
4280 } // ExeDomain = SSEPackedSingle
4282 let ExeDomain = SSEPackedDouble in {
4283 // Vector intrinsic operation, reg
4284 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4285 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4286 !strconcat(OpcodeStr,
4287 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4288 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4290 // Vector intrinsic operation, mem
4291 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4292 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4293 !strconcat(OpcodeStr,
4294 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4296 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4297 EVEX_CD8<64, VForm>;
4298 } // ExeDomain = SSEPackedDouble
4301 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4305 let ExeDomain = GenericDomain in {
4307 let hasSideEffects = 0 in
4308 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4309 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4310 !strconcat(OpcodeStr,
4311 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4314 // Intrinsic operation, reg.
4315 let isCodeGenOnly = 1 in
4316 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4317 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4318 !strconcat(OpcodeStr,
4319 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4320 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4322 // Intrinsic operation, mem.
4323 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4324 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4325 !strconcat(OpcodeStr,
4326 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4327 [(set VR128X:$dst, (F32Int VR128X:$src1,
4328 sse_load_f32:$src2, imm:$src3))]>,
4329 EVEX_CD8<32, CD8VT1>;
4332 let hasSideEffects = 0 in
4333 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4334 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4335 !strconcat(OpcodeStr,
4336 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4339 // Intrinsic operation, reg.
4340 let isCodeGenOnly = 1 in
4341 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4342 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4343 !strconcat(OpcodeStr,
4344 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4345 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4348 // Intrinsic operation, mem.
4349 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4350 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4351 !strconcat(OpcodeStr,
4352 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4354 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4355 VEX_W, EVEX_CD8<64, CD8VT1>;
4356 } // ExeDomain = GenericDomain
4359 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4360 X86MemOperand x86memop, RegisterClass RC,
4361 PatFrag mem_frag, Domain d> {
4362 let ExeDomain = d in {
4363 // Intrinsic operation, reg.
4364 // Vector intrinsic operation, reg
4365 def r : AVX512AIi8<opc, MRMSrcReg,
4366 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4367 !strconcat(OpcodeStr,
4368 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4371 // Vector intrinsic operation, mem
4372 def m : AVX512AIi8<opc, MRMSrcMem,
4373 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4374 !strconcat(OpcodeStr,
4375 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4381 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4382 memopv16f32, SSEPackedSingle>, EVEX_V512,
4383 EVEX_CD8<32, CD8VF>;
4385 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4386 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4388 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4391 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4392 memopv8f64, SSEPackedDouble>, EVEX_V512,
4393 VEX_W, EVEX_CD8<64, CD8VF>;
4395 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4396 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4398 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4400 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4401 Operand x86memop, RegisterClass RC, Domain d> {
4402 let ExeDomain = d in {
4403 def r : AVX512AIi8<opc, MRMSrcReg,
4404 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4405 !strconcat(OpcodeStr,
4406 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4409 def m : AVX512AIi8<opc, MRMSrcMem,
4410 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4411 !strconcat(OpcodeStr,
4412 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4417 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4418 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4420 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4421 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4423 def : Pat<(ffloor FR32X:$src),
4424 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4425 def : Pat<(f64 (ffloor FR64X:$src)),
4426 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4427 def : Pat<(f32 (fnearbyint FR32X:$src)),
4428 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4429 def : Pat<(f64 (fnearbyint FR64X:$src)),
4430 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4431 def : Pat<(f32 (fceil FR32X:$src)),
4432 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4433 def : Pat<(f64 (fceil FR64X:$src)),
4434 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4435 def : Pat<(f32 (frint FR32X:$src)),
4436 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4437 def : Pat<(f64 (frint FR64X:$src)),
4438 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4439 def : Pat<(f32 (ftrunc FR32X:$src)),
4440 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4441 def : Pat<(f64 (ftrunc FR64X:$src)),
4442 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4444 def : Pat<(v16f32 (ffloor VR512:$src)),
4445 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4446 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4447 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4448 def : Pat<(v16f32 (fceil VR512:$src)),
4449 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4450 def : Pat<(v16f32 (frint VR512:$src)),
4451 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4452 def : Pat<(v16f32 (ftrunc VR512:$src)),
4453 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4455 def : Pat<(v8f64 (ffloor VR512:$src)),
4456 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4457 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4458 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4459 def : Pat<(v8f64 (fceil VR512:$src)),
4460 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4461 def : Pat<(v8f64 (frint VR512:$src)),
4462 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4463 def : Pat<(v8f64 (ftrunc VR512:$src)),
4464 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4466 //-------------------------------------------------
4467 // Integer truncate and extend operations
4468 //-------------------------------------------------
4470 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4471 RegisterClass dstRC, RegisterClass srcRC,
4472 RegisterClass KRC, X86MemOperand x86memop> {
4473 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4475 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4478 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4479 (ins KRC:$mask, srcRC:$src),
4480 !strconcat(OpcodeStr,
4481 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4484 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4485 (ins KRC:$mask, srcRC:$src),
4486 !strconcat(OpcodeStr,
4487 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4490 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4491 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4494 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4495 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4496 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4500 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4501 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4502 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4503 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4504 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4505 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4506 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4507 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4508 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4509 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4510 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4511 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4512 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4513 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4514 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4515 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4516 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4517 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4518 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4519 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4520 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4521 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4522 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4523 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4524 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4525 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4526 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4527 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4528 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4529 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4531 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4532 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4533 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4534 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4535 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4537 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4538 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4539 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4540 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4541 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4542 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4543 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4544 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4547 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4548 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4549 PatFrag mem_frag, X86MemOperand x86memop,
4550 ValueType OpVT, ValueType InVT> {
4552 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4554 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4555 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4557 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4558 (ins KRC:$mask, SrcRC:$src),
4559 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4562 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4563 (ins KRC:$mask, SrcRC:$src),
4564 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4567 let mayLoad = 1 in {
4568 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4569 (ins x86memop:$src),
4570 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4572 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4575 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4576 (ins KRC:$mask, x86memop:$src),
4577 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4581 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4582 (ins KRC:$mask, x86memop:$src),
4583 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4589 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4590 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4592 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4593 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4595 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4596 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4597 EVEX_CD8<16, CD8VH>;
4598 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4599 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4600 EVEX_CD8<16, CD8VQ>;
4601 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4602 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4603 EVEX_CD8<32, CD8VH>;
4605 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4606 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4608 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4609 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4611 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4612 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4613 EVEX_CD8<16, CD8VH>;
4614 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4615 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4616 EVEX_CD8<16, CD8VQ>;
4617 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4618 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4619 EVEX_CD8<32, CD8VH>;
4621 //===----------------------------------------------------------------------===//
4622 // GATHER - SCATTER Operations
4624 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4625 RegisterClass RC, X86MemOperand memop> {
4627 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4628 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4629 (ins RC:$src1, KRC:$mask, memop:$src2),
4630 !strconcat(OpcodeStr,
4631 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4635 let ExeDomain = SSEPackedDouble in {
4636 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4637 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4638 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4639 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4642 let ExeDomain = SSEPackedSingle in {
4643 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4644 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4645 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4646 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4649 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4650 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4651 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4652 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4654 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4655 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4656 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4657 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4659 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4660 RegisterClass RC, X86MemOperand memop> {
4661 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4662 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4663 (ins memop:$dst, KRC:$mask, RC:$src2),
4664 !strconcat(OpcodeStr,
4665 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4669 let ExeDomain = SSEPackedDouble in {
4670 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4671 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4672 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4673 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4676 let ExeDomain = SSEPackedSingle in {
4677 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4678 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4679 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4680 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4683 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4684 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4685 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4686 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4688 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4689 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4690 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4691 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4694 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4695 RegisterClass KRC, X86MemOperand memop> {
4696 let Predicates = [HasPFI], hasSideEffects = 1 in
4697 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4698 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4702 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4703 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4705 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4706 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4708 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4709 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4711 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4712 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4714 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4715 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4717 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4718 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4720 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4721 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4723 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4724 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4726 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4727 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4729 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4730 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4732 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4733 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4735 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4736 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4738 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4739 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4741 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4742 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4744 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4745 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4747 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4748 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4749 //===----------------------------------------------------------------------===//
4750 // VSHUFPS - VSHUFPD Operations
4752 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4753 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4755 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4756 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4757 !strconcat(OpcodeStr,
4758 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4759 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4760 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4761 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4762 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4763 (ins RC:$src1, RC:$src2, i8imm:$src3),
4764 !strconcat(OpcodeStr,
4765 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4766 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4767 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4768 EVEX_4V, Sched<[WriteShuffle]>;
4771 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4772 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4773 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4774 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4776 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4777 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4778 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4779 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4780 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4782 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4783 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4784 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4785 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4786 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4788 multiclass avx512_valign<X86VectorVTInfo _> {
4789 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4790 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4792 "$src3, $src2, $src1", "$src1, $src2, $src3",
4793 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4795 AVX512AIi8Base, EVEX_4V;
4797 // Also match valign of packed floats.
4798 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4799 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4802 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4803 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4804 !strconcat("valign"##_.Suffix,
4805 " \t{$src3, $src2, $src1, $dst|"
4806 "$dst, $src1, $src2, $src3}"),
4809 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4810 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4812 // Helper fragments to match sext vXi1 to vXiY.
4813 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4814 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4816 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4817 RegisterClass KRC, RegisterClass RC,
4818 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4820 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4821 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4823 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4824 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4826 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4827 !strconcat(OpcodeStr,
4828 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4830 let mayLoad = 1 in {
4831 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4832 (ins x86memop:$src),
4833 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4835 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4836 (ins KRC:$mask, x86memop:$src),
4837 !strconcat(OpcodeStr,
4838 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4840 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4841 (ins KRC:$mask, x86memop:$src),
4842 !strconcat(OpcodeStr,
4843 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4845 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4846 (ins x86scalar_mop:$src),
4847 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4848 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4850 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4851 (ins KRC:$mask, x86scalar_mop:$src),
4852 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4853 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4854 []>, EVEX, EVEX_B, EVEX_K;
4855 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4856 (ins KRC:$mask, x86scalar_mop:$src),
4857 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4858 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4860 []>, EVEX, EVEX_B, EVEX_KZ;
4864 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4865 i512mem, i32mem, "{1to16}">, EVEX_V512,
4866 EVEX_CD8<32, CD8VF>;
4867 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4868 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4869 EVEX_CD8<64, CD8VF>;
4872 (bc_v16i32 (v16i1sextv16i32)),
4873 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4874 (VPABSDZrr VR512:$src)>;
4876 (bc_v8i64 (v8i1sextv8i64)),
4877 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4878 (VPABSQZrr VR512:$src)>;
4880 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4881 (v16i32 immAllZerosV), (i16 -1))),
4882 (VPABSDZrr VR512:$src)>;
4883 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4884 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4885 (VPABSQZrr VR512:$src)>;
4887 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4888 RegisterClass RC, RegisterClass KRC,
4889 X86MemOperand x86memop,
4890 X86MemOperand x86scalar_mop, string BrdcstStr> {
4891 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4893 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4895 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4896 (ins x86memop:$src),
4897 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4899 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4900 (ins x86scalar_mop:$src),
4901 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4902 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4904 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4905 (ins KRC:$mask, RC:$src),
4906 !strconcat(OpcodeStr,
4907 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4909 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4910 (ins KRC:$mask, x86memop:$src),
4911 !strconcat(OpcodeStr,
4912 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4914 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4915 (ins KRC:$mask, x86scalar_mop:$src),
4916 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4917 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4919 []>, EVEX, EVEX_KZ, EVEX_B;
4921 let Constraints = "$src1 = $dst" in {
4922 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4923 (ins RC:$src1, KRC:$mask, RC:$src2),
4924 !strconcat(OpcodeStr,
4925 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4927 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4928 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4929 !strconcat(OpcodeStr,
4930 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4932 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4933 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4934 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4935 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4936 []>, EVEX, EVEX_K, EVEX_B;
4940 let Predicates = [HasCDI] in {
4941 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4942 i512mem, i32mem, "{1to16}">,
4943 EVEX_V512, EVEX_CD8<32, CD8VF>;
4946 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4947 i512mem, i64mem, "{1to8}">,
4948 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4952 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4954 (VPCONFLICTDrrk VR512:$src1,
4955 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4957 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4959 (VPCONFLICTQrrk VR512:$src1,
4960 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4962 let Predicates = [HasCDI] in {
4963 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4964 i512mem, i32mem, "{1to16}">,
4965 EVEX_V512, EVEX_CD8<32, CD8VF>;
4968 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4969 i512mem, i64mem, "{1to8}">,
4970 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4974 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4976 (VPLZCNTDrrk VR512:$src1,
4977 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4979 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4981 (VPLZCNTQrrk VR512:$src1,
4982 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4984 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4985 (VPLZCNTDrm addr:$src)>;
4986 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4987 (VPLZCNTDrr VR512:$src)>;
4988 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4989 (VPLZCNTQrm addr:$src)>;
4990 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4991 (VPLZCNTQrr VR512:$src)>;
4993 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4994 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4995 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4997 def : Pat<(store VK1:$src, addr:$dst),
4998 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5000 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5001 (truncstore node:$val, node:$ptr), [{
5002 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5005 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5006 (MOV8mr addr:$dst, GR8:$src)>;