1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 int NumEltsInVT = !if (!eq (NumElts, 1),
27 !if (!eq (EltVT.Size, 32), 4,
28 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts);
30 string VTName = "v" # NumEltsInVT # EltVT;
33 ValueType VT = !cast<ValueType>(VTName);
35 string EltTypeName = !cast<string>(EltVT);
36 // Size of the element type in bits, e.g. 32 for v16i32.
37 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
38 int EltSize = EltVT.Size;
40 // "i" for integer types and "f" for floating-point types
41 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
43 // Size of RC in bits, e.g. 512 for VR512.
46 // The corresponding memory operand, e.g. i512mem for VR512.
47 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
48 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
51 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
52 // due to load promotion during legalization
53 PatFrag LdFrag = !cast<PatFrag>("load" #
54 !if (!eq (TypeVariantName, "i"),
55 !if (!eq (Size, 128), "v2i64",
56 !if (!eq (Size, 256), "v4i64",
58 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
60 // Load patterns used for memory operands. We only have this defined in
61 // case of i64 element types for sub-512 integer vectors. For now, keep
62 // MemOpFrag undefined in these cases.
64 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
65 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
66 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
67 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
68 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
70 // The corresponding float type, e.g. v16f32 for v16i32
71 // Note: For EltSize < 32, FloatVT is illegal and TableGen
72 // fails to compile, so we choose FloatVT = VT
73 ValueType FloatVT = !cast<ValueType>(
74 !if (!eq (!srl(EltSize,5),0),
76 !if (!eq(TypeVariantName, "i"),
77 "v" # NumElts # "f" # EltSize,
80 // The string to specify embedded broadcast in assembly.
81 string BroadcastStr = "{1to" # NumElts # "}";
83 // 8-bit compressed displacement tuple/subvector format. This is only
84 // defined for NumElts <= 8.
85 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
86 !cast<CD8VForm>("CD8VT" # NumElts), ?);
88 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
89 !if (!eq (Size, 256), sub_ymm, ?));
91 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
92 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
95 // A vector type of the same width with element type i32. This is used to
96 // create the canonical constant zero node ImmAllZerosV.
97 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
98 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
101 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
102 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
103 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
104 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
105 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
106 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
108 // "x" in v32i8x_info means RC = VR256X
109 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
110 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
111 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
112 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
113 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
114 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
116 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
117 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
118 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
119 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
120 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
121 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
124 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
125 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
127 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
128 X86VectorVTInfo i128> {
129 X86VectorVTInfo info512 = i512;
130 X86VectorVTInfo info256 = i256;
131 X86VectorVTInfo info128 = i128;
134 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
136 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
138 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
140 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
142 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
144 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
147 // This multiclass generates the masking variants from the non-masking
148 // variant. It only provides the assembly pieces for the masking variants.
149 // It assumes custom ISel patterns for masking which can be provided as
150 // template arguments.
151 multiclass AVX512_maskable_custom<bits<8> O, Format F,
153 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
155 string AttSrcAsm, string IntelSrcAsm,
157 list<dag> MaskingPattern,
158 list<dag> ZeroMaskingPattern,
160 string MaskingConstraint = "",
161 InstrItinClass itin = NoItinerary,
162 bit IsCommutable = 0> {
163 let isCommutable = IsCommutable in
164 def NAME: AVX512<O, F, Outs, Ins,
165 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
166 "$dst "#Round#", "#IntelSrcAsm#"}",
169 // Prefer over VMOV*rrk Pat<>
170 let AddedComplexity = 20 in
171 def NAME#k: AVX512<O, F, Outs, MaskingIns,
172 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
173 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
174 MaskingPattern, itin>,
176 // In case of the 3src subclass this is overridden with a let.
177 string Constraints = MaskingConstraint;
179 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
180 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
181 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
182 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
189 // Common base class of AVX512_maskable and AVX512_maskable_3src.
190 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
192 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
194 string AttSrcAsm, string IntelSrcAsm,
195 dag RHS, dag MaskingRHS,
196 SDNode Select = vselect, string Round = "",
197 string MaskingConstraint = "",
198 InstrItinClass itin = NoItinerary,
199 bit IsCommutable = 0> :
200 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
201 AttSrcAsm, IntelSrcAsm,
202 [(set _.RC:$dst, RHS)],
203 [(set _.RC:$dst, MaskingRHS)],
205 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
206 Round, MaskingConstraint, NoItinerary, IsCommutable>;
208 // This multiclass generates the unconditional/non-masking, the masking and
209 // the zero-masking variant of the vector instruction. In the masking case, the
210 // perserved vector elements come from a new dummy input operand tied to $dst.
211 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
212 dag Outs, dag Ins, string OpcodeStr,
213 string AttSrcAsm, string IntelSrcAsm,
214 dag RHS, string Round = "",
215 InstrItinClass itin = NoItinerary,
216 bit IsCommutable = 0> :
217 AVX512_maskable_common<O, F, _, Outs, Ins,
218 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
219 !con((ins _.KRCWM:$mask), Ins),
220 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
221 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
222 Round, "$src0 = $dst", itin, IsCommutable>;
224 // This multiclass generates the unconditional/non-masking, the masking and
225 // the zero-masking variant of the scalar instruction.
226 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
227 dag Outs, dag Ins, string OpcodeStr,
228 string AttSrcAsm, string IntelSrcAsm,
229 dag RHS, string Round = "",
230 InstrItinClass itin = NoItinerary,
231 bit IsCommutable = 0> :
232 AVX512_maskable_common<O, F, _, Outs, Ins,
233 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
234 !con((ins _.KRCWM:$mask), Ins),
235 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
236 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
237 Round, "$src0 = $dst", itin, IsCommutable>;
239 // Similar to AVX512_maskable but in this case one of the source operands
240 // ($src1) is already tied to $dst so we just use that for the preserved
241 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
243 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
244 dag Outs, dag NonTiedIns, string OpcodeStr,
245 string AttSrcAsm, string IntelSrcAsm,
247 AVX512_maskable_common<O, F, _, Outs,
248 !con((ins _.RC:$src1), NonTiedIns),
249 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
250 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
251 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
252 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
255 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
258 string AttSrcAsm, string IntelSrcAsm,
260 AVX512_maskable_custom<O, F, Outs, Ins,
261 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
262 !con((ins _.KRCWM:$mask), Ins),
263 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
266 // Bitcasts between 512-bit vector types. Return the original type since
267 // no instruction is needed for the conversion
268 let Predicates = [HasAVX512] in {
269 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
270 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
271 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
272 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
273 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
274 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
275 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
276 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
277 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
278 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
279 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
280 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
281 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
282 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
283 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
284 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
285 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
286 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
287 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
288 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
289 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
290 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
291 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
292 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
293 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
296 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
297 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
298 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
299 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
302 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
303 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
304 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
305 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
307 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
308 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
309 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
310 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
313 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
314 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
315 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
318 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
319 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
320 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
321 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
322 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
323 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
324 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
325 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
326 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
328 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
329 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
330 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
332 // Bitcasts between 256-bit vector types. Return the original type since
333 // no instruction is needed for the conversion
334 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
335 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
336 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
337 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
338 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
339 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
341 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
342 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
343 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
345 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
346 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
347 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
348 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
350 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
352 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
353 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
354 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
355 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
356 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
358 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
360 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
362 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
363 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
367 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
370 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
371 isPseudo = 1, Predicates = [HasAVX512] in {
372 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
373 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
376 let Predicates = [HasAVX512] in {
377 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
378 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
379 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
382 //===----------------------------------------------------------------------===//
383 // AVX-512 - VECTOR INSERT
386 multiclass vinsert_for_size_no_alt<int Opcode,
387 X86VectorVTInfo From, X86VectorVTInfo To,
388 PatFrag vinsert_insert,
389 SDNodeXForm INSERT_get_vinsert_imm> {
390 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
391 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
392 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
393 "vinsert" # From.EltTypeName # "x" # From.NumElts #
394 "\t{$src3, $src2, $src1, $dst|"
395 "$dst, $src1, $src2, $src3}",
396 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
397 (From.VT From.RC:$src2),
402 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
403 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
404 "vinsert" # From.EltTypeName # "x" # From.NumElts #
405 "\t{$src3, $src2, $src1, $dst|"
406 "$dst, $src1, $src2, $src3}",
408 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
412 multiclass vinsert_for_size<int Opcode,
413 X86VectorVTInfo From, X86VectorVTInfo To,
414 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
415 PatFrag vinsert_insert,
416 SDNodeXForm INSERT_get_vinsert_imm> :
417 vinsert_for_size_no_alt<Opcode, From, To,
418 vinsert_insert, INSERT_get_vinsert_imm> {
419 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
420 // vinserti32x4. Only add this if 64x2 and friends are not supported
421 // natively via AVX512DQ.
422 let Predicates = [NoDQI] in
423 def : Pat<(vinsert_insert:$ins
424 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
425 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
426 VR512:$src1, From.RC:$src2,
427 (INSERT_get_vinsert_imm VR512:$ins)))>;
430 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
431 ValueType EltVT64, int Opcode256> {
432 defm NAME # "32x4" : vinsert_for_size<Opcode128,
433 X86VectorVTInfo< 4, EltVT32, VR128X>,
434 X86VectorVTInfo<16, EltVT32, VR512>,
435 X86VectorVTInfo< 2, EltVT64, VR128X>,
436 X86VectorVTInfo< 8, EltVT64, VR512>,
438 INSERT_get_vinsert128_imm>;
439 let Predicates = [HasDQI] in
440 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
441 X86VectorVTInfo< 2, EltVT64, VR128X>,
442 X86VectorVTInfo< 8, EltVT64, VR512>,
444 INSERT_get_vinsert128_imm>, VEX_W;
445 defm NAME # "64x4" : vinsert_for_size<Opcode256,
446 X86VectorVTInfo< 4, EltVT64, VR256X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
448 X86VectorVTInfo< 8, EltVT32, VR256>,
449 X86VectorVTInfo<16, EltVT32, VR512>,
451 INSERT_get_vinsert256_imm>, VEX_W;
452 let Predicates = [HasDQI] in
453 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
454 X86VectorVTInfo< 8, EltVT32, VR256X>,
455 X86VectorVTInfo<16, EltVT32, VR512>,
457 INSERT_get_vinsert256_imm>;
460 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
461 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
463 // vinsertps - insert f32 to XMM
464 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
465 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
466 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
467 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
469 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
470 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1,
473 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
474 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
476 //===----------------------------------------------------------------------===//
477 // AVX-512 VECTOR EXTRACT
480 multiclass vextract_for_size<int Opcode,
481 X86VectorVTInfo From, X86VectorVTInfo To,
482 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
483 PatFrag vextract_extract,
484 SDNodeXForm EXTRACT_get_vextract_imm> {
485 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
486 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
487 (ins VR512:$src1, i8imm:$idx),
488 "vextract" # To.EltTypeName # "x4",
489 "$idx, $src1", "$src1, $idx",
490 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
492 AVX512AIi8Base, EVEX, EVEX_V512;
494 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
495 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
496 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
497 "$dst, $src1, $src2}",
498 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
501 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
503 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
506 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
508 // A 128/256-bit subvector extract from the first 512-bit vector position is
509 // a subregister copy that needs no instruction.
510 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
512 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
514 // And for the alternative types.
515 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
519 // Intrinsic call with masking.
520 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
522 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
523 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
524 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
525 VR512:$src1, imm:$idx)>;
527 // Intrinsic call with zero-masking.
528 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
530 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
531 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
532 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
533 VR512:$src1, imm:$idx)>;
535 // Intrinsic call without masking.
536 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
538 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
539 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
540 VR512:$src1, imm:$idx)>;
543 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
544 ValueType EltVT64, int Opcode64> {
545 defm NAME # "32x4" : vextract_for_size<Opcode32,
546 X86VectorVTInfo<16, EltVT32, VR512>,
547 X86VectorVTInfo< 4, EltVT32, VR128X>,
548 X86VectorVTInfo< 8, EltVT64, VR512>,
549 X86VectorVTInfo< 2, EltVT64, VR128X>,
551 EXTRACT_get_vextract128_imm>;
552 defm NAME # "64x4" : vextract_for_size<Opcode64,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 4, EltVT64, VR256X>,
555 X86VectorVTInfo<16, EltVT32, VR512>,
556 X86VectorVTInfo< 8, EltVT32, VR256>,
558 EXTRACT_get_vextract256_imm>, VEX_W;
561 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
562 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
564 // A 128-bit subvector insert to the first 512-bit vector position
565 // is a subregister copy that needs no instruction.
566 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
567 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
568 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
570 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
571 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
572 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
574 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
575 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
576 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
578 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
580 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
585 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
586 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
587 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
588 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
589 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
590 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 // vextractps - extract 32 bits from XMM
593 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
594 (ins VR128X:$src1, i32i8imm:$src2),
595 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
596 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
599 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
600 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
601 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
602 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
603 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
605 //===---------------------------------------------------------------------===//
608 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
609 ValueType svt, X86VectorVTInfo _> {
610 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
611 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
612 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
616 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
617 (ins _.ScalarMemOp:$src),
618 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
619 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
624 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
625 AVX512VLVectorVTInfo _> {
626 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
629 let Predicates = [HasVLX] in {
630 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
635 let ExeDomain = SSEPackedSingle in {
636 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
637 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
638 let Predicates = [HasVLX] in {
639 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
640 v4f32, v4f32x_info>, EVEX_V128,
641 EVEX_CD8<32, CD8VT1>;
645 let ExeDomain = SSEPackedDouble in {
646 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
647 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
650 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
651 (VBROADCASTSSZm addr:$src)>;
652 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
653 (VBROADCASTSDZm addr:$src)>;
655 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
656 (VBROADCASTSSZm addr:$src)>;
657 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
658 (VBROADCASTSDZm addr:$src)>;
660 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
661 RegisterClass SrcRC, RegisterClass KRC> {
662 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
664 []>, EVEX, EVEX_V512;
665 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
666 (ins KRC:$mask, SrcRC:$src),
667 !strconcat(OpcodeStr,
668 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
669 []>, EVEX, EVEX_V512, EVEX_KZ;
672 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
673 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
676 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
677 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
679 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
680 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
682 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
683 (VPBROADCASTDrZrr GR32:$src)>;
684 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
685 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
686 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
687 (VPBROADCASTQrZrr GR64:$src)>;
688 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
689 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
691 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
692 (VPBROADCASTDrZrr GR32:$src)>;
693 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
694 (VPBROADCASTQrZrr GR64:$src)>;
696 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
697 (v16i32 immAllZerosV), (i16 GR16:$mask))),
698 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
699 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
700 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
701 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
703 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
704 X86MemOperand x86memop, PatFrag ld_frag,
705 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
707 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
710 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
711 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
713 !strconcat(OpcodeStr,
714 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
716 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
719 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
720 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
722 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
723 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
725 !strconcat(OpcodeStr,
726 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
727 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
728 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
732 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
733 loadi32, VR512, v16i32, v4i32, VK16WM>,
734 EVEX_V512, EVEX_CD8<32, CD8VT1>;
735 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
736 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
737 EVEX_CD8<64, CD8VT1>;
739 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
740 X86MemOperand x86memop, PatFrag ld_frag,
743 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
744 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
746 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
748 !strconcat(OpcodeStr,
749 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
754 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
755 i128mem, loadv2i64, VK16WM>,
756 EVEX_V512, EVEX_CD8<32, CD8VT4>;
757 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
758 i256mem, loadv4i64, VK16WM>, VEX_W,
759 EVEX_V512, EVEX_CD8<64, CD8VT4>;
761 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
762 (VPBROADCASTDZrr VR128X:$src)>;
763 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
764 (VPBROADCASTQZrr VR128X:$src)>;
766 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
767 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
768 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
769 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
771 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
772 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
773 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
774 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
776 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
777 (VBROADCASTSSZr VR128X:$src)>;
778 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
779 (VBROADCASTSDZr VR128X:$src)>;
781 // Provide fallback in case the load node that is used in the patterns above
782 // is used by additional users, which prevents the pattern selection.
783 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
784 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
785 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
786 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
789 let Predicates = [HasAVX512] in {
790 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
792 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
793 addr:$src)), sub_ymm)>;
795 //===----------------------------------------------------------------------===//
796 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
799 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
801 let Predicates = [HasCDI] in
802 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
803 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
804 []>, EVEX, EVEX_V512;
806 let Predicates = [HasCDI, HasVLX] in {
807 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
808 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
809 []>, EVEX, EVEX_V128;
810 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
811 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
812 []>, EVEX, EVEX_V256;
816 let Predicates = [HasCDI] in {
817 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
819 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
823 //===----------------------------------------------------------------------===//
826 // -- immediate form --
827 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
829 let ExeDomain = _.ExeDomain in {
830 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
831 (ins _.RC:$src1, i8imm:$src2),
832 !strconcat(OpcodeStr,
833 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
835 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
837 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
838 (ins _.MemOp:$src1, i8imm:$src2),
839 !strconcat(OpcodeStr,
840 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
842 (_.VT (OpNode (_.MemOpFrag addr:$src1),
844 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
848 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
849 X86VectorVTInfo Ctrl> :
850 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
851 let ExeDomain = _.ExeDomain in {
852 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
853 (ins _.RC:$src1, _.RC:$src2),
854 !strconcat("vpermil" # _.Suffix,
855 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
857 (_.VT (X86VPermilpv _.RC:$src1,
858 (Ctrl.VT Ctrl.RC:$src2))))]>,
860 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
861 (ins _.RC:$src1, Ctrl.MemOp:$src2),
862 !strconcat("vpermil" # _.Suffix,
863 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
865 (_.VT (X86VPermilpv _.RC:$src1,
866 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
871 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
873 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
876 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
878 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
881 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
882 (VPERMILPSZri VR512:$src1, imm:$imm)>;
883 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
884 (VPERMILPDZri VR512:$src1, imm:$imm)>;
886 // -- VPERM - register form --
887 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
888 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
890 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
891 (ins RC:$src1, RC:$src2),
892 !strconcat(OpcodeStr,
893 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
895 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
897 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
898 (ins RC:$src1, x86memop:$src2),
899 !strconcat(OpcodeStr,
900 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
902 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
906 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
907 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
908 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
909 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
910 let ExeDomain = SSEPackedSingle in
911 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
912 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
913 let ExeDomain = SSEPackedDouble in
914 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
915 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
917 // -- VPERM2I - 3 source operands form --
918 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
919 PatFrag mem_frag, X86MemOperand x86memop,
920 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
921 let Constraints = "$src1 = $dst" in {
922 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
923 (ins RC:$src1, RC:$src2, RC:$src3),
924 !strconcat(OpcodeStr,
925 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
927 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
930 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
931 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
932 !strconcat(OpcodeStr,
933 "\t{$src3, $src2, $dst {${mask}}|"
934 "$dst {${mask}}, $src2, $src3}"),
935 [(set RC:$dst, (OpVT (vselect KRC:$mask,
936 (OpNode RC:$src1, RC:$src2,
941 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
942 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
943 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
944 !strconcat(OpcodeStr,
945 "\t{$src3, $src2, $dst {${mask}} {z} |",
946 "$dst {${mask}} {z}, $src2, $src3}"),
947 [(set RC:$dst, (OpVT (vselect KRC:$mask,
948 (OpNode RC:$src1, RC:$src2,
951 (v16i32 immAllZerosV))))))]>,
954 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
955 (ins RC:$src1, RC:$src2, x86memop:$src3),
956 !strconcat(OpcodeStr,
957 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
959 (OpVT (OpNode RC:$src1, RC:$src2,
960 (mem_frag addr:$src3))))]>, EVEX_4V;
962 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
963 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
964 !strconcat(OpcodeStr,
965 "\t{$src3, $src2, $dst {${mask}}|"
966 "$dst {${mask}}, $src2, $src3}"),
968 (OpVT (vselect KRC:$mask,
969 (OpNode RC:$src1, RC:$src2,
970 (mem_frag addr:$src3)),
974 let AddedComplexity = 10 in // Prefer over the rrkz variant
975 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
976 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
977 !strconcat(OpcodeStr,
978 "\t{$src3, $src2, $dst {${mask}} {z}|"
979 "$dst {${mask}} {z}, $src2, $src3}"),
981 (OpVT (vselect KRC:$mask,
982 (OpNode RC:$src1, RC:$src2,
983 (mem_frag addr:$src3)),
985 (v16i32 immAllZerosV))))))]>,
989 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
990 i512mem, X86VPermiv3, v16i32, VK16WM>,
991 EVEX_V512, EVEX_CD8<32, CD8VF>;
992 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
993 i512mem, X86VPermiv3, v8i64, VK8WM>,
994 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
995 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
996 i512mem, X86VPermiv3, v16f32, VK16WM>,
997 EVEX_V512, EVEX_CD8<32, CD8VF>;
998 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
999 i512mem, X86VPermiv3, v8f64, VK8WM>,
1000 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1002 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1003 PatFrag mem_frag, X86MemOperand x86memop,
1004 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1005 ValueType MaskVT, RegisterClass MRC> :
1006 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1008 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1009 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1010 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1012 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1013 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1014 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1015 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1018 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1019 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1020 EVEX_V512, EVEX_CD8<32, CD8VF>;
1021 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1022 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1023 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1024 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1025 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1026 EVEX_V512, EVEX_CD8<32, CD8VF>;
1027 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1028 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1029 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1031 //===----------------------------------------------------------------------===//
1032 // AVX-512 - BLEND using mask
1034 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1035 RegisterClass KRC, RegisterClass RC,
1036 X86MemOperand x86memop, PatFrag mem_frag,
1037 SDNode OpNode, ValueType vt> {
1038 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1039 (ins KRC:$mask, RC:$src1, RC:$src2),
1040 !strconcat(OpcodeStr,
1041 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1042 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1043 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1045 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1046 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1047 !strconcat(OpcodeStr,
1048 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1049 []>, EVEX_4V, EVEX_K;
1052 let ExeDomain = SSEPackedSingle in
1053 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1054 VK16WM, VR512, f512mem,
1055 memopv16f32, vselect, v16f32>,
1056 EVEX_CD8<32, CD8VF>, EVEX_V512;
1057 let ExeDomain = SSEPackedDouble in
1058 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1059 VK8WM, VR512, f512mem,
1060 memopv8f64, vselect, v8f64>,
1061 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1063 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1064 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1065 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1066 VR512:$src1, VR512:$src2)>;
1068 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1069 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1070 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1071 VR512:$src1, VR512:$src2)>;
1073 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1074 VK16WM, VR512, f512mem,
1075 memopv16i32, vselect, v16i32>,
1076 EVEX_CD8<32, CD8VF>, EVEX_V512;
1078 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1079 VK8WM, VR512, f512mem,
1080 memopv8i64, vselect, v8i64>,
1081 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1083 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1084 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1085 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1086 VR512:$src1, VR512:$src2)>;
1088 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1089 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1090 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1091 VR512:$src1, VR512:$src2)>;
1093 let Predicates = [HasAVX512] in {
1094 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1095 (v8f32 VR256X:$src2))),
1097 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1098 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1099 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1101 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1102 (v8i32 VR256X:$src2))),
1104 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1105 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1106 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1108 //===----------------------------------------------------------------------===//
1109 // Compare Instructions
1110 //===----------------------------------------------------------------------===//
1112 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1113 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1114 Operand CC, SDNode OpNode, ValueType VT,
1115 PatFrag ld_frag, string asm, string asm_alt> {
1116 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1117 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1118 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1119 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1120 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1121 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1122 [(set VK1:$dst, (OpNode (VT RC:$src1),
1123 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1124 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1125 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1126 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1127 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1128 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1129 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1130 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1134 let Predicates = [HasAVX512] in {
1135 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1136 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1137 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1139 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1140 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1141 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1145 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1146 X86VectorVTInfo _> {
1147 def rr : AVX512BI<opc, MRMSrcReg,
1148 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1149 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1150 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1151 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1153 def rm : AVX512BI<opc, MRMSrcMem,
1154 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1155 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1156 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1157 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1158 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1159 def rrk : AVX512BI<opc, MRMSrcReg,
1160 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1161 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1162 "$dst {${mask}}, $src1, $src2}"),
1163 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1164 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1165 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1167 def rmk : AVX512BI<opc, MRMSrcMem,
1168 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1169 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1170 "$dst {${mask}}, $src1, $src2}"),
1171 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1172 (OpNode (_.VT _.RC:$src1),
1174 (_.LdFrag addr:$src2))))))],
1175 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1178 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1179 X86VectorVTInfo _> :
1180 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1181 let mayLoad = 1 in {
1182 def rmb : AVX512BI<opc, MRMSrcMem,
1183 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1184 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1185 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1186 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1187 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1188 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1189 def rmbk : AVX512BI<opc, MRMSrcMem,
1190 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1191 _.ScalarMemOp:$src2),
1192 !strconcat(OpcodeStr,
1193 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1194 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1195 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1196 (OpNode (_.VT _.RC:$src1),
1198 (_.ScalarLdFrag addr:$src2)))))],
1199 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1203 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1204 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1205 let Predicates = [prd] in
1206 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1209 let Predicates = [prd, HasVLX] in {
1210 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1212 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1217 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1218 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1220 let Predicates = [prd] in
1221 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1224 let Predicates = [prd, HasVLX] in {
1225 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1227 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1232 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1233 avx512vl_i8_info, HasBWI>,
1236 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1237 avx512vl_i16_info, HasBWI>,
1238 EVEX_CD8<16, CD8VF>;
1240 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1241 avx512vl_i32_info, HasAVX512>,
1242 EVEX_CD8<32, CD8VF>;
1244 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1245 avx512vl_i64_info, HasAVX512>,
1246 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1248 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1249 avx512vl_i8_info, HasBWI>,
1252 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1253 avx512vl_i16_info, HasBWI>,
1254 EVEX_CD8<16, CD8VF>;
1256 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1257 avx512vl_i32_info, HasAVX512>,
1258 EVEX_CD8<32, CD8VF>;
1260 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1261 avx512vl_i64_info, HasAVX512>,
1262 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1264 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1265 (COPY_TO_REGCLASS (VPCMPGTDZrr
1266 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1267 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1269 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1270 (COPY_TO_REGCLASS (VPCMPEQDZrr
1271 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1272 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1274 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1275 X86VectorVTInfo _> {
1276 def rri : AVX512AIi8<opc, MRMSrcReg,
1277 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1278 !strconcat("vpcmp${cc}", Suffix,
1279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1280 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1282 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1284 def rmi : AVX512AIi8<opc, MRMSrcMem,
1285 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1286 !strconcat("vpcmp${cc}", Suffix,
1287 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1288 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1289 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1291 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1292 def rrik : AVX512AIi8<opc, MRMSrcReg,
1293 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1295 !strconcat("vpcmp${cc}", Suffix,
1296 "\t{$src2, $src1, $dst {${mask}}|",
1297 "$dst {${mask}}, $src1, $src2}"),
1298 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1299 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1301 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1303 def rmik : AVX512AIi8<opc, MRMSrcMem,
1304 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1306 !strconcat("vpcmp${cc}", Suffix,
1307 "\t{$src2, $src1, $dst {${mask}}|",
1308 "$dst {${mask}}, $src1, $src2}"),
1309 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1310 (OpNode (_.VT _.RC:$src1),
1311 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1313 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1315 // Accept explicit immediate argument form instead of comparison code.
1316 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1317 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1318 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1319 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1320 "$dst, $src1, $src2, $cc}"),
1321 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1322 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1323 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1324 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1325 "$dst, $src1, $src2, $cc}"),
1326 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1327 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1328 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1330 !strconcat("vpcmp", Suffix,
1331 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1332 "$dst {${mask}}, $src1, $src2, $cc}"),
1333 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1334 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1335 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1337 !strconcat("vpcmp", Suffix,
1338 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1339 "$dst {${mask}}, $src1, $src2, $cc}"),
1340 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1344 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1345 X86VectorVTInfo _> :
1346 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1347 let mayLoad = 1 in {
1348 def rmib : AVX512AIi8<opc, MRMSrcMem,
1349 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1351 !strconcat("vpcmp${cc}", Suffix,
1352 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1353 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1354 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1355 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1357 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1358 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1359 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1360 _.ScalarMemOp:$src2, AVXCC:$cc),
1361 !strconcat("vpcmp${cc}", Suffix,
1362 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1363 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1364 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1365 (OpNode (_.VT _.RC:$src1),
1366 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1368 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1371 // Accept explicit immediate argument form instead of comparison code.
1372 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1373 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1374 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1376 !strconcat("vpcmp", Suffix,
1377 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1378 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1379 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1380 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1381 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1382 _.ScalarMemOp:$src2, i8imm:$cc),
1383 !strconcat("vpcmp", Suffix,
1384 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1385 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1386 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1390 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1391 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1392 let Predicates = [prd] in
1393 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1395 let Predicates = [prd, HasVLX] in {
1396 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1397 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1401 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1402 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1403 let Predicates = [prd] in
1404 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1407 let Predicates = [prd, HasVLX] in {
1408 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1410 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1415 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1416 HasBWI>, EVEX_CD8<8, CD8VF>;
1417 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1418 HasBWI>, EVEX_CD8<8, CD8VF>;
1420 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1421 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1422 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1423 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1425 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1426 HasAVX512>, EVEX_CD8<32, CD8VF>;
1427 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1428 HasAVX512>, EVEX_CD8<32, CD8VF>;
1430 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1431 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1432 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1433 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1435 // avx512_cmp_packed - compare packed instructions
1436 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1437 X86MemOperand x86memop, ValueType vt,
1438 string suffix, Domain d> {
1439 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1440 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1441 !strconcat("vcmp${cc}", suffix,
1442 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1443 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1444 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1445 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1446 !strconcat("vcmp${cc}", suffix,
1447 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1449 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1450 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1451 !strconcat("vcmp${cc}", suffix,
1452 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1454 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1456 // Accept explicit immediate argument form instead of comparison code.
1457 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1458 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1459 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1460 !strconcat("vcmp", suffix,
1461 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1462 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1463 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1464 !strconcat("vcmp", suffix,
1465 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1469 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1470 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1471 EVEX_CD8<32, CD8VF>;
1472 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1473 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1474 EVEX_CD8<64, CD8VF>;
1476 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1477 (COPY_TO_REGCLASS (VCMPPSZrri
1478 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1479 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1481 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1482 (COPY_TO_REGCLASS (VPCMPDZrri
1483 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1484 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1486 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1487 (COPY_TO_REGCLASS (VPCMPUDZrri
1488 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1489 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1492 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1493 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1495 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1496 (I8Imm imm:$cc)), GR16)>;
1498 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1499 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1501 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1502 (I8Imm imm:$cc)), GR8)>;
1504 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1505 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1507 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1508 (I8Imm imm:$cc)), GR16)>;
1510 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1511 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1513 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1514 (I8Imm imm:$cc)), GR8)>;
1516 // Mask register copy, including
1517 // - copy between mask registers
1518 // - load/store mask registers
1519 // - copy from GPR to mask register and vice versa
1521 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1522 string OpcodeStr, RegisterClass KRC,
1523 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1524 let hasSideEffects = 0 in {
1525 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1526 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1528 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1529 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1530 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1532 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1533 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1537 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1539 RegisterClass KRC, RegisterClass GRC> {
1540 let hasSideEffects = 0 in {
1541 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1543 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1544 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1548 let Predicates = [HasDQI] in
1549 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1551 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1554 let Predicates = [HasAVX512] in
1555 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1557 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1560 let Predicates = [HasBWI] in {
1561 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1562 i32mem>, VEX, PD, VEX_W;
1563 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1567 let Predicates = [HasBWI] in {
1568 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1569 i64mem>, VEX, PS, VEX_W;
1570 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1574 // GR from/to mask register
1575 let Predicates = [HasDQI] in {
1576 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1577 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1578 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1579 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1581 let Predicates = [HasAVX512] in {
1582 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1583 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1584 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1585 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1587 let Predicates = [HasBWI] in {
1588 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1589 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1591 let Predicates = [HasBWI] in {
1592 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1593 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1597 let Predicates = [HasDQI] in {
1598 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1599 (KMOVBmk addr:$dst, VK8:$src)>;
1601 let Predicates = [HasAVX512] in {
1602 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1603 (KMOVWmk addr:$dst, VK16:$src)>;
1604 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1605 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1606 def : Pat<(i1 (load addr:$src)),
1607 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1608 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1609 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1611 let Predicates = [HasBWI] in {
1612 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1613 (KMOVDmk addr:$dst, VK32:$src)>;
1615 let Predicates = [HasBWI] in {
1616 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1617 (KMOVQmk addr:$dst, VK64:$src)>;
1620 let Predicates = [HasAVX512] in {
1621 def : Pat<(i1 (trunc (i64 GR64:$src))),
1622 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1625 def : Pat<(i1 (trunc (i32 GR32:$src))),
1626 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1628 def : Pat<(i1 (trunc (i8 GR8:$src))),
1630 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1632 def : Pat<(i1 (trunc (i16 GR16:$src))),
1634 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1637 def : Pat<(i32 (zext VK1:$src)),
1638 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1639 def : Pat<(i8 (zext VK1:$src)),
1642 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1643 def : Pat<(i64 (zext VK1:$src)),
1644 (AND64ri8 (SUBREG_TO_REG (i64 0),
1645 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1646 def : Pat<(i16 (zext VK1:$src)),
1648 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1650 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1651 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1652 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1653 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1655 let Predicates = [HasBWI] in {
1656 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1657 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1658 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1659 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1663 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1664 let Predicates = [HasAVX512] in {
1665 // GR from/to 8-bit mask without native support
1666 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1668 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1670 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1672 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1675 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1676 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1677 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1678 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1680 let Predicates = [HasBWI] in {
1681 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1682 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1683 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1684 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1687 // Mask unary operation
1689 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1690 RegisterClass KRC, SDPatternOperator OpNode,
1692 let Predicates = [prd] in
1693 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1694 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1695 [(set KRC:$dst, (OpNode KRC:$src))]>;
1698 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1699 SDPatternOperator OpNode> {
1700 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1702 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1703 HasAVX512>, VEX, PS;
1704 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1705 HasBWI>, VEX, PD, VEX_W;
1706 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1707 HasBWI>, VEX, PS, VEX_W;
1710 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1712 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1713 let Predicates = [HasAVX512] in
1714 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1716 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1717 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1719 defm : avx512_mask_unop_int<"knot", "KNOT">;
1721 let Predicates = [HasDQI] in
1722 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1723 let Predicates = [HasAVX512] in
1724 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1725 let Predicates = [HasBWI] in
1726 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1727 let Predicates = [HasBWI] in
1728 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1730 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1731 let Predicates = [HasAVX512] in {
1732 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1733 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1735 def : Pat<(not VK8:$src),
1737 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1740 // Mask binary operation
1741 // - KAND, KANDN, KOR, KXNOR, KXOR
1742 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1743 RegisterClass KRC, SDPatternOperator OpNode,
1745 let Predicates = [prd] in
1746 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1747 !strconcat(OpcodeStr,
1748 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1749 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1752 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1753 SDPatternOperator OpNode> {
1754 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1755 HasDQI>, VEX_4V, VEX_L, PD;
1756 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1757 HasAVX512>, VEX_4V, VEX_L, PS;
1758 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1759 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1760 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1761 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1764 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1765 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1767 let isCommutable = 1 in {
1768 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1769 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1770 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1771 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1773 let isCommutable = 0 in
1774 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1776 def : Pat<(xor VK1:$src1, VK1:$src2),
1777 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1778 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1780 def : Pat<(or VK1:$src1, VK1:$src2),
1781 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1782 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1784 def : Pat<(and VK1:$src1, VK1:$src2),
1785 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1786 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1788 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1789 let Predicates = [HasAVX512] in
1790 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1791 (i16 GR16:$src1), (i16 GR16:$src2)),
1792 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1793 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1794 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1797 defm : avx512_mask_binop_int<"kand", "KAND">;
1798 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1799 defm : avx512_mask_binop_int<"kor", "KOR">;
1800 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1801 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1803 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1804 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1805 let Predicates = [HasAVX512] in
1806 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1808 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1809 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1812 defm : avx512_binop_pat<and, KANDWrr>;
1813 defm : avx512_binop_pat<andn, KANDNWrr>;
1814 defm : avx512_binop_pat<or, KORWrr>;
1815 defm : avx512_binop_pat<xnor, KXNORWrr>;
1816 defm : avx512_binop_pat<xor, KXORWrr>;
1819 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1820 RegisterClass KRC> {
1821 let Predicates = [HasAVX512] in
1822 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1823 !strconcat(OpcodeStr,
1824 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1827 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1828 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1832 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1833 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1834 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1835 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1838 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1839 let Predicates = [HasAVX512] in
1840 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1841 (i16 GR16:$src1), (i16 GR16:$src2)),
1842 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1843 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1844 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1846 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1849 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1851 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1852 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1853 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1854 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1857 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1858 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1862 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1864 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1865 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1866 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1869 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1871 let Predicates = [HasAVX512] in
1872 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1873 !strconcat(OpcodeStr,
1874 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1875 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1878 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1880 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1884 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1885 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1887 // Mask setting all 0s or 1s
1888 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1889 let Predicates = [HasAVX512] in
1890 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1891 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1892 [(set KRC:$dst, (VT Val))]>;
1895 multiclass avx512_mask_setop_w<PatFrag Val> {
1896 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1897 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1900 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1901 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1903 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1904 let Predicates = [HasAVX512] in {
1905 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1906 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1907 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1908 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1909 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1911 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1912 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1914 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1915 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1917 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1918 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1920 let Predicates = [HasVLX] in {
1921 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1922 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1923 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1924 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1925 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1926 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1927 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1928 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1931 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1932 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1934 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1935 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1936 //===----------------------------------------------------------------------===//
1937 // AVX-512 - Aligned and unaligned load and store
1940 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1941 RegisterClass KRC, RegisterClass RC,
1942 ValueType vt, ValueType zvt, X86MemOperand memop,
1943 Domain d, bit IsReMaterializable = 1> {
1944 let hasSideEffects = 0 in {
1945 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1946 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1948 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1949 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1950 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1952 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1953 SchedRW = [WriteLoad] in
1954 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1956 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1959 let AddedComplexity = 20 in {
1960 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1961 let hasSideEffects = 0 in
1962 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1963 (ins RC:$src0, KRC:$mask, RC:$src1),
1964 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1965 "${dst} {${mask}}, $src1}"),
1966 [(set RC:$dst, (vt (vselect KRC:$mask,
1970 let mayLoad = 1, SchedRW = [WriteLoad] in
1971 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1972 (ins RC:$src0, KRC:$mask, memop:$src1),
1973 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1974 "${dst} {${mask}}, $src1}"),
1977 (vt (bitconvert (ld_frag addr:$src1))),
1981 let mayLoad = 1, SchedRW = [WriteLoad] in
1982 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1983 (ins KRC:$mask, memop:$src),
1984 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1985 "${dst} {${mask}} {z}, $src}"),
1988 (vt (bitconvert (ld_frag addr:$src))),
1989 (vt (bitconvert (zvt immAllZerosV))))))],
1994 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1995 string elty, string elsz, string vsz512,
1996 string vsz256, string vsz128, Domain d,
1997 Predicate prd, bit IsReMaterializable = 1> {
1998 let Predicates = [prd] in
1999 defm Z : avx512_load<opc, OpcodeStr,
2000 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2001 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2002 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2003 !cast<X86MemOperand>(elty##"512mem"), d,
2004 IsReMaterializable>, EVEX_V512;
2006 let Predicates = [prd, HasVLX] in {
2007 defm Z256 : avx512_load<opc, OpcodeStr,
2008 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2009 "v"##vsz256##elty##elsz, "v4i64")),
2010 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2011 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2012 !cast<X86MemOperand>(elty##"256mem"), d,
2013 IsReMaterializable>, EVEX_V256;
2015 defm Z128 : avx512_load<opc, OpcodeStr,
2016 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2017 "v"##vsz128##elty##elsz, "v2i64")),
2018 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2019 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2020 !cast<X86MemOperand>(elty##"128mem"), d,
2021 IsReMaterializable>, EVEX_V128;
2026 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2027 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2028 X86MemOperand memop, Domain d> {
2029 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2030 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2031 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2033 let Constraints = "$src1 = $dst" in
2034 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2035 (ins RC:$src1, KRC:$mask, RC:$src2),
2036 !strconcat(OpcodeStr,
2037 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2039 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2040 (ins KRC:$mask, RC:$src),
2041 !strconcat(OpcodeStr,
2042 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2043 [], d>, EVEX, EVEX_KZ;
2045 let mayStore = 1 in {
2046 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2047 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2048 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2049 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2050 (ins memop:$dst, KRC:$mask, RC:$src),
2051 !strconcat(OpcodeStr,
2052 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2053 [], d>, EVEX, EVEX_K;
2058 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2059 string st_suff_512, string st_suff_256,
2060 string st_suff_128, string elty, string elsz,
2061 string vsz512, string vsz256, string vsz128,
2062 Domain d, Predicate prd> {
2063 let Predicates = [prd] in
2064 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2065 !cast<ValueType>("v"##vsz512##elty##elsz),
2066 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2067 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2069 let Predicates = [prd, HasVLX] in {
2070 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2071 !cast<ValueType>("v"##vsz256##elty##elsz),
2072 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2073 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2075 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2076 !cast<ValueType>("v"##vsz128##elty##elsz),
2077 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2078 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2082 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2083 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2084 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2085 "512", "256", "", "f", "32", "16", "8", "4",
2086 SSEPackedSingle, HasAVX512>,
2087 PS, EVEX_CD8<32, CD8VF>;
2089 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2090 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2091 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2092 "512", "256", "", "f", "64", "8", "4", "2",
2093 SSEPackedDouble, HasAVX512>,
2094 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2096 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2097 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2098 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2099 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2100 PS, EVEX_CD8<32, CD8VF>;
2102 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2103 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2104 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2105 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2106 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2108 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2109 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2110 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2112 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2113 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2114 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2116 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2118 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2120 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2122 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2125 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2126 (VMOVUPSZmrk addr:$ptr,
2127 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2128 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2130 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2131 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2132 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2134 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2135 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2137 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2138 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2140 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2141 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2143 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2144 (bc_v16f32 (v16i32 immAllZerosV)))),
2145 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2147 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2148 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2150 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2151 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2153 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2154 (bc_v8f64 (v16i32 immAllZerosV)))),
2155 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2157 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2158 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2160 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2161 "16", "8", "4", SSEPackedInt, HasAVX512>,
2162 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2163 "512", "256", "", "i", "32", "16", "8", "4",
2164 SSEPackedInt, HasAVX512>,
2165 PD, EVEX_CD8<32, CD8VF>;
2167 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2168 "8", "4", "2", SSEPackedInt, HasAVX512>,
2169 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2170 "512", "256", "", "i", "64", "8", "4", "2",
2171 SSEPackedInt, HasAVX512>,
2172 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2174 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2175 "64", "32", "16", SSEPackedInt, HasBWI>,
2176 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2177 "i", "8", "64", "32", "16", SSEPackedInt,
2178 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2180 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2181 "32", "16", "8", SSEPackedInt, HasBWI>,
2182 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2183 "i", "16", "32", "16", "8", SSEPackedInt,
2184 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2186 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2187 "16", "8", "4", SSEPackedInt, HasAVX512>,
2188 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2189 "i", "32", "16", "8", "4", SSEPackedInt,
2190 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2192 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2193 "8", "4", "2", SSEPackedInt, HasAVX512>,
2194 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2195 "i", "64", "8", "4", "2", SSEPackedInt,
2196 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2198 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2199 (v16i32 immAllZerosV), GR16:$mask)),
2200 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2202 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2203 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2204 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2206 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2208 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2210 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2212 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2215 let AddedComplexity = 20 in {
2216 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2217 (bc_v8i64 (v16i32 immAllZerosV)))),
2218 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2220 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2221 (v8i64 VR512:$src))),
2222 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2225 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2226 (v16i32 immAllZerosV))),
2227 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2229 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2230 (v16i32 VR512:$src))),
2231 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2234 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2235 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2237 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2238 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2240 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2241 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2243 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2244 (bc_v8i64 (v16i32 immAllZerosV)))),
2245 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2247 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2248 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2250 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2251 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2253 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2254 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2256 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2257 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2260 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2261 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2264 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2265 (VMOVDQU32Zmrk addr:$ptr,
2266 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2267 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2269 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2270 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2271 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2274 // Move Int Doubleword to Packed Double Int
2276 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2277 "vmovd\t{$src, $dst|$dst, $src}",
2279 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2281 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2282 "vmovd\t{$src, $dst|$dst, $src}",
2284 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2285 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2286 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2287 "vmovq\t{$src, $dst|$dst, $src}",
2289 (v2i64 (scalar_to_vector GR64:$src)))],
2290 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2291 let isCodeGenOnly = 1 in {
2292 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2293 "vmovq\t{$src, $dst|$dst, $src}",
2294 [(set FR64:$dst, (bitconvert GR64:$src))],
2295 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2296 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2297 "vmovq\t{$src, $dst|$dst, $src}",
2298 [(set GR64:$dst, (bitconvert FR64:$src))],
2299 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2301 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2302 "vmovq\t{$src, $dst|$dst, $src}",
2303 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2304 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2305 EVEX_CD8<64, CD8VT1>;
2307 // Move Int Doubleword to Single Scalar
2309 let isCodeGenOnly = 1 in {
2310 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2311 "vmovd\t{$src, $dst|$dst, $src}",
2312 [(set FR32X:$dst, (bitconvert GR32:$src))],
2313 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2315 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2316 "vmovd\t{$src, $dst|$dst, $src}",
2317 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2318 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2321 // Move doubleword from xmm register to r/m32
2323 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2324 "vmovd\t{$src, $dst|$dst, $src}",
2325 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2326 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2328 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2329 (ins i32mem:$dst, VR128X:$src),
2330 "vmovd\t{$src, $dst|$dst, $src}",
2331 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2332 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2333 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2335 // Move quadword from xmm1 register to r/m64
2337 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2338 "vmovq\t{$src, $dst|$dst, $src}",
2339 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2341 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2342 Requires<[HasAVX512, In64BitMode]>;
2344 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2345 (ins i64mem:$dst, VR128X:$src),
2346 "vmovq\t{$src, $dst|$dst, $src}",
2347 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2348 addr:$dst)], IIC_SSE_MOVDQ>,
2349 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2350 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2352 // Move Scalar Single to Double Int
2354 let isCodeGenOnly = 1 in {
2355 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2357 "vmovd\t{$src, $dst|$dst, $src}",
2358 [(set GR32:$dst, (bitconvert FR32X:$src))],
2359 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2360 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2361 (ins i32mem:$dst, FR32X:$src),
2362 "vmovd\t{$src, $dst|$dst, $src}",
2363 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2364 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2367 // Move Quadword Int to Packed Quadword Int
2369 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2371 "vmovq\t{$src, $dst|$dst, $src}",
2373 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2374 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2376 //===----------------------------------------------------------------------===//
2377 // AVX-512 MOVSS, MOVSD
2378 //===----------------------------------------------------------------------===//
2380 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2381 SDNode OpNode, ValueType vt,
2382 X86MemOperand x86memop, PatFrag mem_pat> {
2383 let hasSideEffects = 0 in {
2384 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2385 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2386 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2387 (scalar_to_vector RC:$src2))))],
2388 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2389 let Constraints = "$src1 = $dst" in
2390 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2391 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2393 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2394 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2395 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2396 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2397 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2399 let mayStore = 1 in {
2400 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2401 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2402 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2404 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2405 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2406 [], IIC_SSE_MOV_S_MR>,
2407 EVEX, VEX_LIG, EVEX_K;
2409 } //hasSideEffects = 0
2412 let ExeDomain = SSEPackedSingle in
2413 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2414 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2416 let ExeDomain = SSEPackedDouble in
2417 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2418 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2420 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2421 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2422 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2424 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2425 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2426 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2428 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2429 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2430 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2432 // For the disassembler
2433 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2434 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2435 (ins VR128X:$src1, FR32X:$src2),
2436 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2438 XS, EVEX_4V, VEX_LIG;
2439 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2440 (ins VR128X:$src1, FR64X:$src2),
2441 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2443 XD, EVEX_4V, VEX_LIG, VEX_W;
2446 let Predicates = [HasAVX512] in {
2447 let AddedComplexity = 15 in {
2448 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2449 // MOVS{S,D} to the lower bits.
2450 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2451 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2452 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2453 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2454 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2455 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2456 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2457 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2459 // Move low f32 and clear high bits.
2460 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2461 (SUBREG_TO_REG (i32 0),
2462 (VMOVSSZrr (v4f32 (V_SET0)),
2463 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2464 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2465 (SUBREG_TO_REG (i32 0),
2466 (VMOVSSZrr (v4i32 (V_SET0)),
2467 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2470 let AddedComplexity = 20 in {
2471 // MOVSSrm zeros the high parts of the register; represent this
2472 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2473 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2474 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2475 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2476 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2477 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2478 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2480 // MOVSDrm zeros the high parts of the register; represent this
2481 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2482 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2483 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2484 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2485 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2486 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2487 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2488 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2489 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2490 def : Pat<(v2f64 (X86vzload addr:$src)),
2491 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2493 // Represent the same patterns above but in the form they appear for
2495 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2496 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2497 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2498 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2499 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2500 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2501 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2502 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2503 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2505 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2506 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2507 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2508 FR32X:$src)), sub_xmm)>;
2509 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2510 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2511 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2512 FR64X:$src)), sub_xmm)>;
2513 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2514 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2515 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2517 // Move low f64 and clear high bits.
2518 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2519 (SUBREG_TO_REG (i32 0),
2520 (VMOVSDZrr (v2f64 (V_SET0)),
2521 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2523 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2524 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2525 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2527 // Extract and store.
2528 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2530 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2531 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2533 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2535 // Shuffle with VMOVSS
2536 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2537 (VMOVSSZrr (v4i32 VR128X:$src1),
2538 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2539 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2540 (VMOVSSZrr (v4f32 VR128X:$src1),
2541 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2544 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2545 (SUBREG_TO_REG (i32 0),
2546 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2547 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2549 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2550 (SUBREG_TO_REG (i32 0),
2551 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2552 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2555 // Shuffle with VMOVSD
2556 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2557 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2558 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2559 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2560 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2561 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2562 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2563 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2566 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2567 (SUBREG_TO_REG (i32 0),
2568 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2569 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2571 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2572 (SUBREG_TO_REG (i32 0),
2573 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2574 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2577 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2578 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2579 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2580 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2581 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2582 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2583 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2584 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2587 let AddedComplexity = 15 in
2588 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2590 "vmovq\t{$src, $dst|$dst, $src}",
2591 [(set VR128X:$dst, (v2i64 (X86vzmovl
2592 (v2i64 VR128X:$src))))],
2593 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2595 let AddedComplexity = 20 in
2596 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2598 "vmovq\t{$src, $dst|$dst, $src}",
2599 [(set VR128X:$dst, (v2i64 (X86vzmovl
2600 (loadv2i64 addr:$src))))],
2601 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2602 EVEX_CD8<8, CD8VT8>;
2604 let Predicates = [HasAVX512] in {
2605 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2606 let AddedComplexity = 20 in {
2607 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2608 (VMOVDI2PDIZrm addr:$src)>;
2609 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2610 (VMOV64toPQIZrr GR64:$src)>;
2611 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2612 (VMOVDI2PDIZrr GR32:$src)>;
2614 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2615 (VMOVDI2PDIZrm addr:$src)>;
2616 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2617 (VMOVDI2PDIZrm addr:$src)>;
2618 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2619 (VMOVZPQILo2PQIZrm addr:$src)>;
2620 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2621 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2622 def : Pat<(v2i64 (X86vzload addr:$src)),
2623 (VMOVZPQILo2PQIZrm addr:$src)>;
2626 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2627 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2628 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2629 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2630 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2631 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2632 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2635 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2636 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2638 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2639 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2641 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2642 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2644 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2645 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2647 //===----------------------------------------------------------------------===//
2648 // AVX-512 - Non-temporals
2649 //===----------------------------------------------------------------------===//
2650 let SchedRW = [WriteLoad] in {
2651 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2652 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2653 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2654 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2655 EVEX_CD8<64, CD8VF>;
2657 let Predicates = [HasAVX512, HasVLX] in {
2658 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2660 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2661 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2662 EVEX_CD8<64, CD8VF>;
2664 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2666 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2667 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2668 EVEX_CD8<64, CD8VF>;
2672 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2673 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2674 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2675 let SchedRW = [WriteStore], mayStore = 1,
2676 AddedComplexity = 400 in
2677 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2678 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2679 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2682 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2683 string elty, string elsz, string vsz512,
2684 string vsz256, string vsz128, Domain d,
2685 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2686 let Predicates = [prd] in
2687 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2688 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2689 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2692 let Predicates = [prd, HasVLX] in {
2693 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2694 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2695 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2698 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2699 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2700 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2705 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2706 "i", "64", "8", "4", "2", SSEPackedInt,
2707 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2709 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2710 "f", "64", "8", "4", "2", SSEPackedDouble,
2711 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2713 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2714 "f", "32", "16", "8", "4", SSEPackedSingle,
2715 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2717 //===----------------------------------------------------------------------===//
2718 // AVX-512 - Integer arithmetic
2720 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2721 X86VectorVTInfo _, OpndItins itins,
2722 bit IsCommutable = 0> {
2723 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2724 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2725 "$src2, $src1", "$src1, $src2",
2726 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2727 "", itins.rr, IsCommutable>,
2728 AVX512BIBase, EVEX_4V;
2731 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2732 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2733 "$src2, $src1", "$src1, $src2",
2734 (_.VT (OpNode _.RC:$src1,
2735 (bitconvert (_.LdFrag addr:$src2)))),
2737 AVX512BIBase, EVEX_4V;
2740 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2741 X86VectorVTInfo _, OpndItins itins,
2742 bit IsCommutable = 0> :
2743 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2745 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2746 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2747 "${src2}"##_.BroadcastStr##", $src1",
2748 "$src1, ${src2}"##_.BroadcastStr,
2749 (_.VT (OpNode _.RC:$src1,
2751 (_.ScalarLdFrag addr:$src2)))),
2753 AVX512BIBase, EVEX_4V, EVEX_B;
2756 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2757 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2758 Predicate prd, bit IsCommutable = 0> {
2759 let Predicates = [prd] in
2760 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2761 IsCommutable>, EVEX_V512;
2763 let Predicates = [prd, HasVLX] in {
2764 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2765 IsCommutable>, EVEX_V256;
2766 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2767 IsCommutable>, EVEX_V128;
2771 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2772 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2773 Predicate prd, bit IsCommutable = 0> {
2774 let Predicates = [prd] in
2775 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2776 IsCommutable>, EVEX_V512;
2778 let Predicates = [prd, HasVLX] in {
2779 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2780 IsCommutable>, EVEX_V256;
2781 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2782 IsCommutable>, EVEX_V128;
2786 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2787 OpndItins itins, Predicate prd,
2788 bit IsCommutable = 0> {
2789 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2790 itins, prd, IsCommutable>,
2791 VEX_W, EVEX_CD8<64, CD8VF>;
2794 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2795 OpndItins itins, Predicate prd,
2796 bit IsCommutable = 0> {
2797 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2798 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2801 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2802 OpndItins itins, Predicate prd,
2803 bit IsCommutable = 0> {
2804 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2805 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2808 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2809 OpndItins itins, Predicate prd,
2810 bit IsCommutable = 0> {
2811 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2812 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2815 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2816 SDNode OpNode, OpndItins itins, Predicate prd,
2817 bit IsCommutable = 0> {
2818 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2821 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2825 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2826 SDNode OpNode, OpndItins itins, Predicate prd,
2827 bit IsCommutable = 0> {
2828 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2831 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2835 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2836 bits<8> opc_d, bits<8> opc_q,
2837 string OpcodeStr, SDNode OpNode,
2838 OpndItins itins, bit IsCommutable = 0> {
2839 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2840 itins, HasAVX512, IsCommutable>,
2841 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2842 itins, HasBWI, IsCommutable>;
2845 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2846 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2847 PatFrag memop_frag, X86MemOperand x86memop,
2848 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2849 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2850 let isCommutable = IsCommutable in
2852 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2853 (ins RC:$src1, RC:$src2),
2854 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2856 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2857 (ins KRC:$mask, RC:$src1, RC:$src2),
2858 !strconcat(OpcodeStr,
2859 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2860 [], itins.rr>, EVEX_4V, EVEX_K;
2861 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2862 (ins KRC:$mask, RC:$src1, RC:$src2),
2863 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2864 "|$dst {${mask}} {z}, $src1, $src2}"),
2865 [], itins.rr>, EVEX_4V, EVEX_KZ;
2867 let mayLoad = 1 in {
2868 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2869 (ins RC:$src1, x86memop:$src2),
2870 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2872 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2873 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2874 !strconcat(OpcodeStr,
2875 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2876 [], itins.rm>, EVEX_4V, EVEX_K;
2877 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2878 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2879 !strconcat(OpcodeStr,
2880 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2881 [], itins.rm>, EVEX_4V, EVEX_KZ;
2882 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2883 (ins RC:$src1, x86scalar_mop:$src2),
2884 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2885 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2886 [], itins.rm>, EVEX_4V, EVEX_B;
2887 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2888 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2889 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2890 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2892 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2893 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2894 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2895 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2896 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2898 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2902 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2903 SSE_INTALU_ITINS_P, 1>;
2904 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2905 SSE_INTALU_ITINS_P, 0>;
2906 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2907 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2908 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2909 SSE_INTALU_ITINS_P, HasBWI, 1>;
2910 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2911 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2913 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2914 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2915 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2916 EVEX_CD8<64, CD8VF>, VEX_W;
2918 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2919 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2920 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2922 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2923 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2925 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2926 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2927 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2928 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2929 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2930 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2932 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2933 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2934 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2935 SSE_INTALU_ITINS_P, HasBWI, 1>;
2936 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2937 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2939 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2940 SSE_INTALU_ITINS_P, HasBWI, 1>;
2941 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2942 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2943 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2944 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2946 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2947 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2948 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2949 SSE_INTALU_ITINS_P, HasBWI, 1>;
2950 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2951 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2953 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2954 SSE_INTALU_ITINS_P, HasBWI, 1>;
2955 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2956 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2957 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2958 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2960 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2961 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2962 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2963 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2964 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2965 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2966 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2967 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2968 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2969 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2970 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2971 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2972 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2973 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2974 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2975 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2976 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2977 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2978 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2979 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2980 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2981 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2982 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2983 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2984 //===----------------------------------------------------------------------===//
2985 // AVX-512 - Unpack Instructions
2986 //===----------------------------------------------------------------------===//
2988 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2989 PatFrag mem_frag, RegisterClass RC,
2990 X86MemOperand x86memop, string asm,
2992 def rr : AVX512PI<opc, MRMSrcReg,
2993 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2995 (vt (OpNode RC:$src1, RC:$src2)))],
2997 def rm : AVX512PI<opc, MRMSrcMem,
2998 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3000 (vt (OpNode RC:$src1,
3001 (bitconvert (mem_frag addr:$src2)))))],
3005 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3006 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3007 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3008 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3009 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3010 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3011 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3012 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3013 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3014 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3015 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3016 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3018 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3019 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3020 X86MemOperand x86memop> {
3021 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3022 (ins RC:$src1, RC:$src2),
3023 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3024 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3025 IIC_SSE_UNPCK>, EVEX_4V;
3026 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3027 (ins RC:$src1, x86memop:$src2),
3028 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3029 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3030 (bitconvert (memop_frag addr:$src2)))))],
3031 IIC_SSE_UNPCK>, EVEX_4V;
3033 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3034 VR512, memopv16i32, i512mem>, EVEX_V512,
3035 EVEX_CD8<32, CD8VF>;
3036 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3037 VR512, memopv8i64, i512mem>, EVEX_V512,
3038 VEX_W, EVEX_CD8<64, CD8VF>;
3039 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3040 VR512, memopv16i32, i512mem>, EVEX_V512,
3041 EVEX_CD8<32, CD8VF>;
3042 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3043 VR512, memopv8i64, i512mem>, EVEX_V512,
3044 VEX_W, EVEX_CD8<64, CD8VF>;
3045 //===----------------------------------------------------------------------===//
3049 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3050 SDNode OpNode, PatFrag mem_frag,
3051 X86MemOperand x86memop, ValueType OpVT> {
3052 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3053 (ins RC:$src1, i8imm:$src2),
3054 !strconcat(OpcodeStr,
3055 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3057 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3059 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3060 (ins x86memop:$src1, i8imm:$src2),
3061 !strconcat(OpcodeStr,
3062 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3064 (OpVT (OpNode (mem_frag addr:$src1),
3065 (i8 imm:$src2))))]>, EVEX;
3068 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3069 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3071 //===----------------------------------------------------------------------===//
3072 // AVX-512 Logical Instructions
3073 //===----------------------------------------------------------------------===//
3075 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3076 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3077 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3078 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3079 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3080 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3081 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3082 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3084 //===----------------------------------------------------------------------===//
3085 // AVX-512 FP arithmetic
3086 //===----------------------------------------------------------------------===//
3088 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3090 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3091 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3092 EVEX_CD8<32, CD8VT1>;
3093 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3094 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3095 EVEX_CD8<64, CD8VT1>;
3098 let isCommutable = 1 in {
3099 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3100 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3101 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3102 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3104 let isCommutable = 0 in {
3105 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3106 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3109 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3110 X86VectorVTInfo _, bit IsCommutable> {
3111 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3112 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3113 "$src2, $src1", "$src1, $src2",
3114 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3115 let mayLoad = 1 in {
3116 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3117 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3118 "$src2, $src1", "$src1, $src2",
3119 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3120 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3121 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3122 "${src2}"##_.BroadcastStr##", $src1",
3123 "$src1, ${src2}"##_.BroadcastStr,
3124 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3125 (_.ScalarLdFrag addr:$src2))))>,
3130 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3131 bit IsCommutable = 0> {
3132 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3133 IsCommutable>, EVEX_V512, PS,
3134 EVEX_CD8<32, CD8VF>;
3135 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3136 IsCommutable>, EVEX_V512, PD, VEX_W,
3137 EVEX_CD8<64, CD8VF>;
3139 // Define only if AVX512VL feature is present.
3140 let Predicates = [HasVLX] in {
3141 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3142 IsCommutable>, EVEX_V128, PS,
3143 EVEX_CD8<32, CD8VF>;
3144 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3145 IsCommutable>, EVEX_V256, PS,
3146 EVEX_CD8<32, CD8VF>;
3147 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3148 IsCommutable>, EVEX_V128, PD, VEX_W,
3149 EVEX_CD8<64, CD8VF>;
3150 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3151 IsCommutable>, EVEX_V256, PD, VEX_W,
3152 EVEX_CD8<64, CD8VF>;
3156 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3157 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3158 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3159 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3160 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3161 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3163 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3164 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3165 (i16 -1), FROUND_CURRENT)),
3166 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3168 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3169 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3170 (i8 -1), FROUND_CURRENT)),
3171 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3173 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3174 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3175 (i16 -1), FROUND_CURRENT)),
3176 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3178 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3179 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3180 (i8 -1), FROUND_CURRENT)),
3181 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3182 //===----------------------------------------------------------------------===//
3183 // AVX-512 VPTESTM instructions
3184 //===----------------------------------------------------------------------===//
3186 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3187 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3188 SDNode OpNode, ValueType vt> {
3189 def rr : AVX512PI<opc, MRMSrcReg,
3190 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3192 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3193 SSEPackedInt>, EVEX_4V;
3194 def rm : AVX512PI<opc, MRMSrcMem,
3195 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3196 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3197 [(set KRC:$dst, (OpNode (vt RC:$src1),
3198 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3201 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3202 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3203 EVEX_CD8<32, CD8VF>;
3204 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3205 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3206 EVEX_CD8<64, CD8VF>;
3208 let Predicates = [HasCDI] in {
3209 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3210 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3211 EVEX_CD8<32, CD8VF>;
3212 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3213 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3214 EVEX_CD8<64, CD8VF>;
3217 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3218 (v16i32 VR512:$src2), (i16 -1))),
3219 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3221 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3222 (v8i64 VR512:$src2), (i8 -1))),
3223 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3225 //===----------------------------------------------------------------------===//
3226 // AVX-512 Shift instructions
3227 //===----------------------------------------------------------------------===//
3228 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3229 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3230 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3231 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3232 "$src2, $src1", "$src1, $src2",
3233 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3234 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3235 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3236 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3237 "$src2, $src1", "$src1, $src2",
3238 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3239 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3242 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3243 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3244 // src2 is always 128-bit
3245 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3246 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3247 "$src2, $src1", "$src1, $src2",
3248 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3249 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3250 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3251 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3252 "$src2, $src1", "$src1, $src2",
3253 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3254 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3257 multiclass avx512_varshift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3258 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3259 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3262 multiclass avx512_varshift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3264 defm D : avx512_varshift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3265 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3266 defm Q : avx512_varshift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3267 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3270 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3272 EVEX_V512, EVEX_CD8<32, CD8VF>;
3273 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3274 v8i64_info>, EVEX_V512,
3275 EVEX_CD8<64, CD8VF>, VEX_W;
3277 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3278 v16i32_info>, EVEX_V512,
3279 EVEX_CD8<32, CD8VF>;
3280 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3281 v8i64_info>, EVEX_V512,
3282 EVEX_CD8<64, CD8VF>, VEX_W;
3284 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3286 EVEX_V512, EVEX_CD8<32, CD8VF>;
3287 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3288 v8i64_info>, EVEX_V512,
3289 EVEX_CD8<64, CD8VF>, VEX_W;
3291 defm VPSRL : avx512_varshift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3292 defm VPSLL : avx512_varshift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3293 defm VPSRA : avx512_varshift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3295 //===-------------------------------------------------------------------===//
3296 // Variable Bit Shifts
3297 //===-------------------------------------------------------------------===//
3298 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3299 RegisterClass RC, ValueType vt,
3300 X86MemOperand x86memop, PatFrag mem_frag> {
3301 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3302 (ins RC:$src1, RC:$src2),
3303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3305 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3307 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3308 (ins RC:$src1, x86memop:$src2),
3309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3311 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3315 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3316 i512mem, memopv16i32>, EVEX_V512,
3317 EVEX_CD8<32, CD8VF>;
3318 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3319 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3320 EVEX_CD8<64, CD8VF>;
3321 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3322 i512mem, memopv16i32>, EVEX_V512,
3323 EVEX_CD8<32, CD8VF>;
3324 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3325 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3326 EVEX_CD8<64, CD8VF>;
3327 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3328 i512mem, memopv16i32>, EVEX_V512,
3329 EVEX_CD8<32, CD8VF>;
3330 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3331 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3332 EVEX_CD8<64, CD8VF>;
3334 //===----------------------------------------------------------------------===//
3335 // AVX-512 - MOVDDUP
3336 //===----------------------------------------------------------------------===//
3338 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3339 X86MemOperand x86memop, PatFrag memop_frag> {
3340 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3341 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3342 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3343 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3344 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3346 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3349 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3350 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3351 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3352 (VMOVDDUPZrm addr:$src)>;
3354 //===---------------------------------------------------------------------===//
3355 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3356 //===---------------------------------------------------------------------===//
3357 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3358 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3359 X86MemOperand x86memop> {
3360 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3361 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3362 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3364 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3366 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3369 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3370 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3371 EVEX_CD8<32, CD8VF>;
3372 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3373 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3374 EVEX_CD8<32, CD8VF>;
3376 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3377 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3378 (VMOVSHDUPZrm addr:$src)>;
3379 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3380 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3381 (VMOVSLDUPZrm addr:$src)>;
3383 //===----------------------------------------------------------------------===//
3384 // Move Low to High and High to Low packed FP Instructions
3385 //===----------------------------------------------------------------------===//
3386 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3387 (ins VR128X:$src1, VR128X:$src2),
3388 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3389 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3390 IIC_SSE_MOV_LH>, EVEX_4V;
3391 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3392 (ins VR128X:$src1, VR128X:$src2),
3393 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3394 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3395 IIC_SSE_MOV_LH>, EVEX_4V;
3397 let Predicates = [HasAVX512] in {
3399 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3400 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3401 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3402 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3405 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3406 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3409 //===----------------------------------------------------------------------===//
3410 // FMA - Fused Multiply Operations
3413 let Constraints = "$src1 = $dst" in {
3414 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3415 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3416 SDPatternOperator OpNode = null_frag> {
3417 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3418 (ins _.RC:$src2, _.RC:$src3),
3419 OpcodeStr, "$src3, $src2", "$src2, $src3",
3420 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3424 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3425 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3426 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3427 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3428 (_.MemOpFrag addr:$src3))))]>;
3429 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3430 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3431 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
3432 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3433 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3434 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3436 } // Constraints = "$src1 = $dst"
3438 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3439 string OpcodeStr, X86VectorVTInfo VTI,
3440 SDPatternOperator OpNode> {
3441 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3443 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3445 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3447 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3450 let ExeDomain = SSEPackedSingle in {
3451 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3452 v16f32_info, X86Fmadd>;
3453 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3454 v16f32_info, X86Fmsub>;
3455 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3456 v16f32_info, X86Fmaddsub>;
3457 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3458 v16f32_info, X86Fmsubadd>;
3459 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3460 v16f32_info, X86Fnmadd>;
3461 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3462 v16f32_info, X86Fnmsub>;
3464 let ExeDomain = SSEPackedDouble in {
3465 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3466 v8f64_info, X86Fmadd>, VEX_W;
3467 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3468 v8f64_info, X86Fmsub>, VEX_W;
3469 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3470 v8f64_info, X86Fmaddsub>, VEX_W;
3471 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3472 v8f64_info, X86Fmsubadd>, VEX_W;
3473 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3474 v8f64_info, X86Fnmadd>, VEX_W;
3475 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3476 v8f64_info, X86Fnmsub>, VEX_W;
3479 let Constraints = "$src1 = $dst" in {
3480 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3481 X86VectorVTInfo _> {
3483 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3484 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3485 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3486 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3488 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3489 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3490 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3491 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3493 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3494 (_.ScalarLdFrag addr:$src2))),
3495 _.RC:$src3))]>, EVEX_B;
3497 } // Constraints = "$src1 = $dst"
3500 let ExeDomain = SSEPackedSingle in {
3501 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3503 EVEX_V512, EVEX_CD8<32, CD8VF>;
3504 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3506 EVEX_V512, EVEX_CD8<32, CD8VF>;
3507 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3509 EVEX_V512, EVEX_CD8<32, CD8VF>;
3510 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3512 EVEX_V512, EVEX_CD8<32, CD8VF>;
3513 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3515 EVEX_V512, EVEX_CD8<32, CD8VF>;
3516 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3518 EVEX_V512, EVEX_CD8<32, CD8VF>;
3520 let ExeDomain = SSEPackedDouble in {
3521 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3523 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3524 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3526 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3527 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3529 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3530 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3532 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3533 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3535 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3536 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3538 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3542 let Constraints = "$src1 = $dst" in {
3543 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3544 RegisterClass RC, ValueType OpVT,
3545 X86MemOperand x86memop, Operand memop,
3547 let isCommutable = 1 in
3548 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3549 (ins RC:$src1, RC:$src2, RC:$src3),
3550 !strconcat(OpcodeStr,
3551 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3553 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3555 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3556 (ins RC:$src1, RC:$src2, f128mem:$src3),
3557 !strconcat(OpcodeStr,
3558 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3560 (OpVT (OpNode RC:$src2, RC:$src1,
3561 (mem_frag addr:$src3))))]>;
3564 } // Constraints = "$src1 = $dst"
3566 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3567 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3568 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3569 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3570 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3571 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3572 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3573 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3574 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3575 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3576 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3577 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3578 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3579 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3580 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3581 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3583 //===----------------------------------------------------------------------===//
3584 // AVX-512 Scalar convert from sign integer to float/double
3585 //===----------------------------------------------------------------------===//
3587 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3588 X86MemOperand x86memop, string asm> {
3589 let hasSideEffects = 0 in {
3590 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3591 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3594 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3595 (ins DstRC:$src1, x86memop:$src),
3596 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3598 } // hasSideEffects = 0
3600 let Predicates = [HasAVX512] in {
3601 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3602 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3603 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3604 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3605 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3606 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3607 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3608 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3610 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3611 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3612 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3613 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3614 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3615 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3616 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3617 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3619 def : Pat<(f32 (sint_to_fp GR32:$src)),
3620 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3621 def : Pat<(f32 (sint_to_fp GR64:$src)),
3622 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3623 def : Pat<(f64 (sint_to_fp GR32:$src)),
3624 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3625 def : Pat<(f64 (sint_to_fp GR64:$src)),
3626 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3628 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3629 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3630 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3631 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3632 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3633 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3634 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3635 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3637 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3638 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3639 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3640 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3641 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3642 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3643 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3644 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3646 def : Pat<(f32 (uint_to_fp GR32:$src)),
3647 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3648 def : Pat<(f32 (uint_to_fp GR64:$src)),
3649 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3650 def : Pat<(f64 (uint_to_fp GR32:$src)),
3651 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3652 def : Pat<(f64 (uint_to_fp GR64:$src)),
3653 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3656 //===----------------------------------------------------------------------===//
3657 // AVX-512 Scalar convert from float/double to integer
3658 //===----------------------------------------------------------------------===//
3659 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3660 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3662 let hasSideEffects = 0 in {
3663 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3664 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3665 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3666 Requires<[HasAVX512]>;
3668 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3669 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3670 Requires<[HasAVX512]>;
3671 } // hasSideEffects = 0
3673 let Predicates = [HasAVX512] in {
3674 // Convert float/double to signed/unsigned int 32/64
3675 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3676 ssmem, sse_load_f32, "cvtss2si">,
3677 XS, EVEX_CD8<32, CD8VT1>;
3678 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3679 ssmem, sse_load_f32, "cvtss2si">,
3680 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3681 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3682 ssmem, sse_load_f32, "cvtss2usi">,
3683 XS, EVEX_CD8<32, CD8VT1>;
3684 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3685 int_x86_avx512_cvtss2usi64, ssmem,
3686 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3687 EVEX_CD8<32, CD8VT1>;
3688 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3689 sdmem, sse_load_f64, "cvtsd2si">,
3690 XD, EVEX_CD8<64, CD8VT1>;
3691 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3692 sdmem, sse_load_f64, "cvtsd2si">,
3693 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3694 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3695 sdmem, sse_load_f64, "cvtsd2usi">,
3696 XD, EVEX_CD8<64, CD8VT1>;
3697 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3698 int_x86_avx512_cvtsd2usi64, sdmem,
3699 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3700 EVEX_CD8<64, CD8VT1>;
3702 let isCodeGenOnly = 1 in {
3703 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3704 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3705 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3706 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3707 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3708 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3709 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3710 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3711 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3712 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3713 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3714 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3716 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3717 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3718 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3719 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3720 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3721 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3722 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3723 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3724 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3725 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3726 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3727 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3728 } // isCodeGenOnly = 1
3730 // Convert float/double to signed/unsigned int 32/64 with truncation
3731 let isCodeGenOnly = 1 in {
3732 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3733 ssmem, sse_load_f32, "cvttss2si">,
3734 XS, EVEX_CD8<32, CD8VT1>;
3735 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3736 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3737 "cvttss2si">, XS, VEX_W,
3738 EVEX_CD8<32, CD8VT1>;
3739 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3740 sdmem, sse_load_f64, "cvttsd2si">, XD,
3741 EVEX_CD8<64, CD8VT1>;
3742 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3743 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3744 "cvttsd2si">, XD, VEX_W,
3745 EVEX_CD8<64, CD8VT1>;
3746 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3747 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3748 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3749 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3750 int_x86_avx512_cvttss2usi64, ssmem,
3751 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3752 EVEX_CD8<32, CD8VT1>;
3753 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3754 int_x86_avx512_cvttsd2usi,
3755 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3756 EVEX_CD8<64, CD8VT1>;
3757 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3758 int_x86_avx512_cvttsd2usi64, sdmem,
3759 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3760 EVEX_CD8<64, CD8VT1>;
3761 } // isCodeGenOnly = 1
3763 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3764 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3766 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3767 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3768 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3769 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3770 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3771 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3774 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3775 loadf32, "cvttss2si">, XS,
3776 EVEX_CD8<32, CD8VT1>;
3777 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3778 loadf32, "cvttss2usi">, XS,
3779 EVEX_CD8<32, CD8VT1>;
3780 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3781 loadf32, "cvttss2si">, XS, VEX_W,
3782 EVEX_CD8<32, CD8VT1>;
3783 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3784 loadf32, "cvttss2usi">, XS, VEX_W,
3785 EVEX_CD8<32, CD8VT1>;
3786 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3787 loadf64, "cvttsd2si">, XD,
3788 EVEX_CD8<64, CD8VT1>;
3789 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3790 loadf64, "cvttsd2usi">, XD,
3791 EVEX_CD8<64, CD8VT1>;
3792 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3793 loadf64, "cvttsd2si">, XD, VEX_W,
3794 EVEX_CD8<64, CD8VT1>;
3795 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3796 loadf64, "cvttsd2usi">, XD, VEX_W,
3797 EVEX_CD8<64, CD8VT1>;
3799 //===----------------------------------------------------------------------===//
3800 // AVX-512 Convert form float to double and back
3801 //===----------------------------------------------------------------------===//
3802 let hasSideEffects = 0 in {
3803 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3804 (ins FR32X:$src1, FR32X:$src2),
3805 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3806 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3808 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3809 (ins FR32X:$src1, f32mem:$src2),
3810 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3811 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3812 EVEX_CD8<32, CD8VT1>;
3814 // Convert scalar double to scalar single
3815 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3816 (ins FR64X:$src1, FR64X:$src2),
3817 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3818 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3820 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3821 (ins FR64X:$src1, f64mem:$src2),
3822 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3823 []>, EVEX_4V, VEX_LIG, VEX_W,
3824 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3827 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3828 Requires<[HasAVX512]>;
3829 def : Pat<(fextend (loadf32 addr:$src)),
3830 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3832 def : Pat<(extloadf32 addr:$src),
3833 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3834 Requires<[HasAVX512, OptForSize]>;
3836 def : Pat<(extloadf32 addr:$src),
3837 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3838 Requires<[HasAVX512, OptForSpeed]>;
3840 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3841 Requires<[HasAVX512]>;
3843 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3844 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3845 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3847 let hasSideEffects = 0 in {
3848 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3849 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3851 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3852 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3853 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3854 [], d>, EVEX, EVEX_B, EVEX_RC;
3856 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3857 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3859 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3860 } // hasSideEffects = 0
3863 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3864 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3865 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3867 let hasSideEffects = 0 in {
3868 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3869 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3871 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3873 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3874 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3876 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3877 } // hasSideEffects = 0
3880 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3881 memopv8f64, f512mem, v8f32, v8f64,
3882 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3883 EVEX_CD8<64, CD8VF>;
3885 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3886 memopv4f64, f256mem, v8f64, v8f32,
3887 SSEPackedDouble>, EVEX_V512, PS,
3888 EVEX_CD8<32, CD8VH>;
3889 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3890 (VCVTPS2PDZrm addr:$src)>;
3892 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3893 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3894 (VCVTPD2PSZrr VR512:$src)>;
3896 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3897 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3898 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3900 //===----------------------------------------------------------------------===//
3901 // AVX-512 Vector convert from sign integer to float/double
3902 //===----------------------------------------------------------------------===//
3904 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3905 memopv8i64, i512mem, v16f32, v16i32,
3906 SSEPackedSingle>, EVEX_V512, PS,
3907 EVEX_CD8<32, CD8VF>;
3909 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3910 memopv4i64, i256mem, v8f64, v8i32,
3911 SSEPackedDouble>, EVEX_V512, XS,
3912 EVEX_CD8<32, CD8VH>;
3914 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3915 memopv16f32, f512mem, v16i32, v16f32,
3916 SSEPackedSingle>, EVEX_V512, XS,
3917 EVEX_CD8<32, CD8VF>;
3919 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3920 memopv8f64, f512mem, v8i32, v8f64,
3921 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3922 EVEX_CD8<64, CD8VF>;
3924 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3925 memopv16f32, f512mem, v16i32, v16f32,
3926 SSEPackedSingle>, EVEX_V512, PS,
3927 EVEX_CD8<32, CD8VF>;
3929 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3930 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3931 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3932 (VCVTTPS2UDQZrr VR512:$src)>;
3934 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3935 memopv8f64, f512mem, v8i32, v8f64,
3936 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3937 EVEX_CD8<64, CD8VF>;
3939 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3940 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3941 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3942 (VCVTTPD2UDQZrr VR512:$src)>;
3944 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3945 memopv4i64, f256mem, v8f64, v8i32,
3946 SSEPackedDouble>, EVEX_V512, XS,
3947 EVEX_CD8<32, CD8VH>;
3949 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3950 memopv16i32, f512mem, v16f32, v16i32,
3951 SSEPackedSingle>, EVEX_V512, XD,
3952 EVEX_CD8<32, CD8VF>;
3954 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3955 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3956 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3958 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3959 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3960 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3962 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3963 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3964 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3966 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3967 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3968 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3970 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3971 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3972 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3974 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3975 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3976 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3977 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3978 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3979 (VCVTDQ2PDZrr VR256X:$src)>;
3980 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3981 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3982 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3983 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3984 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3985 (VCVTUDQ2PDZrr VR256X:$src)>;
3987 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3988 RegisterClass DstRC, PatFrag mem_frag,
3989 X86MemOperand x86memop, Domain d> {
3990 let hasSideEffects = 0 in {
3991 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3992 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3994 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3995 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3996 [], d>, EVEX, EVEX_B, EVEX_RC;
3998 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3999 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4001 } // hasSideEffects = 0
4004 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4005 memopv16f32, f512mem, SSEPackedSingle>, PD,
4006 EVEX_V512, EVEX_CD8<32, CD8VF>;
4007 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4008 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4009 EVEX_V512, EVEX_CD8<64, CD8VF>;
4011 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4012 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4013 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4015 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4016 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4017 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4019 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4020 memopv16f32, f512mem, SSEPackedSingle>,
4021 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4022 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4023 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4024 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4026 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4027 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4028 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4030 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4031 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4032 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4034 let Predicates = [HasAVX512] in {
4035 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4036 (VCVTPD2PSZrm addr:$src)>;
4037 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4038 (VCVTPS2PDZrm addr:$src)>;
4041 //===----------------------------------------------------------------------===//
4042 // Half precision conversion instructions
4043 //===----------------------------------------------------------------------===//
4044 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4045 X86MemOperand x86memop> {
4046 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4047 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4049 let hasSideEffects = 0, mayLoad = 1 in
4050 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4051 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4054 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4055 X86MemOperand x86memop> {
4056 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4057 (ins srcRC:$src1, i32i8imm:$src2),
4058 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4060 let hasSideEffects = 0, mayStore = 1 in
4061 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4062 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4063 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4066 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4067 EVEX_CD8<32, CD8VH>;
4068 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4069 EVEX_CD8<32, CD8VH>;
4071 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4072 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4073 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4075 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4076 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4077 (VCVTPH2PSZrr VR256X:$src)>;
4079 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4080 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4081 "ucomiss">, PS, EVEX, VEX_LIG,
4082 EVEX_CD8<32, CD8VT1>;
4083 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4084 "ucomisd">, PD, EVEX,
4085 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4086 let Pattern = []<dag> in {
4087 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4088 "comiss">, PS, EVEX, VEX_LIG,
4089 EVEX_CD8<32, CD8VT1>;
4090 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4091 "comisd">, PD, EVEX,
4092 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4094 let isCodeGenOnly = 1 in {
4095 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4096 load, "ucomiss">, PS, EVEX, VEX_LIG,
4097 EVEX_CD8<32, CD8VT1>;
4098 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4099 load, "ucomisd">, PD, EVEX,
4100 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4102 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4103 load, "comiss">, PS, EVEX, VEX_LIG,
4104 EVEX_CD8<32, CD8VT1>;
4105 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4106 load, "comisd">, PD, EVEX,
4107 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4111 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4112 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4113 X86MemOperand x86memop> {
4114 let hasSideEffects = 0 in {
4115 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4116 (ins RC:$src1, RC:$src2),
4117 !strconcat(OpcodeStr,
4118 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4119 let mayLoad = 1 in {
4120 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4121 (ins RC:$src1, x86memop:$src2),
4122 !strconcat(OpcodeStr,
4123 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4128 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4129 EVEX_CD8<32, CD8VT1>;
4130 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4131 VEX_W, EVEX_CD8<64, CD8VT1>;
4132 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4133 EVEX_CD8<32, CD8VT1>;
4134 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4135 VEX_W, EVEX_CD8<64, CD8VT1>;
4137 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4138 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4139 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4140 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4142 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4143 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4144 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4145 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4147 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4148 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4149 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4150 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4152 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4153 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4154 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4155 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4157 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4158 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4159 X86VectorVTInfo _> {
4160 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4161 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4162 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4163 let mayLoad = 1 in {
4164 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4165 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4167 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4168 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4169 (ins _.ScalarMemOp:$src), OpcodeStr,
4170 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4172 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4177 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4178 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4179 EVEX_V512, EVEX_CD8<32, CD8VF>;
4180 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4181 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4183 // Define only if AVX512VL feature is present.
4184 let Predicates = [HasVLX] in {
4185 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4186 OpNode, v4f32x_info>,
4187 EVEX_V128, EVEX_CD8<32, CD8VF>;
4188 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4189 OpNode, v8f32x_info>,
4190 EVEX_V256, EVEX_CD8<32, CD8VF>;
4191 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4192 OpNode, v2f64x_info>,
4193 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4194 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4195 OpNode, v4f64x_info>,
4196 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4200 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4201 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4203 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4204 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4205 (VRSQRT14PSZr VR512:$src)>;
4206 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4207 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4208 (VRSQRT14PDZr VR512:$src)>;
4210 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4211 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4212 (VRCP14PSZr VR512:$src)>;
4213 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4214 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4215 (VRCP14PDZr VR512:$src)>;
4217 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4218 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4221 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4222 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4223 "$src2, $src1", "$src1, $src2",
4224 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4225 (i32 FROUND_CURRENT))>;
4227 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4228 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4229 "$src2, $src1", "$src1, $src2",
4230 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4231 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4233 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4234 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4235 "$src2, $src1", "$src1, $src2",
4236 (OpNode (_.VT _.RC:$src1),
4237 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4238 (i32 FROUND_CURRENT))>;
4241 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4242 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4243 EVEX_CD8<32, CD8VT1>;
4244 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4245 EVEX_CD8<64, CD8VT1>, VEX_W;
4248 let hasSideEffects = 0, Predicates = [HasERI] in {
4249 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4250 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4252 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4254 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4257 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4258 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4259 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4261 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4262 (ins _.RC:$src), OpcodeStr,
4264 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4267 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4268 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4270 (bitconvert (_.LdFrag addr:$src))),
4271 (i32 FROUND_CURRENT))>;
4273 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4274 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4276 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4277 (i32 FROUND_CURRENT))>, EVEX_B;
4280 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4281 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4282 EVEX_CD8<32, CD8VF>;
4283 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4284 VEX_W, EVEX_CD8<32, CD8VF>;
4287 let Predicates = [HasERI], hasSideEffects = 0 in {
4289 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4290 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4291 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4294 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4295 SDNode OpNode, X86VectorVTInfo _>{
4296 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4297 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4298 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4299 let mayLoad = 1 in {
4300 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4301 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4303 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4305 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4306 (ins _.ScalarMemOp:$src), OpcodeStr,
4307 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4309 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4314 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4315 Intrinsic F32Int, Intrinsic F64Int,
4316 OpndItins itins_s, OpndItins itins_d> {
4317 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4318 (ins FR32X:$src1, FR32X:$src2),
4319 !strconcat(OpcodeStr,
4320 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4321 [], itins_s.rr>, XS, EVEX_4V;
4322 let isCodeGenOnly = 1 in
4323 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4324 (ins VR128X:$src1, VR128X:$src2),
4325 !strconcat(OpcodeStr,
4326 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4328 (F32Int VR128X:$src1, VR128X:$src2))],
4329 itins_s.rr>, XS, EVEX_4V;
4330 let mayLoad = 1 in {
4331 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4332 (ins FR32X:$src1, f32mem:$src2),
4333 !strconcat(OpcodeStr,
4334 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4335 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4336 let isCodeGenOnly = 1 in
4337 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4338 (ins VR128X:$src1, ssmem:$src2),
4339 !strconcat(OpcodeStr,
4340 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4342 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4343 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4345 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4346 (ins FR64X:$src1, FR64X:$src2),
4347 !strconcat(OpcodeStr,
4348 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4350 let isCodeGenOnly = 1 in
4351 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4352 (ins VR128X:$src1, VR128X:$src2),
4353 !strconcat(OpcodeStr,
4354 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4356 (F64Int VR128X:$src1, VR128X:$src2))],
4357 itins_s.rr>, XD, EVEX_4V, VEX_W;
4358 let mayLoad = 1 in {
4359 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4360 (ins FR64X:$src1, f64mem:$src2),
4361 !strconcat(OpcodeStr,
4362 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4363 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4364 let isCodeGenOnly = 1 in
4365 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4366 (ins VR128X:$src1, sdmem:$src2),
4367 !strconcat(OpcodeStr,
4368 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4370 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4371 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4375 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4377 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4379 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4380 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4382 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4383 // Define only if AVX512VL feature is present.
4384 let Predicates = [HasVLX] in {
4385 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4386 OpNode, v4f32x_info>,
4387 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4388 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4389 OpNode, v8f32x_info>,
4390 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4391 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4392 OpNode, v2f64x_info>,
4393 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4394 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4395 OpNode, v4f64x_info>,
4396 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4400 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4402 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4403 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4404 SSE_SQRTSS, SSE_SQRTSD>;
4406 let Predicates = [HasAVX512] in {
4407 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4408 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4409 (VSQRTPSZr VR512:$src1)>;
4410 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4411 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4412 (VSQRTPDZr VR512:$src1)>;
4414 def : Pat<(f32 (fsqrt FR32X:$src)),
4415 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4416 def : Pat<(f32 (fsqrt (load addr:$src))),
4417 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4418 Requires<[OptForSize]>;
4419 def : Pat<(f64 (fsqrt FR64X:$src)),
4420 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4421 def : Pat<(f64 (fsqrt (load addr:$src))),
4422 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4423 Requires<[OptForSize]>;
4425 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4426 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4427 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4428 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4429 Requires<[OptForSize]>;
4431 def : Pat<(f32 (X86frcp FR32X:$src)),
4432 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4433 def : Pat<(f32 (X86frcp (load addr:$src))),
4434 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4435 Requires<[OptForSize]>;
4437 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4438 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4439 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4441 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4442 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4444 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4445 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4446 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4448 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4449 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4453 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4454 X86MemOperand x86memop, RegisterClass RC,
4455 PatFrag mem_frag32, PatFrag mem_frag64,
4456 Intrinsic V4F32Int, Intrinsic V2F64Int,
4458 let ExeDomain = SSEPackedSingle in {
4459 // Intrinsic operation, reg.
4460 // Vector intrinsic operation, reg
4461 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4462 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4463 !strconcat(OpcodeStr,
4464 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4465 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4467 // Vector intrinsic operation, mem
4468 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4469 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4470 !strconcat(OpcodeStr,
4471 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4473 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4474 EVEX_CD8<32, VForm>;
4475 } // ExeDomain = SSEPackedSingle
4477 let ExeDomain = SSEPackedDouble in {
4478 // Vector intrinsic operation, reg
4479 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4480 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4481 !strconcat(OpcodeStr,
4482 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4483 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4485 // Vector intrinsic operation, mem
4486 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4487 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4488 !strconcat(OpcodeStr,
4489 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4491 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4492 EVEX_CD8<64, VForm>;
4493 } // ExeDomain = SSEPackedDouble
4496 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4500 let ExeDomain = GenericDomain in {
4502 let hasSideEffects = 0 in
4503 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4504 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4505 !strconcat(OpcodeStr,
4506 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4509 // Intrinsic operation, reg.
4510 let isCodeGenOnly = 1 in
4511 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4512 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4513 !strconcat(OpcodeStr,
4514 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4515 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4517 // Intrinsic operation, mem.
4518 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4519 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4520 !strconcat(OpcodeStr,
4521 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4522 [(set VR128X:$dst, (F32Int VR128X:$src1,
4523 sse_load_f32:$src2, imm:$src3))]>,
4524 EVEX_CD8<32, CD8VT1>;
4527 let hasSideEffects = 0 in
4528 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4529 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4530 !strconcat(OpcodeStr,
4531 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4534 // Intrinsic operation, reg.
4535 let isCodeGenOnly = 1 in
4536 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4537 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4538 !strconcat(OpcodeStr,
4539 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4540 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4543 // Intrinsic operation, mem.
4544 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4545 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4546 !strconcat(OpcodeStr,
4547 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4549 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4550 VEX_W, EVEX_CD8<64, CD8VT1>;
4551 } // ExeDomain = GenericDomain
4554 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4555 X86MemOperand x86memop, RegisterClass RC,
4556 PatFrag mem_frag, Domain d> {
4557 let ExeDomain = d in {
4558 // Intrinsic operation, reg.
4559 // Vector intrinsic operation, reg
4560 def r : AVX512AIi8<opc, MRMSrcReg,
4561 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4562 !strconcat(OpcodeStr,
4563 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4566 // Vector intrinsic operation, mem
4567 def m : AVX512AIi8<opc, MRMSrcMem,
4568 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4569 !strconcat(OpcodeStr,
4570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4576 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4577 memopv16f32, SSEPackedSingle>, EVEX_V512,
4578 EVEX_CD8<32, CD8VF>;
4580 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4581 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4583 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4586 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4587 memopv8f64, SSEPackedDouble>, EVEX_V512,
4588 VEX_W, EVEX_CD8<64, CD8VF>;
4590 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4591 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4593 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4595 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4596 Operand x86memop, RegisterClass RC, Domain d> {
4597 let ExeDomain = d in {
4598 def r : AVX512AIi8<opc, MRMSrcReg,
4599 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4600 !strconcat(OpcodeStr,
4601 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4604 def m : AVX512AIi8<opc, MRMSrcMem,
4605 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4606 !strconcat(OpcodeStr,
4607 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4612 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4613 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4615 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4616 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4618 def : Pat<(ffloor FR32X:$src),
4619 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4620 def : Pat<(f64 (ffloor FR64X:$src)),
4621 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4622 def : Pat<(f32 (fnearbyint FR32X:$src)),
4623 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4624 def : Pat<(f64 (fnearbyint FR64X:$src)),
4625 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4626 def : Pat<(f32 (fceil FR32X:$src)),
4627 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4628 def : Pat<(f64 (fceil FR64X:$src)),
4629 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4630 def : Pat<(f32 (frint FR32X:$src)),
4631 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4632 def : Pat<(f64 (frint FR64X:$src)),
4633 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4634 def : Pat<(f32 (ftrunc FR32X:$src)),
4635 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4636 def : Pat<(f64 (ftrunc FR64X:$src)),
4637 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4639 def : Pat<(v16f32 (ffloor VR512:$src)),
4640 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4641 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4642 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4643 def : Pat<(v16f32 (fceil VR512:$src)),
4644 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4645 def : Pat<(v16f32 (frint VR512:$src)),
4646 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4647 def : Pat<(v16f32 (ftrunc VR512:$src)),
4648 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4650 def : Pat<(v8f64 (ffloor VR512:$src)),
4651 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4652 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4653 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4654 def : Pat<(v8f64 (fceil VR512:$src)),
4655 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4656 def : Pat<(v8f64 (frint VR512:$src)),
4657 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4658 def : Pat<(v8f64 (ftrunc VR512:$src)),
4659 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4661 //-------------------------------------------------
4662 // Integer truncate and extend operations
4663 //-------------------------------------------------
4665 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4666 RegisterClass dstRC, RegisterClass srcRC,
4667 RegisterClass KRC, X86MemOperand x86memop> {
4668 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4670 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4673 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4674 (ins KRC:$mask, srcRC:$src),
4675 !strconcat(OpcodeStr,
4676 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4679 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4680 (ins KRC:$mask, srcRC:$src),
4681 !strconcat(OpcodeStr,
4682 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4685 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4686 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4689 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4690 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4691 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4695 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4696 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4697 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4698 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4699 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4700 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4701 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4702 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4703 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4704 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4705 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4706 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4707 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4708 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4709 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4710 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4711 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4712 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4713 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4714 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4715 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4716 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4717 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4718 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4719 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4720 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4721 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4722 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4723 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4724 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4726 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4727 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4728 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4729 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4730 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4732 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4733 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4734 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4735 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4736 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4737 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4738 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4739 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4742 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4743 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4744 PatFrag mem_frag, X86MemOperand x86memop,
4745 ValueType OpVT, ValueType InVT> {
4747 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4749 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4750 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4752 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4753 (ins KRC:$mask, SrcRC:$src),
4754 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4757 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4758 (ins KRC:$mask, SrcRC:$src),
4759 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4762 let mayLoad = 1 in {
4763 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4764 (ins x86memop:$src),
4765 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4767 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4770 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4771 (ins KRC:$mask, x86memop:$src),
4772 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4776 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4777 (ins KRC:$mask, x86memop:$src),
4778 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4784 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4785 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4787 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4788 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4790 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4791 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4792 EVEX_CD8<16, CD8VH>;
4793 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4794 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4795 EVEX_CD8<16, CD8VQ>;
4796 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4797 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4798 EVEX_CD8<32, CD8VH>;
4800 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4801 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4803 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4804 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4806 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4807 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4808 EVEX_CD8<16, CD8VH>;
4809 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4810 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4811 EVEX_CD8<16, CD8VQ>;
4812 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4813 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4814 EVEX_CD8<32, CD8VH>;
4816 //===----------------------------------------------------------------------===//
4817 // GATHER - SCATTER Operations
4819 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4820 RegisterClass RC, X86MemOperand memop> {
4822 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4823 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4824 (ins RC:$src1, KRC:$mask, memop:$src2),
4825 !strconcat(OpcodeStr,
4826 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4830 let ExeDomain = SSEPackedDouble in {
4831 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4832 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4833 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4834 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4837 let ExeDomain = SSEPackedSingle in {
4838 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4839 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4840 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4841 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4844 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4845 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4846 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4847 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4849 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4850 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4851 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4852 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4854 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4855 RegisterClass RC, X86MemOperand memop> {
4856 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4857 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4858 (ins memop:$dst, KRC:$mask, RC:$src2),
4859 !strconcat(OpcodeStr,
4860 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4864 let ExeDomain = SSEPackedDouble in {
4865 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4866 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4867 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4868 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4871 let ExeDomain = SSEPackedSingle in {
4872 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4873 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4874 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4875 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4878 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4879 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4880 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4881 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4883 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4884 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4885 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4886 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4889 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4890 RegisterClass KRC, X86MemOperand memop> {
4891 let Predicates = [HasPFI], hasSideEffects = 1 in
4892 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4893 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4897 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4898 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4900 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4901 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4903 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4904 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4906 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4907 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4909 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4910 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4912 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4913 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4915 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4916 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4918 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4919 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4921 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4922 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4924 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4925 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4927 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4928 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4930 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4931 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4933 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4934 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4936 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4937 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4939 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4940 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4942 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4943 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4944 //===----------------------------------------------------------------------===//
4945 // VSHUFPS - VSHUFPD Operations
4947 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4948 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4950 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4951 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4952 !strconcat(OpcodeStr,
4953 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4954 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4955 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4956 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4957 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4958 (ins RC:$src1, RC:$src2, i8imm:$src3),
4959 !strconcat(OpcodeStr,
4960 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4961 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4962 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4963 EVEX_4V, Sched<[WriteShuffle]>;
4966 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4967 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4968 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4969 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4971 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4972 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4973 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4974 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4975 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4977 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4978 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4979 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4980 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4981 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4983 multiclass avx512_valign<X86VectorVTInfo _> {
4984 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4985 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4987 "$src3, $src2, $src1", "$src1, $src2, $src3",
4988 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4990 AVX512AIi8Base, EVEX_4V;
4992 // Also match valign of packed floats.
4993 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4994 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4997 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4998 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4999 !strconcat("valign"##_.Suffix,
5000 "\t{$src3, $src2, $src1, $dst|"
5001 "$dst, $src1, $src2, $src3}"),
5004 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5005 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5007 // Helper fragments to match sext vXi1 to vXiY.
5008 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5009 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5011 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5012 RegisterClass KRC, RegisterClass RC,
5013 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5015 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5016 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5018 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5019 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5021 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5022 !strconcat(OpcodeStr,
5023 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5025 let mayLoad = 1 in {
5026 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5027 (ins x86memop:$src),
5028 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5030 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5031 (ins KRC:$mask, x86memop:$src),
5032 !strconcat(OpcodeStr,
5033 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5035 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5036 (ins KRC:$mask, x86memop:$src),
5037 !strconcat(OpcodeStr,
5038 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5040 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5041 (ins x86scalar_mop:$src),
5042 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5043 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5045 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5046 (ins KRC:$mask, x86scalar_mop:$src),
5047 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5048 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5049 []>, EVEX, EVEX_B, EVEX_K;
5050 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5051 (ins KRC:$mask, x86scalar_mop:$src),
5052 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5053 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5055 []>, EVEX, EVEX_B, EVEX_KZ;
5059 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5060 i512mem, i32mem, "{1to16}">, EVEX_V512,
5061 EVEX_CD8<32, CD8VF>;
5062 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5063 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5064 EVEX_CD8<64, CD8VF>;
5067 (bc_v16i32 (v16i1sextv16i32)),
5068 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5069 (VPABSDZrr VR512:$src)>;
5071 (bc_v8i64 (v8i1sextv8i64)),
5072 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5073 (VPABSQZrr VR512:$src)>;
5075 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5076 (v16i32 immAllZerosV), (i16 -1))),
5077 (VPABSDZrr VR512:$src)>;
5078 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5079 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5080 (VPABSQZrr VR512:$src)>;
5082 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5083 RegisterClass RC, RegisterClass KRC,
5084 X86MemOperand x86memop,
5085 X86MemOperand x86scalar_mop, string BrdcstStr> {
5086 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5088 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5090 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5091 (ins x86memop:$src),
5092 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5094 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5095 (ins x86scalar_mop:$src),
5096 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5097 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5099 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5100 (ins KRC:$mask, RC:$src),
5101 !strconcat(OpcodeStr,
5102 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5104 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5105 (ins KRC:$mask, x86memop:$src),
5106 !strconcat(OpcodeStr,
5107 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5109 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5110 (ins KRC:$mask, x86scalar_mop:$src),
5111 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5112 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5114 []>, EVEX, EVEX_KZ, EVEX_B;
5116 let Constraints = "$src1 = $dst" in {
5117 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5118 (ins RC:$src1, KRC:$mask, RC:$src2),
5119 !strconcat(OpcodeStr,
5120 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5122 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5123 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5124 !strconcat(OpcodeStr,
5125 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5127 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5128 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5129 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5130 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5131 []>, EVEX, EVEX_K, EVEX_B;
5135 let Predicates = [HasCDI] in {
5136 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5137 i512mem, i32mem, "{1to16}">,
5138 EVEX_V512, EVEX_CD8<32, CD8VF>;
5141 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5142 i512mem, i64mem, "{1to8}">,
5143 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5147 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5149 (VPCONFLICTDrrk VR512:$src1,
5150 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5152 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5154 (VPCONFLICTQrrk VR512:$src1,
5155 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5157 let Predicates = [HasCDI] in {
5158 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5159 i512mem, i32mem, "{1to16}">,
5160 EVEX_V512, EVEX_CD8<32, CD8VF>;
5163 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5164 i512mem, i64mem, "{1to8}">,
5165 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5169 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5171 (VPLZCNTDrrk VR512:$src1,
5172 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5174 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5176 (VPLZCNTQrrk VR512:$src1,
5177 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5179 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5180 (VPLZCNTDrm addr:$src)>;
5181 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5182 (VPLZCNTDrr VR512:$src)>;
5183 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5184 (VPLZCNTQrm addr:$src)>;
5185 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5186 (VPLZCNTQrr VR512:$src)>;
5188 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5189 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5190 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5192 def : Pat<(store VK1:$src, addr:$dst),
5193 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5195 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5196 (truncstore node:$val, node:$ptr), [{
5197 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5200 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5201 (MOV8mr addr:$dst, GR8:$src)>;
5203 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5204 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5205 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5206 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5209 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5210 string OpcodeStr, Predicate prd> {
5211 let Predicates = [prd] in
5212 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5214 let Predicates = [prd, HasVLX] in {
5215 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5216 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5220 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5221 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5223 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5225 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5227 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5231 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;