1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
11 // Corresponding mask register class.
12 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
14 // Corresponding write-mask register class.
15 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
17 // The GPR register class that can hold the write mask. Use GR8 for fewer
18 // than 8 elements. Use shift-right and equal to work around the lack of
21 !cast<RegisterClass>("GR" #
22 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
24 // Suffix used in the instruction mnemonic.
25 string Suffix = suffix;
27 // VTName is a string name for vector VT. For vector types it will be
28 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
29 // It is a little bit complex for scalar types, where NumElts = 1.
30 // In this case we build v4f32 or v2f64
31 string VTName = "v" # !if (!eq (NumElts, 1),
32 !if (!eq (EltVT.Size, 32), 4,
33 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
36 ValueType VT = !cast<ValueType>(VTName);
38 string EltTypeName = !cast<string>(EltVT);
39 // Size of the element type in bits, e.g. 32 for v16i32.
40 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
41 int EltSize = EltVT.Size;
43 // "i" for integer types and "f" for floating-point types
44 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
46 // Size of RC in bits, e.g. 512 for VR512.
49 // The corresponding memory operand, e.g. i512mem for VR512.
50 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
51 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
54 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
55 // due to load promotion during legalization
56 PatFrag LdFrag = !cast<PatFrag>("load" #
57 !if (!eq (TypeVariantName, "i"),
58 !if (!eq (Size, 128), "v2i64",
59 !if (!eq (Size, 256), "v4i64",
61 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
63 // Load patterns used for memory operands. We only have this defined in
64 // case of i64 element types for sub-512 integer vectors. For now, keep
65 // MemOpFrag undefined in these cases.
67 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
68 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
69 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
70 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
73 // The corresponding float type, e.g. v16f32 for v16i32
74 // Note: For EltSize < 32, FloatVT is illegal and TableGen
75 // fails to compile, so we choose FloatVT = VT
76 ValueType FloatVT = !cast<ValueType>(
77 !if (!eq (!srl(EltSize,5),0),
79 !if (!eq(TypeVariantName, "i"),
80 "v" # NumElts # "f" # EltSize,
83 // The string to specify embedded broadcast in assembly.
84 string BroadcastStr = "{1to" # NumElts # "}";
86 // 8-bit compressed displacement tuple/subvector format. This is only
87 // defined for NumElts <= 8.
88 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
89 !cast<CD8VForm>("CD8VT" # NumElts), ?);
91 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
92 !if (!eq (Size, 256), sub_ymm, ?));
94 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
95 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
98 // A vector type of the same width with element type i32. This is used to
99 // create the canonical constant zero node ImmAllZerosV.
100 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
101 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
104 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
105 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
106 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
107 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
108 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
109 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
111 // "x" in v32i8x_info means RC = VR256X
112 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
113 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
114 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
115 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
116 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
117 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
119 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
120 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
121 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
122 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
123 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
124 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
126 // We map scalar types to the smallest (128-bit) vector type
127 // with the appropriate element type. This allows to use the same masking logic.
128 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
129 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
131 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
132 X86VectorVTInfo i128> {
133 X86VectorVTInfo info512 = i512;
134 X86VectorVTInfo info256 = i256;
135 X86VectorVTInfo info128 = i128;
138 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
140 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
142 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
144 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
146 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
148 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
151 // This multiclass generates the masking variants from the non-masking
152 // variant. It only provides the assembly pieces for the masking variants.
153 // It assumes custom ISel patterns for masking which can be provided as
154 // template arguments.
155 multiclass AVX512_maskable_custom<bits<8> O, Format F,
157 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
159 string AttSrcAsm, string IntelSrcAsm,
161 list<dag> MaskingPattern,
162 list<dag> ZeroMaskingPattern,
164 string MaskingConstraint = "",
165 InstrItinClass itin = NoItinerary,
166 bit IsCommutable = 0> {
167 let isCommutable = IsCommutable in
168 def NAME: AVX512<O, F, Outs, Ins,
169 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
170 "$dst "#Round#", "#IntelSrcAsm#"}",
173 // Prefer over VMOV*rrk Pat<>
174 let AddedComplexity = 20 in
175 def NAME#k: AVX512<O, F, Outs, MaskingIns,
176 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
177 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
178 MaskingPattern, itin>,
180 // In case of the 3src subclass this is overridden with a let.
181 string Constraints = MaskingConstraint;
183 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
184 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
185 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
186 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
193 // Common base class of AVX512_maskable and AVX512_maskable_3src.
194 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
196 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
198 string AttSrcAsm, string IntelSrcAsm,
199 dag RHS, dag MaskingRHS,
200 SDNode Select = vselect, string Round = "",
201 string MaskingConstraint = "",
202 InstrItinClass itin = NoItinerary,
203 bit IsCommutable = 0> :
204 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
205 AttSrcAsm, IntelSrcAsm,
206 [(set _.RC:$dst, RHS)],
207 [(set _.RC:$dst, MaskingRHS)],
209 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
210 Round, MaskingConstraint, NoItinerary, IsCommutable>;
212 // This multiclass generates the unconditional/non-masking, the masking and
213 // the zero-masking variant of the vector instruction. In the masking case, the
214 // perserved vector elements come from a new dummy input operand tied to $dst.
215 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
216 dag Outs, dag Ins, string OpcodeStr,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, string Round = "",
219 InstrItinClass itin = NoItinerary,
220 bit IsCommutable = 0> :
221 AVX512_maskable_common<O, F, _, Outs, Ins,
222 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
223 !con((ins _.KRCWM:$mask), Ins),
224 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
225 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
226 Round, "$src0 = $dst", itin, IsCommutable>;
228 // This multiclass generates the unconditional/non-masking, the masking and
229 // the zero-masking variant of the scalar instruction.
230 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
231 dag Outs, dag Ins, string OpcodeStr,
232 string AttSrcAsm, string IntelSrcAsm,
233 dag RHS, string Round = "",
234 InstrItinClass itin = NoItinerary,
235 bit IsCommutable = 0> :
236 AVX512_maskable_common<O, F, _, Outs, Ins,
237 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
238 !con((ins _.KRCWM:$mask), Ins),
239 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
240 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
241 Round, "$src0 = $dst", itin, IsCommutable>;
243 // Similar to AVX512_maskable but in this case one of the source operands
244 // ($src1) is already tied to $dst so we just use that for the preserved
245 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
247 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
248 dag Outs, dag NonTiedIns, string OpcodeStr,
249 string AttSrcAsm, string IntelSrcAsm,
251 AVX512_maskable_common<O, F, _, Outs,
252 !con((ins _.RC:$src1), NonTiedIns),
253 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
256 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
259 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
262 string AttSrcAsm, string IntelSrcAsm,
264 AVX512_maskable_custom<O, F, Outs, Ins,
265 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
266 !con((ins _.KRCWM:$mask), Ins),
267 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
270 // Bitcasts between 512-bit vector types. Return the original type since
271 // no instruction is needed for the conversion
272 let Predicates = [HasAVX512] in {
273 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
274 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
305 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
306 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
336 // Bitcasts between 256-bit vector types. Return the original type since
337 // no instruction is needed for the conversion
338 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
371 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
374 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
375 isPseudo = 1, Predicates = [HasAVX512] in {
376 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
377 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
380 let Predicates = [HasAVX512] in {
381 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
382 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
386 //===----------------------------------------------------------------------===//
387 // AVX-512 - VECTOR INSERT
390 multiclass vinsert_for_size_no_alt<int Opcode,
391 X86VectorVTInfo From, X86VectorVTInfo To,
392 PatFrag vinsert_insert,
393 SDNodeXForm INSERT_get_vinsert_imm> {
394 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
395 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
396 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
397 "vinsert" # From.EltTypeName # "x" # From.NumElts #
398 "\t{$src3, $src2, $src1, $dst|"
399 "$dst, $src1, $src2, $src3}",
400 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
401 (From.VT From.RC:$src2),
406 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
407 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
408 "vinsert" # From.EltTypeName # "x" # From.NumElts #
409 "\t{$src3, $src2, $src1, $dst|"
410 "$dst, $src1, $src2, $src3}",
412 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
416 multiclass vinsert_for_size<int Opcode,
417 X86VectorVTInfo From, X86VectorVTInfo To,
418 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
419 PatFrag vinsert_insert,
420 SDNodeXForm INSERT_get_vinsert_imm> :
421 vinsert_for_size_no_alt<Opcode, From, To,
422 vinsert_insert, INSERT_get_vinsert_imm> {
423 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
424 // vinserti32x4. Only add this if 64x2 and friends are not supported
425 // natively via AVX512DQ.
426 let Predicates = [NoDQI] in
427 def : Pat<(vinsert_insert:$ins
428 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
429 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
430 VR512:$src1, From.RC:$src2,
431 (INSERT_get_vinsert_imm VR512:$ins)))>;
434 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
435 ValueType EltVT64, int Opcode256> {
436 defm NAME # "32x4" : vinsert_for_size<Opcode128,
437 X86VectorVTInfo< 4, EltVT32, VR128X>,
438 X86VectorVTInfo<16, EltVT32, VR512>,
439 X86VectorVTInfo< 2, EltVT64, VR128X>,
440 X86VectorVTInfo< 8, EltVT64, VR512>,
442 INSERT_get_vinsert128_imm>;
443 let Predicates = [HasDQI] in
444 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
445 X86VectorVTInfo< 2, EltVT64, VR128X>,
446 X86VectorVTInfo< 8, EltVT64, VR512>,
448 INSERT_get_vinsert128_imm>, VEX_W;
449 defm NAME # "64x4" : vinsert_for_size<Opcode256,
450 X86VectorVTInfo< 4, EltVT64, VR256X>,
451 X86VectorVTInfo< 8, EltVT64, VR512>,
452 X86VectorVTInfo< 8, EltVT32, VR256>,
453 X86VectorVTInfo<16, EltVT32, VR512>,
455 INSERT_get_vinsert256_imm>, VEX_W;
456 let Predicates = [HasDQI] in
457 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
458 X86VectorVTInfo< 8, EltVT32, VR256X>,
459 X86VectorVTInfo<16, EltVT32, VR512>,
461 INSERT_get_vinsert256_imm>;
464 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
465 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
467 // vinsertps - insert f32 to XMM
468 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
469 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
470 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
471 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
473 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
474 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
475 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
476 [(set VR128X:$dst, (X86insertps VR128X:$src1,
477 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
478 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
480 //===----------------------------------------------------------------------===//
481 // AVX-512 VECTOR EXTRACT
484 multiclass vextract_for_size<int Opcode,
485 X86VectorVTInfo From, X86VectorVTInfo To,
486 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
487 PatFrag vextract_extract,
488 SDNodeXForm EXTRACT_get_vextract_imm> {
489 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
490 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
491 (ins VR512:$src1, i8imm:$idx),
492 "vextract" # To.EltTypeName # "x4",
493 "$idx, $src1", "$src1, $idx",
494 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
496 AVX512AIi8Base, EVEX, EVEX_V512;
498 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
499 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
500 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
501 "$dst, $src1, $src2}",
502 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
505 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
507 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
508 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
510 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
512 // A 128/256-bit subvector extract from the first 512-bit vector position is
513 // a subregister copy that needs no instruction.
514 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
516 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
518 // And for the alternative types.
519 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
521 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
523 // Intrinsic call with masking.
524 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
526 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
527 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
528 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
529 VR512:$src1, imm:$idx)>;
531 // Intrinsic call with zero-masking.
532 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
534 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
535 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
536 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
537 VR512:$src1, imm:$idx)>;
539 // Intrinsic call without masking.
540 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
542 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
543 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
544 VR512:$src1, imm:$idx)>;
547 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
548 ValueType EltVT64, int Opcode64> {
549 defm NAME # "32x4" : vextract_for_size<Opcode32,
550 X86VectorVTInfo<16, EltVT32, VR512>,
551 X86VectorVTInfo< 4, EltVT32, VR128X>,
552 X86VectorVTInfo< 8, EltVT64, VR512>,
553 X86VectorVTInfo< 2, EltVT64, VR128X>,
555 EXTRACT_get_vextract128_imm>;
556 defm NAME # "64x4" : vextract_for_size<Opcode64,
557 X86VectorVTInfo< 8, EltVT64, VR512>,
558 X86VectorVTInfo< 4, EltVT64, VR256X>,
559 X86VectorVTInfo<16, EltVT32, VR512>,
560 X86VectorVTInfo< 8, EltVT32, VR256>,
562 EXTRACT_get_vextract256_imm>, VEX_W;
565 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
566 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
568 // A 128-bit subvector insert to the first 512-bit vector position
569 // is a subregister copy that needs no instruction.
570 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
571 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
572 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
574 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
575 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
576 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
578 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
580 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
582 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
583 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
584 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
587 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
588 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
589 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
590 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
591 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
592 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
593 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
594 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
596 // vextractps - extract 32 bits from XMM
597 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
598 (ins VR128X:$src1, i32i8imm:$src2),
599 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
600 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
603 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
604 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
605 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
606 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
607 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
609 //===---------------------------------------------------------------------===//
612 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
613 ValueType svt, X86VectorVTInfo _> {
614 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
615 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
616 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
620 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
621 (ins _.ScalarMemOp:$src),
622 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
623 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
628 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
629 AVX512VLVectorVTInfo _> {
630 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
633 let Predicates = [HasVLX] in {
634 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
639 let ExeDomain = SSEPackedSingle in {
640 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
641 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
642 let Predicates = [HasVLX] in {
643 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
644 v4f32, v4f32x_info>, EVEX_V128,
645 EVEX_CD8<32, CD8VT1>;
649 let ExeDomain = SSEPackedDouble in {
650 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
651 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
654 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
655 // representations of source
656 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
657 X86VectorVTInfo _, RegisterClass SrcRC_v,
658 RegisterClass SrcRC_s> {
659 def : Pat<(_.VT (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src))),
660 (!cast<Instruction>(InstName##"r")
661 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
663 let AddedComplexity = 30 in {
664 def : Pat<(_.VT (vselect _.KRCWM:$mask,
665 (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),
667 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
668 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
670 def : Pat<(_.VT(vselect _.KRCWM:$mask,
671 (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),
673 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
674 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
678 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
680 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
683 let Predicates = [HasVLX] in {
684 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
685 v8f32x_info, VR128X, FR32X>;
686 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
687 v4f32x_info, VR128X, FR32X>;
688 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
689 v4f64x_info, VR128X, FR64X>;
692 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
693 (VBROADCASTSSZm addr:$src)>;
694 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
695 (VBROADCASTSDZm addr:$src)>;
697 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
698 (VBROADCASTSSZm addr:$src)>;
699 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
700 (VBROADCASTSDZm addr:$src)>;
702 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
703 RegisterClass SrcRC> {
704 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
705 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
706 "$src", "$src", []>, T8PD, EVEX;
709 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
710 RegisterClass SrcRC, Predicate prd> {
711 let Predicates = [prd] in
712 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
713 let Predicates = [prd, HasVLX] in {
714 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
715 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
719 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
721 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
723 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
725 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
728 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
729 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
731 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
732 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
734 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
735 (VPBROADCASTDrZr GR32:$src)>;
736 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
737 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
738 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
739 (VPBROADCASTQrZr GR64:$src)>;
740 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
741 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
743 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
744 (VPBROADCASTDrZr GR32:$src)>;
745 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
746 (VPBROADCASTQrZr GR64:$src)>;
748 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
749 (v16i32 immAllZerosV), (i16 GR16:$mask))),
750 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
751 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
752 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
753 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
755 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
756 X86MemOperand x86memop, PatFrag ld_frag,
757 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
759 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
760 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
762 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
763 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
765 !strconcat(OpcodeStr,
766 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
768 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
771 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
772 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
774 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
775 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
777 !strconcat(OpcodeStr,
778 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
779 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
780 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
784 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
785 loadi32, VR512, v16i32, v4i32, VK16WM>,
786 EVEX_V512, EVEX_CD8<32, CD8VT1>;
787 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
788 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
789 EVEX_CD8<64, CD8VT1>;
791 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
792 X86MemOperand x86memop, PatFrag ld_frag,
795 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
798 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
800 !strconcat(OpcodeStr,
801 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
806 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
807 i128mem, loadv2i64, VK16WM>,
808 EVEX_V512, EVEX_CD8<32, CD8VT4>;
809 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
810 i256mem, loadv4i64, VK16WM>, VEX_W,
811 EVEX_V512, EVEX_CD8<64, CD8VT4>;
813 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
814 (VPBROADCASTDZrr VR128X:$src)>;
815 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
816 (VPBROADCASTQZrr VR128X:$src)>;
818 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
819 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
820 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
821 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
823 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
824 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
825 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
826 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
828 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
829 (VBROADCASTSSZr VR128X:$src)>;
830 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
831 (VBROADCASTSDZr VR128X:$src)>;
833 // Provide fallback in case the load node that is used in the patterns above
834 // is used by additional users, which prevents the pattern selection.
835 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
836 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
837 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
838 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
841 let Predicates = [HasAVX512] in {
842 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
844 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
845 addr:$src)), sub_ymm)>;
847 //===----------------------------------------------------------------------===//
848 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
851 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
853 let Predicates = [HasCDI] in
854 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
855 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
856 []>, EVEX, EVEX_V512;
858 let Predicates = [HasCDI, HasVLX] in {
859 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
860 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
861 []>, EVEX, EVEX_V128;
862 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
864 []>, EVEX, EVEX_V256;
868 let Predicates = [HasCDI] in {
869 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
871 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
875 //===----------------------------------------------------------------------===//
878 // -- immediate form --
879 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
881 let ExeDomain = _.ExeDomain in {
882 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
883 (ins _.RC:$src1, i8imm:$src2),
884 !strconcat(OpcodeStr,
885 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
887 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
889 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
890 (ins _.MemOp:$src1, i8imm:$src2),
891 !strconcat(OpcodeStr,
892 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
894 (_.VT (OpNode (_.MemOpFrag addr:$src1),
896 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
900 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
901 X86VectorVTInfo Ctrl> :
902 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
903 let ExeDomain = _.ExeDomain in {
904 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
905 (ins _.RC:$src1, _.RC:$src2),
906 !strconcat("vpermil" # _.Suffix,
907 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
909 (_.VT (X86VPermilpv _.RC:$src1,
910 (Ctrl.VT Ctrl.RC:$src2))))]>,
912 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
913 (ins _.RC:$src1, Ctrl.MemOp:$src2),
914 !strconcat("vpermil" # _.Suffix,
915 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
917 (_.VT (X86VPermilpv _.RC:$src1,
918 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
923 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
925 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
928 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
930 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
933 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
934 (VPERMILPSZri VR512:$src1, imm:$imm)>;
935 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
936 (VPERMILPDZri VR512:$src1, imm:$imm)>;
938 // -- VPERM - register form --
939 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
940 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
942 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
943 (ins RC:$src1, RC:$src2),
944 !strconcat(OpcodeStr,
945 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
947 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
949 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
950 (ins RC:$src1, x86memop:$src2),
951 !strconcat(OpcodeStr,
952 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
958 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
959 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
960 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
961 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
962 let ExeDomain = SSEPackedSingle in
963 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
964 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
965 let ExeDomain = SSEPackedDouble in
966 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
967 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
969 // -- VPERM2I - 3 source operands form --
970 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
971 PatFrag mem_frag, X86MemOperand x86memop,
972 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
973 let Constraints = "$src1 = $dst" in {
974 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
975 (ins RC:$src1, RC:$src2, RC:$src3),
976 !strconcat(OpcodeStr,
977 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
979 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
982 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
983 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
984 !strconcat(OpcodeStr,
985 "\t{$src3, $src2, $dst {${mask}}|"
986 "$dst {${mask}}, $src2, $src3}"),
987 [(set RC:$dst, (OpVT (vselect KRC:$mask,
988 (OpNode RC:$src1, RC:$src2,
993 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
994 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
995 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
996 !strconcat(OpcodeStr,
997 "\t{$src3, $src2, $dst {${mask}} {z} |",
998 "$dst {${mask}} {z}, $src2, $src3}"),
999 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1000 (OpNode RC:$src1, RC:$src2,
1003 (v16i32 immAllZerosV))))))]>,
1006 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1007 (ins RC:$src1, RC:$src2, x86memop:$src3),
1008 !strconcat(OpcodeStr,
1009 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1011 (OpVT (OpNode RC:$src1, RC:$src2,
1012 (mem_frag addr:$src3))))]>, EVEX_4V;
1014 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1015 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1016 !strconcat(OpcodeStr,
1017 "\t{$src3, $src2, $dst {${mask}}|"
1018 "$dst {${mask}}, $src2, $src3}"),
1020 (OpVT (vselect KRC:$mask,
1021 (OpNode RC:$src1, RC:$src2,
1022 (mem_frag addr:$src3)),
1026 let AddedComplexity = 10 in // Prefer over the rrkz variant
1027 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1028 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1029 !strconcat(OpcodeStr,
1030 "\t{$src3, $src2, $dst {${mask}} {z}|"
1031 "$dst {${mask}} {z}, $src2, $src3}"),
1033 (OpVT (vselect KRC:$mask,
1034 (OpNode RC:$src1, RC:$src2,
1035 (mem_frag addr:$src3)),
1037 (v16i32 immAllZerosV))))))]>,
1041 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1042 i512mem, X86VPermiv3, v16i32, VK16WM>,
1043 EVEX_V512, EVEX_CD8<32, CD8VF>;
1044 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1045 i512mem, X86VPermiv3, v8i64, VK8WM>,
1046 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1047 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1048 i512mem, X86VPermiv3, v16f32, VK16WM>,
1049 EVEX_V512, EVEX_CD8<32, CD8VF>;
1050 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1051 i512mem, X86VPermiv3, v8f64, VK8WM>,
1052 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1054 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1055 PatFrag mem_frag, X86MemOperand x86memop,
1056 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1057 ValueType MaskVT, RegisterClass MRC> :
1058 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1060 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1061 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1062 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1064 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1065 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1066 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1067 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1070 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1071 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1072 EVEX_V512, EVEX_CD8<32, CD8VF>;
1073 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1074 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1075 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1076 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1077 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1078 EVEX_V512, EVEX_CD8<32, CD8VF>;
1079 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1080 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1081 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1083 //===----------------------------------------------------------------------===//
1084 // AVX-512 - BLEND using mask
1086 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1087 RegisterClass KRC, RegisterClass RC,
1088 X86MemOperand x86memop, PatFrag mem_frag,
1089 SDNode OpNode, ValueType vt> {
1090 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1091 (ins KRC:$mask, RC:$src1, RC:$src2),
1092 !strconcat(OpcodeStr,
1093 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1094 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1095 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1097 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1098 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1099 !strconcat(OpcodeStr,
1100 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1101 []>, EVEX_4V, EVEX_K;
1104 let ExeDomain = SSEPackedSingle in
1105 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1106 VK16WM, VR512, f512mem,
1107 memopv16f32, vselect, v16f32>,
1108 EVEX_CD8<32, CD8VF>, EVEX_V512;
1109 let ExeDomain = SSEPackedDouble in
1110 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1111 VK8WM, VR512, f512mem,
1112 memopv8f64, vselect, v8f64>,
1113 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1115 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1116 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1117 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1118 VR512:$src1, VR512:$src2)>;
1120 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1121 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1122 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1123 VR512:$src1, VR512:$src2)>;
1125 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1126 VK16WM, VR512, f512mem,
1127 memopv16i32, vselect, v16i32>,
1128 EVEX_CD8<32, CD8VF>, EVEX_V512;
1130 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1131 VK8WM, VR512, f512mem,
1132 memopv8i64, vselect, v8i64>,
1133 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1135 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1136 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1137 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1138 VR512:$src1, VR512:$src2)>;
1140 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1141 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1142 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1143 VR512:$src1, VR512:$src2)>;
1145 let Predicates = [HasAVX512] in {
1146 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1147 (v8f32 VR256X:$src2))),
1149 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1150 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1151 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1153 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1154 (v8i32 VR256X:$src2))),
1156 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1157 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1158 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1160 //===----------------------------------------------------------------------===//
1161 // Compare Instructions
1162 //===----------------------------------------------------------------------===//
1164 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1165 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1166 Operand CC, SDNode OpNode, ValueType VT,
1167 PatFrag ld_frag, string asm, string asm_alt> {
1168 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1169 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1170 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1171 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1172 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1173 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1174 [(set VK1:$dst, (OpNode (VT RC:$src1),
1175 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1176 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1177 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1178 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1179 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1180 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1181 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1182 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1186 let Predicates = [HasAVX512] in {
1187 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1188 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1189 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1191 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1192 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1193 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1197 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1198 X86VectorVTInfo _> {
1199 def rr : AVX512BI<opc, MRMSrcReg,
1200 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1201 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1202 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1203 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1205 def rm : AVX512BI<opc, MRMSrcMem,
1206 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1207 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1208 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1209 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1210 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1211 def rrk : AVX512BI<opc, MRMSrcReg,
1212 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1213 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1214 "$dst {${mask}}, $src1, $src2}"),
1215 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1216 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1217 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1219 def rmk : AVX512BI<opc, MRMSrcMem,
1220 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1221 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1222 "$dst {${mask}}, $src1, $src2}"),
1223 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1224 (OpNode (_.VT _.RC:$src1),
1226 (_.LdFrag addr:$src2))))))],
1227 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1230 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1231 X86VectorVTInfo _> :
1232 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1233 let mayLoad = 1 in {
1234 def rmb : AVX512BI<opc, MRMSrcMem,
1235 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1236 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1237 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1238 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1239 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1240 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1241 def rmbk : AVX512BI<opc, MRMSrcMem,
1242 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1243 _.ScalarMemOp:$src2),
1244 !strconcat(OpcodeStr,
1245 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1246 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1247 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1248 (OpNode (_.VT _.RC:$src1),
1250 (_.ScalarLdFrag addr:$src2)))))],
1251 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1255 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1256 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1257 let Predicates = [prd] in
1258 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1261 let Predicates = [prd, HasVLX] in {
1262 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1264 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1269 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1270 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1272 let Predicates = [prd] in
1273 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1276 let Predicates = [prd, HasVLX] in {
1277 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1279 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1284 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1285 avx512vl_i8_info, HasBWI>,
1288 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1289 avx512vl_i16_info, HasBWI>,
1290 EVEX_CD8<16, CD8VF>;
1292 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1293 avx512vl_i32_info, HasAVX512>,
1294 EVEX_CD8<32, CD8VF>;
1296 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1297 avx512vl_i64_info, HasAVX512>,
1298 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1300 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1301 avx512vl_i8_info, HasBWI>,
1304 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1305 avx512vl_i16_info, HasBWI>,
1306 EVEX_CD8<16, CD8VF>;
1308 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1309 avx512vl_i32_info, HasAVX512>,
1310 EVEX_CD8<32, CD8VF>;
1312 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1313 avx512vl_i64_info, HasAVX512>,
1314 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1316 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1317 (COPY_TO_REGCLASS (VPCMPGTDZrr
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1319 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1321 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1322 (COPY_TO_REGCLASS (VPCMPEQDZrr
1323 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1324 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1326 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1327 X86VectorVTInfo _> {
1328 def rri : AVX512AIi8<opc, MRMSrcReg,
1329 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1330 !strconcat("vpcmp${cc}", Suffix,
1331 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1332 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1334 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1336 def rmi : AVX512AIi8<opc, MRMSrcMem,
1337 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1338 !strconcat("vpcmp${cc}", Suffix,
1339 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1340 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1341 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1343 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1344 def rrik : AVX512AIi8<opc, MRMSrcReg,
1345 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1347 !strconcat("vpcmp${cc}", Suffix,
1348 "\t{$src2, $src1, $dst {${mask}}|",
1349 "$dst {${mask}}, $src1, $src2}"),
1350 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1351 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1353 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1355 def rmik : AVX512AIi8<opc, MRMSrcMem,
1356 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1358 !strconcat("vpcmp${cc}", Suffix,
1359 "\t{$src2, $src1, $dst {${mask}}|",
1360 "$dst {${mask}}, $src1, $src2}"),
1361 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1362 (OpNode (_.VT _.RC:$src1),
1363 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1365 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1367 // Accept explicit immediate argument form instead of comparison code.
1368 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1369 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1370 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1371 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1372 "$dst, $src1, $src2, $cc}"),
1373 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1374 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1375 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1376 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1377 "$dst, $src1, $src2, $cc}"),
1378 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1379 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1380 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1382 !strconcat("vpcmp", Suffix,
1383 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1384 "$dst {${mask}}, $src1, $src2, $cc}"),
1385 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1386 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1387 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1389 !strconcat("vpcmp", Suffix,
1390 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1391 "$dst {${mask}}, $src1, $src2, $cc}"),
1392 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1396 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1397 X86VectorVTInfo _> :
1398 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1399 let mayLoad = 1 in {
1400 def rmib : AVX512AIi8<opc, MRMSrcMem,
1401 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1403 !strconcat("vpcmp${cc}", Suffix,
1404 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1405 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1406 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1407 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1409 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1410 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1411 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1412 _.ScalarMemOp:$src2, AVXCC:$cc),
1413 !strconcat("vpcmp${cc}", Suffix,
1414 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1415 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1416 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1417 (OpNode (_.VT _.RC:$src1),
1418 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1420 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1423 // Accept explicit immediate argument form instead of comparison code.
1424 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1425 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1426 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1428 !strconcat("vpcmp", Suffix,
1429 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1430 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1431 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1432 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1433 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1434 _.ScalarMemOp:$src2, i8imm:$cc),
1435 !strconcat("vpcmp", Suffix,
1436 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1437 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1438 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1442 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1443 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1444 let Predicates = [prd] in
1445 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1447 let Predicates = [prd, HasVLX] in {
1448 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1449 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1453 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1454 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1455 let Predicates = [prd] in
1456 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1459 let Predicates = [prd, HasVLX] in {
1460 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1462 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1467 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1468 HasBWI>, EVEX_CD8<8, CD8VF>;
1469 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1470 HasBWI>, EVEX_CD8<8, CD8VF>;
1472 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1473 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1474 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1475 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1477 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1478 HasAVX512>, EVEX_CD8<32, CD8VF>;
1479 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1480 HasAVX512>, EVEX_CD8<32, CD8VF>;
1482 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1483 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1484 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1485 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1487 // avx512_cmp_packed - compare packed instructions
1488 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1489 X86MemOperand x86memop, ValueType vt,
1490 string suffix, Domain d> {
1491 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1492 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1493 !strconcat("vcmp${cc}", suffix,
1494 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1495 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1496 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1497 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1498 !strconcat("vcmp${cc}", suffix,
1499 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1501 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1502 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1503 !strconcat("vcmp${cc}", suffix,
1504 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1506 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1508 // Accept explicit immediate argument form instead of comparison code.
1509 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1510 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1511 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1512 !strconcat("vcmp", suffix,
1513 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1514 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1515 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1516 !strconcat("vcmp", suffix,
1517 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1521 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1522 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1523 EVEX_CD8<32, CD8VF>;
1524 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1525 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1526 EVEX_CD8<64, CD8VF>;
1528 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1529 (COPY_TO_REGCLASS (VCMPPSZrri
1530 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1531 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1533 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1534 (COPY_TO_REGCLASS (VPCMPDZrri
1535 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1536 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1538 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1539 (COPY_TO_REGCLASS (VPCMPUDZrri
1540 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1541 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1544 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1545 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1547 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1548 (I8Imm imm:$cc)), GR16)>;
1550 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1551 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1553 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1554 (I8Imm imm:$cc)), GR8)>;
1556 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1557 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1559 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1560 (I8Imm imm:$cc)), GR16)>;
1562 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1563 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1565 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1566 (I8Imm imm:$cc)), GR8)>;
1568 // Mask register copy, including
1569 // - copy between mask registers
1570 // - load/store mask registers
1571 // - copy from GPR to mask register and vice versa
1573 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1574 string OpcodeStr, RegisterClass KRC,
1575 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1576 let hasSideEffects = 0 in {
1577 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1580 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1582 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1584 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1589 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1591 RegisterClass KRC, RegisterClass GRC> {
1592 let hasSideEffects = 0 in {
1593 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1595 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1600 let Predicates = [HasDQI] in
1601 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1603 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1606 let Predicates = [HasAVX512] in
1607 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1609 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1612 let Predicates = [HasBWI] in {
1613 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1614 i32mem>, VEX, PD, VEX_W;
1615 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1619 let Predicates = [HasBWI] in {
1620 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1621 i64mem>, VEX, PS, VEX_W;
1622 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1626 // GR from/to mask register
1627 let Predicates = [HasDQI] in {
1628 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1629 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1630 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1631 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1633 let Predicates = [HasAVX512] in {
1634 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1635 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1636 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1637 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1639 let Predicates = [HasBWI] in {
1640 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1641 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1643 let Predicates = [HasBWI] in {
1644 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1645 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1649 let Predicates = [HasDQI] in {
1650 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1651 (KMOVBmk addr:$dst, VK8:$src)>;
1653 let Predicates = [HasAVX512] in {
1654 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1655 (KMOVWmk addr:$dst, VK16:$src)>;
1656 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1657 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1658 def : Pat<(i1 (load addr:$src)),
1659 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1660 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1661 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1663 let Predicates = [HasBWI] in {
1664 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1665 (KMOVDmk addr:$dst, VK32:$src)>;
1667 let Predicates = [HasBWI] in {
1668 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1669 (KMOVQmk addr:$dst, VK64:$src)>;
1672 let Predicates = [HasAVX512] in {
1673 def : Pat<(i1 (trunc (i64 GR64:$src))),
1674 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1677 def : Pat<(i1 (trunc (i32 GR32:$src))),
1678 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1680 def : Pat<(i1 (trunc (i8 GR8:$src))),
1682 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1684 def : Pat<(i1 (trunc (i16 GR16:$src))),
1686 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1689 def : Pat<(i32 (zext VK1:$src)),
1690 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1691 def : Pat<(i8 (zext VK1:$src)),
1694 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1695 def : Pat<(i64 (zext VK1:$src)),
1696 (AND64ri8 (SUBREG_TO_REG (i64 0),
1697 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1698 def : Pat<(i16 (zext VK1:$src)),
1700 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1702 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1703 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1704 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1705 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1707 let Predicates = [HasBWI] in {
1708 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1709 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1710 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1711 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1715 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1716 let Predicates = [HasAVX512] in {
1717 // GR from/to 8-bit mask without native support
1718 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1720 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1722 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1724 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1727 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1728 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1729 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1730 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1732 let Predicates = [HasBWI] in {
1733 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1734 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1735 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1736 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1739 // Mask unary operation
1741 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1742 RegisterClass KRC, SDPatternOperator OpNode,
1744 let Predicates = [prd] in
1745 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1746 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1747 [(set KRC:$dst, (OpNode KRC:$src))]>;
1750 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1751 SDPatternOperator OpNode> {
1752 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1754 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1755 HasAVX512>, VEX, PS;
1756 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1757 HasBWI>, VEX, PD, VEX_W;
1758 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1759 HasBWI>, VEX, PS, VEX_W;
1762 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1764 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1765 let Predicates = [HasAVX512] in
1766 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1768 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1769 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1771 defm : avx512_mask_unop_int<"knot", "KNOT">;
1773 let Predicates = [HasDQI] in
1774 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1775 let Predicates = [HasAVX512] in
1776 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1777 let Predicates = [HasBWI] in
1778 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1779 let Predicates = [HasBWI] in
1780 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1782 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1783 let Predicates = [HasAVX512] in {
1784 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1785 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1787 def : Pat<(not VK8:$src),
1789 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1792 // Mask binary operation
1793 // - KAND, KANDN, KOR, KXNOR, KXOR
1794 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1795 RegisterClass KRC, SDPatternOperator OpNode,
1797 let Predicates = [prd] in
1798 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1799 !strconcat(OpcodeStr,
1800 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1801 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1804 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1805 SDPatternOperator OpNode> {
1806 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1807 HasDQI>, VEX_4V, VEX_L, PD;
1808 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1809 HasAVX512>, VEX_4V, VEX_L, PS;
1810 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1811 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1812 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1813 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1816 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1817 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1819 let isCommutable = 1 in {
1820 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1821 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1822 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1823 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1825 let isCommutable = 0 in
1826 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1828 def : Pat<(xor VK1:$src1, VK1:$src2),
1829 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1830 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1832 def : Pat<(or VK1:$src1, VK1:$src2),
1833 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1834 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1836 def : Pat<(and VK1:$src1, VK1:$src2),
1837 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1838 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1840 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1841 let Predicates = [HasAVX512] in
1842 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1843 (i16 GR16:$src1), (i16 GR16:$src2)),
1844 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1845 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1846 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1849 defm : avx512_mask_binop_int<"kand", "KAND">;
1850 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1851 defm : avx512_mask_binop_int<"kor", "KOR">;
1852 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1853 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1855 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1856 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1857 let Predicates = [HasAVX512] in
1858 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1860 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1861 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1864 defm : avx512_binop_pat<and, KANDWrr>;
1865 defm : avx512_binop_pat<andn, KANDNWrr>;
1866 defm : avx512_binop_pat<or, KORWrr>;
1867 defm : avx512_binop_pat<xnor, KXNORWrr>;
1868 defm : avx512_binop_pat<xor, KXORWrr>;
1871 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1872 RegisterClass KRC> {
1873 let Predicates = [HasAVX512] in
1874 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1875 !strconcat(OpcodeStr,
1876 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1879 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1880 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1884 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1885 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1886 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1887 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1890 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1891 let Predicates = [HasAVX512] in
1892 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1893 (i16 GR16:$src1), (i16 GR16:$src2)),
1894 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1895 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1896 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1898 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1901 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1903 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1904 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1905 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1906 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1909 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1910 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1914 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1916 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1917 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1918 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1921 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1923 let Predicates = [HasAVX512] in
1924 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1925 !strconcat(OpcodeStr,
1926 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1927 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1930 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1932 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1936 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1937 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1939 // Mask setting all 0s or 1s
1940 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1941 let Predicates = [HasAVX512] in
1942 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1943 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1944 [(set KRC:$dst, (VT Val))]>;
1947 multiclass avx512_mask_setop_w<PatFrag Val> {
1948 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1949 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1952 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1953 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1955 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1956 let Predicates = [HasAVX512] in {
1957 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1958 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1959 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1960 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1961 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1963 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1964 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1966 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1967 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1969 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1970 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1972 let Predicates = [HasVLX] in {
1973 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1974 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1975 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1976 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1977 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1978 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1979 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1980 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1983 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1984 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1986 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1987 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1988 //===----------------------------------------------------------------------===//
1989 // AVX-512 - Aligned and unaligned load and store
1992 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1993 RegisterClass KRC, RegisterClass RC,
1994 ValueType vt, ValueType zvt, X86MemOperand memop,
1995 Domain d, bit IsReMaterializable = 1> {
1996 let hasSideEffects = 0 in {
1997 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1998 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2000 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2001 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2002 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2004 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2005 SchedRW = [WriteLoad] in
2006 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2007 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2008 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2011 let AddedComplexity = 20 in {
2012 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2013 let hasSideEffects = 0 in
2014 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2015 (ins RC:$src0, KRC:$mask, RC:$src1),
2016 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2017 "${dst} {${mask}}, $src1}"),
2018 [(set RC:$dst, (vt (vselect KRC:$mask,
2022 let mayLoad = 1, SchedRW = [WriteLoad] in
2023 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2024 (ins RC:$src0, KRC:$mask, memop:$src1),
2025 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2026 "${dst} {${mask}}, $src1}"),
2029 (vt (bitconvert (ld_frag addr:$src1))),
2033 let mayLoad = 1, SchedRW = [WriteLoad] in
2034 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2035 (ins KRC:$mask, memop:$src),
2036 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2037 "${dst} {${mask}} {z}, $src}"),
2040 (vt (bitconvert (ld_frag addr:$src))),
2041 (vt (bitconvert (zvt immAllZerosV))))))],
2046 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2047 string elty, string elsz, string vsz512,
2048 string vsz256, string vsz128, Domain d,
2049 Predicate prd, bit IsReMaterializable = 1> {
2050 let Predicates = [prd] in
2051 defm Z : avx512_load<opc, OpcodeStr,
2052 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2053 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2054 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2055 !cast<X86MemOperand>(elty##"512mem"), d,
2056 IsReMaterializable>, EVEX_V512;
2058 let Predicates = [prd, HasVLX] in {
2059 defm Z256 : avx512_load<opc, OpcodeStr,
2060 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2061 "v"##vsz256##elty##elsz, "v4i64")),
2062 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2063 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2064 !cast<X86MemOperand>(elty##"256mem"), d,
2065 IsReMaterializable>, EVEX_V256;
2067 defm Z128 : avx512_load<opc, OpcodeStr,
2068 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2069 "v"##vsz128##elty##elsz, "v2i64")),
2070 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2071 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2072 !cast<X86MemOperand>(elty##"128mem"), d,
2073 IsReMaterializable>, EVEX_V128;
2078 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2079 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2080 X86MemOperand memop, Domain d> {
2081 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2082 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2083 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2085 let Constraints = "$src1 = $dst" in
2086 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2087 (ins RC:$src1, KRC:$mask, RC:$src2),
2088 !strconcat(OpcodeStr,
2089 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2091 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2092 (ins KRC:$mask, RC:$src),
2093 !strconcat(OpcodeStr,
2094 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2095 [], d>, EVEX, EVEX_KZ;
2097 let mayStore = 1 in {
2098 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2099 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2100 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2101 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2102 (ins memop:$dst, KRC:$mask, RC:$src),
2103 !strconcat(OpcodeStr,
2104 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2105 [], d>, EVEX, EVEX_K;
2110 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2111 string st_suff_512, string st_suff_256,
2112 string st_suff_128, string elty, string elsz,
2113 string vsz512, string vsz256, string vsz128,
2114 Domain d, Predicate prd> {
2115 let Predicates = [prd] in
2116 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2117 !cast<ValueType>("v"##vsz512##elty##elsz),
2118 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2119 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2121 let Predicates = [prd, HasVLX] in {
2122 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2123 !cast<ValueType>("v"##vsz256##elty##elsz),
2124 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2125 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2127 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2128 !cast<ValueType>("v"##vsz128##elty##elsz),
2129 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2130 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2134 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2135 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2136 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2137 "512", "256", "", "f", "32", "16", "8", "4",
2138 SSEPackedSingle, HasAVX512>,
2139 PS, EVEX_CD8<32, CD8VF>;
2141 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2142 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2143 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2144 "512", "256", "", "f", "64", "8", "4", "2",
2145 SSEPackedDouble, HasAVX512>,
2146 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2148 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2149 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2150 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2151 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2152 PS, EVEX_CD8<32, CD8VF>;
2154 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2155 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2156 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2157 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2158 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2160 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2161 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2162 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2164 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2165 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2166 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2168 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2170 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2172 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2174 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2177 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2178 (VMOVUPSZmrk addr:$ptr,
2179 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2180 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2182 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2183 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2184 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2186 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2187 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2189 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2190 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2192 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2193 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2195 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2196 (bc_v16f32 (v16i32 immAllZerosV)))),
2197 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2199 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2200 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2202 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2203 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2205 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2206 (bc_v8f64 (v16i32 immAllZerosV)))),
2207 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2209 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2210 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2212 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2213 "16", "8", "4", SSEPackedInt, HasAVX512>,
2214 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2215 "512", "256", "", "i", "32", "16", "8", "4",
2216 SSEPackedInt, HasAVX512>,
2217 PD, EVEX_CD8<32, CD8VF>;
2219 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2220 "8", "4", "2", SSEPackedInt, HasAVX512>,
2221 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2222 "512", "256", "", "i", "64", "8", "4", "2",
2223 SSEPackedInt, HasAVX512>,
2224 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2226 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2227 "64", "32", "16", SSEPackedInt, HasBWI>,
2228 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2229 "i", "8", "64", "32", "16", SSEPackedInt,
2230 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2232 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2233 "32", "16", "8", SSEPackedInt, HasBWI>,
2234 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2235 "i", "16", "32", "16", "8", SSEPackedInt,
2236 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2238 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2239 "16", "8", "4", SSEPackedInt, HasAVX512>,
2240 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2241 "i", "32", "16", "8", "4", SSEPackedInt,
2242 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2244 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2245 "8", "4", "2", SSEPackedInt, HasAVX512>,
2246 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2247 "i", "64", "8", "4", "2", SSEPackedInt,
2248 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2250 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2251 (v16i32 immAllZerosV), GR16:$mask)),
2252 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2254 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2255 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2256 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2258 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2260 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2262 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2264 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2267 let AddedComplexity = 20 in {
2268 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2269 (bc_v8i64 (v16i32 immAllZerosV)))),
2270 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2272 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2273 (v8i64 VR512:$src))),
2274 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2277 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2278 (v16i32 immAllZerosV))),
2279 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2281 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2282 (v16i32 VR512:$src))),
2283 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2286 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2287 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2289 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2290 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2292 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2293 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2295 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2296 (bc_v8i64 (v16i32 immAllZerosV)))),
2297 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2299 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2300 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2302 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2303 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2305 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2306 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2308 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2309 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2312 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2313 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2316 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2317 (VMOVDQU32Zmrk addr:$ptr,
2318 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2319 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2321 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2322 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2323 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2326 // Move Int Doubleword to Packed Double Int
2328 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2329 "vmovd\t{$src, $dst|$dst, $src}",
2331 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2333 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2334 "vmovd\t{$src, $dst|$dst, $src}",
2336 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2337 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2338 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2339 "vmovq\t{$src, $dst|$dst, $src}",
2341 (v2i64 (scalar_to_vector GR64:$src)))],
2342 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2343 let isCodeGenOnly = 1 in {
2344 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2345 "vmovq\t{$src, $dst|$dst, $src}",
2346 [(set FR64:$dst, (bitconvert GR64:$src))],
2347 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2348 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2349 "vmovq\t{$src, $dst|$dst, $src}",
2350 [(set GR64:$dst, (bitconvert FR64:$src))],
2351 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2353 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2354 "vmovq\t{$src, $dst|$dst, $src}",
2355 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2356 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2357 EVEX_CD8<64, CD8VT1>;
2359 // Move Int Doubleword to Single Scalar
2361 let isCodeGenOnly = 1 in {
2362 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2363 "vmovd\t{$src, $dst|$dst, $src}",
2364 [(set FR32X:$dst, (bitconvert GR32:$src))],
2365 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2367 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2368 "vmovd\t{$src, $dst|$dst, $src}",
2369 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2370 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2373 // Move doubleword from xmm register to r/m32
2375 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2376 "vmovd\t{$src, $dst|$dst, $src}",
2377 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2378 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2380 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2381 (ins i32mem:$dst, VR128X:$src),
2382 "vmovd\t{$src, $dst|$dst, $src}",
2383 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2384 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2385 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2387 // Move quadword from xmm1 register to r/m64
2389 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2390 "vmovq\t{$src, $dst|$dst, $src}",
2391 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2393 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2394 Requires<[HasAVX512, In64BitMode]>;
2396 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2397 (ins i64mem:$dst, VR128X:$src),
2398 "vmovq\t{$src, $dst|$dst, $src}",
2399 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2400 addr:$dst)], IIC_SSE_MOVDQ>,
2401 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2402 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2404 // Move Scalar Single to Double Int
2406 let isCodeGenOnly = 1 in {
2407 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2409 "vmovd\t{$src, $dst|$dst, $src}",
2410 [(set GR32:$dst, (bitconvert FR32X:$src))],
2411 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2412 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2413 (ins i32mem:$dst, FR32X:$src),
2414 "vmovd\t{$src, $dst|$dst, $src}",
2415 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2416 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2419 // Move Quadword Int to Packed Quadword Int
2421 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2423 "vmovq\t{$src, $dst|$dst, $src}",
2425 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2426 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2428 //===----------------------------------------------------------------------===//
2429 // AVX-512 MOVSS, MOVSD
2430 //===----------------------------------------------------------------------===//
2432 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2433 SDNode OpNode, ValueType vt,
2434 X86MemOperand x86memop, PatFrag mem_pat> {
2435 let hasSideEffects = 0 in {
2436 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2437 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2438 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2439 (scalar_to_vector RC:$src2))))],
2440 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2441 let Constraints = "$src1 = $dst" in
2442 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2443 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2445 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2446 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2447 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2448 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2449 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2451 let mayStore = 1 in {
2452 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2453 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2454 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2456 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2457 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2458 [], IIC_SSE_MOV_S_MR>,
2459 EVEX, VEX_LIG, EVEX_K;
2461 } //hasSideEffects = 0
2464 let ExeDomain = SSEPackedSingle in
2465 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2466 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2468 let ExeDomain = SSEPackedDouble in
2469 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2470 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2472 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2473 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2474 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2476 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2477 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2478 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2480 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2481 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2482 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2484 // For the disassembler
2485 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2486 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2487 (ins VR128X:$src1, FR32X:$src2),
2488 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2490 XS, EVEX_4V, VEX_LIG;
2491 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2492 (ins VR128X:$src1, FR64X:$src2),
2493 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2495 XD, EVEX_4V, VEX_LIG, VEX_W;
2498 let Predicates = [HasAVX512] in {
2499 let AddedComplexity = 15 in {
2500 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2501 // MOVS{S,D} to the lower bits.
2502 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2503 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2504 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2505 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2506 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2507 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2508 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2509 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2511 // Move low f32 and clear high bits.
2512 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2513 (SUBREG_TO_REG (i32 0),
2514 (VMOVSSZrr (v4f32 (V_SET0)),
2515 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2516 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2517 (SUBREG_TO_REG (i32 0),
2518 (VMOVSSZrr (v4i32 (V_SET0)),
2519 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2522 let AddedComplexity = 20 in {
2523 // MOVSSrm zeros the high parts of the register; represent this
2524 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2525 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2526 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2527 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2528 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2529 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2530 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2532 // MOVSDrm zeros the high parts of the register; represent this
2533 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2534 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2535 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2536 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2537 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2538 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2539 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2540 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2541 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2542 def : Pat<(v2f64 (X86vzload addr:$src)),
2543 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2545 // Represent the same patterns above but in the form they appear for
2547 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2548 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2549 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2550 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2551 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2552 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2553 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2554 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2555 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2557 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2558 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2559 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2560 FR32X:$src)), sub_xmm)>;
2561 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2562 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2563 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2564 FR64X:$src)), sub_xmm)>;
2565 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2566 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2567 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2569 // Move low f64 and clear high bits.
2570 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2571 (SUBREG_TO_REG (i32 0),
2572 (VMOVSDZrr (v2f64 (V_SET0)),
2573 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2575 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2576 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2577 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2579 // Extract and store.
2580 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2582 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2583 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2585 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2587 // Shuffle with VMOVSS
2588 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2589 (VMOVSSZrr (v4i32 VR128X:$src1),
2590 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2591 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2592 (VMOVSSZrr (v4f32 VR128X:$src1),
2593 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2596 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2597 (SUBREG_TO_REG (i32 0),
2598 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2599 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2601 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2602 (SUBREG_TO_REG (i32 0),
2603 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2604 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2607 // Shuffle with VMOVSD
2608 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2609 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2610 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2611 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2612 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2613 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2614 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2615 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2618 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2619 (SUBREG_TO_REG (i32 0),
2620 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2621 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2623 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2624 (SUBREG_TO_REG (i32 0),
2625 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2626 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2629 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2630 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2631 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2632 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2633 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2634 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2635 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2636 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2639 let AddedComplexity = 15 in
2640 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2642 "vmovq\t{$src, $dst|$dst, $src}",
2643 [(set VR128X:$dst, (v2i64 (X86vzmovl
2644 (v2i64 VR128X:$src))))],
2645 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2647 let AddedComplexity = 20 in
2648 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2650 "vmovq\t{$src, $dst|$dst, $src}",
2651 [(set VR128X:$dst, (v2i64 (X86vzmovl
2652 (loadv2i64 addr:$src))))],
2653 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2654 EVEX_CD8<8, CD8VT8>;
2656 let Predicates = [HasAVX512] in {
2657 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2658 let AddedComplexity = 20 in {
2659 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2660 (VMOVDI2PDIZrm addr:$src)>;
2661 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2662 (VMOV64toPQIZrr GR64:$src)>;
2663 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2664 (VMOVDI2PDIZrr GR32:$src)>;
2666 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2667 (VMOVDI2PDIZrm addr:$src)>;
2668 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2669 (VMOVDI2PDIZrm addr:$src)>;
2670 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2671 (VMOVZPQILo2PQIZrm addr:$src)>;
2672 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2673 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2674 def : Pat<(v2i64 (X86vzload addr:$src)),
2675 (VMOVZPQILo2PQIZrm addr:$src)>;
2678 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2679 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2680 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2681 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2682 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2683 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2684 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2687 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2688 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2690 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2691 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2693 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2694 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2696 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2697 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2699 //===----------------------------------------------------------------------===//
2700 // AVX-512 - Non-temporals
2701 //===----------------------------------------------------------------------===//
2702 let SchedRW = [WriteLoad] in {
2703 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2704 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2705 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2706 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2707 EVEX_CD8<64, CD8VF>;
2709 let Predicates = [HasAVX512, HasVLX] in {
2710 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2712 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2713 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2714 EVEX_CD8<64, CD8VF>;
2716 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2718 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2719 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2720 EVEX_CD8<64, CD8VF>;
2724 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2725 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2726 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2727 let SchedRW = [WriteStore], mayStore = 1,
2728 AddedComplexity = 400 in
2729 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2730 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2731 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2734 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2735 string elty, string elsz, string vsz512,
2736 string vsz256, string vsz128, Domain d,
2737 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2738 let Predicates = [prd] in
2739 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2740 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2741 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2744 let Predicates = [prd, HasVLX] in {
2745 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2746 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2747 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2750 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2751 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2752 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2757 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2758 "i", "64", "8", "4", "2", SSEPackedInt,
2759 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2761 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2762 "f", "64", "8", "4", "2", SSEPackedDouble,
2763 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2765 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2766 "f", "32", "16", "8", "4", SSEPackedSingle,
2767 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2769 //===----------------------------------------------------------------------===//
2770 // AVX-512 - Integer arithmetic
2772 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2773 X86VectorVTInfo _, OpndItins itins,
2774 bit IsCommutable = 0> {
2775 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2776 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2777 "$src2, $src1", "$src1, $src2",
2778 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2779 "", itins.rr, IsCommutable>,
2780 AVX512BIBase, EVEX_4V;
2783 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2784 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2785 "$src2, $src1", "$src1, $src2",
2786 (_.VT (OpNode _.RC:$src1,
2787 (bitconvert (_.LdFrag addr:$src2)))),
2789 AVX512BIBase, EVEX_4V;
2792 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2793 X86VectorVTInfo _, OpndItins itins,
2794 bit IsCommutable = 0> :
2795 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2797 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2798 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2799 "${src2}"##_.BroadcastStr##", $src1",
2800 "$src1, ${src2}"##_.BroadcastStr,
2801 (_.VT (OpNode _.RC:$src1,
2803 (_.ScalarLdFrag addr:$src2)))),
2805 AVX512BIBase, EVEX_4V, EVEX_B;
2808 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2809 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2810 Predicate prd, bit IsCommutable = 0> {
2811 let Predicates = [prd] in
2812 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2813 IsCommutable>, EVEX_V512;
2815 let Predicates = [prd, HasVLX] in {
2816 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2817 IsCommutable>, EVEX_V256;
2818 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2819 IsCommutable>, EVEX_V128;
2823 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2824 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2825 Predicate prd, bit IsCommutable = 0> {
2826 let Predicates = [prd] in
2827 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2828 IsCommutable>, EVEX_V512;
2830 let Predicates = [prd, HasVLX] in {
2831 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2832 IsCommutable>, EVEX_V256;
2833 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2834 IsCommutable>, EVEX_V128;
2838 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2839 OpndItins itins, Predicate prd,
2840 bit IsCommutable = 0> {
2841 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2842 itins, prd, IsCommutable>,
2843 VEX_W, EVEX_CD8<64, CD8VF>;
2846 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2847 OpndItins itins, Predicate prd,
2848 bit IsCommutable = 0> {
2849 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2850 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2853 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2854 OpndItins itins, Predicate prd,
2855 bit IsCommutable = 0> {
2856 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2857 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2860 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2861 OpndItins itins, Predicate prd,
2862 bit IsCommutable = 0> {
2863 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2864 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2867 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2868 SDNode OpNode, OpndItins itins, Predicate prd,
2869 bit IsCommutable = 0> {
2870 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2873 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2877 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2878 SDNode OpNode, OpndItins itins, Predicate prd,
2879 bit IsCommutable = 0> {
2880 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2883 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2887 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2888 bits<8> opc_d, bits<8> opc_q,
2889 string OpcodeStr, SDNode OpNode,
2890 OpndItins itins, bit IsCommutable = 0> {
2891 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2892 itins, HasAVX512, IsCommutable>,
2893 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2894 itins, HasBWI, IsCommutable>;
2897 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2898 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2899 PatFrag memop_frag, X86MemOperand x86memop,
2900 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2901 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2902 let isCommutable = IsCommutable in
2904 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2905 (ins RC:$src1, RC:$src2),
2906 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2908 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2909 (ins KRC:$mask, RC:$src1, RC:$src2),
2910 !strconcat(OpcodeStr,
2911 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2912 [], itins.rr>, EVEX_4V, EVEX_K;
2913 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2914 (ins KRC:$mask, RC:$src1, RC:$src2),
2915 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2916 "|$dst {${mask}} {z}, $src1, $src2}"),
2917 [], itins.rr>, EVEX_4V, EVEX_KZ;
2919 let mayLoad = 1 in {
2920 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2921 (ins RC:$src1, x86memop:$src2),
2922 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2924 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2925 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2926 !strconcat(OpcodeStr,
2927 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2928 [], itins.rm>, EVEX_4V, EVEX_K;
2929 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2930 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2931 !strconcat(OpcodeStr,
2932 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2933 [], itins.rm>, EVEX_4V, EVEX_KZ;
2934 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2935 (ins RC:$src1, x86scalar_mop:$src2),
2936 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2937 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2938 [], itins.rm>, EVEX_4V, EVEX_B;
2939 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2940 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2941 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2942 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2944 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2945 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2946 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2947 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2948 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2950 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2954 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2955 SSE_INTALU_ITINS_P, 1>;
2956 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2957 SSE_INTALU_ITINS_P, 0>;
2958 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2959 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2960 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2961 SSE_INTALU_ITINS_P, HasBWI, 1>;
2962 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2963 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2965 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2966 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2967 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2968 EVEX_CD8<64, CD8VF>, VEX_W;
2970 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2971 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2972 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2974 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2975 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2977 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2978 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2979 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2980 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2981 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2982 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2984 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2985 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2986 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2987 SSE_INTALU_ITINS_P, HasBWI, 1>;
2988 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2989 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2991 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2992 SSE_INTALU_ITINS_P, HasBWI, 1>;
2993 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2994 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2995 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2996 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2998 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2999 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3000 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3001 SSE_INTALU_ITINS_P, HasBWI, 1>;
3002 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3003 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3005 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3006 SSE_INTALU_ITINS_P, HasBWI, 1>;
3007 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3008 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3009 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3010 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3012 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3013 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3014 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3015 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3016 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3017 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3018 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3019 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3020 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3021 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3022 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3023 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3024 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3025 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3026 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3027 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3028 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3029 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3030 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3031 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3032 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3033 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3034 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3035 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3036 //===----------------------------------------------------------------------===//
3037 // AVX-512 - Unpack Instructions
3038 //===----------------------------------------------------------------------===//
3040 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3041 PatFrag mem_frag, RegisterClass RC,
3042 X86MemOperand x86memop, string asm,
3044 def rr : AVX512PI<opc, MRMSrcReg,
3045 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3047 (vt (OpNode RC:$src1, RC:$src2)))],
3049 def rm : AVX512PI<opc, MRMSrcMem,
3050 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3052 (vt (OpNode RC:$src1,
3053 (bitconvert (mem_frag addr:$src2)))))],
3057 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3058 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3059 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3060 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3061 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3062 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3063 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3064 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3065 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3066 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3067 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3068 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3070 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3071 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3072 X86MemOperand x86memop> {
3073 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3074 (ins RC:$src1, RC:$src2),
3075 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3076 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3077 IIC_SSE_UNPCK>, EVEX_4V;
3078 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3079 (ins RC:$src1, x86memop:$src2),
3080 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3081 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3082 (bitconvert (memop_frag addr:$src2)))))],
3083 IIC_SSE_UNPCK>, EVEX_4V;
3085 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3086 VR512, memopv16i32, i512mem>, EVEX_V512,
3087 EVEX_CD8<32, CD8VF>;
3088 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3089 VR512, memopv8i64, i512mem>, EVEX_V512,
3090 VEX_W, EVEX_CD8<64, CD8VF>;
3091 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3092 VR512, memopv16i32, i512mem>, EVEX_V512,
3093 EVEX_CD8<32, CD8VF>;
3094 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3095 VR512, memopv8i64, i512mem>, EVEX_V512,
3096 VEX_W, EVEX_CD8<64, CD8VF>;
3097 //===----------------------------------------------------------------------===//
3101 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3102 SDNode OpNode, PatFrag mem_frag,
3103 X86MemOperand x86memop, ValueType OpVT> {
3104 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3105 (ins RC:$src1, i8imm:$src2),
3106 !strconcat(OpcodeStr,
3107 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3109 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3111 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3112 (ins x86memop:$src1, i8imm:$src2),
3113 !strconcat(OpcodeStr,
3114 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3116 (OpVT (OpNode (mem_frag addr:$src1),
3117 (i8 imm:$src2))))]>, EVEX;
3120 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3121 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3123 //===----------------------------------------------------------------------===//
3124 // AVX-512 Logical Instructions
3125 //===----------------------------------------------------------------------===//
3127 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3128 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3129 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3130 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3131 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3132 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3133 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3134 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3136 //===----------------------------------------------------------------------===//
3137 // AVX-512 FP arithmetic
3138 //===----------------------------------------------------------------------===//
3140 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3142 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3143 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3144 EVEX_CD8<32, CD8VT1>;
3145 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3146 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3147 EVEX_CD8<64, CD8VT1>;
3150 let isCommutable = 1 in {
3151 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3152 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3153 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3154 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3156 let isCommutable = 0 in {
3157 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3158 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3161 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3162 X86VectorVTInfo _, bit IsCommutable> {
3163 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3164 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3165 "$src2, $src1", "$src1, $src2",
3166 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3167 let mayLoad = 1 in {
3168 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3169 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3170 "$src2, $src1", "$src1, $src2",
3171 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3172 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3173 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3174 "${src2}"##_.BroadcastStr##", $src1",
3175 "$src1, ${src2}"##_.BroadcastStr,
3176 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3177 (_.ScalarLdFrag addr:$src2))))>,
3182 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3183 bit IsCommutable = 0> {
3184 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3185 IsCommutable>, EVEX_V512, PS,
3186 EVEX_CD8<32, CD8VF>;
3187 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3188 IsCommutable>, EVEX_V512, PD, VEX_W,
3189 EVEX_CD8<64, CD8VF>;
3191 // Define only if AVX512VL feature is present.
3192 let Predicates = [HasVLX] in {
3193 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3194 IsCommutable>, EVEX_V128, PS,
3195 EVEX_CD8<32, CD8VF>;
3196 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3197 IsCommutable>, EVEX_V256, PS,
3198 EVEX_CD8<32, CD8VF>;
3199 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3200 IsCommutable>, EVEX_V128, PD, VEX_W,
3201 EVEX_CD8<64, CD8VF>;
3202 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3203 IsCommutable>, EVEX_V256, PD, VEX_W,
3204 EVEX_CD8<64, CD8VF>;
3208 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3209 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3210 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3211 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3212 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3213 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3215 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3216 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3217 (i16 -1), FROUND_CURRENT)),
3218 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3220 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3221 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3222 (i8 -1), FROUND_CURRENT)),
3223 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3225 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3226 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3227 (i16 -1), FROUND_CURRENT)),
3228 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3230 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3231 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3232 (i8 -1), FROUND_CURRENT)),
3233 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3234 //===----------------------------------------------------------------------===//
3235 // AVX-512 VPTESTM instructions
3236 //===----------------------------------------------------------------------===//
3238 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3239 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3240 SDNode OpNode, ValueType vt> {
3241 def rr : AVX512PI<opc, MRMSrcReg,
3242 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3243 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3244 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3245 SSEPackedInt>, EVEX_4V;
3246 def rm : AVX512PI<opc, MRMSrcMem,
3247 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3249 [(set KRC:$dst, (OpNode (vt RC:$src1),
3250 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3253 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3254 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3255 EVEX_CD8<32, CD8VF>;
3256 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3257 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3258 EVEX_CD8<64, CD8VF>;
3260 let Predicates = [HasCDI] in {
3261 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3262 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3263 EVEX_CD8<32, CD8VF>;
3264 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3265 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3266 EVEX_CD8<64, CD8VF>;
3269 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3270 (v16i32 VR512:$src2), (i16 -1))),
3271 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3273 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3274 (v8i64 VR512:$src2), (i8 -1))),
3275 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3277 //===----------------------------------------------------------------------===//
3278 // AVX-512 Shift instructions
3279 //===----------------------------------------------------------------------===//
3280 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3281 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3282 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3283 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3284 "$src2, $src1", "$src1, $src2",
3285 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3286 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3287 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3288 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3289 "$src2, $src1", "$src1, $src2",
3290 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3291 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3294 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3295 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3296 // src2 is always 128-bit
3297 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3298 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3299 "$src2, $src1", "$src1, $src2",
3300 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3301 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3302 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3303 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3304 "$src2, $src1", "$src1, $src2",
3305 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3306 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3309 multiclass avx512_varshift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3310 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3311 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3314 multiclass avx512_varshift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3316 defm D : avx512_varshift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3317 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3318 defm Q : avx512_varshift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3319 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3322 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3324 EVEX_V512, EVEX_CD8<32, CD8VF>;
3325 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3326 v8i64_info>, EVEX_V512,
3327 EVEX_CD8<64, CD8VF>, VEX_W;
3329 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3330 v16i32_info>, EVEX_V512,
3331 EVEX_CD8<32, CD8VF>;
3332 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3333 v8i64_info>, EVEX_V512,
3334 EVEX_CD8<64, CD8VF>, VEX_W;
3336 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3338 EVEX_V512, EVEX_CD8<32, CD8VF>;
3339 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3340 v8i64_info>, EVEX_V512,
3341 EVEX_CD8<64, CD8VF>, VEX_W;
3343 defm VPSRL : avx512_varshift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3344 defm VPSLL : avx512_varshift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3345 defm VPSRA : avx512_varshift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3347 //===-------------------------------------------------------------------===//
3348 // Variable Bit Shifts
3349 //===-------------------------------------------------------------------===//
3350 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3351 RegisterClass RC, ValueType vt,
3352 X86MemOperand x86memop, PatFrag mem_frag> {
3353 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3354 (ins RC:$src1, RC:$src2),
3355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3357 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3359 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3360 (ins RC:$src1, x86memop:$src2),
3361 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3363 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3367 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3368 i512mem, memopv16i32>, EVEX_V512,
3369 EVEX_CD8<32, CD8VF>;
3370 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3371 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3372 EVEX_CD8<64, CD8VF>;
3373 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3374 i512mem, memopv16i32>, EVEX_V512,
3375 EVEX_CD8<32, CD8VF>;
3376 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3377 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3378 EVEX_CD8<64, CD8VF>;
3379 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3380 i512mem, memopv16i32>, EVEX_V512,
3381 EVEX_CD8<32, CD8VF>;
3382 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3383 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3384 EVEX_CD8<64, CD8VF>;
3386 //===----------------------------------------------------------------------===//
3387 // AVX-512 - MOVDDUP
3388 //===----------------------------------------------------------------------===//
3390 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3391 X86MemOperand x86memop, PatFrag memop_frag> {
3392 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3393 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3394 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3395 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3396 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3398 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3401 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3402 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3403 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3404 (VMOVDDUPZrm addr:$src)>;
3406 //===---------------------------------------------------------------------===//
3407 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3408 //===---------------------------------------------------------------------===//
3409 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3410 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3411 X86MemOperand x86memop> {
3412 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3413 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3414 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3416 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3417 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3418 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3421 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3422 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3423 EVEX_CD8<32, CD8VF>;
3424 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3425 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3426 EVEX_CD8<32, CD8VF>;
3428 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3429 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3430 (VMOVSHDUPZrm addr:$src)>;
3431 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3432 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3433 (VMOVSLDUPZrm addr:$src)>;
3435 //===----------------------------------------------------------------------===//
3436 // Move Low to High and High to Low packed FP Instructions
3437 //===----------------------------------------------------------------------===//
3438 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3439 (ins VR128X:$src1, VR128X:$src2),
3440 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3441 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3442 IIC_SSE_MOV_LH>, EVEX_4V;
3443 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3444 (ins VR128X:$src1, VR128X:$src2),
3445 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3446 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3447 IIC_SSE_MOV_LH>, EVEX_4V;
3449 let Predicates = [HasAVX512] in {
3451 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3452 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3453 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3454 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3457 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3458 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3461 //===----------------------------------------------------------------------===//
3462 // FMA - Fused Multiply Operations
3465 let Constraints = "$src1 = $dst" in {
3466 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3467 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3468 SDPatternOperator OpNode = null_frag> {
3469 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3470 (ins _.RC:$src2, _.RC:$src3),
3471 OpcodeStr, "$src3, $src2", "$src2, $src3",
3472 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3476 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3477 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3478 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3479 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3480 (_.MemOpFrag addr:$src3))))]>;
3481 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3482 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3483 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
3484 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3485 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3486 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3488 } // Constraints = "$src1 = $dst"
3490 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3491 string OpcodeStr, X86VectorVTInfo VTI,
3492 SDPatternOperator OpNode> {
3493 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3495 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3497 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3499 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3502 let ExeDomain = SSEPackedSingle in {
3503 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3504 v16f32_info, X86Fmadd>;
3505 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3506 v16f32_info, X86Fmsub>;
3507 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3508 v16f32_info, X86Fmaddsub>;
3509 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3510 v16f32_info, X86Fmsubadd>;
3511 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3512 v16f32_info, X86Fnmadd>;
3513 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3514 v16f32_info, X86Fnmsub>;
3516 let ExeDomain = SSEPackedDouble in {
3517 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3518 v8f64_info, X86Fmadd>, VEX_W;
3519 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3520 v8f64_info, X86Fmsub>, VEX_W;
3521 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3522 v8f64_info, X86Fmaddsub>, VEX_W;
3523 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3524 v8f64_info, X86Fmsubadd>, VEX_W;
3525 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3526 v8f64_info, X86Fnmadd>, VEX_W;
3527 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3528 v8f64_info, X86Fnmsub>, VEX_W;
3531 let Constraints = "$src1 = $dst" in {
3532 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3533 X86VectorVTInfo _> {
3535 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3536 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3537 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3538 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3540 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3541 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3542 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3543 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3545 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3546 (_.ScalarLdFrag addr:$src2))),
3547 _.RC:$src3))]>, EVEX_B;
3549 } // Constraints = "$src1 = $dst"
3552 let ExeDomain = SSEPackedSingle in {
3553 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3555 EVEX_V512, EVEX_CD8<32, CD8VF>;
3556 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3558 EVEX_V512, EVEX_CD8<32, CD8VF>;
3559 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3561 EVEX_V512, EVEX_CD8<32, CD8VF>;
3562 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3564 EVEX_V512, EVEX_CD8<32, CD8VF>;
3565 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3567 EVEX_V512, EVEX_CD8<32, CD8VF>;
3568 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3570 EVEX_V512, EVEX_CD8<32, CD8VF>;
3572 let ExeDomain = SSEPackedDouble in {
3573 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3575 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3576 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3578 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3579 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3581 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3582 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3584 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3585 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3587 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3588 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3590 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3594 let Constraints = "$src1 = $dst" in {
3595 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3596 RegisterClass RC, ValueType OpVT,
3597 X86MemOperand x86memop, Operand memop,
3599 let isCommutable = 1 in
3600 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3601 (ins RC:$src1, RC:$src2, RC:$src3),
3602 !strconcat(OpcodeStr,
3603 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3605 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3607 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3608 (ins RC:$src1, RC:$src2, f128mem:$src3),
3609 !strconcat(OpcodeStr,
3610 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3612 (OpVT (OpNode RC:$src2, RC:$src1,
3613 (mem_frag addr:$src3))))]>;
3616 } // Constraints = "$src1 = $dst"
3618 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3619 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3620 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3621 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3622 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3623 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3624 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3625 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3626 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3627 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3628 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3629 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3630 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3631 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3632 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3633 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3635 //===----------------------------------------------------------------------===//
3636 // AVX-512 Scalar convert from sign integer to float/double
3637 //===----------------------------------------------------------------------===//
3639 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3640 X86MemOperand x86memop, string asm> {
3641 let hasSideEffects = 0 in {
3642 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3643 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3646 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3647 (ins DstRC:$src1, x86memop:$src),
3648 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3650 } // hasSideEffects = 0
3652 let Predicates = [HasAVX512] in {
3653 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3654 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3655 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3656 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3657 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3658 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3659 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3660 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3662 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3663 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3664 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3665 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3666 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3667 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3668 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3669 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3671 def : Pat<(f32 (sint_to_fp GR32:$src)),
3672 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3673 def : Pat<(f32 (sint_to_fp GR64:$src)),
3674 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3675 def : Pat<(f64 (sint_to_fp GR32:$src)),
3676 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3677 def : Pat<(f64 (sint_to_fp GR64:$src)),
3678 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3680 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3681 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3682 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3683 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3684 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3685 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3686 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3687 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3689 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3690 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3691 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3692 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3693 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3694 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3695 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3696 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3698 def : Pat<(f32 (uint_to_fp GR32:$src)),
3699 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3700 def : Pat<(f32 (uint_to_fp GR64:$src)),
3701 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3702 def : Pat<(f64 (uint_to_fp GR32:$src)),
3703 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3704 def : Pat<(f64 (uint_to_fp GR64:$src)),
3705 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3708 //===----------------------------------------------------------------------===//
3709 // AVX-512 Scalar convert from float/double to integer
3710 //===----------------------------------------------------------------------===//
3711 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3712 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3714 let hasSideEffects = 0 in {
3715 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3716 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3717 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3718 Requires<[HasAVX512]>;
3720 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3721 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3722 Requires<[HasAVX512]>;
3723 } // hasSideEffects = 0
3725 let Predicates = [HasAVX512] in {
3726 // Convert float/double to signed/unsigned int 32/64
3727 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3728 ssmem, sse_load_f32, "cvtss2si">,
3729 XS, EVEX_CD8<32, CD8VT1>;
3730 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3731 ssmem, sse_load_f32, "cvtss2si">,
3732 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3733 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3734 ssmem, sse_load_f32, "cvtss2usi">,
3735 XS, EVEX_CD8<32, CD8VT1>;
3736 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3737 int_x86_avx512_cvtss2usi64, ssmem,
3738 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3739 EVEX_CD8<32, CD8VT1>;
3740 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3741 sdmem, sse_load_f64, "cvtsd2si">,
3742 XD, EVEX_CD8<64, CD8VT1>;
3743 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3744 sdmem, sse_load_f64, "cvtsd2si">,
3745 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3746 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3747 sdmem, sse_load_f64, "cvtsd2usi">,
3748 XD, EVEX_CD8<64, CD8VT1>;
3749 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3750 int_x86_avx512_cvtsd2usi64, sdmem,
3751 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3752 EVEX_CD8<64, CD8VT1>;
3754 let isCodeGenOnly = 1 in {
3755 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3756 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3757 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3758 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3759 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3760 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3761 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3762 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3763 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3764 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3765 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3766 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3768 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3769 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3770 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3771 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3772 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3773 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3774 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3775 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3776 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3777 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3778 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3779 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3780 } // isCodeGenOnly = 1
3782 // Convert float/double to signed/unsigned int 32/64 with truncation
3783 let isCodeGenOnly = 1 in {
3784 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3785 ssmem, sse_load_f32, "cvttss2si">,
3786 XS, EVEX_CD8<32, CD8VT1>;
3787 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3788 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3789 "cvttss2si">, XS, VEX_W,
3790 EVEX_CD8<32, CD8VT1>;
3791 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3792 sdmem, sse_load_f64, "cvttsd2si">, XD,
3793 EVEX_CD8<64, CD8VT1>;
3794 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3795 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3796 "cvttsd2si">, XD, VEX_W,
3797 EVEX_CD8<64, CD8VT1>;
3798 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3799 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3800 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3801 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3802 int_x86_avx512_cvttss2usi64, ssmem,
3803 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3804 EVEX_CD8<32, CD8VT1>;
3805 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3806 int_x86_avx512_cvttsd2usi,
3807 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3808 EVEX_CD8<64, CD8VT1>;
3809 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3810 int_x86_avx512_cvttsd2usi64, sdmem,
3811 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3812 EVEX_CD8<64, CD8VT1>;
3813 } // isCodeGenOnly = 1
3815 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3816 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3818 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3819 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3820 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3821 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3822 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3823 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3826 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3827 loadf32, "cvttss2si">, XS,
3828 EVEX_CD8<32, CD8VT1>;
3829 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3830 loadf32, "cvttss2usi">, XS,
3831 EVEX_CD8<32, CD8VT1>;
3832 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3833 loadf32, "cvttss2si">, XS, VEX_W,
3834 EVEX_CD8<32, CD8VT1>;
3835 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3836 loadf32, "cvttss2usi">, XS, VEX_W,
3837 EVEX_CD8<32, CD8VT1>;
3838 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3839 loadf64, "cvttsd2si">, XD,
3840 EVEX_CD8<64, CD8VT1>;
3841 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3842 loadf64, "cvttsd2usi">, XD,
3843 EVEX_CD8<64, CD8VT1>;
3844 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3845 loadf64, "cvttsd2si">, XD, VEX_W,
3846 EVEX_CD8<64, CD8VT1>;
3847 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3848 loadf64, "cvttsd2usi">, XD, VEX_W,
3849 EVEX_CD8<64, CD8VT1>;
3851 //===----------------------------------------------------------------------===//
3852 // AVX-512 Convert form float to double and back
3853 //===----------------------------------------------------------------------===//
3854 let hasSideEffects = 0 in {
3855 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3856 (ins FR32X:$src1, FR32X:$src2),
3857 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3858 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3860 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3861 (ins FR32X:$src1, f32mem:$src2),
3862 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3863 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3864 EVEX_CD8<32, CD8VT1>;
3866 // Convert scalar double to scalar single
3867 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3868 (ins FR64X:$src1, FR64X:$src2),
3869 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3870 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3872 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3873 (ins FR64X:$src1, f64mem:$src2),
3874 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3875 []>, EVEX_4V, VEX_LIG, VEX_W,
3876 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3879 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3880 Requires<[HasAVX512]>;
3881 def : Pat<(fextend (loadf32 addr:$src)),
3882 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3884 def : Pat<(extloadf32 addr:$src),
3885 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3886 Requires<[HasAVX512, OptForSize]>;
3888 def : Pat<(extloadf32 addr:$src),
3889 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3890 Requires<[HasAVX512, OptForSpeed]>;
3892 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3893 Requires<[HasAVX512]>;
3895 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3896 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3897 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3899 let hasSideEffects = 0 in {
3900 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3901 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3903 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3904 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3905 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3906 [], d>, EVEX, EVEX_B, EVEX_RC;
3908 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3909 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3911 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3912 } // hasSideEffects = 0
3915 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3916 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3917 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3919 let hasSideEffects = 0 in {
3920 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3921 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3923 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3925 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3926 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3928 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3929 } // hasSideEffects = 0
3932 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3933 memopv8f64, f512mem, v8f32, v8f64,
3934 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3935 EVEX_CD8<64, CD8VF>;
3937 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3938 memopv4f64, f256mem, v8f64, v8f32,
3939 SSEPackedDouble>, EVEX_V512, PS,
3940 EVEX_CD8<32, CD8VH>;
3941 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3942 (VCVTPS2PDZrm addr:$src)>;
3944 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3945 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3946 (VCVTPD2PSZrr VR512:$src)>;
3948 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3949 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3950 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3952 //===----------------------------------------------------------------------===//
3953 // AVX-512 Vector convert from sign integer to float/double
3954 //===----------------------------------------------------------------------===//
3956 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3957 memopv8i64, i512mem, v16f32, v16i32,
3958 SSEPackedSingle>, EVEX_V512, PS,
3959 EVEX_CD8<32, CD8VF>;
3961 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3962 memopv4i64, i256mem, v8f64, v8i32,
3963 SSEPackedDouble>, EVEX_V512, XS,
3964 EVEX_CD8<32, CD8VH>;
3966 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3967 memopv16f32, f512mem, v16i32, v16f32,
3968 SSEPackedSingle>, EVEX_V512, XS,
3969 EVEX_CD8<32, CD8VF>;
3971 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3972 memopv8f64, f512mem, v8i32, v8f64,
3973 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3974 EVEX_CD8<64, CD8VF>;
3976 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3977 memopv16f32, f512mem, v16i32, v16f32,
3978 SSEPackedSingle>, EVEX_V512, PS,
3979 EVEX_CD8<32, CD8VF>;
3981 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3982 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3983 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3984 (VCVTTPS2UDQZrr VR512:$src)>;
3986 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3987 memopv8f64, f512mem, v8i32, v8f64,
3988 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3989 EVEX_CD8<64, CD8VF>;
3991 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3992 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3993 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3994 (VCVTTPD2UDQZrr VR512:$src)>;
3996 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3997 memopv4i64, f256mem, v8f64, v8i32,
3998 SSEPackedDouble>, EVEX_V512, XS,
3999 EVEX_CD8<32, CD8VH>;
4001 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4002 memopv16i32, f512mem, v16f32, v16i32,
4003 SSEPackedSingle>, EVEX_V512, XD,
4004 EVEX_CD8<32, CD8VF>;
4006 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4007 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4008 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4010 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4011 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4012 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4014 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4015 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4016 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4018 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4019 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4020 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4022 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4023 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4024 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4026 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4027 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4028 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4029 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4030 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4031 (VCVTDQ2PDZrr VR256X:$src)>;
4032 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4033 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4034 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4035 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4036 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4037 (VCVTUDQ2PDZrr VR256X:$src)>;
4039 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4040 RegisterClass DstRC, PatFrag mem_frag,
4041 X86MemOperand x86memop, Domain d> {
4042 let hasSideEffects = 0 in {
4043 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4044 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4046 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4047 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4048 [], d>, EVEX, EVEX_B, EVEX_RC;
4050 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4051 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4053 } // hasSideEffects = 0
4056 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4057 memopv16f32, f512mem, SSEPackedSingle>, PD,
4058 EVEX_V512, EVEX_CD8<32, CD8VF>;
4059 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4060 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4061 EVEX_V512, EVEX_CD8<64, CD8VF>;
4063 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4064 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4065 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4067 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4068 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4069 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4071 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4072 memopv16f32, f512mem, SSEPackedSingle>,
4073 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4074 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4075 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4076 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4078 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4079 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4080 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4082 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4083 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4084 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4086 let Predicates = [HasAVX512] in {
4087 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4088 (VCVTPD2PSZrm addr:$src)>;
4089 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4090 (VCVTPS2PDZrm addr:$src)>;
4093 //===----------------------------------------------------------------------===//
4094 // Half precision conversion instructions
4095 //===----------------------------------------------------------------------===//
4096 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4097 X86MemOperand x86memop> {
4098 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4099 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4101 let hasSideEffects = 0, mayLoad = 1 in
4102 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4103 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4106 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4107 X86MemOperand x86memop> {
4108 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4109 (ins srcRC:$src1, i32i8imm:$src2),
4110 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4112 let hasSideEffects = 0, mayStore = 1 in
4113 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4114 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4115 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4118 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4119 EVEX_CD8<32, CD8VH>;
4120 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4121 EVEX_CD8<32, CD8VH>;
4123 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4124 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4125 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4127 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4128 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4129 (VCVTPH2PSZrr VR256X:$src)>;
4131 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4132 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4133 "ucomiss">, PS, EVEX, VEX_LIG,
4134 EVEX_CD8<32, CD8VT1>;
4135 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4136 "ucomisd">, PD, EVEX,
4137 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4138 let Pattern = []<dag> in {
4139 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4140 "comiss">, PS, EVEX, VEX_LIG,
4141 EVEX_CD8<32, CD8VT1>;
4142 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4143 "comisd">, PD, EVEX,
4144 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4146 let isCodeGenOnly = 1 in {
4147 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4148 load, "ucomiss">, PS, EVEX, VEX_LIG,
4149 EVEX_CD8<32, CD8VT1>;
4150 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4151 load, "ucomisd">, PD, EVEX,
4152 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4154 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4155 load, "comiss">, PS, EVEX, VEX_LIG,
4156 EVEX_CD8<32, CD8VT1>;
4157 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4158 load, "comisd">, PD, EVEX,
4159 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4163 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4164 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4165 X86MemOperand x86memop> {
4166 let hasSideEffects = 0 in {
4167 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4168 (ins RC:$src1, RC:$src2),
4169 !strconcat(OpcodeStr,
4170 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4171 let mayLoad = 1 in {
4172 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4173 (ins RC:$src1, x86memop:$src2),
4174 !strconcat(OpcodeStr,
4175 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4180 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4181 EVEX_CD8<32, CD8VT1>;
4182 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4183 VEX_W, EVEX_CD8<64, CD8VT1>;
4184 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4185 EVEX_CD8<32, CD8VT1>;
4186 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4187 VEX_W, EVEX_CD8<64, CD8VT1>;
4189 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4190 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4191 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4192 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4194 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4195 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4196 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4197 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4199 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4200 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4201 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4202 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4204 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4205 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4206 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4207 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4209 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4210 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4211 X86VectorVTInfo _> {
4212 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4213 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4214 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4215 let mayLoad = 1 in {
4216 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4217 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4219 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4220 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4221 (ins _.ScalarMemOp:$src), OpcodeStr,
4222 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4224 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4229 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4230 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4231 EVEX_V512, EVEX_CD8<32, CD8VF>;
4232 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4233 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4235 // Define only if AVX512VL feature is present.
4236 let Predicates = [HasVLX] in {
4237 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4238 OpNode, v4f32x_info>,
4239 EVEX_V128, EVEX_CD8<32, CD8VF>;
4240 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4241 OpNode, v8f32x_info>,
4242 EVEX_V256, EVEX_CD8<32, CD8VF>;
4243 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4244 OpNode, v2f64x_info>,
4245 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4246 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4247 OpNode, v4f64x_info>,
4248 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4252 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4253 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4255 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4256 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4257 (VRSQRT14PSZr VR512:$src)>;
4258 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4259 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4260 (VRSQRT14PDZr VR512:$src)>;
4262 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4263 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4264 (VRCP14PSZr VR512:$src)>;
4265 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4266 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4267 (VRCP14PDZr VR512:$src)>;
4269 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4270 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4273 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4274 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4275 "$src2, $src1", "$src1, $src2",
4276 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4277 (i32 FROUND_CURRENT))>;
4279 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4280 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4281 "$src2, $src1", "$src1, $src2",
4282 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4283 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4285 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4286 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4287 "$src2, $src1", "$src1, $src2",
4288 (OpNode (_.VT _.RC:$src1),
4289 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4290 (i32 FROUND_CURRENT))>;
4293 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4294 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4295 EVEX_CD8<32, CD8VT1>;
4296 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4297 EVEX_CD8<64, CD8VT1>, VEX_W;
4300 let hasSideEffects = 0, Predicates = [HasERI] in {
4301 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4302 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4304 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4306 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4309 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4310 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4311 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4313 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4314 (ins _.RC:$src), OpcodeStr,
4316 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4319 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4320 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4322 (bitconvert (_.LdFrag addr:$src))),
4323 (i32 FROUND_CURRENT))>;
4325 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4326 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4328 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4329 (i32 FROUND_CURRENT))>, EVEX_B;
4332 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4333 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4334 EVEX_CD8<32, CD8VF>;
4335 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4336 VEX_W, EVEX_CD8<32, CD8VF>;
4339 let Predicates = [HasERI], hasSideEffects = 0 in {
4341 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4342 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4343 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4346 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4347 SDNode OpNode, X86VectorVTInfo _>{
4348 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4349 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4350 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4351 let mayLoad = 1 in {
4352 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4353 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4355 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4357 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4358 (ins _.ScalarMemOp:$src), OpcodeStr,
4359 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4361 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4366 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4367 Intrinsic F32Int, Intrinsic F64Int,
4368 OpndItins itins_s, OpndItins itins_d> {
4369 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4370 (ins FR32X:$src1, FR32X:$src2),
4371 !strconcat(OpcodeStr,
4372 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4373 [], itins_s.rr>, XS, EVEX_4V;
4374 let isCodeGenOnly = 1 in
4375 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4376 (ins VR128X:$src1, VR128X:$src2),
4377 !strconcat(OpcodeStr,
4378 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4380 (F32Int VR128X:$src1, VR128X:$src2))],
4381 itins_s.rr>, XS, EVEX_4V;
4382 let mayLoad = 1 in {
4383 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4384 (ins FR32X:$src1, f32mem:$src2),
4385 !strconcat(OpcodeStr,
4386 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4387 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4388 let isCodeGenOnly = 1 in
4389 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4390 (ins VR128X:$src1, ssmem:$src2),
4391 !strconcat(OpcodeStr,
4392 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4394 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4395 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4397 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4398 (ins FR64X:$src1, FR64X:$src2),
4399 !strconcat(OpcodeStr,
4400 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4402 let isCodeGenOnly = 1 in
4403 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4404 (ins VR128X:$src1, VR128X:$src2),
4405 !strconcat(OpcodeStr,
4406 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4408 (F64Int VR128X:$src1, VR128X:$src2))],
4409 itins_s.rr>, XD, EVEX_4V, VEX_W;
4410 let mayLoad = 1 in {
4411 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4412 (ins FR64X:$src1, f64mem:$src2),
4413 !strconcat(OpcodeStr,
4414 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4415 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4416 let isCodeGenOnly = 1 in
4417 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4418 (ins VR128X:$src1, sdmem:$src2),
4419 !strconcat(OpcodeStr,
4420 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4422 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4423 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4427 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4429 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4431 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4432 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4434 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4435 // Define only if AVX512VL feature is present.
4436 let Predicates = [HasVLX] in {
4437 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4438 OpNode, v4f32x_info>,
4439 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4440 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4441 OpNode, v8f32x_info>,
4442 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4443 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4444 OpNode, v2f64x_info>,
4445 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4446 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4447 OpNode, v4f64x_info>,
4448 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4452 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4454 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4455 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4456 SSE_SQRTSS, SSE_SQRTSD>;
4458 let Predicates = [HasAVX512] in {
4459 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4460 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4461 (VSQRTPSZr VR512:$src1)>;
4462 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4463 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4464 (VSQRTPDZr VR512:$src1)>;
4466 def : Pat<(f32 (fsqrt FR32X:$src)),
4467 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4468 def : Pat<(f32 (fsqrt (load addr:$src))),
4469 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4470 Requires<[OptForSize]>;
4471 def : Pat<(f64 (fsqrt FR64X:$src)),
4472 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4473 def : Pat<(f64 (fsqrt (load addr:$src))),
4474 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4475 Requires<[OptForSize]>;
4477 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4478 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4479 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4480 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4481 Requires<[OptForSize]>;
4483 def : Pat<(f32 (X86frcp FR32X:$src)),
4484 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4485 def : Pat<(f32 (X86frcp (load addr:$src))),
4486 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4487 Requires<[OptForSize]>;
4489 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4490 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4491 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4493 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4494 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4496 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4497 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4498 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4500 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4501 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4505 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4506 X86MemOperand x86memop, RegisterClass RC,
4507 PatFrag mem_frag32, PatFrag mem_frag64,
4508 Intrinsic V4F32Int, Intrinsic V2F64Int,
4510 let ExeDomain = SSEPackedSingle in {
4511 // Intrinsic operation, reg.
4512 // Vector intrinsic operation, reg
4513 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4514 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4515 !strconcat(OpcodeStr,
4516 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4517 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4519 // Vector intrinsic operation, mem
4520 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4521 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4522 !strconcat(OpcodeStr,
4523 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4525 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4526 EVEX_CD8<32, VForm>;
4527 } // ExeDomain = SSEPackedSingle
4529 let ExeDomain = SSEPackedDouble in {
4530 // Vector intrinsic operation, reg
4531 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4532 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4533 !strconcat(OpcodeStr,
4534 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4535 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4537 // Vector intrinsic operation, mem
4538 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4539 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4540 !strconcat(OpcodeStr,
4541 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4543 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4544 EVEX_CD8<64, VForm>;
4545 } // ExeDomain = SSEPackedDouble
4548 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4552 let ExeDomain = GenericDomain in {
4554 let hasSideEffects = 0 in
4555 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4556 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4557 !strconcat(OpcodeStr,
4558 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4561 // Intrinsic operation, reg.
4562 let isCodeGenOnly = 1 in
4563 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4564 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4565 !strconcat(OpcodeStr,
4566 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4567 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4569 // Intrinsic operation, mem.
4570 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4571 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4572 !strconcat(OpcodeStr,
4573 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4574 [(set VR128X:$dst, (F32Int VR128X:$src1,
4575 sse_load_f32:$src2, imm:$src3))]>,
4576 EVEX_CD8<32, CD8VT1>;
4579 let hasSideEffects = 0 in
4580 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4581 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4582 !strconcat(OpcodeStr,
4583 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4586 // Intrinsic operation, reg.
4587 let isCodeGenOnly = 1 in
4588 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4589 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4590 !strconcat(OpcodeStr,
4591 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4592 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4595 // Intrinsic operation, mem.
4596 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4597 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4598 !strconcat(OpcodeStr,
4599 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4601 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4602 VEX_W, EVEX_CD8<64, CD8VT1>;
4603 } // ExeDomain = GenericDomain
4606 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4607 X86MemOperand x86memop, RegisterClass RC,
4608 PatFrag mem_frag, Domain d> {
4609 let ExeDomain = d in {
4610 // Intrinsic operation, reg.
4611 // Vector intrinsic operation, reg
4612 def r : AVX512AIi8<opc, MRMSrcReg,
4613 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4614 !strconcat(OpcodeStr,
4615 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4618 // Vector intrinsic operation, mem
4619 def m : AVX512AIi8<opc, MRMSrcMem,
4620 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4621 !strconcat(OpcodeStr,
4622 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4628 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4629 memopv16f32, SSEPackedSingle>, EVEX_V512,
4630 EVEX_CD8<32, CD8VF>;
4632 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4633 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4635 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4638 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4639 memopv8f64, SSEPackedDouble>, EVEX_V512,
4640 VEX_W, EVEX_CD8<64, CD8VF>;
4642 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4643 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4645 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4647 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4648 Operand x86memop, RegisterClass RC, Domain d> {
4649 let ExeDomain = d in {
4650 def r : AVX512AIi8<opc, MRMSrcReg,
4651 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4652 !strconcat(OpcodeStr,
4653 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4656 def m : AVX512AIi8<opc, MRMSrcMem,
4657 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4658 !strconcat(OpcodeStr,
4659 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4664 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4665 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4667 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4668 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4670 def : Pat<(ffloor FR32X:$src),
4671 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4672 def : Pat<(f64 (ffloor FR64X:$src)),
4673 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4674 def : Pat<(f32 (fnearbyint FR32X:$src)),
4675 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4676 def : Pat<(f64 (fnearbyint FR64X:$src)),
4677 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4678 def : Pat<(f32 (fceil FR32X:$src)),
4679 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4680 def : Pat<(f64 (fceil FR64X:$src)),
4681 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4682 def : Pat<(f32 (frint FR32X:$src)),
4683 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4684 def : Pat<(f64 (frint FR64X:$src)),
4685 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4686 def : Pat<(f32 (ftrunc FR32X:$src)),
4687 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4688 def : Pat<(f64 (ftrunc FR64X:$src)),
4689 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4691 def : Pat<(v16f32 (ffloor VR512:$src)),
4692 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4693 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4694 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4695 def : Pat<(v16f32 (fceil VR512:$src)),
4696 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4697 def : Pat<(v16f32 (frint VR512:$src)),
4698 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4699 def : Pat<(v16f32 (ftrunc VR512:$src)),
4700 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4702 def : Pat<(v8f64 (ffloor VR512:$src)),
4703 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4704 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4705 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4706 def : Pat<(v8f64 (fceil VR512:$src)),
4707 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4708 def : Pat<(v8f64 (frint VR512:$src)),
4709 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4710 def : Pat<(v8f64 (ftrunc VR512:$src)),
4711 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4713 //-------------------------------------------------
4714 // Integer truncate and extend operations
4715 //-------------------------------------------------
4717 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4718 RegisterClass dstRC, RegisterClass srcRC,
4719 RegisterClass KRC, X86MemOperand x86memop> {
4720 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4722 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4725 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4726 (ins KRC:$mask, srcRC:$src),
4727 !strconcat(OpcodeStr,
4728 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4731 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4732 (ins KRC:$mask, srcRC:$src),
4733 !strconcat(OpcodeStr,
4734 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4737 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4738 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4741 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4742 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4743 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4747 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4748 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4749 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4750 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4751 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4752 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4753 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4754 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4755 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4756 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4757 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4758 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4759 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4760 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4761 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4762 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4763 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4764 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4765 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4766 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4767 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4768 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4769 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4770 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4771 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4772 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4773 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4774 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4775 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4776 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4778 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4779 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4780 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4781 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4782 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4784 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4785 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4786 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4787 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4788 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4789 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4790 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4791 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4794 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4795 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4796 PatFrag mem_frag, X86MemOperand x86memop,
4797 ValueType OpVT, ValueType InVT> {
4799 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4801 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4802 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4804 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4805 (ins KRC:$mask, SrcRC:$src),
4806 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4809 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4810 (ins KRC:$mask, SrcRC:$src),
4811 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4814 let mayLoad = 1 in {
4815 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4816 (ins x86memop:$src),
4817 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4819 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4822 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4823 (ins KRC:$mask, x86memop:$src),
4824 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4828 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4829 (ins KRC:$mask, x86memop:$src),
4830 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4836 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4837 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4839 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4840 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4842 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4843 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4844 EVEX_CD8<16, CD8VH>;
4845 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4846 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4847 EVEX_CD8<16, CD8VQ>;
4848 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4849 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4850 EVEX_CD8<32, CD8VH>;
4852 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4853 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4855 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4856 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4858 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4859 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4860 EVEX_CD8<16, CD8VH>;
4861 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4862 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4863 EVEX_CD8<16, CD8VQ>;
4864 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4865 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4866 EVEX_CD8<32, CD8VH>;
4868 //===----------------------------------------------------------------------===//
4869 // GATHER - SCATTER Operations
4871 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4872 RegisterClass RC, X86MemOperand memop> {
4874 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4875 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4876 (ins RC:$src1, KRC:$mask, memop:$src2),
4877 !strconcat(OpcodeStr,
4878 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4882 let ExeDomain = SSEPackedDouble in {
4883 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4884 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4885 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4886 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4889 let ExeDomain = SSEPackedSingle in {
4890 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4891 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4892 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4893 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4896 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4897 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4898 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4899 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4901 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4902 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4903 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4904 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4906 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4907 RegisterClass RC, X86MemOperand memop> {
4908 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4909 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4910 (ins memop:$dst, KRC:$mask, RC:$src2),
4911 !strconcat(OpcodeStr,
4912 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4916 let ExeDomain = SSEPackedDouble in {
4917 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4918 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4919 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4920 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4923 let ExeDomain = SSEPackedSingle in {
4924 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4925 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4926 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4927 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4930 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4931 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4932 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4933 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4935 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4936 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4937 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4938 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4941 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4942 RegisterClass KRC, X86MemOperand memop> {
4943 let Predicates = [HasPFI], hasSideEffects = 1 in
4944 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4945 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4949 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4950 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4952 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4953 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4955 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4956 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4958 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4959 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4961 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4962 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4964 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4965 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4967 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4968 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4970 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4971 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4973 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4974 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4976 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4977 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4979 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4980 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4982 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4983 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4985 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4986 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4988 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4989 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4991 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4992 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4994 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4995 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4996 //===----------------------------------------------------------------------===//
4997 // VSHUFPS - VSHUFPD Operations
4999 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5000 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5002 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5003 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
5004 !strconcat(OpcodeStr,
5005 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5006 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5007 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5008 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5009 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5010 (ins RC:$src1, RC:$src2, i8imm:$src3),
5011 !strconcat(OpcodeStr,
5012 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5013 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5014 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5015 EVEX_4V, Sched<[WriteShuffle]>;
5018 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
5019 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5020 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
5021 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5023 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5024 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5025 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5026 (memopv16i32 addr:$src2), (i8 imm:$imm))),
5027 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5029 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5030 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5031 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5032 (memopv8i64 addr:$src2), (i8 imm:$imm))),
5033 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5035 multiclass avx512_valign<X86VectorVTInfo _> {
5036 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5037 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
5039 "$src3, $src2, $src1", "$src1, $src2, $src3",
5040 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5042 AVX512AIi8Base, EVEX_4V;
5044 // Also match valign of packed floats.
5045 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5046 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5049 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5050 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5051 !strconcat("valign"##_.Suffix,
5052 "\t{$src3, $src2, $src1, $dst|"
5053 "$dst, $src1, $src2, $src3}"),
5056 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5057 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5059 // Helper fragments to match sext vXi1 to vXiY.
5060 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5061 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5063 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5064 RegisterClass KRC, RegisterClass RC,
5065 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5067 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5068 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5070 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5071 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5073 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5074 !strconcat(OpcodeStr,
5075 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5077 let mayLoad = 1 in {
5078 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5079 (ins x86memop:$src),
5080 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5082 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5083 (ins KRC:$mask, x86memop:$src),
5084 !strconcat(OpcodeStr,
5085 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5087 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5088 (ins KRC:$mask, x86memop:$src),
5089 !strconcat(OpcodeStr,
5090 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5092 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5093 (ins x86scalar_mop:$src),
5094 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5095 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5097 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5098 (ins KRC:$mask, x86scalar_mop:$src),
5099 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5100 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5101 []>, EVEX, EVEX_B, EVEX_K;
5102 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5103 (ins KRC:$mask, x86scalar_mop:$src),
5104 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5105 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5107 []>, EVEX, EVEX_B, EVEX_KZ;
5111 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5112 i512mem, i32mem, "{1to16}">, EVEX_V512,
5113 EVEX_CD8<32, CD8VF>;
5114 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5115 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5116 EVEX_CD8<64, CD8VF>;
5119 (bc_v16i32 (v16i1sextv16i32)),
5120 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5121 (VPABSDZrr VR512:$src)>;
5123 (bc_v8i64 (v8i1sextv8i64)),
5124 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5125 (VPABSQZrr VR512:$src)>;
5127 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5128 (v16i32 immAllZerosV), (i16 -1))),
5129 (VPABSDZrr VR512:$src)>;
5130 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5131 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5132 (VPABSQZrr VR512:$src)>;
5134 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5135 RegisterClass RC, RegisterClass KRC,
5136 X86MemOperand x86memop,
5137 X86MemOperand x86scalar_mop, string BrdcstStr> {
5138 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5140 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5142 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5143 (ins x86memop:$src),
5144 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5146 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5147 (ins x86scalar_mop:$src),
5148 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5149 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5151 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5152 (ins KRC:$mask, RC:$src),
5153 !strconcat(OpcodeStr,
5154 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5156 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5157 (ins KRC:$mask, x86memop:$src),
5158 !strconcat(OpcodeStr,
5159 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5161 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5162 (ins KRC:$mask, x86scalar_mop:$src),
5163 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5164 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5166 []>, EVEX, EVEX_KZ, EVEX_B;
5168 let Constraints = "$src1 = $dst" in {
5169 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5170 (ins RC:$src1, KRC:$mask, RC:$src2),
5171 !strconcat(OpcodeStr,
5172 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5174 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5175 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5176 !strconcat(OpcodeStr,
5177 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5179 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5180 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5181 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5182 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5183 []>, EVEX, EVEX_K, EVEX_B;
5187 let Predicates = [HasCDI] in {
5188 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5189 i512mem, i32mem, "{1to16}">,
5190 EVEX_V512, EVEX_CD8<32, CD8VF>;
5193 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5194 i512mem, i64mem, "{1to8}">,
5195 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5199 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5201 (VPCONFLICTDrrk VR512:$src1,
5202 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5204 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5206 (VPCONFLICTQrrk VR512:$src1,
5207 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5209 let Predicates = [HasCDI] in {
5210 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5211 i512mem, i32mem, "{1to16}">,
5212 EVEX_V512, EVEX_CD8<32, CD8VF>;
5215 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5216 i512mem, i64mem, "{1to8}">,
5217 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5221 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5223 (VPLZCNTDrrk VR512:$src1,
5224 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5226 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5228 (VPLZCNTQrrk VR512:$src1,
5229 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5231 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5232 (VPLZCNTDrm addr:$src)>;
5233 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5234 (VPLZCNTDrr VR512:$src)>;
5235 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5236 (VPLZCNTQrm addr:$src)>;
5237 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5238 (VPLZCNTQrr VR512:$src)>;
5240 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5241 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5242 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5244 def : Pat<(store VK1:$src, addr:$dst),
5245 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5247 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5248 (truncstore node:$val, node:$ptr), [{
5249 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5252 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5253 (MOV8mr addr:$dst, GR8:$src)>;
5255 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5256 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5257 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5258 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5261 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5262 string OpcodeStr, Predicate prd> {
5263 let Predicates = [prd] in
5264 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5266 let Predicates = [prd, HasVLX] in {
5267 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5268 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5272 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5273 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5275 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5277 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5279 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5283 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5285 //===----------------------------------------------------------------------===//
5286 // AVX-512 - COMPRESS and EXPAND
5288 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5290 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5291 (ins _.KRCWM:$mask, _.RC:$src),
5292 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5293 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5294 _.ImmAllZerosV)))]>, EVEX_KZ;
5296 let Constraints = "$src0 = $dst" in
5297 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5298 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5299 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5300 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5301 _.RC:$src0)))]>, EVEX_K;
5303 let mayStore = 1 in {
5304 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5305 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5306 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5307 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5309 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5313 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5314 AVX512VLVectorVTInfo VTInfo> {
5315 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5317 let Predicates = [HasVLX] in {
5318 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5319 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5323 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5325 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5327 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5329 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,