1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
406 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
410 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
413 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
416 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
421 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
422 X86MemOperand x86memop, PatFrag ld_frag,
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
431 !strconcat(OpcodeStr,
432 "\t{$src, ${dst}{${mask}}{z}|${dst}{${mask}}{z}, $src}"),
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
442 !strconcat(OpcodeStr,
443 "\t{$src, ${dst}{${mask}}{z}|${dst}{${mask}}{z}, $src}"),
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
448 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
451 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
453 EVEX_CD8<64, CD8VT1>;
455 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
456 (VBROADCASTSSZrr VR128X:$src)>;
457 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
458 (VBROADCASTSDZrr VR128X:$src)>;
460 // Provide fallback in case the load node that is used in the patterns above
461 // is used by additional users, which prevents the pattern selection.
462 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
464 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
468 let Predicates = [HasAVX512] in {
469 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
472 addr:$src)), sub_ymm)>;
474 //===----------------------------------------------------------------------===//
475 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
478 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
479 RegisterClass DstRC, RegisterClass KRC,
480 ValueType OpVT, ValueType SrcVT> {
481 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
486 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
487 VK16, v16i32, v16i1>, EVEX_V512;
488 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
491 //===----------------------------------------------------------------------===//
494 // -- immediate form --
495 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
496 SDNode OpNode, PatFrag mem_frag,
497 X86MemOperand x86memop, ValueType OpVT> {
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
499 (ins RC:$src1, i8imm:$src2),
500 !strconcat(OpcodeStr,
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
506 (ins x86memop:$src1, i8imm:$src2),
507 !strconcat(OpcodeStr,
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
510 (OpVT (OpNode (mem_frag addr:$src1),
511 (i8 imm:$src2))))]>, EVEX;
514 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
516 let ExeDomain = SSEPackedDouble in
517 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
520 // -- VPERM - register form --
521 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, RC:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
532 (ins RC:$src1, x86memop:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
540 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
542 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
544 let ExeDomain = SSEPackedSingle in
545 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
547 let ExeDomain = SSEPackedDouble in
548 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
551 // -- VPERM2I - 3 source operands form --
552 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
553 PatFrag mem_frag, X86MemOperand x86memop,
555 let Constraints = "$src1 = $dst" in {
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, RC:$src2, RC:$src3),
558 !strconcat(OpcodeStr,
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
566 !strconcat(OpcodeStr,
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
570 (mem_frag addr:$src3))))]>, EVEX_4V;
573 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
582 //===----------------------------------------------------------------------===//
583 // AVX-512 - BLEND using mask
585 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
586 RegisterClass KRC, RegisterClass RC,
587 X86MemOperand x86memop, PatFrag mem_frag,
588 SDNode OpNode, ValueType vt> {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins KRC:$mask, RC:$src1, RC:$src2),
591 !strconcat(OpcodeStr,
592 "\t{$src2, $src1, ${dst}{${mask}}|${dst}{${mask}}, $src1, $src2}"),
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
598 !strconcat(OpcodeStr,
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
604 let ExeDomain = SSEPackedSingle in
605 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
606 memopv16f32, vselect, v16f32>,
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
608 let ExeDomain = SSEPackedDouble in
609 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
610 memopv8f64, vselect, v8f64>,
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
613 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
614 memopv8i64, vselect, v16i32>,
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
617 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
618 memopv8i64, vselect, v8i64>, VEX_W,
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
622 let Predicates = [HasAVX512] in {
623 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
624 (v8f32 VR256X:$src2))),
626 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
628 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
630 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
631 (v8i32 VR256X:$src2))),
633 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
635 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
638 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
639 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
640 SDNode OpNode, ValueType vt> {
641 def rr : AVX512BI<opc, MRMSrcReg,
642 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
644 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
645 IIC_SSE_CMPP_RR>, EVEX_4V;
646 def rm : AVX512BI<opc, MRMSrcMem,
647 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
649 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
650 IIC_SSE_CMPP_RM>, EVEX_4V;
653 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
654 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
655 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
656 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
658 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
659 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
660 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
661 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
663 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
664 (COPY_TO_REGCLASS (VPCMPGTDZrr
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
666 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
668 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
669 (COPY_TO_REGCLASS (VPCMPEQDZrr
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
671 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
673 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
674 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
675 SDNode OpNode, ValueType vt, Operand CC, string asm,
677 def rri : AVX512AIi8<opc, MRMSrcReg,
678 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
679 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
680 IIC_SSE_CMPP_RR>, EVEX_4V;
681 def rmi : AVX512AIi8<opc, MRMSrcMem,
682 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
683 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
684 imm:$cc))], IIC_SSE_CMPP_RM>, EVEX_4V;
685 // Accept explicit immediate argument form instead of comparison code.
686 let neverHasSideEffects = 1 in {
687 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
688 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
689 asm_alt, [], IIC_SSE_CMPP_RR>, EVEX_4V;
690 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
691 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
692 asm_alt, [], IIC_SSE_CMPP_RM>, EVEX_4V;
696 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
697 X86cmpm, v16i32, AVXCC,
698 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
699 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
700 EVEX_V512, EVEX_CD8<32, CD8VF>;
701 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
702 X86cmpmu, v16i32, AVXCC,
703 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
704 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
707 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
708 X86cmpm, v8i64, AVXCC,
709 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
710 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
711 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
712 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
713 X86cmpmu, v8i64, AVXCC,
714 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
716 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
718 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
719 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
720 X86MemOperand x86memop, Operand CC,
721 SDNode OpNode, ValueType vt, string asm,
722 string asm_alt, Domain d> {
723 def rri : AVX512PIi8<0xC2, MRMSrcReg,
724 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
725 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
726 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
727 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
729 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
731 // Accept explicit immediate argument form instead of comparison code.
732 let neverHasSideEffects = 1 in {
733 def rri_alt : PIi8<0xC2, MRMSrcReg,
734 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
735 asm_alt, [], IIC_SSE_CMPP_RR, d>;
736 def rmi_alt : PIi8<0xC2, MRMSrcMem,
737 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_CMPP_RM, d>;
742 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
743 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
744 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
745 SSEPackedSingle>, TB, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
746 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
747 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
749 SSEPackedDouble>, TB, OpSize, EVEX_4V, VEX_W, EVEX_V512,
752 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
753 (COPY_TO_REGCLASS (VCMPPSZrri
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
755 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
757 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
758 (COPY_TO_REGCLASS (VPCMPDZrri
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
760 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
762 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
763 (COPY_TO_REGCLASS (VPCMPUDZrri
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
768 // Mask register copy, including
769 // - copy between mask registers
770 // - load/store mask registers
771 // - copy from GPR to mask register and vice versa
773 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
774 string OpcodeStr, RegisterClass KRC,
775 ValueType vt, X86MemOperand x86memop> {
776 let neverHasSideEffects = 1 in {
777 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
780 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
782 [(set KRC:$dst, (vt (load addr:$src)))]>;
784 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
789 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
791 RegisterClass KRC, RegisterClass GRC> {
792 let neverHasSideEffects = 1 in {
793 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
795 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
800 let Predicates = [HasAVX512] in {
801 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
803 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
807 let Predicates = [HasAVX512] in {
808 // GR16 from/to 16-bit mask
809 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
810 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
811 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
812 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
814 // Store kreg in memory
815 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
816 (KMOVWmk addr:$dst, VK16:$src)>;
818 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
819 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
821 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
822 let Predicates = [HasAVX512] in {
823 // GR from/to 8-bit mask without native support
824 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
826 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
828 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
830 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
834 // Mask unary operation
836 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
837 RegisterClass KRC, SDPatternOperator OpNode> {
838 let Predicates = [HasAVX512] in
839 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
840 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
841 [(set KRC:$dst, (OpNode KRC:$src))]>;
844 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
845 SDPatternOperator OpNode> {
846 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
850 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
852 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
853 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
854 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
856 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
857 def : Pat<(not VK8:$src),
859 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
861 // Mask binary operation
862 // - KADD, KAND, KANDN, KOR, KXNOR, KXOR
863 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
864 RegisterClass KRC, SDPatternOperator OpNode> {
865 let Predicates = [HasAVX512] in
866 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
867 !strconcat(OpcodeStr,
868 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
869 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
872 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
873 SDPatternOperator OpNode> {
874 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
878 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
879 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
881 let isCommutable = 1 in {
882 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
883 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
884 let isCommutable = 0 in
885 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
886 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
887 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
888 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
891 multiclass avx512_mask_binop_int<string IntName, string InstName> {
892 let Predicates = [HasAVX512] in
893 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
894 VK16:$src1, VK16:$src2),
895 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
898 defm : avx512_mask_binop_int<"kadd", "KADD">;
899 defm : avx512_mask_binop_int<"kand", "KAND">;
900 defm : avx512_mask_binop_int<"kandn", "KANDN">;
901 defm : avx512_mask_binop_int<"kor", "KOR">;
902 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
903 defm : avx512_mask_binop_int<"kxor", "KXOR">;
904 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
905 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
906 let Predicates = [HasAVX512] in
907 def : Pat<(OpNode VK8:$src1, VK8:$src2),
909 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
910 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
913 defm : avx512_binop_pat<and, KANDWrr>;
914 defm : avx512_binop_pat<andn, KANDNWrr>;
915 defm : avx512_binop_pat<or, KORWrr>;
916 defm : avx512_binop_pat<xnor, KXNORWrr>;
917 defm : avx512_binop_pat<xor, KXORWrr>;
920 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
921 RegisterClass KRC1, RegisterClass KRC2> {
922 let Predicates = [HasAVX512] in
923 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
924 !strconcat(OpcodeStr,
925 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
928 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
929 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
930 VEX_4V, VEX_L, OpSize, TB;
933 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
935 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
936 let Predicates = [HasAVX512] in
937 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
938 VK8:$src1, VK8:$src2),
939 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
942 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
944 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
946 let Predicates = [HasAVX512], Defs = [EFLAGS] in
947 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
949 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
952 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
953 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
957 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
958 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
961 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
963 let Predicates = [HasAVX512] in
964 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
965 !strconcat(OpcodeStr,
966 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
967 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
970 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
972 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
973 VEX, OpSize, TA, VEX_W;
976 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
977 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
979 // Mask setting all 0s or 1s
980 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
981 let Predicates = [HasAVX512] in
982 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
983 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
984 [(set KRC:$dst, (VT Val))]>;
987 multiclass avx512_mask_setop_w<PatFrag Val> {
988 defm B : avx512_mask_setop<VK8, v8i1, Val>;
989 defm W : avx512_mask_setop<VK16, v16i1, Val>;
992 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
993 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
995 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
996 let Predicates = [HasAVX512] in {
997 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
998 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1000 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1001 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1003 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1004 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1006 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1007 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1009 //===----------------------------------------------------------------------===//
1010 // AVX-512 - Aligned and unaligned load and store
1013 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1014 X86MemOperand x86memop, PatFrag ld_frag,
1015 string asm, Domain d> {
1016 let neverHasSideEffects = 1 in
1017 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1018 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1020 let canFoldAsLoad = 1 in
1021 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1022 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1023 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1024 let Constraints = "$src1 = $dst" in {
1025 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1026 (ins RC:$src1, KRC:$mask, RC:$src2),
1028 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"), [], d>,
1030 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1031 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1033 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"),
1034 [], d>, EVEX, EVEX_K;
1038 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1039 "vmovaps", SSEPackedSingle>,
1040 EVEX_V512, EVEX_CD8<32, CD8VF>;
1041 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1042 "vmovapd", SSEPackedDouble>,
1043 OpSize, EVEX_V512, VEX_W,
1044 EVEX_CD8<64, CD8VF>;
1045 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1046 "vmovups", SSEPackedSingle>,
1047 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1048 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1049 "vmovupd", SSEPackedDouble>,
1050 OpSize, EVEX_V512, VEX_W,
1051 EVEX_CD8<64, CD8VF>;
1052 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1053 "vmovaps\t{$src, $dst|$dst, $src}",
1054 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1055 SSEPackedSingle>, EVEX, EVEX_V512, TB,
1056 EVEX_CD8<32, CD8VF>;
1057 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1058 "vmovapd\t{$src, $dst|$dst, $src}",
1059 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1060 SSEPackedDouble>, EVEX, EVEX_V512,
1061 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
1062 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1063 "vmovups\t{$src, $dst|$dst, $src}",
1064 [(store (v16f32 VR512:$src), addr:$dst)],
1065 SSEPackedSingle>, EVEX, EVEX_V512, TB,
1066 EVEX_CD8<32, CD8VF>;
1067 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1068 "vmovupd\t{$src, $dst|$dst, $src}",
1069 [(store (v8f64 VR512:$src), addr:$dst)],
1070 SSEPackedDouble>, EVEX, EVEX_V512,
1071 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
1073 // Use vmovaps/vmovups for AVX-512 integer load/store.
1074 // 512-bit load/store
1075 def : Pat<(alignedloadv8i64 addr:$src),
1076 (VMOVAPSZrm addr:$src)>;
1077 def : Pat<(loadv8i64 addr:$src),
1078 (VMOVUPSZrm addr:$src)>;
1080 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1081 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1082 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1083 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1085 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1086 (VMOVUPDZmr addr:$dst, VR512:$src)>;
1087 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1088 (VMOVUPSZmr addr:$dst, VR512:$src)>;
1090 let neverHasSideEffects = 1 in {
1091 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1093 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1095 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1097 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1098 EVEX, EVEX_V512, VEX_W;
1099 let mayStore = 1 in {
1100 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1101 (ins i512mem:$dst, VR512:$src),
1102 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1103 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1104 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1105 (ins i512mem:$dst, VR512:$src),
1106 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1107 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1109 let mayLoad = 1 in {
1110 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1112 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1113 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1114 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1116 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1117 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1121 multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
1123 PatFrag ld_frag, X86MemOperand x86memop> {
1124 let neverHasSideEffects = 1 in
1125 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1126 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
1128 let canFoldAsLoad = 1 in
1129 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1130 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1131 [(set RC:$dst, (ld_frag addr:$src))]>,
1133 let Constraints = "$src1 = $dst" in {
1134 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
1135 (ins RC:$src1, KRC:$mask, RC:$src2),
1137 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"), []>,
1139 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
1140 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1142 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"),
1147 defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
1148 EVEX_V512, EVEX_CD8<32, CD8VF>;
1149 defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
1150 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1152 let AddedComplexity = 20 in {
1153 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1154 (v16f32 VR512:$src2))),
1155 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1156 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1157 (v8f64 VR512:$src2))),
1158 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1159 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1160 (v16i32 VR512:$src2))),
1161 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1162 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1163 (v8i64 VR512:$src2))),
1164 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1166 // Move Int Doubleword to Packed Double Int
1168 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1169 "vmovd{z}\t{$src, $dst|$dst, $src}",
1171 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1173 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1174 "vmovd{z}\t{$src, $dst|$dst, $src}",
1176 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1177 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1178 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1179 "vmovq{z}\t{$src, $dst|$dst, $src}",
1181 (v2i64 (scalar_to_vector GR64:$src)))],
1182 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1183 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1184 "vmovq{z}\t{$src, $dst|$dst, $src}",
1185 [(set FR64:$dst, (bitconvert GR64:$src))],
1186 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1187 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1188 "vmovq{z}\t{$src, $dst|$dst, $src}",
1189 [(set GR64:$dst, (bitconvert FR64:$src))],
1190 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1191 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1192 "vmovq{z}\t{$src, $dst|$dst, $src}",
1193 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1194 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1195 EVEX_CD8<64, CD8VT1>;
1197 // Move Int Doubleword to Single Scalar
1199 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1200 "vmovd{z}\t{$src, $dst|$dst, $src}",
1201 [(set FR32X:$dst, (bitconvert GR32:$src))],
1202 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1204 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1205 "vmovd{z}\t{$src, $dst|$dst, $src}",
1206 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1209 // Move Packed Doubleword Int to Packed Double Int
1211 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1212 "vmovd{z}\t{$src, $dst|$dst, $src}",
1213 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1214 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1216 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1217 (ins i32mem:$dst, VR128X:$src),
1218 "vmovd{z}\t{$src, $dst|$dst, $src}",
1219 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1220 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1221 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1223 // Move Packed Doubleword Int first element to Doubleword Int
1225 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1226 "vmovq{z}\t{$src, $dst|$dst, $src}",
1227 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1229 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1230 Requires<[HasAVX512, In64BitMode]>;
1232 def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs),
1233 (ins i64mem:$dst, VR128X:$src),
1234 "vmovq{z}\t{$src, $dst|$dst, $src}",
1235 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1236 addr:$dst)], IIC_SSE_MOVDQ>,
1237 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1238 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1240 // Move Scalar Single to Double Int
1242 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1244 "vmovd{z}\t{$src, $dst|$dst, $src}",
1245 [(set GR32:$dst, (bitconvert FR32X:$src))],
1246 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1247 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1248 (ins i32mem:$dst, FR32X:$src),
1249 "vmovd{z}\t{$src, $dst|$dst, $src}",
1250 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1251 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1253 // Move Quadword Int to Packed Quadword Int
1255 def VMOVQI2PQIZrm : AVX512SI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1257 "vmovq{z}\t{$src, $dst|$dst, $src}",
1259 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1260 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1262 //===----------------------------------------------------------------------===//
1263 // AVX-512 MOVSS, MOVSD
1264 //===----------------------------------------------------------------------===//
1266 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1267 SDNode OpNode, ValueType vt,
1268 X86MemOperand x86memop, PatFrag mem_pat> {
1269 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1271 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1272 (scalar_to_vector RC:$src2))))],
1273 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1274 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1275 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1276 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1278 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1279 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1280 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1284 let ExeDomain = SSEPackedSingle in
1285 defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1286 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1288 let ExeDomain = SSEPackedDouble in
1289 defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1290 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1293 // For the disassembler
1294 let isCodeGenOnly = 1 in {
1295 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1296 (ins VR128X:$src1, FR32X:$src2),
1297 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1299 XS, EVEX_4V, VEX_LIG;
1300 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1301 (ins VR128X:$src1, FR64X:$src2),
1302 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1304 XD, EVEX_4V, VEX_LIG, VEX_W;
1307 let Predicates = [HasAVX512] in {
1308 let AddedComplexity = 15 in {
1309 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1310 // MOVS{S,D} to the lower bits.
1311 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1312 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1313 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1314 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1315 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1316 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1317 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1318 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1320 // Move low f32 and clear high bits.
1321 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1322 (SUBREG_TO_REG (i32 0),
1323 (VMOVSSZrr (v4f32 (V_SET0)),
1324 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1325 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1326 (SUBREG_TO_REG (i32 0),
1327 (VMOVSSZrr (v4i32 (V_SET0)),
1328 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1331 let AddedComplexity = 20 in {
1332 // MOVSSrm zeros the high parts of the register; represent this
1333 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1334 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1335 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1336 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1337 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1338 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1339 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1341 // MOVSDrm zeros the high parts of the register; represent this
1342 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1343 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1344 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1345 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1346 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1347 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1348 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1349 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1350 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1351 def : Pat<(v2f64 (X86vzload addr:$src)),
1352 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1354 // Represent the same patterns above but in the form they appear for
1356 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1357 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1358 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1359 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1360 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1361 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1362 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1363 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1364 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1366 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1367 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1368 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1369 FR32X:$src)), sub_xmm)>;
1370 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1371 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1372 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1373 FR64X:$src)), sub_xmm)>;
1374 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1375 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1376 (SUBREG_TO_REG (i64 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1378 // Move low f64 and clear high bits.
1379 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1380 (SUBREG_TO_REG (i32 0),
1381 (VMOVSDZrr (v2f64 (V_SET0)),
1382 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1384 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1385 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1386 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1388 // Extract and store.
1389 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1391 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1392 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1394 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1396 // Shuffle with VMOVSS
1397 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1398 (VMOVSSZrr (v4i32 VR128X:$src1),
1399 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1400 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1401 (VMOVSSZrr (v4f32 VR128X:$src1),
1402 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1405 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1406 (SUBREG_TO_REG (i32 0),
1407 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1408 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1410 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1411 (SUBREG_TO_REG (i32 0),
1412 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1413 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1416 // Shuffle with VMOVSD
1417 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1418 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1419 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1420 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1421 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1422 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1423 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1424 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1427 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1428 (SUBREG_TO_REG (i32 0),
1429 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1430 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1432 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1433 (SUBREG_TO_REG (i32 0),
1434 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1435 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1438 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1439 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1440 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1441 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1442 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1443 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1444 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1445 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1448 let AddedComplexity = 15 in
1449 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1451 "vmovq{z}\t{$src, $dst|$dst, $src}",
1452 [(set VR128X:$dst, (v2i64 (X86vzmovl
1453 (v2i64 VR128X:$src))))],
1454 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1456 let AddedComplexity = 20 in
1457 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1459 "vmovq{z}\t{$src, $dst|$dst, $src}",
1460 [(set VR128X:$dst, (v2i64 (X86vzmovl
1461 (loadv2i64 addr:$src))))],
1462 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1463 EVEX_CD8<8, CD8VT8>;
1465 let Predicates = [HasAVX512] in {
1466 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1467 let AddedComplexity = 20 in {
1468 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1469 (VMOVDI2PDIZrm addr:$src)>;
1471 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1472 (VMOVDI2PDIZrm addr:$src)>;
1473 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1474 (VMOVDI2PDIZrm addr:$src)>;
1475 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1476 (VMOVZPQILo2PQIZrm addr:$src)>;
1477 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1478 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1480 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1481 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1482 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1483 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1484 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1485 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1486 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1489 //===----------------------------------------------------------------------===//
1490 // AVX-512 - Integer arithmetic
1492 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1493 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1494 X86MemOperand x86memop, PatFrag scalar_mfrag,
1495 X86MemOperand x86scalar_mop, string BrdcstStr,
1496 OpndItins itins, bit IsCommutable = 0> {
1497 let isCommutable = IsCommutable in
1498 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1499 (ins RC:$src1, RC:$src2),
1500 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1501 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1503 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1504 (ins RC:$src1, x86memop:$src2),
1505 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1506 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1508 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1509 (ins RC:$src1, x86scalar_mop:$src2),
1510 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1511 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1512 [(set RC:$dst, (OpNode RC:$src1,
1513 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1514 itins.rm>, EVEX_4V, EVEX_B;
1516 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1517 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1518 PatFrag memop_frag, X86MemOperand x86memop,
1520 bit IsCommutable = 0> {
1521 let isCommutable = IsCommutable in
1522 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1523 (ins RC:$src1, RC:$src2),
1524 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1525 []>, EVEX_4V, VEX_W;
1526 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1527 (ins RC:$src1, x86memop:$src2),
1528 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1529 []>, EVEX_4V, VEX_W;
1532 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1533 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1534 EVEX_V512, EVEX_CD8<32, CD8VF>;
1536 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1537 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1538 EVEX_V512, EVEX_CD8<32, CD8VF>;
1540 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1541 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1542 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1544 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1545 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1546 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1548 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1549 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1550 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1552 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1553 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1554 EVEX_V512, EVEX_CD8<64, CD8VF>;
1556 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1557 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1558 EVEX_CD8<64, CD8VF>;
1560 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1561 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1563 //===----------------------------------------------------------------------===//
1564 // AVX-512 Logical Instructions
1565 //===----------------------------------------------------------------------===//
1567 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1568 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1569 EVEX_V512, EVEX_CD8<32, CD8VF>;
1570 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1571 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1572 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1573 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1574 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1575 EVEX_V512, EVEX_CD8<32, CD8VF>;
1576 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1577 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1578 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1579 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1580 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1581 EVEX_V512, EVEX_CD8<32, CD8VF>;
1582 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1583 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1584 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1585 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1586 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1587 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1588 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1589 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1590 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1592 //===----------------------------------------------------------------------===//
1593 // AVX-512 FP arithmetic
1594 //===----------------------------------------------------------------------===//
1596 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1598 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1599 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1600 EVEX_CD8<32, CD8VT1>;
1601 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1602 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1603 EVEX_CD8<64, CD8VT1>;
1606 let isCommutable = 1 in {
1607 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1608 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1609 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1610 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1612 let isCommutable = 0 in {
1613 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1614 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1617 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1618 RegisterClass RC, ValueType vt,
1619 X86MemOperand x86memop, PatFrag mem_frag,
1620 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1622 Domain d, OpndItins itins, bit commutable> {
1623 let isCommutable = commutable in
1624 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1626 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1628 let mayLoad = 1 in {
1629 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1630 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1631 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1632 itins.rm, d>, EVEX_4V;
1633 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1634 (ins RC:$src1, x86scalar_mop:$src2),
1635 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1636 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1637 [(set RC:$dst, (OpNode RC:$src1,
1638 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1639 itins.rm, d>, EVEX_4V, EVEX_B;
1643 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1644 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1645 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1647 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1648 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1649 SSE_ALU_ITINS_P.d, 1>,
1650 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1652 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1653 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1654 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1655 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1656 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1657 SSE_ALU_ITINS_P.d, 1>,
1658 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1660 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1661 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1662 SSE_ALU_ITINS_P.s, 1>,
1663 EVEX_V512, EVEX_CD8<32, CD8VF>;
1664 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1665 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1666 SSE_ALU_ITINS_P.s, 1>,
1667 EVEX_V512, EVEX_CD8<32, CD8VF>;
1669 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1670 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1671 SSE_ALU_ITINS_P.d, 1>,
1672 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1673 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1674 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1675 SSE_ALU_ITINS_P.d, 1>,
1676 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1678 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1679 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1680 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1681 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1682 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1683 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1685 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1686 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1687 SSE_ALU_ITINS_P.d, 0>,
1688 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1689 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1690 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1691 SSE_ALU_ITINS_P.d, 0>,
1692 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1694 //===----------------------------------------------------------------------===//
1695 // AVX-512 VPTESTM instructions
1696 //===----------------------------------------------------------------------===//
1698 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1699 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1700 SDNode OpNode, ValueType vt> {
1701 def rr : AVX5128I<opc, MRMSrcReg,
1702 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1703 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1704 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1705 def rm : AVX5128I<opc, MRMSrcMem,
1706 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1708 [(set KRC:$dst, (OpNode (vt RC:$src1),
1709 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1712 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1713 memopv16i32, X86testm, v16i32>, EVEX_V512,
1714 EVEX_CD8<32, CD8VF>;
1715 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem, memopv8i64,
1716 X86testm, v8i64>, EVEX_V512, VEX_W,
1717 EVEX_CD8<64, CD8VF>;
1719 //===----------------------------------------------------------------------===//
1720 // AVX-512 Shift instructions
1721 //===----------------------------------------------------------------------===//
1722 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1723 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1724 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1725 RegisterClass KRC> {
1726 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1727 (ins RC:$src1, i32i8imm:$src2),
1728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1729 [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
1730 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1731 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1732 (ins KRC:$mask, RC:$src1, i32i8imm:$src2),
1733 !strconcat(OpcodeStr,
1734 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1735 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1736 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1737 (ins x86memop:$src1, i32i8imm:$src2),
1738 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1739 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1740 (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1741 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1742 (ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
1743 !strconcat(OpcodeStr,
1744 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1745 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1748 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1749 RegisterClass RC, ValueType vt, ValueType SrcVT,
1750 PatFrag bc_frag, RegisterClass KRC> {
1751 // src2 is always 128-bit
1752 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1753 (ins RC:$src1, VR128X:$src2),
1754 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1755 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1756 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1757 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1758 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1759 !strconcat(OpcodeStr,
1760 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1761 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1762 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1763 (ins RC:$src1, i128mem:$src2),
1764 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1765 [(set RC:$dst, (vt (OpNode RC:$src1,
1766 (bc_frag (memopv2i64 addr:$src2)))))],
1767 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1768 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1769 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1770 !strconcat(OpcodeStr,
1771 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1772 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1775 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1776 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1777 EVEX_V512, EVEX_CD8<32, CD8VF>;
1778 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1779 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1780 EVEX_CD8<32, CD8VQ>;
1782 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1783 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1784 EVEX_CD8<64, CD8VF>, VEX_W;
1785 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1786 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1787 EVEX_CD8<64, CD8VQ>, VEX_W;
1789 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1790 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1791 EVEX_CD8<32, CD8VF>;
1792 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1793 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1794 EVEX_CD8<32, CD8VQ>;
1796 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1797 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1798 EVEX_CD8<64, CD8VF>, VEX_W;
1799 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1800 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1801 EVEX_CD8<64, CD8VQ>, VEX_W;
1803 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1804 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1805 EVEX_V512, EVEX_CD8<32, CD8VF>;
1806 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1807 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1808 EVEX_CD8<32, CD8VQ>;
1810 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1811 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1812 EVEX_CD8<64, CD8VF>, VEX_W;
1813 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1814 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1815 EVEX_CD8<64, CD8VQ>, VEX_W;
1817 //===-------------------------------------------------------------------===//
1818 // Variable Bit Shifts
1819 //===-------------------------------------------------------------------===//
1820 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1821 RegisterClass RC, ValueType vt,
1822 X86MemOperand x86memop, PatFrag mem_frag> {
1823 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1824 (ins RC:$src1, RC:$src2),
1825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1827 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1829 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1830 (ins RC:$src1, x86memop:$src2),
1831 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1833 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1837 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1838 i512mem, memopv16i32>, EVEX_V512,
1839 EVEX_CD8<32, CD8VF>;
1840 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1841 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1842 EVEX_CD8<64, CD8VF>;
1843 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1844 i512mem, memopv16i32>, EVEX_V512,
1845 EVEX_CD8<32, CD8VF>;
1846 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1847 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1848 EVEX_CD8<64, CD8VF>;
1849 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1850 i512mem, memopv16i32>, EVEX_V512,
1851 EVEX_CD8<32, CD8VF>;
1852 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1853 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1854 EVEX_CD8<64, CD8VF>;