1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
95 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
97 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
99 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
102 // "x" in v32i8x_info means RC = VR256X
103 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
107 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
108 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
110 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
111 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
112 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
113 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
114 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
115 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
117 // We map scalar types to the smallest (128-bit) vector type
118 // with the appropriate element type. This allows to use the same masking logic.
119 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
120 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
122 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
123 X86VectorVTInfo i128> {
124 X86VectorVTInfo info512 = i512;
125 X86VectorVTInfo info256 = i256;
126 X86VectorVTInfo info128 = i128;
129 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
131 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
133 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
135 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
137 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
139 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
142 // This multiclass generates the masking variants from the non-masking
143 // variant. It only provides the assembly pieces for the masking variants.
144 // It assumes custom ISel patterns for masking which can be provided as
145 // template arguments.
146 multiclass AVX512_maskable_custom<bits<8> O, Format F,
148 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
150 string AttSrcAsm, string IntelSrcAsm,
152 list<dag> MaskingPattern,
153 list<dag> ZeroMaskingPattern,
155 string MaskingConstraint = "",
156 InstrItinClass itin = NoItinerary,
157 bit IsCommutable = 0> {
158 let isCommutable = IsCommutable in
159 def NAME: AVX512<O, F, Outs, Ins,
160 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
161 "$dst "#Round#", "#IntelSrcAsm#"}",
164 // Prefer over VMOV*rrk Pat<>
165 let AddedComplexity = 20 in
166 def NAME#k: AVX512<O, F, Outs, MaskingIns,
167 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
168 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
169 MaskingPattern, itin>,
171 // In case of the 3src subclass this is overridden with a let.
172 string Constraints = MaskingConstraint;
174 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
175 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
176 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
177 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
184 // Common base class of AVX512_maskable and AVX512_maskable_3src.
185 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
187 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
189 string AttSrcAsm, string IntelSrcAsm,
190 dag RHS, dag MaskingRHS,
191 SDNode Select = vselect, string Round = "",
192 string MaskingConstraint = "",
193 InstrItinClass itin = NoItinerary,
194 bit IsCommutable = 0> :
195 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
196 AttSrcAsm, IntelSrcAsm,
197 [(set _.RC:$dst, RHS)],
198 [(set _.RC:$dst, MaskingRHS)],
200 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
201 Round, MaskingConstraint, NoItinerary, IsCommutable>;
203 // This multiclass generates the unconditional/non-masking, the masking and
204 // the zero-masking variant of the vector instruction. In the masking case, the
205 // perserved vector elements come from a new dummy input operand tied to $dst.
206 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
207 dag Outs, dag Ins, string OpcodeStr,
208 string AttSrcAsm, string IntelSrcAsm,
209 dag RHS, string Round = "",
210 InstrItinClass itin = NoItinerary,
211 bit IsCommutable = 0> :
212 AVX512_maskable_common<O, F, _, Outs, Ins,
213 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
214 !con((ins _.KRCWM:$mask), Ins),
215 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
216 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
217 Round, "$src0 = $dst", itin, IsCommutable>;
219 // This multiclass generates the unconditional/non-masking, the masking and
220 // the zero-masking variant of the scalar instruction.
221 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
222 dag Outs, dag Ins, string OpcodeStr,
223 string AttSrcAsm, string IntelSrcAsm,
224 dag RHS, string Round = "",
225 InstrItinClass itin = NoItinerary,
226 bit IsCommutable = 0> :
227 AVX512_maskable_common<O, F, _, Outs, Ins,
228 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
229 !con((ins _.KRCWM:$mask), Ins),
230 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
231 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
232 Round, "$src0 = $dst", itin, IsCommutable>;
234 // Similar to AVX512_maskable but in this case one of the source operands
235 // ($src1) is already tied to $dst so we just use that for the preserved
236 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
238 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
239 dag Outs, dag NonTiedIns, string OpcodeStr,
240 string AttSrcAsm, string IntelSrcAsm,
242 AVX512_maskable_common<O, F, _, Outs,
243 !con((ins _.RC:$src1), NonTiedIns),
244 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
245 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
246 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
247 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
250 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
253 string AttSrcAsm, string IntelSrcAsm,
255 AVX512_maskable_custom<O, F, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
261 // Bitcasts between 512-bit vector types. Return the original type since
262 // no instruction is needed for the conversion
263 let Predicates = [HasAVX512] in {
264 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
265 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
266 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
267 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
268 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
269 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
270 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
271 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
272 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
273 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
274 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
275 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
276 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
277 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
278 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
279 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
280 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
281 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
282 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
283 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
284 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
285 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
286 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
287 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
288 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
289 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
290 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
291 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
292 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
293 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
294 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
296 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
297 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
298 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
299 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
300 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
301 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
302 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
303 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
304 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
305 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
306 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
307 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
308 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
309 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
310 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
311 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
312 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
313 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
314 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
315 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
316 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
317 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
318 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
319 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
320 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
321 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
322 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
323 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
324 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
325 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
327 // Bitcasts between 256-bit vector types. Return the original type since
328 // no instruction is needed for the conversion
329 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
330 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
331 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
332 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
333 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
334 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
335 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
336 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
337 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
338 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
339 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
340 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
341 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
342 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
343 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
344 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
345 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
346 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
347 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
348 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
349 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
350 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
351 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
352 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
353 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
354 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
355 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
356 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
357 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
358 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
362 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
365 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
366 isPseudo = 1, Predicates = [HasAVX512] in {
367 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
368 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
371 let Predicates = [HasAVX512] in {
372 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
373 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
374 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
377 //===----------------------------------------------------------------------===//
378 // AVX-512 - VECTOR INSERT
381 multiclass vinsert_for_size_no_alt<int Opcode,
382 X86VectorVTInfo From, X86VectorVTInfo To,
383 PatFrag vinsert_insert,
384 SDNodeXForm INSERT_get_vinsert_imm> {
385 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
386 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
387 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
388 "vinsert" # From.EltTypeName # "x" # From.NumElts #
389 "\t{$src3, $src2, $src1, $dst|"
390 "$dst, $src1, $src2, $src3}",
391 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
392 (From.VT From.RC:$src2),
397 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
398 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
399 "vinsert" # From.EltTypeName # "x" # From.NumElts #
400 "\t{$src3, $src2, $src1, $dst|"
401 "$dst, $src1, $src2, $src3}",
403 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
407 multiclass vinsert_for_size<int Opcode,
408 X86VectorVTInfo From, X86VectorVTInfo To,
409 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
410 PatFrag vinsert_insert,
411 SDNodeXForm INSERT_get_vinsert_imm> :
412 vinsert_for_size_no_alt<Opcode, From, To,
413 vinsert_insert, INSERT_get_vinsert_imm> {
414 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
415 // vinserti32x4. Only add this if 64x2 and friends are not supported
416 // natively via AVX512DQ.
417 let Predicates = [NoDQI] in
418 def : Pat<(vinsert_insert:$ins
419 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
420 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
421 VR512:$src1, From.RC:$src2,
422 (INSERT_get_vinsert_imm VR512:$ins)))>;
425 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
426 ValueType EltVT64, int Opcode256> {
427 defm NAME # "32x4" : vinsert_for_size<Opcode128,
428 X86VectorVTInfo< 4, EltVT32, VR128X>,
429 X86VectorVTInfo<16, EltVT32, VR512>,
430 X86VectorVTInfo< 2, EltVT64, VR128X>,
431 X86VectorVTInfo< 8, EltVT64, VR512>,
433 INSERT_get_vinsert128_imm>;
434 let Predicates = [HasDQI] in
435 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
436 X86VectorVTInfo< 2, EltVT64, VR128X>,
437 X86VectorVTInfo< 8, EltVT64, VR512>,
439 INSERT_get_vinsert128_imm>, VEX_W;
440 defm NAME # "64x4" : vinsert_for_size<Opcode256,
441 X86VectorVTInfo< 4, EltVT64, VR256X>,
442 X86VectorVTInfo< 8, EltVT64, VR512>,
443 X86VectorVTInfo< 8, EltVT32, VR256>,
444 X86VectorVTInfo<16, EltVT32, VR512>,
446 INSERT_get_vinsert256_imm>, VEX_W;
447 let Predicates = [HasDQI] in
448 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
449 X86VectorVTInfo< 8, EltVT32, VR256X>,
450 X86VectorVTInfo<16, EltVT32, VR512>,
452 INSERT_get_vinsert256_imm>;
455 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
456 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
458 // vinsertps - insert f32 to XMM
459 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
460 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
461 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
462 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
464 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
465 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
466 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
467 [(set VR128X:$dst, (X86insertps VR128X:$src1,
468 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
469 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
471 //===----------------------------------------------------------------------===//
472 // AVX-512 VECTOR EXTRACT
475 multiclass vextract_for_size<int Opcode,
476 X86VectorVTInfo From, X86VectorVTInfo To,
477 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
478 PatFrag vextract_extract,
479 SDNodeXForm EXTRACT_get_vextract_imm> {
480 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
481 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
482 (ins VR512:$src1, u8imm:$idx),
483 "vextract" # To.EltTypeName # "x4",
484 "$idx, $src1", "$src1, $idx",
485 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
487 AVX512AIi8Base, EVEX, EVEX_V512;
489 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
490 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
491 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
492 "$dst, $src1, $src2}",
493 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
496 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
498 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
499 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
501 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
503 // A 128/256-bit subvector extract from the first 512-bit vector position is
504 // a subregister copy that needs no instruction.
505 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
507 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
509 // And for the alternative types.
510 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
512 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
514 // Intrinsic call with masking.
515 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
517 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
518 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
519 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
520 VR512:$src1, imm:$idx)>;
522 // Intrinsic call with zero-masking.
523 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
525 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
526 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
527 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
528 VR512:$src1, imm:$idx)>;
530 // Intrinsic call without masking.
531 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
533 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
534 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
535 VR512:$src1, imm:$idx)>;
538 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
539 ValueType EltVT64, int Opcode64> {
540 defm NAME # "32x4" : vextract_for_size<Opcode32,
541 X86VectorVTInfo<16, EltVT32, VR512>,
542 X86VectorVTInfo< 4, EltVT32, VR128X>,
543 X86VectorVTInfo< 8, EltVT64, VR512>,
544 X86VectorVTInfo< 2, EltVT64, VR128X>,
546 EXTRACT_get_vextract128_imm>;
547 defm NAME # "64x4" : vextract_for_size<Opcode64,
548 X86VectorVTInfo< 8, EltVT64, VR512>,
549 X86VectorVTInfo< 4, EltVT64, VR256X>,
550 X86VectorVTInfo<16, EltVT32, VR512>,
551 X86VectorVTInfo< 8, EltVT32, VR256>,
553 EXTRACT_get_vextract256_imm>, VEX_W;
556 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
557 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
559 // A 128-bit subvector insert to the first 512-bit vector position
560 // is a subregister copy that needs no instruction.
561 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
562 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
563 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
565 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
566 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
567 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
569 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
570 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
571 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
573 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
574 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
575 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
578 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
580 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
581 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
582 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
583 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
584 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
585 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
587 // vextractps - extract 32 bits from XMM
588 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
589 (ins VR128X:$src1, u8imm:$src2),
590 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
591 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
594 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
595 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
596 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
597 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
598 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
600 //===---------------------------------------------------------------------===//
603 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
604 ValueType svt, X86VectorVTInfo _> {
605 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
606 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
607 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
611 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
612 (ins _.ScalarMemOp:$src),
613 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
614 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
619 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
620 AVX512VLVectorVTInfo _> {
621 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
624 let Predicates = [HasVLX] in {
625 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
630 let ExeDomain = SSEPackedSingle in {
631 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
632 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
633 let Predicates = [HasVLX] in {
634 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
635 v4f32, v4f32x_info>, EVEX_V128,
636 EVEX_CD8<32, CD8VT1>;
640 let ExeDomain = SSEPackedDouble in {
641 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
642 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
645 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
646 // Later, we can canonize broadcast instructions before ISel phase and
647 // eliminate additional patterns on ISel.
648 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
649 // representations of source
650 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
651 X86VectorVTInfo _, RegisterClass SrcRC_v,
652 RegisterClass SrcRC_s> {
653 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
654 (!cast<Instruction>(InstName##"r")
655 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
657 let AddedComplexity = 30 in {
658 def : Pat<(_.VT (vselect _.KRCWM:$mask,
659 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
660 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
661 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
663 def : Pat<(_.VT(vselect _.KRCWM:$mask,
664 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
665 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
666 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
670 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
672 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
675 let Predicates = [HasVLX] in {
676 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
677 v8f32x_info, VR128X, FR32X>;
678 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
679 v4f32x_info, VR128X, FR32X>;
680 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
681 v4f64x_info, VR128X, FR64X>;
684 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
685 (VBROADCASTSSZm addr:$src)>;
686 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
687 (VBROADCASTSDZm addr:$src)>;
689 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
690 (VBROADCASTSSZm addr:$src)>;
691 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
692 (VBROADCASTSDZm addr:$src)>;
694 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
695 RegisterClass SrcRC> {
696 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
697 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
698 "$src", "$src", []>, T8PD, EVEX;
701 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
702 RegisterClass SrcRC, Predicate prd> {
703 let Predicates = [prd] in
704 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
705 let Predicates = [prd, HasVLX] in {
706 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
707 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
711 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
713 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
715 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
717 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
720 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
721 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
723 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
724 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
726 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
727 (VPBROADCASTDrZr GR32:$src)>;
728 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
729 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
730 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
731 (VPBROADCASTQrZr GR64:$src)>;
732 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
733 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
735 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
736 (VPBROADCASTDrZr GR32:$src)>;
737 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
738 (VPBROADCASTQrZr GR64:$src)>;
740 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
741 (v16i32 immAllZerosV), (i16 GR16:$mask))),
742 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
743 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
744 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
745 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
747 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
748 X86MemOperand x86memop, PatFrag ld_frag,
749 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
751 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
752 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
754 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
755 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
757 !strconcat(OpcodeStr,
758 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
760 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
763 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
766 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
767 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
769 !strconcat(OpcodeStr,
770 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
771 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
772 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
776 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
777 loadi32, VR512, v16i32, v4i32, VK16WM>,
778 EVEX_V512, EVEX_CD8<32, CD8VT1>;
779 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
780 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
781 EVEX_CD8<64, CD8VT1>;
783 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
784 X86MemOperand x86memop, PatFrag ld_frag,
787 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
790 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
792 !strconcat(OpcodeStr,
793 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
798 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
799 i128mem, loadv2i64, VK16WM>,
800 EVEX_V512, EVEX_CD8<32, CD8VT4>;
801 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
802 i256mem, loadv4i64, VK16WM>, VEX_W,
803 EVEX_V512, EVEX_CD8<64, CD8VT4>;
805 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
806 (VPBROADCASTDZrr VR128X:$src)>;
807 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
808 (VPBROADCASTQZrr VR128X:$src)>;
810 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
811 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
812 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
813 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
815 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
816 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
817 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
818 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
820 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
821 (VBROADCASTSSZr VR128X:$src)>;
822 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
823 (VBROADCASTSDZr VR128X:$src)>;
825 // Provide fallback in case the load node that is used in the patterns above
826 // is used by additional users, which prevents the pattern selection.
827 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
828 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
829 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
830 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
833 let Predicates = [HasAVX512] in {
834 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
836 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
837 addr:$src)), sub_ymm)>;
839 //===----------------------------------------------------------------------===//
840 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
843 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
845 let Predicates = [HasCDI] in
846 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
848 []>, EVEX, EVEX_V512;
850 let Predicates = [HasCDI, HasVLX] in {
851 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
852 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
853 []>, EVEX, EVEX_V128;
854 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
855 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
856 []>, EVEX, EVEX_V256;
860 let Predicates = [HasCDI] in {
861 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
863 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
867 //===----------------------------------------------------------------------===//
870 // -- immediate form --
871 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
873 let ExeDomain = _.ExeDomain in {
874 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
875 (ins _.RC:$src1, u8imm:$src2),
876 !strconcat(OpcodeStr,
877 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
879 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
881 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
882 (ins _.MemOp:$src1, u8imm:$src2),
883 !strconcat(OpcodeStr,
884 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
886 (_.VT (OpNode (_.LdFrag addr:$src1),
888 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
892 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
893 X86VectorVTInfo Ctrl> :
894 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
895 let ExeDomain = _.ExeDomain in {
896 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
897 (ins _.RC:$src1, _.RC:$src2),
898 !strconcat("vpermil" # _.Suffix,
899 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
901 (_.VT (X86VPermilpv _.RC:$src1,
902 (Ctrl.VT Ctrl.RC:$src2))))]>,
904 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
905 (ins _.RC:$src1, Ctrl.MemOp:$src2),
906 !strconcat("vpermil" # _.Suffix,
907 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
909 (_.VT (X86VPermilpv _.RC:$src1,
910 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
915 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
917 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
920 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
922 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
925 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
926 (VPERMILPSZri VR512:$src1, imm:$imm)>;
927 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
928 (VPERMILPDZri VR512:$src1, imm:$imm)>;
930 // -- VPERM - register form --
931 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
932 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
934 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
935 (ins RC:$src1, RC:$src2),
936 !strconcat(OpcodeStr,
937 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
939 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
941 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
942 (ins RC:$src1, x86memop:$src2),
943 !strconcat(OpcodeStr,
944 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
946 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
950 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
951 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
952 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
953 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
954 let ExeDomain = SSEPackedSingle in
955 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
956 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
957 let ExeDomain = SSEPackedDouble in
958 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
959 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
961 // -- VPERM2I - 3 source operands form --
962 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
963 PatFrag mem_frag, X86MemOperand x86memop,
964 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
965 let Constraints = "$src1 = $dst" in {
966 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
967 (ins RC:$src1, RC:$src2, RC:$src3),
968 !strconcat(OpcodeStr,
969 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
971 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
974 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
975 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
976 !strconcat(OpcodeStr,
977 "\t{$src3, $src2, $dst {${mask}}|"
978 "$dst {${mask}}, $src2, $src3}"),
979 [(set RC:$dst, (OpVT (vselect KRC:$mask,
980 (OpNode RC:$src1, RC:$src2,
985 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
986 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
987 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
988 !strconcat(OpcodeStr,
989 "\t{$src3, $src2, $dst {${mask}} {z} |",
990 "$dst {${mask}} {z}, $src2, $src3}"),
991 [(set RC:$dst, (OpVT (vselect KRC:$mask,
992 (OpNode RC:$src1, RC:$src2,
995 (v16i32 immAllZerosV))))))]>,
998 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
999 (ins RC:$src1, RC:$src2, x86memop:$src3),
1000 !strconcat(OpcodeStr,
1001 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1003 (OpVT (OpNode RC:$src1, RC:$src2,
1004 (mem_frag addr:$src3))))]>, EVEX_4V;
1006 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1007 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1008 !strconcat(OpcodeStr,
1009 "\t{$src3, $src2, $dst {${mask}}|"
1010 "$dst {${mask}}, $src2, $src3}"),
1012 (OpVT (vselect KRC:$mask,
1013 (OpNode RC:$src1, RC:$src2,
1014 (mem_frag addr:$src3)),
1018 let AddedComplexity = 10 in // Prefer over the rrkz variant
1019 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1020 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1021 !strconcat(OpcodeStr,
1022 "\t{$src3, $src2, $dst {${mask}} {z}|"
1023 "$dst {${mask}} {z}, $src2, $src3}"),
1025 (OpVT (vselect KRC:$mask,
1026 (OpNode RC:$src1, RC:$src2,
1027 (mem_frag addr:$src3)),
1029 (v16i32 immAllZerosV))))))]>,
1033 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1034 i512mem, X86VPermiv3, v16i32, VK16WM>,
1035 EVEX_V512, EVEX_CD8<32, CD8VF>;
1036 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1037 i512mem, X86VPermiv3, v8i64, VK8WM>,
1038 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1039 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1040 i512mem, X86VPermiv3, v16f32, VK16WM>,
1041 EVEX_V512, EVEX_CD8<32, CD8VF>;
1042 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1043 i512mem, X86VPermiv3, v8f64, VK8WM>,
1044 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1046 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1047 PatFrag mem_frag, X86MemOperand x86memop,
1048 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1049 ValueType MaskVT, RegisterClass MRC> :
1050 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1052 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1053 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1054 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1056 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1057 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1058 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1059 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1062 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1063 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1064 EVEX_V512, EVEX_CD8<32, CD8VF>;
1065 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1066 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1067 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1068 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1069 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1070 EVEX_V512, EVEX_CD8<32, CD8VF>;
1071 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1072 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1073 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1075 //===----------------------------------------------------------------------===//
1076 // AVX-512 - BLEND using mask
1078 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1079 let ExeDomain = _.ExeDomain in {
1080 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1081 (ins _.RC:$src1, _.RC:$src2),
1082 !strconcat(OpcodeStr,
1083 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1085 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1086 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1087 !strconcat(OpcodeStr,
1088 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1089 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1090 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1091 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1092 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1093 !strconcat(OpcodeStr,
1094 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1095 []>, EVEX_4V, EVEX_KZ;
1096 let mayLoad = 1 in {
1097 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1098 (ins _.RC:$src1, _.MemOp:$src2),
1099 !strconcat(OpcodeStr,
1100 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1101 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1102 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1103 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1104 !strconcat(OpcodeStr,
1105 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1106 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1107 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1108 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1109 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1110 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1111 !strconcat(OpcodeStr,
1112 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1113 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1117 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1119 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1120 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1121 !strconcat(OpcodeStr,
1122 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1123 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1124 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1125 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1126 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1128 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1129 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1130 !strconcat(OpcodeStr,
1131 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1132 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1133 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1137 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1138 AVX512VLVectorVTInfo VTInfo> {
1139 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1140 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1142 let Predicates = [HasVLX] in {
1143 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1144 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1145 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1146 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1150 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1151 AVX512VLVectorVTInfo VTInfo> {
1152 let Predicates = [HasBWI] in
1153 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1155 let Predicates = [HasBWI, HasVLX] in {
1156 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1157 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1162 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1163 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1164 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1165 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1166 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1167 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1170 let Predicates = [HasAVX512] in {
1171 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1172 (v8f32 VR256X:$src2))),
1174 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1175 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1176 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1178 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1179 (v8i32 VR256X:$src2))),
1181 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1182 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1183 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1185 //===----------------------------------------------------------------------===//
1186 // Compare Instructions
1187 //===----------------------------------------------------------------------===//
1189 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1190 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1191 SDNode OpNode, ValueType VT,
1192 PatFrag ld_frag, string Suffix> {
1193 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1194 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1195 !strconcat("vcmp${cc}", Suffix,
1196 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1197 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1198 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1199 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1200 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1201 !strconcat("vcmp${cc}", Suffix,
1202 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1203 [(set VK1:$dst, (OpNode (VT RC:$src1),
1204 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1205 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1206 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1207 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1208 !strconcat("vcmp", Suffix,
1209 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1210 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1212 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1213 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1214 !strconcat("vcmp", Suffix,
1215 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1216 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1220 let Predicates = [HasAVX512] in {
1221 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1223 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1227 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1228 X86VectorVTInfo _> {
1229 def rr : AVX512BI<opc, MRMSrcReg,
1230 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1231 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1232 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1233 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1235 def rm : AVX512BI<opc, MRMSrcMem,
1236 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1237 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1238 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1239 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1240 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1241 def rrk : AVX512BI<opc, MRMSrcReg,
1242 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1243 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1244 "$dst {${mask}}, $src1, $src2}"),
1245 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1246 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1247 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1249 def rmk : AVX512BI<opc, MRMSrcMem,
1250 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1251 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1252 "$dst {${mask}}, $src1, $src2}"),
1253 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1254 (OpNode (_.VT _.RC:$src1),
1256 (_.LdFrag addr:$src2))))))],
1257 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1260 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1261 X86VectorVTInfo _> :
1262 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1263 let mayLoad = 1 in {
1264 def rmb : AVX512BI<opc, MRMSrcMem,
1265 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1266 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1267 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1268 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1269 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1270 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1271 def rmbk : AVX512BI<opc, MRMSrcMem,
1272 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1273 _.ScalarMemOp:$src2),
1274 !strconcat(OpcodeStr,
1275 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1276 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1277 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1278 (OpNode (_.VT _.RC:$src1),
1280 (_.ScalarLdFrag addr:$src2)))))],
1281 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1285 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1286 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1287 let Predicates = [prd] in
1288 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1291 let Predicates = [prd, HasVLX] in {
1292 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1294 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1299 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1300 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1302 let Predicates = [prd] in
1303 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1306 let Predicates = [prd, HasVLX] in {
1307 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1309 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1314 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1315 avx512vl_i8_info, HasBWI>,
1318 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1319 avx512vl_i16_info, HasBWI>,
1320 EVEX_CD8<16, CD8VF>;
1322 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1323 avx512vl_i32_info, HasAVX512>,
1324 EVEX_CD8<32, CD8VF>;
1326 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1327 avx512vl_i64_info, HasAVX512>,
1328 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1330 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1331 avx512vl_i8_info, HasBWI>,
1334 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1335 avx512vl_i16_info, HasBWI>,
1336 EVEX_CD8<16, CD8VF>;
1338 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1339 avx512vl_i32_info, HasAVX512>,
1340 EVEX_CD8<32, CD8VF>;
1342 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1343 avx512vl_i64_info, HasAVX512>,
1344 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1346 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1347 (COPY_TO_REGCLASS (VPCMPGTDZrr
1348 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1349 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1351 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1352 (COPY_TO_REGCLASS (VPCMPEQDZrr
1353 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1354 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1356 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1357 X86VectorVTInfo _> {
1358 def rri : AVX512AIi8<opc, MRMSrcReg,
1359 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1360 !strconcat("vpcmp${cc}", Suffix,
1361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1362 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1364 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1366 def rmi : AVX512AIi8<opc, MRMSrcMem,
1367 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1368 !strconcat("vpcmp${cc}", Suffix,
1369 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1370 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1371 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1373 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1374 def rrik : AVX512AIi8<opc, MRMSrcReg,
1375 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1377 !strconcat("vpcmp${cc}", Suffix,
1378 "\t{$src2, $src1, $dst {${mask}}|",
1379 "$dst {${mask}}, $src1, $src2}"),
1380 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1381 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1383 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1385 def rmik : AVX512AIi8<opc, MRMSrcMem,
1386 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1388 !strconcat("vpcmp${cc}", Suffix,
1389 "\t{$src2, $src1, $dst {${mask}}|",
1390 "$dst {${mask}}, $src1, $src2}"),
1391 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1392 (OpNode (_.VT _.RC:$src1),
1393 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1395 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1397 // Accept explicit immediate argument form instead of comparison code.
1398 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1399 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1400 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1401 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1402 "$dst, $src1, $src2, $cc}"),
1403 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1405 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1406 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1407 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1408 "$dst, $src1, $src2, $cc}"),
1409 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1410 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1411 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1413 !strconcat("vpcmp", Suffix,
1414 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1415 "$dst {${mask}}, $src1, $src2, $cc}"),
1416 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1418 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1419 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1421 !strconcat("vpcmp", Suffix,
1422 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1423 "$dst {${mask}}, $src1, $src2, $cc}"),
1424 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1428 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1429 X86VectorVTInfo _> :
1430 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1431 def rmib : AVX512AIi8<opc, MRMSrcMem,
1432 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1434 !strconcat("vpcmp${cc}", Suffix,
1435 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1436 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1437 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1438 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1440 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1441 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1442 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1443 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1444 !strconcat("vpcmp${cc}", Suffix,
1445 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1446 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1447 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1448 (OpNode (_.VT _.RC:$src1),
1449 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1451 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1453 // Accept explicit immediate argument form instead of comparison code.
1454 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1455 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1456 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1458 !strconcat("vpcmp", Suffix,
1459 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1460 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1461 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1462 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1463 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1464 _.ScalarMemOp:$src2, u8imm:$cc),
1465 !strconcat("vpcmp", Suffix,
1466 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1467 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1468 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1472 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1473 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1474 let Predicates = [prd] in
1475 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1477 let Predicates = [prd, HasVLX] in {
1478 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1479 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1483 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1484 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1485 let Predicates = [prd] in
1486 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1489 let Predicates = [prd, HasVLX] in {
1490 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1492 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1497 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1498 HasBWI>, EVEX_CD8<8, CD8VF>;
1499 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1500 HasBWI>, EVEX_CD8<8, CD8VF>;
1502 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1503 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1504 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1505 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1507 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1508 HasAVX512>, EVEX_CD8<32, CD8VF>;
1509 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1510 HasAVX512>, EVEX_CD8<32, CD8VF>;
1512 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1513 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1514 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1515 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1517 // avx512_cmp_packed - compare packed instructions
1518 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1519 X86MemOperand x86memop, ValueType vt,
1520 string suffix, Domain d> {
1521 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1522 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1523 !strconcat("vcmp${cc}", suffix,
1524 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1525 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1526 let hasSideEffects = 0 in
1527 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1528 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1529 !strconcat("vcmp${cc}", suffix,
1530 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1532 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1533 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1534 !strconcat("vcmp${cc}", suffix,
1535 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1537 (X86cmpm (vt RC:$src1), (load addr:$src2), imm:$cc))], d>;
1539 // Accept explicit immediate argument form instead of comparison code.
1540 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1541 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1542 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1543 !strconcat("vcmp", suffix,
1544 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1546 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1547 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1548 !strconcat("vcmp", suffix,
1549 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1553 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1554 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1555 EVEX_CD8<32, CD8VF>;
1556 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1557 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1558 EVEX_CD8<64, CD8VF>;
1560 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1561 (COPY_TO_REGCLASS (VCMPPSZrri
1562 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1563 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1565 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1566 (COPY_TO_REGCLASS (VPCMPDZrri
1567 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1568 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1570 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1571 (COPY_TO_REGCLASS (VPCMPUDZrri
1572 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1573 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1576 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1577 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1579 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1580 (I8Imm imm:$cc)), GR16)>;
1582 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1583 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1585 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1586 (I8Imm imm:$cc)), GR8)>;
1588 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1589 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1591 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1592 (I8Imm imm:$cc)), GR16)>;
1594 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1595 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1597 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1598 (I8Imm imm:$cc)), GR8)>;
1600 // Mask register copy, including
1601 // - copy between mask registers
1602 // - load/store mask registers
1603 // - copy from GPR to mask register and vice versa
1605 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1606 string OpcodeStr, RegisterClass KRC,
1607 ValueType vvt, X86MemOperand x86memop> {
1608 let hasSideEffects = 0 in {
1609 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1610 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1612 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1614 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1616 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1617 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1618 [(store KRC:$src, addr:$dst)]>;
1622 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1624 RegisterClass KRC, RegisterClass GRC> {
1625 let hasSideEffects = 0 in {
1626 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1628 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1633 let Predicates = [HasDQI] in
1634 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1635 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1638 let Predicates = [HasAVX512] in
1639 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1640 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1643 let Predicates = [HasBWI] in {
1644 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1646 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1650 let Predicates = [HasBWI] in {
1651 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1653 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1657 // GR from/to mask register
1658 let Predicates = [HasDQI] in {
1659 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1660 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1661 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1662 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1664 let Predicates = [HasAVX512] in {
1665 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1666 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1667 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1668 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1670 let Predicates = [HasBWI] in {
1671 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1672 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1674 let Predicates = [HasBWI] in {
1675 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1676 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1680 let Predicates = [HasDQI] in {
1681 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1682 (KMOVBmk addr:$dst, VK8:$src)>;
1683 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1684 (KMOVBkm addr:$src)>;
1686 let Predicates = [HasAVX512, NoDQI] in {
1687 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1688 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1689 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1690 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1692 let Predicates = [HasAVX512] in {
1693 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1694 (KMOVWmk addr:$dst, VK16:$src)>;
1695 def : Pat<(i1 (load addr:$src)),
1696 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1697 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1698 (KMOVWkm addr:$src)>;
1700 let Predicates = [HasBWI] in {
1701 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1702 (KMOVDmk addr:$dst, VK32:$src)>;
1703 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1704 (KMOVDkm addr:$src)>;
1706 let Predicates = [HasBWI] in {
1707 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1708 (KMOVQmk addr:$dst, VK64:$src)>;
1709 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1710 (KMOVQkm addr:$src)>;
1713 let Predicates = [HasAVX512] in {
1714 def : Pat<(i1 (trunc (i64 GR64:$src))),
1715 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1718 def : Pat<(i1 (trunc (i32 GR32:$src))),
1719 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1721 def : Pat<(i1 (trunc (i8 GR8:$src))),
1723 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1725 def : Pat<(i1 (trunc (i16 GR16:$src))),
1727 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1730 def : Pat<(i32 (zext VK1:$src)),
1731 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1732 def : Pat<(i8 (zext VK1:$src)),
1735 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1736 def : Pat<(i64 (zext VK1:$src)),
1737 (AND64ri8 (SUBREG_TO_REG (i64 0),
1738 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1739 def : Pat<(i16 (zext VK1:$src)),
1741 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1743 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1744 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1745 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1746 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1748 let Predicates = [HasBWI] in {
1749 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1750 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1751 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1752 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1756 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1757 let Predicates = [HasAVX512] in {
1758 // GR from/to 8-bit mask without native support
1759 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1761 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1763 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1765 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1768 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1769 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1770 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1771 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1773 let Predicates = [HasBWI] in {
1774 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1775 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1776 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1777 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1780 // Mask unary operation
1782 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1783 RegisterClass KRC, SDPatternOperator OpNode,
1785 let Predicates = [prd] in
1786 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1787 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1788 [(set KRC:$dst, (OpNode KRC:$src))]>;
1791 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1792 SDPatternOperator OpNode> {
1793 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1795 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1796 HasAVX512>, VEX, PS;
1797 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1798 HasBWI>, VEX, PD, VEX_W;
1799 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1800 HasBWI>, VEX, PS, VEX_W;
1803 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1805 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1806 let Predicates = [HasAVX512] in
1807 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1809 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1810 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1812 defm : avx512_mask_unop_int<"knot", "KNOT">;
1814 let Predicates = [HasDQI] in
1815 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1816 let Predicates = [HasAVX512] in
1817 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1818 let Predicates = [HasBWI] in
1819 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1820 let Predicates = [HasBWI] in
1821 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1823 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1824 let Predicates = [HasAVX512, NoDQI] in {
1825 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1826 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1828 def : Pat<(not VK8:$src),
1830 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1833 // Mask binary operation
1834 // - KAND, KANDN, KOR, KXNOR, KXOR
1835 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1836 RegisterClass KRC, SDPatternOperator OpNode,
1838 let Predicates = [prd] in
1839 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1840 !strconcat(OpcodeStr,
1841 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1842 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1845 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1846 SDPatternOperator OpNode> {
1847 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1848 HasDQI>, VEX_4V, VEX_L, PD;
1849 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1850 HasAVX512>, VEX_4V, VEX_L, PS;
1851 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1852 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1853 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1854 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1857 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1858 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1860 let isCommutable = 1 in {
1861 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1862 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1863 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1864 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1866 let isCommutable = 0 in
1867 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1869 def : Pat<(xor VK1:$src1, VK1:$src2),
1870 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1871 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1873 def : Pat<(or VK1:$src1, VK1:$src2),
1874 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1875 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1877 def : Pat<(and VK1:$src1, VK1:$src2),
1878 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1879 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1881 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1882 let Predicates = [HasAVX512] in
1883 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1884 (i16 GR16:$src1), (i16 GR16:$src2)),
1885 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1886 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1887 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1890 defm : avx512_mask_binop_int<"kand", "KAND">;
1891 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1892 defm : avx512_mask_binop_int<"kor", "KOR">;
1893 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1894 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1896 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1897 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1898 let Predicates = [HasAVX512] in
1899 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1901 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1902 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1905 defm : avx512_binop_pat<and, KANDWrr>;
1906 defm : avx512_binop_pat<andn, KANDNWrr>;
1907 defm : avx512_binop_pat<or, KORWrr>;
1908 defm : avx512_binop_pat<xnor, KXNORWrr>;
1909 defm : avx512_binop_pat<xor, KXORWrr>;
1912 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1913 RegisterClass KRC> {
1914 let Predicates = [HasAVX512] in
1915 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1916 !strconcat(OpcodeStr,
1917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1920 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1921 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1925 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1926 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1927 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1928 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1931 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1932 let Predicates = [HasAVX512] in
1933 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1934 (i16 GR16:$src1), (i16 GR16:$src2)),
1935 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1936 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1937 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1939 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1942 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1944 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1945 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1946 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1947 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1950 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1951 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1953 let Predicates = [HasDQI] in
1954 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1956 let Predicates = [HasBWI] in {
1957 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1959 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1964 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1967 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1969 let Predicates = [HasAVX512] in
1970 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
1971 !strconcat(OpcodeStr,
1972 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1973 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1976 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1978 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1980 let Predicates = [HasDQI] in
1981 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1983 let Predicates = [HasBWI] in {
1984 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1986 let Predicates = [HasDQI] in
1987 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1992 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1993 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1995 // Mask setting all 0s or 1s
1996 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1997 let Predicates = [HasAVX512] in
1998 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1999 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2000 [(set KRC:$dst, (VT Val))]>;
2003 multiclass avx512_mask_setop_w<PatFrag Val> {
2004 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2005 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2008 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2009 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2011 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2012 let Predicates = [HasAVX512] in {
2013 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2014 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2015 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2016 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2017 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2019 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2020 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2022 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2023 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2025 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2026 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2028 let Predicates = [HasVLX] in {
2029 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2030 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2031 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2032 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2033 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2034 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2035 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2036 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2039 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2040 (v8i1 (COPY_TO_REGCLASS
2041 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2042 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2044 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2045 (v8i1 (COPY_TO_REGCLASS
2046 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2047 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2048 //===----------------------------------------------------------------------===//
2049 // AVX-512 - Aligned and unaligned load and store
2052 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2053 RegisterClass KRC, RegisterClass RC,
2054 ValueType vt, ValueType zvt, X86MemOperand memop,
2055 Domain d, bit IsReMaterializable = 1> {
2056 let hasSideEffects = 0 in {
2057 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2058 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2060 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2061 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2062 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2064 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2065 SchedRW = [WriteLoad] in
2066 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2067 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2068 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2071 let AddedComplexity = 20 in {
2072 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2073 let hasSideEffects = 0 in
2074 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2075 (ins RC:$src0, KRC:$mask, RC:$src1),
2076 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2077 "${dst} {${mask}}, $src1}"),
2078 [(set RC:$dst, (vt (vselect KRC:$mask,
2082 let mayLoad = 1, SchedRW = [WriteLoad] in
2083 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2084 (ins RC:$src0, KRC:$mask, memop:$src1),
2085 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2086 "${dst} {${mask}}, $src1}"),
2089 (vt (bitconvert (ld_frag addr:$src1))),
2093 let mayLoad = 1, SchedRW = [WriteLoad] in
2094 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2095 (ins KRC:$mask, memop:$src),
2096 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2097 "${dst} {${mask}} {z}, $src}"),
2100 (vt (bitconvert (ld_frag addr:$src))),
2101 (vt (bitconvert (zvt immAllZerosV))))))],
2106 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2107 string elty, string elsz, string vsz512,
2108 string vsz256, string vsz128, Domain d,
2109 Predicate prd, bit IsReMaterializable = 1> {
2110 let Predicates = [prd] in
2111 defm Z : avx512_load<opc, OpcodeStr,
2112 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2113 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2114 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2115 !cast<X86MemOperand>(elty##"512mem"), d,
2116 IsReMaterializable>, EVEX_V512;
2118 let Predicates = [prd, HasVLX] in {
2119 defm Z256 : avx512_load<opc, OpcodeStr,
2120 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2121 "v"##vsz256##elty##elsz, "v4i64")),
2122 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2123 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2124 !cast<X86MemOperand>(elty##"256mem"), d,
2125 IsReMaterializable>, EVEX_V256;
2127 defm Z128 : avx512_load<opc, OpcodeStr,
2128 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2129 "v"##vsz128##elty##elsz, "v2i64")),
2130 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2131 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2132 !cast<X86MemOperand>(elty##"128mem"), d,
2133 IsReMaterializable>, EVEX_V128;
2138 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2139 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2140 X86MemOperand memop, Domain d> {
2141 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2142 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2143 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2145 let Constraints = "$src1 = $dst" in
2146 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2147 (ins RC:$src1, KRC:$mask, RC:$src2),
2148 !strconcat(OpcodeStr,
2149 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2151 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2152 (ins KRC:$mask, RC:$src),
2153 !strconcat(OpcodeStr,
2154 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2155 [], d>, EVEX, EVEX_KZ;
2157 let mayStore = 1 in {
2158 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2159 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2160 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2161 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2162 (ins memop:$dst, KRC:$mask, RC:$src),
2163 !strconcat(OpcodeStr,
2164 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2165 [], d>, EVEX, EVEX_K;
2170 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2171 string st_suff_512, string st_suff_256,
2172 string st_suff_128, string elty, string elsz,
2173 string vsz512, string vsz256, string vsz128,
2174 Domain d, Predicate prd> {
2175 let Predicates = [prd] in
2176 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2177 !cast<ValueType>("v"##vsz512##elty##elsz),
2178 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2179 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2181 let Predicates = [prd, HasVLX] in {
2182 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2183 !cast<ValueType>("v"##vsz256##elty##elsz),
2184 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2185 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2187 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2188 !cast<ValueType>("v"##vsz128##elty##elsz),
2189 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2190 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2194 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2195 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2196 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2197 "512", "256", "", "f", "32", "16", "8", "4",
2198 SSEPackedSingle, HasAVX512>,
2199 PS, EVEX_CD8<32, CD8VF>;
2201 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2202 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2203 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2204 "512", "256", "", "f", "64", "8", "4", "2",
2205 SSEPackedDouble, HasAVX512>,
2206 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2208 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2209 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2210 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2211 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2212 PS, EVEX_CD8<32, CD8VF>;
2214 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2215 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2216 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2217 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2218 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2220 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2221 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2222 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2224 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2225 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2226 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2228 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2229 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2230 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2232 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2233 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2234 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2236 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2237 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2238 (VMOVAPDZrm addr:$ptr)>;
2240 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2241 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2242 (VMOVAPSZrm addr:$ptr)>;
2244 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2246 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2248 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2250 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2253 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2255 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2257 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2259 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2262 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2263 (VMOVUPSZmrk addr:$ptr,
2264 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2265 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2267 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2268 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2269 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2271 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2272 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2274 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2275 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2277 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2278 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2280 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2281 (bc_v16f32 (v16i32 immAllZerosV)))),
2282 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2284 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2285 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2287 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2288 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2290 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2291 (bc_v8f64 (v16i32 immAllZerosV)))),
2292 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2294 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2295 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2297 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2298 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2299 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2300 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2302 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2303 "16", "8", "4", SSEPackedInt, HasAVX512>,
2304 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2305 "512", "256", "", "i", "32", "16", "8", "4",
2306 SSEPackedInt, HasAVX512>,
2307 PD, EVEX_CD8<32, CD8VF>;
2309 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2310 "8", "4", "2", SSEPackedInt, HasAVX512>,
2311 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2312 "512", "256", "", "i", "64", "8", "4", "2",
2313 SSEPackedInt, HasAVX512>,
2314 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2316 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2317 "64", "32", "16", SSEPackedInt, HasBWI>,
2318 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2319 "i", "8", "64", "32", "16", SSEPackedInt,
2320 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2322 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2323 "32", "16", "8", SSEPackedInt, HasBWI>,
2324 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2325 "i", "16", "32", "16", "8", SSEPackedInt,
2326 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2328 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2329 "16", "8", "4", SSEPackedInt, HasAVX512>,
2330 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2331 "i", "32", "16", "8", "4", SSEPackedInt,
2332 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2334 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2335 "8", "4", "2", SSEPackedInt, HasAVX512>,
2336 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2337 "i", "64", "8", "4", "2", SSEPackedInt,
2338 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2340 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2341 (v16i32 immAllZerosV), GR16:$mask)),
2342 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2344 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2345 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2346 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2348 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2350 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2352 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2354 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2357 let AddedComplexity = 20 in {
2358 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2359 (bc_v8i64 (v16i32 immAllZerosV)))),
2360 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2362 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2363 (v8i64 VR512:$src))),
2364 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2367 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2368 (v16i32 immAllZerosV))),
2369 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2371 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2372 (v16i32 VR512:$src))),
2373 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2376 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2377 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2379 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2380 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2382 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2383 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2385 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2386 (bc_v8i64 (v16i32 immAllZerosV)))),
2387 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2389 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2390 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2392 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2393 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2395 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2396 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2398 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2399 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2402 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2403 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2406 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2407 (VMOVDQU32Zmrk addr:$ptr,
2408 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2409 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2411 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2412 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2413 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2416 // Move Int Doubleword to Packed Double Int
2418 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2419 "vmovd\t{$src, $dst|$dst, $src}",
2421 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2423 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2424 "vmovd\t{$src, $dst|$dst, $src}",
2426 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2427 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2428 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2429 "vmovq\t{$src, $dst|$dst, $src}",
2431 (v2i64 (scalar_to_vector GR64:$src)))],
2432 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2433 let isCodeGenOnly = 1 in {
2434 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2435 "vmovq\t{$src, $dst|$dst, $src}",
2436 [(set FR64:$dst, (bitconvert GR64:$src))],
2437 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2438 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2439 "vmovq\t{$src, $dst|$dst, $src}",
2440 [(set GR64:$dst, (bitconvert FR64:$src))],
2441 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2443 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2444 "vmovq\t{$src, $dst|$dst, $src}",
2445 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2446 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2447 EVEX_CD8<64, CD8VT1>;
2449 // Move Int Doubleword to Single Scalar
2451 let isCodeGenOnly = 1 in {
2452 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2453 "vmovd\t{$src, $dst|$dst, $src}",
2454 [(set FR32X:$dst, (bitconvert GR32:$src))],
2455 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2457 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2458 "vmovd\t{$src, $dst|$dst, $src}",
2459 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2460 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2463 // Move doubleword from xmm register to r/m32
2465 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2466 "vmovd\t{$src, $dst|$dst, $src}",
2467 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2468 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2470 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2471 (ins i32mem:$dst, VR128X:$src),
2472 "vmovd\t{$src, $dst|$dst, $src}",
2473 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2474 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2475 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2477 // Move quadword from xmm1 register to r/m64
2479 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2480 "vmovq\t{$src, $dst|$dst, $src}",
2481 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2483 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2484 Requires<[HasAVX512, In64BitMode]>;
2486 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2487 (ins i64mem:$dst, VR128X:$src),
2488 "vmovq\t{$src, $dst|$dst, $src}",
2489 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2490 addr:$dst)], IIC_SSE_MOVDQ>,
2491 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2492 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2494 // Move Scalar Single to Double Int
2496 let isCodeGenOnly = 1 in {
2497 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2499 "vmovd\t{$src, $dst|$dst, $src}",
2500 [(set GR32:$dst, (bitconvert FR32X:$src))],
2501 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2502 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2503 (ins i32mem:$dst, FR32X:$src),
2504 "vmovd\t{$src, $dst|$dst, $src}",
2505 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2506 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2509 // Move Quadword Int to Packed Quadword Int
2511 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2513 "vmovq\t{$src, $dst|$dst, $src}",
2515 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2516 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2518 //===----------------------------------------------------------------------===//
2519 // AVX-512 MOVSS, MOVSD
2520 //===----------------------------------------------------------------------===//
2522 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2523 SDNode OpNode, ValueType vt,
2524 X86MemOperand x86memop, PatFrag mem_pat> {
2525 let hasSideEffects = 0 in {
2526 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2527 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2528 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2529 (scalar_to_vector RC:$src2))))],
2530 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2531 let Constraints = "$src1 = $dst" in
2532 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2533 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2535 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2536 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2537 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2538 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2539 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2541 let mayStore = 1 in {
2542 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2543 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2544 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2546 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2547 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2548 [], IIC_SSE_MOV_S_MR>,
2549 EVEX, VEX_LIG, EVEX_K;
2551 } //hasSideEffects = 0
2554 let ExeDomain = SSEPackedSingle in
2555 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2556 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2558 let ExeDomain = SSEPackedDouble in
2559 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2560 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2562 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2563 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2564 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2566 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2567 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2568 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2570 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2571 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2572 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2574 // For the disassembler
2575 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2576 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2577 (ins VR128X:$src1, FR32X:$src2),
2578 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2580 XS, EVEX_4V, VEX_LIG;
2581 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2582 (ins VR128X:$src1, FR64X:$src2),
2583 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2585 XD, EVEX_4V, VEX_LIG, VEX_W;
2588 let Predicates = [HasAVX512] in {
2589 let AddedComplexity = 15 in {
2590 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2591 // MOVS{S,D} to the lower bits.
2592 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2593 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2594 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2595 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2596 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2597 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2598 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2599 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2601 // Move low f32 and clear high bits.
2602 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2603 (SUBREG_TO_REG (i32 0),
2604 (VMOVSSZrr (v4f32 (V_SET0)),
2605 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2606 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2607 (SUBREG_TO_REG (i32 0),
2608 (VMOVSSZrr (v4i32 (V_SET0)),
2609 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2612 let AddedComplexity = 20 in {
2613 // MOVSSrm zeros the high parts of the register; represent this
2614 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2615 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2616 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2617 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2618 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2619 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2620 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2622 // MOVSDrm zeros the high parts of the register; represent this
2623 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2624 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2625 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2626 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2627 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2628 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2629 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2630 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2631 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2632 def : Pat<(v2f64 (X86vzload addr:$src)),
2633 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2635 // Represent the same patterns above but in the form they appear for
2637 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2638 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2639 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2640 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2641 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2642 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2643 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2644 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2645 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2647 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2648 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2649 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2650 FR32X:$src)), sub_xmm)>;
2651 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2652 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2653 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2654 FR64X:$src)), sub_xmm)>;
2655 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2656 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2657 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2659 // Move low f64 and clear high bits.
2660 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2661 (SUBREG_TO_REG (i32 0),
2662 (VMOVSDZrr (v2f64 (V_SET0)),
2663 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2665 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2666 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2667 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2669 // Extract and store.
2670 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2672 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2673 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2675 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2677 // Shuffle with VMOVSS
2678 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2679 (VMOVSSZrr (v4i32 VR128X:$src1),
2680 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2681 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2682 (VMOVSSZrr (v4f32 VR128X:$src1),
2683 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2686 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2687 (SUBREG_TO_REG (i32 0),
2688 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2689 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2691 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2692 (SUBREG_TO_REG (i32 0),
2693 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2694 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2697 // Shuffle with VMOVSD
2698 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2699 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2700 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2701 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2702 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2703 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2704 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2705 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2708 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2709 (SUBREG_TO_REG (i32 0),
2710 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2711 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2713 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2714 (SUBREG_TO_REG (i32 0),
2715 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2716 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2719 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2720 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2721 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2722 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2723 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2724 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2725 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2726 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2729 let AddedComplexity = 15 in
2730 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2732 "vmovq\t{$src, $dst|$dst, $src}",
2733 [(set VR128X:$dst, (v2i64 (X86vzmovl
2734 (v2i64 VR128X:$src))))],
2735 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2737 let AddedComplexity = 20 in
2738 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2740 "vmovq\t{$src, $dst|$dst, $src}",
2741 [(set VR128X:$dst, (v2i64 (X86vzmovl
2742 (loadv2i64 addr:$src))))],
2743 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2744 EVEX_CD8<8, CD8VT8>;
2746 let Predicates = [HasAVX512] in {
2747 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2748 let AddedComplexity = 20 in {
2749 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2750 (VMOVDI2PDIZrm addr:$src)>;
2751 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2752 (VMOV64toPQIZrr GR64:$src)>;
2753 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2754 (VMOVDI2PDIZrr GR32:$src)>;
2756 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2757 (VMOVDI2PDIZrm addr:$src)>;
2758 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2759 (VMOVDI2PDIZrm addr:$src)>;
2760 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2761 (VMOVZPQILo2PQIZrm addr:$src)>;
2762 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2763 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2764 def : Pat<(v2i64 (X86vzload addr:$src)),
2765 (VMOVZPQILo2PQIZrm addr:$src)>;
2768 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2769 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2770 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2771 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2772 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2773 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2774 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2777 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2778 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2780 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2781 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2783 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2784 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2786 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2787 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2789 //===----------------------------------------------------------------------===//
2790 // AVX-512 - Non-temporals
2791 //===----------------------------------------------------------------------===//
2792 let SchedRW = [WriteLoad] in {
2793 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2794 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2795 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2796 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2797 EVEX_CD8<64, CD8VF>;
2799 let Predicates = [HasAVX512, HasVLX] in {
2800 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2802 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2803 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2804 EVEX_CD8<64, CD8VF>;
2806 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2808 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2809 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2810 EVEX_CD8<64, CD8VF>;
2814 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2815 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2816 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2817 let SchedRW = [WriteStore], mayStore = 1,
2818 AddedComplexity = 400 in
2819 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2820 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2821 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2824 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2825 string elty, string elsz, string vsz512,
2826 string vsz256, string vsz128, Domain d,
2827 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2828 let Predicates = [prd] in
2829 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2830 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2831 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2834 let Predicates = [prd, HasVLX] in {
2835 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2836 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2837 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2840 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2841 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2842 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2847 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2848 "i", "64", "8", "4", "2", SSEPackedInt,
2849 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2851 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2852 "f", "64", "8", "4", "2", SSEPackedDouble,
2853 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2855 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2856 "f", "32", "16", "8", "4", SSEPackedSingle,
2857 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2859 //===----------------------------------------------------------------------===//
2860 // AVX-512 - Integer arithmetic
2862 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2863 X86VectorVTInfo _, OpndItins itins,
2864 bit IsCommutable = 0> {
2865 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2866 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2867 "$src2, $src1", "$src1, $src2",
2868 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2869 "", itins.rr, IsCommutable>,
2870 AVX512BIBase, EVEX_4V;
2873 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2874 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2875 "$src2, $src1", "$src1, $src2",
2876 (_.VT (OpNode _.RC:$src1,
2877 (bitconvert (_.LdFrag addr:$src2)))),
2879 AVX512BIBase, EVEX_4V;
2882 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2883 X86VectorVTInfo _, OpndItins itins,
2884 bit IsCommutable = 0> :
2885 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2887 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2888 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2889 "${src2}"##_.BroadcastStr##", $src1",
2890 "$src1, ${src2}"##_.BroadcastStr,
2891 (_.VT (OpNode _.RC:$src1,
2893 (_.ScalarLdFrag addr:$src2)))),
2895 AVX512BIBase, EVEX_4V, EVEX_B;
2898 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2899 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2900 Predicate prd, bit IsCommutable = 0> {
2901 let Predicates = [prd] in
2902 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2903 IsCommutable>, EVEX_V512;
2905 let Predicates = [prd, HasVLX] in {
2906 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2907 IsCommutable>, EVEX_V256;
2908 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2909 IsCommutable>, EVEX_V128;
2913 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2914 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2915 Predicate prd, bit IsCommutable = 0> {
2916 let Predicates = [prd] in
2917 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2918 IsCommutable>, EVEX_V512;
2920 let Predicates = [prd, HasVLX] in {
2921 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2922 IsCommutable>, EVEX_V256;
2923 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2924 IsCommutable>, EVEX_V128;
2928 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2929 OpndItins itins, Predicate prd,
2930 bit IsCommutable = 0> {
2931 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2932 itins, prd, IsCommutable>,
2933 VEX_W, EVEX_CD8<64, CD8VF>;
2936 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2937 OpndItins itins, Predicate prd,
2938 bit IsCommutable = 0> {
2939 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2940 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2943 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2944 OpndItins itins, Predicate prd,
2945 bit IsCommutable = 0> {
2946 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2947 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2950 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2951 OpndItins itins, Predicate prd,
2952 bit IsCommutable = 0> {
2953 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2954 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2957 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2958 SDNode OpNode, OpndItins itins, Predicate prd,
2959 bit IsCommutable = 0> {
2960 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2963 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2967 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2968 SDNode OpNode, OpndItins itins, Predicate prd,
2969 bit IsCommutable = 0> {
2970 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2973 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2977 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2978 bits<8> opc_d, bits<8> opc_q,
2979 string OpcodeStr, SDNode OpNode,
2980 OpndItins itins, bit IsCommutable = 0> {
2981 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2982 itins, HasAVX512, IsCommutable>,
2983 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2984 itins, HasBWI, IsCommutable>;
2987 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2988 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2989 PatFrag memop_frag, X86MemOperand x86memop,
2990 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2991 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2992 let isCommutable = IsCommutable in
2994 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2995 (ins RC:$src1, RC:$src2),
2996 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2998 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2999 (ins KRC:$mask, RC:$src1, RC:$src2),
3000 !strconcat(OpcodeStr,
3001 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3002 [], itins.rr>, EVEX_4V, EVEX_K;
3003 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3004 (ins KRC:$mask, RC:$src1, RC:$src2),
3005 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
3006 "|$dst {${mask}} {z}, $src1, $src2}"),
3007 [], itins.rr>, EVEX_4V, EVEX_KZ;
3009 let mayLoad = 1 in {
3010 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3011 (ins RC:$src1, x86memop:$src2),
3012 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3014 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3015 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3016 !strconcat(OpcodeStr,
3017 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3018 [], itins.rm>, EVEX_4V, EVEX_K;
3019 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3020 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3021 !strconcat(OpcodeStr,
3022 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3023 [], itins.rm>, EVEX_4V, EVEX_KZ;
3024 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3025 (ins RC:$src1, x86scalar_mop:$src2),
3026 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3027 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3028 [], itins.rm>, EVEX_4V, EVEX_B;
3029 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3030 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3031 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3032 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
3034 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
3035 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3036 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3037 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3038 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3040 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
3044 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3045 SSE_INTALU_ITINS_P, 1>;
3046 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3047 SSE_INTALU_ITINS_P, 0>;
3048 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3049 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3050 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3051 SSE_INTALU_ITINS_P, HasBWI, 1>;
3052 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3053 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3055 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3056 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3057 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3058 EVEX_CD8<64, CD8VF>, VEX_W;
3060 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3061 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3062 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3064 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3065 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3067 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3068 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3069 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3070 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3071 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3072 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3074 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3075 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3076 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3077 SSE_INTALU_ITINS_P, HasBWI, 1>;
3078 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3079 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3081 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3082 SSE_INTALU_ITINS_P, HasBWI, 1>;
3083 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3084 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3085 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3086 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3088 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3089 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3090 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3091 SSE_INTALU_ITINS_P, HasBWI, 1>;
3092 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3093 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3095 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3096 SSE_INTALU_ITINS_P, HasBWI, 1>;
3097 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3098 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3099 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3100 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3102 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3103 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3104 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3105 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3106 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3107 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3108 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3109 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3110 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3111 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3112 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3113 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3114 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3115 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3116 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3117 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3118 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3119 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3120 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3121 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3122 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3123 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3124 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3125 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3126 //===----------------------------------------------------------------------===//
3127 // AVX-512 - Unpack Instructions
3128 //===----------------------------------------------------------------------===//
3130 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3131 PatFrag mem_frag, RegisterClass RC,
3132 X86MemOperand x86memop, string asm,
3134 def rr : AVX512PI<opc, MRMSrcReg,
3135 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3137 (vt (OpNode RC:$src1, RC:$src2)))],
3139 def rm : AVX512PI<opc, MRMSrcMem,
3140 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3142 (vt (OpNode RC:$src1,
3143 (bitconvert (mem_frag addr:$src2)))))],
3147 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3148 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3149 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3150 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3151 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3152 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3153 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3154 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3155 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3156 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3157 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3158 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3160 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3161 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3162 X86MemOperand x86memop> {
3163 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3164 (ins RC:$src1, RC:$src2),
3165 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3166 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3167 IIC_SSE_UNPCK>, EVEX_4V;
3168 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3169 (ins RC:$src1, x86memop:$src2),
3170 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3171 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3172 (bitconvert (memop_frag addr:$src2)))))],
3173 IIC_SSE_UNPCK>, EVEX_4V;
3175 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3176 VR512, loadv16i32, i512mem>, EVEX_V512,
3177 EVEX_CD8<32, CD8VF>;
3178 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3179 VR512, loadv8i64, i512mem>, EVEX_V512,
3180 VEX_W, EVEX_CD8<64, CD8VF>;
3181 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3182 VR512, loadv16i32, i512mem>, EVEX_V512,
3183 EVEX_CD8<32, CD8VF>;
3184 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3185 VR512, loadv8i64, i512mem>, EVEX_V512,
3186 VEX_W, EVEX_CD8<64, CD8VF>;
3187 //===----------------------------------------------------------------------===//
3191 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3192 SDNode OpNode, PatFrag mem_frag,
3193 X86MemOperand x86memop, ValueType OpVT> {
3194 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3195 (ins RC:$src1, u8imm:$src2),
3196 !strconcat(OpcodeStr,
3197 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3199 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3201 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3202 (ins x86memop:$src1, u8imm:$src2),
3203 !strconcat(OpcodeStr,
3204 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3206 (OpVT (OpNode (mem_frag addr:$src1),
3207 (i8 imm:$src2))))]>, EVEX;
3210 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3211 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3213 //===----------------------------------------------------------------------===//
3214 // AVX-512 Logical Instructions
3215 //===----------------------------------------------------------------------===//
3217 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3218 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3219 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3220 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3221 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3222 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3223 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3224 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3226 //===----------------------------------------------------------------------===//
3227 // AVX-512 FP arithmetic
3228 //===----------------------------------------------------------------------===//
3230 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3232 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3233 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3234 EVEX_CD8<32, CD8VT1>;
3235 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3236 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3237 EVEX_CD8<64, CD8VT1>;
3240 let isCommutable = 1 in {
3241 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3242 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3243 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3244 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3246 let isCommutable = 0 in {
3247 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3248 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3251 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3252 X86VectorVTInfo _, bit IsCommutable> {
3253 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3254 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3255 "$src2, $src1", "$src1, $src2",
3256 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3257 let mayLoad = 1 in {
3258 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3259 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3260 "$src2, $src1", "$src1, $src2",
3261 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3262 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3263 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3264 "${src2}"##_.BroadcastStr##", $src1",
3265 "$src1, ${src2}"##_.BroadcastStr,
3266 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3267 (_.ScalarLdFrag addr:$src2))))>,
3272 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3273 bit IsCommutable = 0> {
3274 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3275 IsCommutable>, EVEX_V512, PS,
3276 EVEX_CD8<32, CD8VF>;
3277 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3278 IsCommutable>, EVEX_V512, PD, VEX_W,
3279 EVEX_CD8<64, CD8VF>;
3281 // Define only if AVX512VL feature is present.
3282 let Predicates = [HasVLX] in {
3283 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3284 IsCommutable>, EVEX_V128, PS,
3285 EVEX_CD8<32, CD8VF>;
3286 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3287 IsCommutable>, EVEX_V256, PS,
3288 EVEX_CD8<32, CD8VF>;
3289 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3290 IsCommutable>, EVEX_V128, PD, VEX_W,
3291 EVEX_CD8<64, CD8VF>;
3292 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3293 IsCommutable>, EVEX_V256, PD, VEX_W,
3294 EVEX_CD8<64, CD8VF>;
3298 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3299 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3300 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3301 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3302 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3303 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3305 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3306 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3307 (i16 -1), FROUND_CURRENT)),
3308 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3310 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3311 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3312 (i8 -1), FROUND_CURRENT)),
3313 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3315 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3316 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3317 (i16 -1), FROUND_CURRENT)),
3318 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3320 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3321 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3322 (i8 -1), FROUND_CURRENT)),
3323 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3324 //===----------------------------------------------------------------------===//
3325 // AVX-512 VPTESTM instructions
3326 //===----------------------------------------------------------------------===//
3328 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3329 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3330 SDNode OpNode, ValueType vt> {
3331 def rr : AVX512PI<opc, MRMSrcReg,
3332 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3333 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3334 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3335 SSEPackedInt>, EVEX_4V;
3336 def rm : AVX512PI<opc, MRMSrcMem,
3337 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3339 [(set KRC:$dst, (OpNode (vt RC:$src1),
3340 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3343 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3344 loadv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3345 EVEX_CD8<32, CD8VF>;
3346 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3347 loadv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3348 EVEX_CD8<64, CD8VF>;
3350 let Predicates = [HasCDI] in {
3351 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3352 loadv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3353 EVEX_CD8<32, CD8VF>;
3354 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3355 loadv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3356 EVEX_CD8<64, CD8VF>;
3359 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3360 (v16i32 VR512:$src2), (i16 -1))),
3361 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3363 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3364 (v8i64 VR512:$src2), (i8 -1))),
3365 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3367 //===----------------------------------------------------------------------===//
3368 // AVX-512 Shift instructions
3369 //===----------------------------------------------------------------------===//
3370 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3371 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3372 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3373 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3374 "$src2, $src1", "$src1, $src2",
3375 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3376 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3377 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3378 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3379 "$src2, $src1", "$src1, $src2",
3380 (_.VT (OpNode (_.LdFrag addr:$src1), (i8 imm:$src2))),
3381 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3384 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3385 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3386 // src2 is always 128-bit
3387 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3388 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3389 "$src2, $src1", "$src1, $src2",
3390 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3391 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3392 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3393 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3394 "$src2, $src1", "$src1, $src2",
3395 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3396 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3399 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3400 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3401 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3404 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3406 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3407 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3408 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3409 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3412 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3414 EVEX_V512, EVEX_CD8<32, CD8VF>;
3415 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3416 v8i64_info>, EVEX_V512,
3417 EVEX_CD8<64, CD8VF>, VEX_W;
3419 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3420 v16i32_info>, EVEX_V512,
3421 EVEX_CD8<32, CD8VF>;
3422 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3423 v8i64_info>, EVEX_V512,
3424 EVEX_CD8<64, CD8VF>, VEX_W;
3426 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3428 EVEX_V512, EVEX_CD8<32, CD8VF>;
3429 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3430 v8i64_info>, EVEX_V512,
3431 EVEX_CD8<64, CD8VF>, VEX_W;
3433 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3434 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3435 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3437 //===-------------------------------------------------------------------===//
3438 // Variable Bit Shifts
3439 //===-------------------------------------------------------------------===//
3440 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3441 X86VectorVTInfo _> {
3442 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3443 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3444 "$src2, $src1", "$src1, $src2",
3445 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3446 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3447 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3448 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3449 "$src2, $src1", "$src1, $src2",
3450 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3451 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3454 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3455 AVX512VLVectorVTInfo _> {
3456 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3459 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3461 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3462 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3463 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3464 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3467 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3468 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3469 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3471 //===----------------------------------------------------------------------===//
3472 // AVX-512 - MOVDDUP
3473 //===----------------------------------------------------------------------===//
3475 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3476 X86MemOperand x86memop, PatFrag memop_frag> {
3477 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3478 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3479 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3480 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3481 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3483 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3486 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3487 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3488 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3489 (VMOVDDUPZrm addr:$src)>;
3491 //===---------------------------------------------------------------------===//
3492 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3493 //===---------------------------------------------------------------------===//
3494 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3495 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3496 X86MemOperand x86memop> {
3497 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3498 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3499 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3501 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3502 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3503 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3506 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3507 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3508 EVEX_CD8<32, CD8VF>;
3509 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3510 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3511 EVEX_CD8<32, CD8VF>;
3513 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3514 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3515 (VMOVSHDUPZrm addr:$src)>;
3516 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3517 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3518 (VMOVSLDUPZrm addr:$src)>;
3520 //===----------------------------------------------------------------------===//
3521 // Move Low to High and High to Low packed FP Instructions
3522 //===----------------------------------------------------------------------===//
3523 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3524 (ins VR128X:$src1, VR128X:$src2),
3525 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3526 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3527 IIC_SSE_MOV_LH>, EVEX_4V;
3528 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3529 (ins VR128X:$src1, VR128X:$src2),
3530 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3531 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3532 IIC_SSE_MOV_LH>, EVEX_4V;
3534 let Predicates = [HasAVX512] in {
3536 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3537 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3538 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3539 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3542 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3543 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3546 //===----------------------------------------------------------------------===//
3547 // FMA - Fused Multiply Operations
3550 let Constraints = "$src1 = $dst" in {
3551 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3552 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3553 SDPatternOperator OpNode = null_frag> {
3554 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3555 (ins _.RC:$src2, _.RC:$src3),
3556 OpcodeStr, "$src3, $src2", "$src2, $src3",
3557 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3561 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3562 (ins _.RC:$src2, _.MemOp:$src3),
3563 OpcodeStr, "$src3, $src2", "$src2, $src3",
3564 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3567 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3568 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3569 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3570 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3571 AVX512FMA3Base, EVEX_B;
3573 } // Constraints = "$src1 = $dst"
3575 let Constraints = "$src1 = $dst" in {
3576 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3577 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3578 SDPatternOperator OpNode> {
3579 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3580 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3581 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3582 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3583 AVX512FMA3Base, EVEX_B, EVEX_RC;
3585 } // Constraints = "$src1 = $dst"
3587 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3588 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3589 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3590 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3593 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3594 string OpcodeStr, X86VectorVTInfo VTI,
3595 SDPatternOperator OpNode> {
3596 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3597 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3599 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3600 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3603 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3605 SDPatternOperator OpNode,
3606 SDPatternOperator OpNodeRnd> {
3607 let ExeDomain = SSEPackedSingle in {
3608 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3609 v16f32_info, OpNode>,
3610 avx512_fma3_round_forms<opc213, OpcodeStr,
3611 v16f32_info, OpNodeRnd>, EVEX_V512;
3612 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3613 v8f32x_info, OpNode>, EVEX_V256;
3614 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3615 v4f32x_info, OpNode>, EVEX_V128;
3617 let ExeDomain = SSEPackedDouble in {
3618 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3619 v8f64_info, OpNode>,
3620 avx512_fma3_round_forms<opc213, OpcodeStr,
3621 v8f64_info, OpNodeRnd>, EVEX_V512, VEX_W;
3622 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3623 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3624 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3625 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3629 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
3630 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
3631 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
3632 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
3633 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
3634 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
3636 let Constraints = "$src1 = $dst" in {
3637 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3638 X86VectorVTInfo _> {
3640 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3641 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3642 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3643 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
3645 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3646 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3647 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3648 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3650 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3651 (_.ScalarLdFrag addr:$src2))),
3652 _.RC:$src3))]>, EVEX_B;
3654 } // Constraints = "$src1 = $dst"
3657 multiclass avx512_fma3p_m132_f<bits<8> opc,
3661 let ExeDomain = SSEPackedSingle in {
3662 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3663 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3664 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3665 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3666 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3667 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3669 let ExeDomain = SSEPackedDouble in {
3670 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3671 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3672 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3673 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3674 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3675 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3679 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3680 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3681 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3682 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3683 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3684 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3688 let Constraints = "$src1 = $dst" in {
3689 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3690 RegisterClass RC, ValueType OpVT,
3691 X86MemOperand x86memop, Operand memop,
3693 let isCommutable = 1 in
3694 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3695 (ins RC:$src1, RC:$src2, RC:$src3),
3696 !strconcat(OpcodeStr,
3697 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3699 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3701 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3702 (ins RC:$src1, RC:$src2, f128mem:$src3),
3703 !strconcat(OpcodeStr,
3704 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3706 (OpVT (OpNode RC:$src2, RC:$src1,
3707 (mem_frag addr:$src3))))]>;
3710 } // Constraints = "$src1 = $dst"
3712 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3713 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3714 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3715 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3716 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3717 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3718 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3719 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3720 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3721 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3722 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3723 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3724 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3725 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3726 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3727 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3729 //===----------------------------------------------------------------------===//
3730 // AVX-512 Scalar convert from sign integer to float/double
3731 //===----------------------------------------------------------------------===//
3733 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3734 X86MemOperand x86memop, string asm> {
3735 let hasSideEffects = 0 in {
3736 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3737 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3740 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3741 (ins DstRC:$src1, x86memop:$src),
3742 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3744 } // hasSideEffects = 0
3746 let Predicates = [HasAVX512] in {
3747 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3748 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3749 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3750 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3751 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3752 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3753 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3754 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3756 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3757 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3758 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3759 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3760 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3761 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3762 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3763 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3765 def : Pat<(f32 (sint_to_fp GR32:$src)),
3766 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3767 def : Pat<(f32 (sint_to_fp GR64:$src)),
3768 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3769 def : Pat<(f64 (sint_to_fp GR32:$src)),
3770 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3771 def : Pat<(f64 (sint_to_fp GR64:$src)),
3772 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3774 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3775 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3776 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3777 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3778 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3779 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3780 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3781 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3783 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3784 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3785 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3786 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3787 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3788 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3789 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3790 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3792 def : Pat<(f32 (uint_to_fp GR32:$src)),
3793 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3794 def : Pat<(f32 (uint_to_fp GR64:$src)),
3795 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3796 def : Pat<(f64 (uint_to_fp GR32:$src)),
3797 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3798 def : Pat<(f64 (uint_to_fp GR64:$src)),
3799 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3802 //===----------------------------------------------------------------------===//
3803 // AVX-512 Scalar convert from float/double to integer
3804 //===----------------------------------------------------------------------===//
3805 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3806 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3808 let hasSideEffects = 0 in {
3809 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3810 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3811 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3812 Requires<[HasAVX512]>;
3814 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3815 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3816 Requires<[HasAVX512]>;
3817 } // hasSideEffects = 0
3819 let Predicates = [HasAVX512] in {
3820 // Convert float/double to signed/unsigned int 32/64
3821 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3822 ssmem, sse_load_f32, "cvtss2si">,
3823 XS, EVEX_CD8<32, CD8VT1>;
3824 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3825 ssmem, sse_load_f32, "cvtss2si">,
3826 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3827 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3828 ssmem, sse_load_f32, "cvtss2usi">,
3829 XS, EVEX_CD8<32, CD8VT1>;
3830 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3831 int_x86_avx512_cvtss2usi64, ssmem,
3832 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3833 EVEX_CD8<32, CD8VT1>;
3834 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3835 sdmem, sse_load_f64, "cvtsd2si">,
3836 XD, EVEX_CD8<64, CD8VT1>;
3837 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3838 sdmem, sse_load_f64, "cvtsd2si">,
3839 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3840 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3841 sdmem, sse_load_f64, "cvtsd2usi">,
3842 XD, EVEX_CD8<64, CD8VT1>;
3843 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3844 int_x86_avx512_cvtsd2usi64, sdmem,
3845 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3846 EVEX_CD8<64, CD8VT1>;
3848 let isCodeGenOnly = 1 in {
3849 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3850 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3851 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3852 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3853 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3854 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3855 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3856 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3857 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3858 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3859 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3860 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3862 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3863 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3864 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3865 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3866 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3867 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3868 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3869 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3870 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3871 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3872 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3873 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3874 } // isCodeGenOnly = 1
3876 // Convert float/double to signed/unsigned int 32/64 with truncation
3877 let isCodeGenOnly = 1 in {
3878 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3879 ssmem, sse_load_f32, "cvttss2si">,
3880 XS, EVEX_CD8<32, CD8VT1>;
3881 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3882 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3883 "cvttss2si">, XS, VEX_W,
3884 EVEX_CD8<32, CD8VT1>;
3885 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3886 sdmem, sse_load_f64, "cvttsd2si">, XD,
3887 EVEX_CD8<64, CD8VT1>;
3888 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3889 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3890 "cvttsd2si">, XD, VEX_W,
3891 EVEX_CD8<64, CD8VT1>;
3892 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3893 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3894 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3895 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3896 int_x86_avx512_cvttss2usi64, ssmem,
3897 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3898 EVEX_CD8<32, CD8VT1>;
3899 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3900 int_x86_avx512_cvttsd2usi,
3901 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3902 EVEX_CD8<64, CD8VT1>;
3903 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3904 int_x86_avx512_cvttsd2usi64, sdmem,
3905 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3906 EVEX_CD8<64, CD8VT1>;
3907 } // isCodeGenOnly = 1
3909 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3910 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3912 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3913 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3914 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3915 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3916 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3917 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3920 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3921 loadf32, "cvttss2si">, XS,
3922 EVEX_CD8<32, CD8VT1>;
3923 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3924 loadf32, "cvttss2usi">, XS,
3925 EVEX_CD8<32, CD8VT1>;
3926 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3927 loadf32, "cvttss2si">, XS, VEX_W,
3928 EVEX_CD8<32, CD8VT1>;
3929 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3930 loadf32, "cvttss2usi">, XS, VEX_W,
3931 EVEX_CD8<32, CD8VT1>;
3932 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3933 loadf64, "cvttsd2si">, XD,
3934 EVEX_CD8<64, CD8VT1>;
3935 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3936 loadf64, "cvttsd2usi">, XD,
3937 EVEX_CD8<64, CD8VT1>;
3938 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3939 loadf64, "cvttsd2si">, XD, VEX_W,
3940 EVEX_CD8<64, CD8VT1>;
3941 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3942 loadf64, "cvttsd2usi">, XD, VEX_W,
3943 EVEX_CD8<64, CD8VT1>;
3945 //===----------------------------------------------------------------------===//
3946 // AVX-512 Convert form float to double and back
3947 //===----------------------------------------------------------------------===//
3948 let hasSideEffects = 0 in {
3949 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3950 (ins FR32X:$src1, FR32X:$src2),
3951 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3952 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3954 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3955 (ins FR32X:$src1, f32mem:$src2),
3956 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3957 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3958 EVEX_CD8<32, CD8VT1>;
3960 // Convert scalar double to scalar single
3961 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3962 (ins FR64X:$src1, FR64X:$src2),
3963 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3964 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3966 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3967 (ins FR64X:$src1, f64mem:$src2),
3968 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3969 []>, EVEX_4V, VEX_LIG, VEX_W,
3970 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3973 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3974 Requires<[HasAVX512]>;
3975 def : Pat<(fextend (loadf32 addr:$src)),
3976 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3978 def : Pat<(extloadf32 addr:$src),
3979 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3980 Requires<[HasAVX512, OptForSize]>;
3982 def : Pat<(extloadf32 addr:$src),
3983 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3984 Requires<[HasAVX512, OptForSpeed]>;
3986 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3987 Requires<[HasAVX512]>;
3989 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3990 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3991 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3993 let hasSideEffects = 0 in {
3994 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3995 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3997 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3998 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3999 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4000 [], d>, EVEX, EVEX_B, EVEX_RC;
4002 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4003 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4005 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4006 } // hasSideEffects = 0
4009 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4010 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4011 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4013 let hasSideEffects = 0 in {
4014 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4015 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4017 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4019 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4020 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4022 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4023 } // hasSideEffects = 0
4026 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4027 loadv8f64, f512mem, v8f32, v8f64,
4028 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4029 EVEX_CD8<64, CD8VF>;
4031 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4032 loadv4f64, f256mem, v8f64, v8f32,
4033 SSEPackedDouble>, EVEX_V512, PS,
4034 EVEX_CD8<32, CD8VH>;
4035 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4036 (VCVTPS2PDZrm addr:$src)>;
4038 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4039 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4040 (VCVTPD2PSZrr VR512:$src)>;
4042 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4043 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4044 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4046 //===----------------------------------------------------------------------===//
4047 // AVX-512 Vector convert from sign integer to float/double
4048 //===----------------------------------------------------------------------===//
4050 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4051 loadv8i64, i512mem, v16f32, v16i32,
4052 SSEPackedSingle>, EVEX_V512, PS,
4053 EVEX_CD8<32, CD8VF>;
4055 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4056 loadv4i64, i256mem, v8f64, v8i32,
4057 SSEPackedDouble>, EVEX_V512, XS,
4058 EVEX_CD8<32, CD8VH>;
4060 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4061 loadv16f32, f512mem, v16i32, v16f32,
4062 SSEPackedSingle>, EVEX_V512, XS,
4063 EVEX_CD8<32, CD8VF>;
4065 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4066 loadv8f64, f512mem, v8i32, v8f64,
4067 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4068 EVEX_CD8<64, CD8VF>;
4070 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4071 loadv16f32, f512mem, v16i32, v16f32,
4072 SSEPackedSingle>, EVEX_V512, PS,
4073 EVEX_CD8<32, CD8VF>;
4075 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4076 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4077 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4078 (VCVTTPS2UDQZrr VR512:$src)>;
4080 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4081 loadv8f64, f512mem, v8i32, v8f64,
4082 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4083 EVEX_CD8<64, CD8VF>;
4085 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4086 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4087 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4088 (VCVTTPD2UDQZrr VR512:$src)>;
4090 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4091 loadv4i64, f256mem, v8f64, v8i32,
4092 SSEPackedDouble>, EVEX_V512, XS,
4093 EVEX_CD8<32, CD8VH>;
4095 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4096 loadv16i32, f512mem, v16f32, v16i32,
4097 SSEPackedSingle>, EVEX_V512, XD,
4098 EVEX_CD8<32, CD8VF>;
4100 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4101 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4102 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4104 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4105 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4106 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4108 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4109 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4110 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4112 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4113 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4114 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4116 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4117 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4118 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4120 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4121 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4122 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4123 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4124 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4125 (VCVTDQ2PDZrr VR256X:$src)>;
4126 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4127 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4128 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4129 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4130 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4131 (VCVTUDQ2PDZrr VR256X:$src)>;
4133 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4134 RegisterClass DstRC, PatFrag mem_frag,
4135 X86MemOperand x86memop, Domain d> {
4136 let hasSideEffects = 0 in {
4137 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4138 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4140 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4141 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4142 [], d>, EVEX, EVEX_B, EVEX_RC;
4144 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4145 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4147 } // hasSideEffects = 0
4150 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4151 loadv16f32, f512mem, SSEPackedSingle>, PD,
4152 EVEX_V512, EVEX_CD8<32, CD8VF>;
4153 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4154 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4155 EVEX_V512, EVEX_CD8<64, CD8VF>;
4157 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4158 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4159 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4161 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4162 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4163 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4165 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4166 loadv16f32, f512mem, SSEPackedSingle>,
4167 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4168 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4169 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4170 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4172 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4173 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4174 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4176 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4177 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4178 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4180 let Predicates = [HasAVX512] in {
4181 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4182 (VCVTPD2PSZrm addr:$src)>;
4183 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4184 (VCVTPS2PDZrm addr:$src)>;
4187 //===----------------------------------------------------------------------===//
4188 // Half precision conversion instructions
4189 //===----------------------------------------------------------------------===//
4190 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4191 X86MemOperand x86memop> {
4192 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4193 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4195 let hasSideEffects = 0, mayLoad = 1 in
4196 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4197 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4200 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4201 X86MemOperand x86memop> {
4202 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4203 (ins srcRC:$src1, i32u8imm:$src2),
4204 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4206 let hasSideEffects = 0, mayStore = 1 in
4207 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4208 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4209 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4212 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4213 EVEX_CD8<32, CD8VH>;
4214 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4215 EVEX_CD8<32, CD8VH>;
4217 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4218 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4219 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4221 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4222 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4223 (VCVTPH2PSZrr VR256X:$src)>;
4225 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4226 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4227 "ucomiss">, PS, EVEX, VEX_LIG,
4228 EVEX_CD8<32, CD8VT1>;
4229 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4230 "ucomisd">, PD, EVEX,
4231 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4232 let Pattern = []<dag> in {
4233 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4234 "comiss">, PS, EVEX, VEX_LIG,
4235 EVEX_CD8<32, CD8VT1>;
4236 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4237 "comisd">, PD, EVEX,
4238 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4240 let isCodeGenOnly = 1 in {
4241 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4242 load, "ucomiss">, PS, EVEX, VEX_LIG,
4243 EVEX_CD8<32, CD8VT1>;
4244 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4245 load, "ucomisd">, PD, EVEX,
4246 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4248 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4249 load, "comiss">, PS, EVEX, VEX_LIG,
4250 EVEX_CD8<32, CD8VT1>;
4251 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4252 load, "comisd">, PD, EVEX,
4253 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4257 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4258 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4259 X86MemOperand x86memop> {
4260 let hasSideEffects = 0 in {
4261 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4262 (ins RC:$src1, RC:$src2),
4263 !strconcat(OpcodeStr,
4264 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4265 let mayLoad = 1 in {
4266 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4267 (ins RC:$src1, x86memop:$src2),
4268 !strconcat(OpcodeStr,
4269 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4274 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4275 EVEX_CD8<32, CD8VT1>;
4276 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4277 VEX_W, EVEX_CD8<64, CD8VT1>;
4278 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4279 EVEX_CD8<32, CD8VT1>;
4280 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4281 VEX_W, EVEX_CD8<64, CD8VT1>;
4283 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4284 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4285 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4286 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4288 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4289 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4290 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4291 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4293 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4294 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4295 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4296 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4298 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4299 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4300 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4301 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4303 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4304 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4305 X86VectorVTInfo _> {
4306 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4307 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4308 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4309 let mayLoad = 1 in {
4310 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4311 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4313 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4314 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4315 (ins _.ScalarMemOp:$src), OpcodeStr,
4316 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4318 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4323 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4324 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4325 EVEX_V512, EVEX_CD8<32, CD8VF>;
4326 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4327 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4329 // Define only if AVX512VL feature is present.
4330 let Predicates = [HasVLX] in {
4331 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4332 OpNode, v4f32x_info>,
4333 EVEX_V128, EVEX_CD8<32, CD8VF>;
4334 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4335 OpNode, v8f32x_info>,
4336 EVEX_V256, EVEX_CD8<32, CD8VF>;
4337 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4338 OpNode, v2f64x_info>,
4339 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4340 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4341 OpNode, v4f64x_info>,
4342 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4346 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4347 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4349 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4350 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4351 (VRSQRT14PSZr VR512:$src)>;
4352 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4353 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4354 (VRSQRT14PDZr VR512:$src)>;
4356 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4357 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4358 (VRCP14PSZr VR512:$src)>;
4359 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4360 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4361 (VRCP14PDZr VR512:$src)>;
4363 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4364 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4367 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4368 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4369 "$src2, $src1", "$src1, $src2",
4370 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4371 (i32 FROUND_CURRENT))>;
4373 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4374 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4375 "$src2, $src1", "$src1, $src2",
4376 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4377 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4379 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4380 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4381 "$src2, $src1", "$src1, $src2",
4382 (OpNode (_.VT _.RC:$src1),
4383 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4384 (i32 FROUND_CURRENT))>;
4387 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4388 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4389 EVEX_CD8<32, CD8VT1>;
4390 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4391 EVEX_CD8<64, CD8VT1>, VEX_W;
4394 let hasSideEffects = 0, Predicates = [HasERI] in {
4395 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4396 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4398 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4400 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4403 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4404 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4405 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4407 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4408 (ins _.RC:$src), OpcodeStr,
4410 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4413 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4414 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4416 (bitconvert (_.LdFrag addr:$src))),
4417 (i32 FROUND_CURRENT))>;
4419 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4420 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4422 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4423 (i32 FROUND_CURRENT))>, EVEX_B;
4426 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4427 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4428 EVEX_CD8<32, CD8VF>;
4429 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4430 VEX_W, EVEX_CD8<32, CD8VF>;
4433 let Predicates = [HasERI], hasSideEffects = 0 in {
4435 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4436 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4437 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4440 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4441 SDNode OpNode, X86VectorVTInfo _>{
4442 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4443 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4444 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4445 let mayLoad = 1 in {
4446 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4447 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4449 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4451 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4452 (ins _.ScalarMemOp:$src), OpcodeStr,
4453 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4455 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4460 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4461 Intrinsic F32Int, Intrinsic F64Int,
4462 OpndItins itins_s, OpndItins itins_d> {
4463 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4464 (ins FR32X:$src1, FR32X:$src2),
4465 !strconcat(OpcodeStr,
4466 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4467 [], itins_s.rr>, XS, EVEX_4V;
4468 let isCodeGenOnly = 1 in
4469 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4470 (ins VR128X:$src1, VR128X:$src2),
4471 !strconcat(OpcodeStr,
4472 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4474 (F32Int VR128X:$src1, VR128X:$src2))],
4475 itins_s.rr>, XS, EVEX_4V;
4476 let mayLoad = 1 in {
4477 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4478 (ins FR32X:$src1, f32mem:$src2),
4479 !strconcat(OpcodeStr,
4480 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4481 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4482 let isCodeGenOnly = 1 in
4483 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4484 (ins VR128X:$src1, ssmem:$src2),
4485 !strconcat(OpcodeStr,
4486 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4488 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4489 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4491 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4492 (ins FR64X:$src1, FR64X:$src2),
4493 !strconcat(OpcodeStr,
4494 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4496 let isCodeGenOnly = 1 in
4497 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4498 (ins VR128X:$src1, VR128X:$src2),
4499 !strconcat(OpcodeStr,
4500 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4502 (F64Int VR128X:$src1, VR128X:$src2))],
4503 itins_s.rr>, XD, EVEX_4V, VEX_W;
4504 let mayLoad = 1 in {
4505 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4506 (ins FR64X:$src1, f64mem:$src2),
4507 !strconcat(OpcodeStr,
4508 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4509 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4510 let isCodeGenOnly = 1 in
4511 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4512 (ins VR128X:$src1, sdmem:$src2),
4513 !strconcat(OpcodeStr,
4514 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4516 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4517 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4521 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4523 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4525 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4526 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4528 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4529 // Define only if AVX512VL feature is present.
4530 let Predicates = [HasVLX] in {
4531 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4532 OpNode, v4f32x_info>,
4533 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4534 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4535 OpNode, v8f32x_info>,
4536 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4537 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4538 OpNode, v2f64x_info>,
4539 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4540 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4541 OpNode, v4f64x_info>,
4542 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4546 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4548 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4549 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4550 SSE_SQRTSS, SSE_SQRTSD>;
4552 let Predicates = [HasAVX512] in {
4553 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4554 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4555 (VSQRTPSZr VR512:$src1)>;
4556 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4557 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4558 (VSQRTPDZr VR512:$src1)>;
4560 def : Pat<(f32 (fsqrt FR32X:$src)),
4561 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4562 def : Pat<(f32 (fsqrt (load addr:$src))),
4563 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4564 Requires<[OptForSize]>;
4565 def : Pat<(f64 (fsqrt FR64X:$src)),
4566 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4567 def : Pat<(f64 (fsqrt (load addr:$src))),
4568 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4569 Requires<[OptForSize]>;
4571 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4572 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4573 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4574 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4575 Requires<[OptForSize]>;
4577 def : Pat<(f32 (X86frcp FR32X:$src)),
4578 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4579 def : Pat<(f32 (X86frcp (load addr:$src))),
4580 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4581 Requires<[OptForSize]>;
4583 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4584 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4585 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4587 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4588 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4590 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4591 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4592 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4594 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4595 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4599 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4600 X86MemOperand x86memop, RegisterClass RC,
4601 PatFrag mem_frag, Domain d> {
4602 let ExeDomain = d in {
4603 // Intrinsic operation, reg.
4604 // Vector intrinsic operation, reg
4605 def r : AVX512AIi8<opc, MRMSrcReg,
4606 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4607 !strconcat(OpcodeStr,
4608 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4611 // Vector intrinsic operation, mem
4612 def m : AVX512AIi8<opc, MRMSrcMem,
4613 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4614 !strconcat(OpcodeStr,
4615 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4621 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4622 loadv16f32, SSEPackedSingle>, EVEX_V512,
4623 EVEX_CD8<32, CD8VF>;
4625 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4626 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4628 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4631 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4632 loadv8f64, SSEPackedDouble>, EVEX_V512,
4633 VEX_W, EVEX_CD8<64, CD8VF>;
4635 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4636 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4638 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4640 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4641 Operand x86memop, RegisterClass RC, Domain d> {
4642 let ExeDomain = d in {
4643 def r : AVX512AIi8<opc, MRMSrcReg,
4644 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32u8imm:$src3),
4645 !strconcat(OpcodeStr,
4646 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4649 def m : AVX512AIi8<opc, MRMSrcMem,
4650 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32u8imm:$src3),
4651 !strconcat(OpcodeStr,
4652 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4657 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4658 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4660 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4661 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4663 let Predicates = [HasAVX512] in {
4664 def : Pat<(ffloor FR32X:$src),
4665 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4666 def : Pat<(f64 (ffloor FR64X:$src)),
4667 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4668 def : Pat<(f32 (fnearbyint FR32X:$src)),
4669 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4670 def : Pat<(f64 (fnearbyint FR64X:$src)),
4671 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4672 def : Pat<(f32 (fceil FR32X:$src)),
4673 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4674 def : Pat<(f64 (fceil FR64X:$src)),
4675 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4676 def : Pat<(f32 (frint FR32X:$src)),
4677 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4678 def : Pat<(f64 (frint FR64X:$src)),
4679 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4680 def : Pat<(f32 (ftrunc FR32X:$src)),
4681 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4682 def : Pat<(f64 (ftrunc FR64X:$src)),
4683 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4686 def : Pat<(v16f32 (ffloor VR512:$src)),
4687 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4688 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4689 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4690 def : Pat<(v16f32 (fceil VR512:$src)),
4691 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4692 def : Pat<(v16f32 (frint VR512:$src)),
4693 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4694 def : Pat<(v16f32 (ftrunc VR512:$src)),
4695 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4697 def : Pat<(v8f64 (ffloor VR512:$src)),
4698 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4699 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4700 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4701 def : Pat<(v8f64 (fceil VR512:$src)),
4702 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4703 def : Pat<(v8f64 (frint VR512:$src)),
4704 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4705 def : Pat<(v8f64 (ftrunc VR512:$src)),
4706 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4708 //-------------------------------------------------
4709 // Integer truncate and extend operations
4710 //-------------------------------------------------
4712 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4713 RegisterClass dstRC, RegisterClass srcRC,
4714 RegisterClass KRC, X86MemOperand x86memop> {
4715 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4717 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4720 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4721 (ins KRC:$mask, srcRC:$src),
4722 !strconcat(OpcodeStr,
4723 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4726 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4727 (ins KRC:$mask, srcRC:$src),
4728 !strconcat(OpcodeStr,
4729 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4732 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4733 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4736 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4737 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4738 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4742 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4743 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4744 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4745 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4746 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4747 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4748 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4749 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4750 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4751 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4752 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4753 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4754 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4755 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4756 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4757 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4758 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4759 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4760 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4761 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4762 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4763 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4764 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4765 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4766 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4767 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4768 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4769 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4770 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4771 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4773 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4774 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4775 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4776 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4777 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4779 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4780 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4781 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4782 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4783 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4784 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4785 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4786 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4789 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4790 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4791 PatFrag mem_frag, X86MemOperand x86memop,
4792 ValueType OpVT, ValueType InVT> {
4794 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4797 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4799 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4800 (ins KRC:$mask, SrcRC:$src),
4801 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4804 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4805 (ins KRC:$mask, SrcRC:$src),
4806 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4809 let mayLoad = 1 in {
4810 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4811 (ins x86memop:$src),
4812 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4814 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4817 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4818 (ins KRC:$mask, x86memop:$src),
4819 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4823 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4824 (ins KRC:$mask, x86memop:$src),
4825 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4831 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4832 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4834 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4835 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4837 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4838 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4839 EVEX_CD8<16, CD8VH>;
4840 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4841 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4842 EVEX_CD8<16, CD8VQ>;
4843 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4844 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4845 EVEX_CD8<32, CD8VH>;
4847 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4848 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4850 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4851 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4853 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4854 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4855 EVEX_CD8<16, CD8VH>;
4856 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4857 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4858 EVEX_CD8<16, CD8VQ>;
4859 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4860 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4861 EVEX_CD8<32, CD8VH>;
4863 //===----------------------------------------------------------------------===//
4864 // GATHER - SCATTER Operations
4866 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4867 RegisterClass RC, X86MemOperand memop> {
4869 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4870 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4871 (ins RC:$src1, KRC:$mask, memop:$src2),
4872 !strconcat(OpcodeStr,
4873 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4877 let ExeDomain = SSEPackedDouble in {
4878 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4879 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4880 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4881 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4884 let ExeDomain = SSEPackedSingle in {
4885 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4886 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4887 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4888 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4891 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4892 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4893 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4894 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4896 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4897 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4898 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4899 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4901 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4902 RegisterClass RC, X86MemOperand memop> {
4903 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4904 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4905 (ins memop:$dst, KRC:$mask, RC:$src2),
4906 !strconcat(OpcodeStr,
4907 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4911 let ExeDomain = SSEPackedDouble in {
4912 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4913 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4914 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4915 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4918 let ExeDomain = SSEPackedSingle in {
4919 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4920 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4921 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4922 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4925 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4926 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4927 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4928 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4930 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4931 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4932 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4933 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4936 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4937 RegisterClass KRC, X86MemOperand memop> {
4938 let Predicates = [HasPFI], hasSideEffects = 1 in
4939 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4940 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4944 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4945 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4947 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4948 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4950 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4951 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4953 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4954 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4956 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4957 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4959 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4960 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4962 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4963 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4965 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4966 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4968 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4969 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4971 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4972 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4974 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4975 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4977 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4978 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4980 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4981 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4983 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4984 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4986 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4987 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4989 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4990 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4991 //===----------------------------------------------------------------------===//
4992 // VSHUFPS - VSHUFPD Operations
4994 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4995 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4997 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4998 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
4999 !strconcat(OpcodeStr,
5000 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5001 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5002 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5003 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5004 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5005 (ins RC:$src1, RC:$src2, u8imm:$src3),
5006 !strconcat(OpcodeStr,
5007 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5008 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5009 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5010 EVEX_4V, Sched<[WriteShuffle]>;
5013 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5014 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5015 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5016 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5018 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5019 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5020 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5021 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5022 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5024 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5025 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5026 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5027 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5028 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5030 multiclass avx512_valign<X86VectorVTInfo _> {
5031 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5032 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5034 "$src3, $src2, $src1", "$src1, $src2, $src3",
5035 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5037 AVX512AIi8Base, EVEX_4V;
5039 // Also match valign of packed floats.
5040 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5041 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5044 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5045 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5046 !strconcat("valign"##_.Suffix,
5047 "\t{$src3, $src2, $src1, $dst|"
5048 "$dst, $src1, $src2, $src3}"),
5051 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5052 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5054 // Helper fragments to match sext vXi1 to vXiY.
5055 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5056 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5058 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5059 RegisterClass KRC, RegisterClass RC,
5060 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5062 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5063 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5065 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5066 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5068 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5069 !strconcat(OpcodeStr,
5070 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5072 let mayLoad = 1 in {
5073 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5074 (ins x86memop:$src),
5075 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5077 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5078 (ins KRC:$mask, x86memop:$src),
5079 !strconcat(OpcodeStr,
5080 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5082 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5083 (ins KRC:$mask, x86memop:$src),
5084 !strconcat(OpcodeStr,
5085 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5087 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5088 (ins x86scalar_mop:$src),
5089 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5090 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5092 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5093 (ins KRC:$mask, x86scalar_mop:$src),
5094 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5095 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5096 []>, EVEX, EVEX_B, EVEX_K;
5097 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5098 (ins KRC:$mask, x86scalar_mop:$src),
5099 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5100 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5102 []>, EVEX, EVEX_B, EVEX_KZ;
5106 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5107 i512mem, i32mem, "{1to16}">, EVEX_V512,
5108 EVEX_CD8<32, CD8VF>;
5109 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5110 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5111 EVEX_CD8<64, CD8VF>;
5114 (bc_v16i32 (v16i1sextv16i32)),
5115 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5116 (VPABSDZrr VR512:$src)>;
5118 (bc_v8i64 (v8i1sextv8i64)),
5119 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5120 (VPABSQZrr VR512:$src)>;
5122 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5123 (v16i32 immAllZerosV), (i16 -1))),
5124 (VPABSDZrr VR512:$src)>;
5125 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5126 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5127 (VPABSQZrr VR512:$src)>;
5129 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5130 RegisterClass RC, RegisterClass KRC,
5131 X86MemOperand x86memop,
5132 X86MemOperand x86scalar_mop, string BrdcstStr> {
5133 let hasSideEffects = 0 in {
5134 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5136 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5139 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5140 (ins x86memop:$src),
5141 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5144 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5145 (ins x86scalar_mop:$src),
5146 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5147 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5149 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5150 (ins KRC:$mask, RC:$src),
5151 !strconcat(OpcodeStr,
5152 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5155 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5156 (ins KRC:$mask, x86memop:$src),
5157 !strconcat(OpcodeStr,
5158 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5161 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5162 (ins KRC:$mask, x86scalar_mop:$src),
5163 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5164 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5166 []>, EVEX, EVEX_KZ, EVEX_B;
5168 let Constraints = "$src1 = $dst" in {
5169 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5170 (ins RC:$src1, KRC:$mask, RC:$src2),
5171 !strconcat(OpcodeStr,
5172 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5175 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5176 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5177 !strconcat(OpcodeStr,
5178 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5181 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5182 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5183 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5184 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5185 []>, EVEX, EVEX_K, EVEX_B;
5190 let Predicates = [HasCDI] in {
5191 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5192 i512mem, i32mem, "{1to16}">,
5193 EVEX_V512, EVEX_CD8<32, CD8VF>;
5196 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5197 i512mem, i64mem, "{1to8}">,
5198 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5202 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5204 (VPCONFLICTDrrk VR512:$src1,
5205 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5207 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5209 (VPCONFLICTQrrk VR512:$src1,
5210 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5212 let Predicates = [HasCDI] in {
5213 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5214 i512mem, i32mem, "{1to16}">,
5215 EVEX_V512, EVEX_CD8<32, CD8VF>;
5218 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5219 i512mem, i64mem, "{1to8}">,
5220 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5224 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5226 (VPLZCNTDrrk VR512:$src1,
5227 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5229 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5231 (VPLZCNTQrrk VR512:$src1,
5232 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5234 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5235 (VPLZCNTDrm addr:$src)>;
5236 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5237 (VPLZCNTDrr VR512:$src)>;
5238 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5239 (VPLZCNTQrm addr:$src)>;
5240 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5241 (VPLZCNTQrr VR512:$src)>;
5243 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5244 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5245 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5247 def : Pat<(store VK1:$src, addr:$dst),
5249 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5250 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5252 def : Pat<(store VK8:$src, addr:$dst),
5254 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5255 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5257 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5258 (truncstore node:$val, node:$ptr), [{
5259 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5262 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5263 (MOV8mr addr:$dst, GR8:$src)>;
5265 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5266 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5267 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5268 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5271 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5272 string OpcodeStr, Predicate prd> {
5273 let Predicates = [prd] in
5274 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5276 let Predicates = [prd, HasVLX] in {
5277 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5278 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5282 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5283 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5285 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5287 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5289 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5293 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5295 //===----------------------------------------------------------------------===//
5296 // AVX-512 - COMPRESS and EXPAND
5298 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5300 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5301 (ins _.KRCWM:$mask, _.RC:$src),
5302 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5303 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5304 _.ImmAllZerosV)))]>, EVEX_KZ;
5306 let Constraints = "$src0 = $dst" in
5307 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5308 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5309 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5310 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5311 _.RC:$src0)))]>, EVEX_K;
5313 let mayStore = 1 in {
5314 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5315 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5316 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5317 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5319 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5323 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5324 AVX512VLVectorVTInfo VTInfo> {
5325 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5327 let Predicates = [HasVLX] in {
5328 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5329 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5333 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5335 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5337 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5339 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5343 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5345 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5346 (ins _.KRCWM:$mask, _.RC:$src),
5347 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5348 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5349 _.ImmAllZerosV)))]>, EVEX_KZ;
5351 let Constraints = "$src0 = $dst" in
5352 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5353 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5354 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5355 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5356 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5358 let mayLoad = 1, Constraints = "$src0 = $dst" in
5359 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5360 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5361 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5362 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5364 (_.LdFrag addr:$src))),
5366 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5369 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5370 (ins _.KRCWM:$mask, _.MemOp:$src),
5371 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5372 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5373 (_.VT (bitconvert (_.LdFrag addr:$src))),
5374 _.ImmAllZerosV)))]>,
5375 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5379 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5380 AVX512VLVectorVTInfo VTInfo> {
5381 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5383 let Predicates = [HasVLX] in {
5384 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5385 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5389 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5391 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5393 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5395 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,